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    Q67106-H5157 SDA5649 SDA5649X Q67100-H5156

SIEMENS[Siemens Semiconductor Group]
Infineon
Part No. Q67106-H5157 SDA5649 SDA5649X Q67100-H5156
OCR Text ...of the PDC system from the data lines broadcast during the vertical blanking interval of a standard video signal. The SDA 5649 is devised to handle PDC data transported either in Broadcast Data Service Packet (BDSP) 8/30 format 2 (bytes no....
Description From old datasheet system
Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder

File Size 477.76K  /  26 Page

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    EXAR[Exar Corporation]
Part No. XR16V2552_07 XR16V2552 XR16V2552IJ XR16V2552IL32
OCR Text ...D3 D2 D1 D0 IOR# I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I Input/Output Read Strobe (active...
Description HIGH PERFORMANCE DUART WITH 16-BYTE FIFO

File Size 477.20K  /  48 Page

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    NCV7341D20G

ON SEMICONDUCTOR
Part No. NCV7341D20G
OCR Text ...able to communicate via the bus lines. the can controller can transmit data to the bus via txd pin and receive data from the bus via pin rxd. the bus lines (canh and canl) are internally biased to v cc /2 via the common ? mode input resista...
Description Improved High Speed, Low Power CAN Transceiver

File Size 214.55K  /  18 Page

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    QL8050 QL8150 QL8250 QL8025 QL8325

ETC[ETC]
Part No. QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text ... 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell accommodates many us...
Description LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

File Size 442.48K  /  49 Page

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    AGERE[Agere Systems]
Part No. T8110
OCR Text ...ll H.100/H.110 support (32 data lines, all clock modes) n 32 local I/O lines (2, 4, 8, or 16 Mbits/s) n PCI interface: combined master/slave with burst n Microprocessor interface: Motorola*/Intel modes n Minibridge with programmable chip s...
Description Version History

File Size 1,850.89K  /  222 Page

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    EXAR[Exar Corporation]
Part No. XR16V2652_07 XR16V2652 XR16V2652IJ XR16V2652IL32
OCR Text ...D3 D2 D1 D0 IOR# I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I Input/Output Read Strobe (active...
Description HIGH PERFORMANCE DUART WITH 32-BYTE FIFO

File Size 474.78K  /  48 Page

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    SAK-C167CS-LM C167CS-4R SAB-C167CS-4R33M SAB-C167CS-4RM SAK-C167CS-4R33M SAK-C167CS-4RM SAB-C167CS-LM SAK-C167CS-L33M SA

Infineon Technologies AG
Part No. SAK-C167CS-LM C167CS-4R SAB-C167CS-4R33M SAB-C167CS-4RM SAK-C167CS-4R33M SAK-C167CS-4RM SAB-C167CS-LM SAK-C167CS-L33M SAB-C167CS-L33M
OCR Text ...* Up to 111 General Purpose I/O lines, partly with Selectable Input Thresholds and Hysteresis Data Sheet 1 V2.0, 2000-06 C167CS-4R C167CS-L * Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages,...
Description 16-Bit Single-Chip Microcontroller

File Size 758.25K  /  80 Page

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    MACRONIX INTERNATIONAL CO LTD
Part No. MX29GA128EHXCI-90G
OCR Text ... x-decoder decodes the word-lines of the fash array, while the y-decoder decodes the bit-lines of the fash array. the bit lines are electrically connected to the "sense amplifier" and "pgm data hv" sele...
Description 16M X 8 FLASH 3V PROM, 90 ns, PBGA64

File Size 2,262.28K  /  70 Page

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    EXAR[Exar Corporation]
Part No. XR16V554IV80 XR16V554 XR16V554D XR16V554DIV XR16V554IJ XR16V554IL XR16V554IV
OCR Text ...2 71 70 69 68 51 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I When 16/68# pin is HIGH, the Int...
Description 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO

File Size 333.92K  /  45 Page

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    EXAR[Exar Corporation]
Part No. XR16V564IV80 XR16V564 XR16V564D XR16V564DIV XR16V564IJ XR16V564IL XR16V564IV
OCR Text ...2 71 70 69 68 51 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I When 16/68# pin is HIGH, the Int...
Description 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO

File Size 413.10K  /  55 Page

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