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pmc
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| Part No. |
2001562
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| OCR Text |
...mable inter-packet gap (IPG). * implements in-band PAUSE flowcontrol and provides support for out-ofband flow control. * Upper layer device can flow-control using dedicated pins or host signaling to cause generation of a PAUSE frame.
FEA... |
| Description |
From old datasheet system
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| File Size |
20.97K /
2 Page |
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MAXIM - Dallas Semiconductor
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| Part No. |
DS2282/87-22282-000
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| OCR Text |
implements the fdl message format as de- scribed in the ansi document t1.4031989 ? fully implements the maintenance message protocol described in at&t tr 54016 (1986/89) ? provides highlevel monitor counts, namely: errored seconds severel... |
| Description |
T1 FDL Controller/Monitor Stik
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| File Size |
138.99K /
22 Page |
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SiS
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| Part No. |
SIS748 748
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...Disk1 Disk2
RAID
* RAID 0 implements a striped disk array, the data is divided into small blocks and each block is written to a separate disk drive. * I/O performance is improved by separate the I/O access via different channels and d... |
| Description |
North Bridge Chipset
From old datasheet system
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| File Size |
3,448.65K /
38 Page |
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it Online |
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pmc
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| Part No. |
1990996
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| OCR Text |
implements the Physical Layer Convergence Protocol (PLCP) for T1 and DS3 transmission systems according to the ATM Forum UNI Specification and ANSI TA-TSY-000773, TA-TSY-000772, and for E1 and E3 transmission systems according to ETSI 300-2... |
| Description |
From old datasheet system
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| File Size |
92.58K /
2 Page |
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Zarlink
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| Part No. |
MT90502 160
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...s per VC. Maximum of 1023 CIDs. implements AAL2 Common Part Sub-layer (CPS) functions specified in ITU I.363.2. implements AAL2 Service Specific Convergence Sub-layer (SSCS) functions for G.711 PCM and G.726 ADPCM voice. Supports 44-byte PC... |
| Description |
Multi-Channel AAL2 SAR
From old datasheet system
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| File Size |
1,236.02K /
191 Page |
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it Online |
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INTEL
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| Part No. |
GDS1110
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| OCR Text |
...RM SA-1110 CPU
The SA-1110 CPU implements the ARM V4 architecture as defined in the ARM Architecture Reference Manual. Architectural enhancements beyond the ARM V4 are implemented through use of coprocessor 15. Control register reads and w... |
| Description |
StrongARM / Microprocessor
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| File Size |
50.80K /
11 Page |
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Keysight Technologies
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| Part No. |
M9703A
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| OCR Text |
...ents. the standard coniguration implements 8 channels of 12-bit resolution with dc to 650 mhz input frequency range (C3 db analog bandwidth), and acquiring data at 1 gs/s. if higher speed is required, the -sr2 option enables the eight... |
| Description |
AXIe High-Speed Digitizer/ Wideband Digital Receiver
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| File Size |
1,255.15K /
16 Page |
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it Online |
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