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    74ACTQ464ASPC 74ACQ464ASPC 74ACQ646 74ACTQ646 74ACTQ646SC 74ACQ646SC 74ACQ657 74ACTQ646SPC 74ACQ646CW 74ACQ646SCX 74ACQ6

Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
Part No. 74ACTQ464ASPC 74ACQ464ASPC 74ACQ646 74ACTQ646 74ACTQ646SC 74ACQ646SC 74ACQ657 74ACTQ646SPC 74ACQ646CW 74ACQ646SCX 74ACQ646SPC 74ACTQ646CW 74ACTQ646SCX
OCR Text ...uits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers ...
Description Quiet SeriesOctal Transceiver/Register with 3-STATE Outputs 安静系列⑩八路收发器/ 3注册态输
Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs
Quiet Series⑩ Octal Transceiver/Register with 3-STATE Outputs
Quiet Series Octal Transceiver/Register with 3-STATE Outputs
Quiet Series???? Octal Transceiver/Register
From old datasheet system
Quiet Series?/a> Octal Transceiver/Register with 3-STATE Outputs

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    74ACTQ533 74ACTQ533MTC 74ACTQ533PC 74ACTQ533SC 74ACTQ533SCX 74ACTQ533MTCX

FAIRCHILD[Fairchild Semiconductor]
Part No. 74ACTQ533 74ACTQ533MTC 74ACTQ533PC 74ACTQ533SC 74ACTQ533SCX 74ACTQ533MTCX
OCR Text ...d system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. W...
Description Quiet Series Octal Transparent Latch with 3-STATE Outputs
From old datasheet system

File Size 92.24K  /  8 Page

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    74ACTQ574PC 74ACQ574 74ACQ574PC 74ACQ574SC 74ACQ574SJ 74ACTQ574SJ 74ACTQ574SC 74ACQ574CW 74ACTQ574CW

Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
Part No. 74ACTQ574PC 74ACQ574 74ACQ574PC 74ACQ574SC 74ACQ574SJ 74ACTQ574SJ 74ACTQ574SC 74ACQ574CW 74ACTQ574CW
OCR Text ... D inputs is stored in the flip-flops on the LOW-to-HIGH clock (CP) transition. ACQ/ACTQ574 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO ...
Description Quiet Series Octal D Flip-Flop with 3-STATE Outputs
Quiet SeriesOctal D-Type Flip-Flop with 3-STATE Outputs
18-Bit LVTTL-to-GTLP Bus Transceiver with Source Synchronous Clock Outputs 56-TSSOP -40 to 85
Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
Quiet Series⑩ Octal D-Type Flip-Flop with 3-STATE Outputs
From old datasheet system

File Size 96.78K  /  10 Page

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    74AHC574 74AHC574D 74AHC574PW 74AHC574PWDH 74AHCT574 74AHCT574PWDH 74AHCT574D 74AHCT574PW

PHILIPS[Philips Semiconductors]
Part No. 74AHC574 74AHC574D 74AHC574PW 74AHC574PWDH 74AHCT574 74AHCT574PWDH 74AHCT574D 74AHCT574PW
OCR Text ...C/AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will st...
Description Octal D-type flip-flop; positive edge-trigger; 3-state

File Size 91.82K  /  20 Page

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    74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ

Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
Part No. 74F161APC 74F161ASC 74F161ASJ 74F163APC 74F163ASC 74F163ASJ
OCR Text ...). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the 74F161A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the...
Description Synchronous Presettable Binary Counter F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16

File Size 70.56K  /  7 Page

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    74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN

NXP Semiconductors
http://
PHILIPS[Philips Semiconductors]
Part No. 74F161A I74F161AD I74F161AN N74F161AD N74F161AN 74F163A I74F163AD I74F163AN N74F163AD N74F163AN
OCR Text ... is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input...
Description 4-bit binary counter

File Size 111.89K  /  14 Page

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    74HC273 74HCT273 74HC273D 74HCT273D 74HC273PW 74HC273DB 74HC273N 74HCT273DB 74HCT273N 74HCT273PW 74HC273BQ 74HC273U

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74HC273 74HCT273 74HC273D 74HCT273D 74HC273PW 74HC273DB 74HC273N 74HCT273DB 74HCT273N 74HCT273PW 74HC273BQ 74HC273U
OCR Text ...tive edge-triggered D-type flip-flops * See "377" for clock enable version * See "373" for transparent latch version * See "374" for 3-state version * Output capability; standard * ICC category: MSI GENERAL DESCRIPTION 74HC/HCT273 The...
Description Octal D-type flip-flop with reset positive-edge trigger
74HC/HCT273; Octal D-type flip-flop with reset; positive-edge trigger

File Size 58.30K  /  8 Page

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    74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74H

PHILIPS[Philips Semiconductors]
Part No. 74HC40105 74HC40105D 74HC40105DB 74HC40105N 74HC40105PW 74HCT40105 74HCT40105D 74HCT40105DB 74HCT40105N 74HCT40105PW 74HCT40105U 74HC40105U
OCR Text ...The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (data-in ready o...
Description 4-bit x 16-word FIFO register

File Size 199.99K  /  25 Page

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    74HC4046A 74HCT4046A 74HC4046AD HCT4046A 74HC4046 74HC4046ADB 74HC4046AN 74HC4046APW 74HCT4046AD 74HCT4046ADB 74HCT4046A

PHILIPS[Philips Semiconductors]
Part No. 74HC4046A 74HCT4046A 74HC4046AD HCT4046A 74HC4046 74HC4046ADB 74HC4046AN 74HC4046APW 74HCT4046AD 74HCT4046ADB 74HCT4046AN 74HCT4046APW
OCR Text .... PC2 comprises two D-type flip-flops, control-gating and a 3-state output stage. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr ...
Description Phase-locked-loop with VCO

File Size 467.34K  /  34 Page

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