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  1m-word Datasheet PDF File

For 1m-word Found Datasheets File :: 2143    Search Time::1.594ms    
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    PC7410

List of Unclassifed Manufacturers
Part No. PC7410
OCR Text ...gs; external data SRAMs - 512K, 1M and 2-Mbyte 2-way set associative L2 cache support - Copyback or write-through data cache (on a page basis or for all L2) - 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size - Supports pipe...
Description PowerPC 7410 RISC Microprocessor

File Size 786.26K  /  57 Page

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    Mitsubishi Electric, Corp.
Part No. M5M4V16169DRT-15 M5M4V16169DTP
OCR Text 1m-word by 16-bit) cached dram with 16k (1024-word by 16-bit) sram mitsubishi lsis (rev 1.0) jul. 1998 mitsubishi electric 1. 2. preliminary this document is a preliminary target spec. and some of the contents are subject to change without...
Description 16MCDRAM:16M(1m-word BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM 16MCDRAM6米(100万字6位)6K的缓存内存(1024字由16位)的SRAM

File Size 752.46K  /  64 Page

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    CY7C11501KV18 CY7C11501KV18-400BZXC CY7C11501KV18-400BZXI CY7C11461KV18 CY7C11481KV18-400BZC CY7C11571KV18

Cypress Semiconductor
Part No. CY7C11501KV18 CY7C11501KV18-400BZXC CY7C11501KV18-400BZXI CY7C11461KV18 CY7C11481KV18-400BZC CY7C11571KV18
OCR Text ...8-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 450 MHz Clock for High Bandwidth 2-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz Available in 2.0 Clock Cycle Lat...
Description 18-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 596.13K  /  29 Page

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    CY7C12461KV18 CY7C12501KV18 CY7C12501KV18-400BZC CY7C12481KV18 CY7C12571KV18 CY7C12481KV18-400BZC

Cypress Semiconductor
Part No. CY7C12461KV18 CY7C12501KV18 CY7C12501KV18-400BZC CY7C12481KV18 CY7C12571KV18 CY7C12481KV18-400BZC
OCR Text ...nsity (4M x 8, 4M x 9, 2M x 18, 1M x 36) 450 MHz Clock for High Bandwidth 2-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz Available in 2.0 Clock Cycle Latency Two In...
Description 36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 608.41K  /  29 Page

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Part No. K8D1716UBC-PC070
OCR Text 1m x16) dual bank nor flash memory revision history revision no. 0.0 0.1 0.2 1.0 remark advance preliminary preliminary history initial dra...word) and erases in units of a block. single or multiple blocks can be erased. the block erase opera...
Description 1M X 16 FLASH 2.7V PROM, 70 ns, PDSO48

File Size 565.81K  /  41 Page

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    Asahi Kasei Microsystems Co.,Ltd
Part No. AK7712 AK7712A-VT
OCR Text ...memory: 256k(32k 8-bit),1m(128k 8-bit) 1 / sram 256k(32k 8-bit),1m(128k 8-bit) 1 / pseudo-sram 256k(64k 4-bit),1m(...word 16-bit. two pointers are prepared. cp0 is reset to the address"0(hex)" and cp1 is reset to "...
Description Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No

File Size 982.57K  /  87 Page

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    RMP116MFAW-70E

Emerging Memory & Logic Solutions Inc
Part No. RMP116MFAW-70E
OCR Text 1M x 16 bit Pseudo SRAM ( EMP116MFAW Series ) Specification Revision History Revision No. 0.0 History Initial Draft Draft Date ...Word Read Lower Byte Write Upper Byte Write Word Write Power Stand by Deep Power Down Stand by Activ...
Description 1Mx16 Pseudo Static RAM

File Size 420.25K  /  11 Page

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    CY7C12761KV18 CY7C12631KV18 CY7C12651KV18 CY7C12611KV18

Cypress Semiconductor
Part No. CY7C12761KV18 CY7C12631KV18 CY7C12651KV18 CY7C12611KV18
OCR Text ...8 write reg write reg write reg 1m x 8 array 1m x 8 array 1m x 8 array 1m x 8 array q [8:0] 9 clk a (19:0) gen. k k control logic address re...word of data is driven onto the q [17:0] using k as the output timing reference. on the subsequen...
Description 36-Mbit QDR? II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

File Size 601.27K  /  30 Page

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