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Cypress Semiconductor, Corp.
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| Part No. |
CY2304SXC-2T CY2304SXI-1T
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| OCR Text |
...djustable by capacitive load on fbk input multiple configurations multiple low-skew outputs 10 mhz to 133 mhz operating range 90 ps typical peak cycle-to-cycle jitter at 15 pf, 66 mhz space-saving 8-pin 150-mil small outline integrated... |
| Description |
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 4; Operating Range: 0 to 70 C 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
3.3V Zero Delay Buffer 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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| File Size |
367.71K /
15 Page |
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Analog Devices
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| Part No. |
AD8364 AD8364-EVAL
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| OCR Text |
...VST[A,B] = OUT[A,B], OUT[P,N] = fbk[A,B], differential input via Balun1, CW input f 2.7GHz unless otherwise noted)
Conditions Channel A and Channel B, CW sine wave input INH[A,B] (Pins 26, 31) INL[A,B] (Pins 27, 30) LF 2.5 OUT[A,B] (Pins ... |
| Description |
LF to 2.7GHz Dual 60dB TruPwr™ Detector
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| File Size |
1,428.18K /
24 Page |
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ON Semiconductor
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| Part No. |
NB2308AC1HDTR2 NB2308AI4DT
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| OCR Text |
...ack is required to be driven to fbk pin, and can be obtained from one of the outputs. the input ? to ? output propagation delay is guaranteed to be less than 250 ps, and the output ? to ? output skew is guaranteed to be less than 200 ps. th... |
| Description |
3.3V Eight Output Zero Delay Buffer; Package: TSSOP-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
3.3V Eight Output Zero Delay Buffer; Package: TSSOP-16; No of Pins: 16; Container: Rail; Qty per Container: 96 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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| File Size |
170.46K /
13 Page |
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Silicon Laboratories, Inc.
HIROSE ELECTRIC Co., Ltd.
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| Part No. |
SL23EP08SC-2T SL23EP08SC-2H
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| OCR Text |
...on-chip pll and a feedback pin (fbk) which can be used to obtain feedback from any one of the output clocks. the sl23ep08 has two (2) clock driver banks each with four (4) clock outputs. these outputs are controlled by two (2) select in... |
| Description |
23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT,SOIC-16
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| File Size |
239.03K /
18 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY23S08SXI-2T CY23S08SXC-2T CY23S08SXI-4 CY23S08SXI-4T CY23S08SXC-4
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| OCR Text |
...justable by capacitive load on fbk input multiple configurations (see ta b l e 3 on page 3) multiple low-skew outputs ? 45 ps typical output-output skew (?1) ? two banks of four outputs, three-stateable by two select inputs 10 mhz ... |
| Description |
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 140 MHz; Outputs: 8; Operating Range: -40 to 85 C 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
3.3V Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 140 MHz; Outputs: 8; Operating Range: 0 to 70 C 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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| File Size |
204.64K /
11 Page |
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it Online |
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Price and Availability
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