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clocks Datasheet PDF File

For clocks Found Datasheets File :: 21168 Search Time::0.968ms
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				AKM Asahi Kasei Microsystems
Part No.	AK436604 AK4366VT AK4366
OCR Text	...VIEW System Clock The external clocks required to operate the AK4366 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter....
Description	24-bit DAC 8-48KHz with 50mW Headphone Amp Low Power 24-Bit 2ch DAC with HP-AMP
File Size	332.18K / 31 Page	View it Online	Download Datasheet

				Asahi Kasei Microsystems
Part No.	AKD4121A07
OCR Text	...rough the 10-pin port and other clocks are fed from the AK4112B. The X1(X'tal) or external clock (via PORT1) can be used as the system clock of the input block. Please remove X1 when unsed. The system clock can be selected as 256fsi or 512f...
Description	Asynchronous Sample Rate Converter
File Size	279.81K / 36 Page	View it Online	Download Datasheet

				Asahi Kasei Microsystems
Part No.	AKD4126-A
OCR Text	...2. Set up IBICK, ILRCK and SDTI clocks (IBICK and ILRCK) and data (SDTI) of the AK4126 (U1) are supplied from the AK4114 (U2). As 10-pin connector: PORT2 (INPUT) is not used, please don't connect anything. JP8 X T I-R X (O p e n ) JP13 IM ...
Description	digital sample rate converter.
File Size	899.87K / 29 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT8941B MT8941BE MT8941BP
OCR Text	...d CEPT (2.048 MHz) transmission clocks and ST-BUS timing signals. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the ...
Description	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
File Size	130.44K / 22 Page	View it Online	Download Datasheet

				MITEL[Mitel Networks Corporation]
Part No.	MT8941 MT8941AE MT8941AP
OCR Text	...d CEPT (2.048 MHz) transmission clocks and ST-BUS timing signals. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the ...
Description	CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
File Size	246.12K / 18 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C142XAV18 CY7C130XBV25 CY7C132XBV25
OCR Text	...- fined state after controls or clocks are left floating. no proper read/write access can be done on the device until a dummy read is performed. 9mb - ?d? rev - ram9 18mb - ?b? rev - ram9 36mb - ?a? rev - ram9 72mb - ram9 qdr-i/ddr-i/ qd...
Description	(CY7C1xxxxVxx) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
File Size	242.79K / 8 Page	View it Online	Download Datasheet

				Asahi Kasei Microsystems
Part No.	AKD4127-A
OCR Text	...KASEI [AKD4127-A] (2) All clocks are fed through the 10pin port When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR). JP2 IBICK JP3 SDTI JP4 ILRCK * SW3 setting (See Table 2) Upper-side is "H" and low...
Description	digital sample rate converter.
File Size	212.67K / 20 Page	View it Online	Download Datasheet

				LSI CORP
Part No.	T8100A--BAL3-DB T8105---BAL3-BB T8102---BAL3-DB T8100A--SC3-DB
OCR Text	... and the board generates a or b clocks, the watchdog will indicate an error on the a or b clocks it generates. the error will be reported even though the generated clocks are good. workaround : use the master board to accurately monitor...
Description	DATACOM, TIME SLOT ASSIGNER, PBGA217 DATACOM, TIME SLOT ASSIGNER, PQFP208
File Size	1,371.38K / 112 Page	View it Online	Download Datasheet

				Asahi Kasei Microsystems
Part No.	AKD4634-A
OCR Text	...r (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then "MCKO bit" in the AK4634 is set to "1". When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE)....
Description	16bit mono CODEC with MIC/SPK/VIDEO amplifier.
File Size	1,144.50K / 46 Page	View it Online	Download Datasheet

				EXAR[Exar Corporation]
Part No.	XRT8000_06 XRT8000 XRT8000ID XRT8000IP
OCR Text	...aneous, very low jitter, output clocks for synchronization applications in wide area networking systems. The outputs are phase locked to the input signal. The chip has four basic modes of operation; referred to as master (FORWARD, REVERSE) ...
Description	Clock Synchronizer/Adapter for Communications
File Size	624.22K / 24 Page	View it Online	Download Datasheet

For clocks Found Datasheets File :: 21168 Search Time::0.968ms
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