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www.irf.com ? 2009 international rectifier april 26, 2011 irs2336(d) irs23364d high voltage 3 phase gate driver ic features ? drives up to six igbt/mosfet power devices ? gate drive supplies up to 20 v per channel ? integrated bootstrap functionality (irs2336(4)d) ? overcurrent protection ? overtemperature shutdown input ? advanced input filter ? integrated deadtime protection ? shootthrough (crossconduction) protection ? undervoltage lockout for v cc & v bs ? enable/disable input and fault reporting ? adjustable fault clear timing ? separate logic and power grounds ? 3.3 v input logic compatible ? tolerant to negative transient voltage ? designed for use with bootstrap power supplies ? matched propagation delays for all channels ? 40c to 125c operating range ? rohs compliant ? leadfree typical applications ? appliance motor drives ? servo drives ? micro inverter drives ? general purpose three phase inverters product summary topology 3 phase v offset 600 v irs2336(d) 10 v C 20 v v out irs23364d 11.5 v C 20 v i o+ & i o (typical) 200 ma & 350 ma t on & t off (typical) 530 ns & 530 ns deadtime (typical) 275 ns package options typical connection diagram 28lead pdip 28lead soic wide body 48lead mlpq7x7 44lead plcc (without 14 leads) (without 12 leads ) downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 2 table of contents page description 3 feature comparison 3 simplified block diagram 4 typical application diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating conditions 7 static electrical characteristics 89 dynamic electrical characteristics 10 functional block diagram 1112 input/output pin equivalent circuit diagram 1314 lead definitions 1516 lead assignments 17 application information and additional details 1835 parameter temperature trends 3639 package details 4043 tape and reel details 4446 part marking information 47 ordering information 48 downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 3 description the irs2336xd are high voltage, high speed, power m osfet and igbt gate drivers with three highside an d three lowside referenced output channels for 3pha se applications. this ic is designed to be used wi th lowcost bootstrap power supplies; the bootstrap diode funct ionality has been integrated into this device to re duce the component count and the pcb size. proprietary hvic and latch immune cmos technologies have been implemented in a rugged monolithic structure. the floating logic input is compatible with standard cm os or lsttl outputs (down to 3.3 v logic). a current tri p function which terminates all six outputs can be derived from an external current sense resistor. enable functio nality is available to terminate all six outputs si multaneously. an opendrain fault signal is provided to indicate that a fault (e.g., overcurrent, overtemperature, or undervoltage shutdown event) has occurred. fault c onditions are cleared automatically after a delay programmed externally via an rc network connected t o the rcin input. the output drivers feature a hi ghpulse current buffer stage designed for minimum driver cr ossconduction. shootthrough protection circuitry and a minimum deadtime circuitry have been integrated int o this ic. propagation delays are matched to simpl ify the hvics use in high frequency applications. the floa ting channels can be used to drive nchannel power mosfets or igbts in the highside configuration, wh ich operate up to 600 v. feature comparison: irs2336xd family part number input logic uvlo v it,th t on , t off v out irs2336(d) hin/n, lin/n 8.9 v/ 8.2 v 0.46 v 530 ns, 530 ns 10 v C 20 v irs23364d hin, lin 11.1 v/ 10.9 v 0.46 v 530 ns, 53 0 ns 11.5 v C 20 v downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 4 simplified block diagram typical application diagram irs2336xd control inputs, en, & fault v cc input voltage dc bus 600 v to load + downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 5 qualification information ? industrial ?? qualification level comments: this family of ics has passed jedecs industrial qualification. irs consumer qualificat ion level is granted by extension of the higher industrial level . soic28w mlpq7x7 msl3 ??? , 260 c (per ipc/jedec jstd020) plcc44 msl3 ??? , 245 c (per ipc/jedec jstd020) moisture sensitivity level pdip28 not applicable (nonsurface mount package style) human body model class 1c (per jedec standard jesd22a114) machine model class b (per eia/jedec standard eia/jesd22a115) esd charged device model ???? class iv (per jedec standard jesd22c101) ic latchup test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative for fu rther information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. ???? charged device model classification is based on soi c28w package. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all v oltage parameters are absolute voltages referenced to v ss unless otherwise stated in the table. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. voltage clamps a re included between v cc & com (25 v), v cc & v ss (20 v), and v b & v s (20 v). symbol definition min max units v cc low side supply voltage 0.3 20 ? irs2336(d) v ss 0.3 v ss +5.2 v in logic input voltage (hin, lin, itrip, en) irs23364d v ss 0.3 v cc +0.3 v rcin rcin input voltage v ss 0.3 v cc +0.3 v b highside floating well supply voltage 0.3 620 ? v s highside floating well supply return voltage v b 20 ? v b +0.3 v ho floating gate drive output voltage v s 0.3 v b +0.3 v lo lowside output voltage com0.3 v cc +0.3 v flt fault output voltage v ss 0.3 v cc +0.3 com power ground v cc 25 v cc +0.3 v dv s /dt allowable v s offset supply transient relative to v ss 50 v/ns pw hin highside input pulse width 500 ns 28lead pdip 1.5 28lead soicw 1.6 44lead plcc 2.0 p d package power dissipation @ t a +25oc 48lead mlpq7x7 2.0 w 28lead pdip 83 28lead soicw 78 44lead plcc 63 rth ja thermal resistance, junction to ambient 48lead mlpq7x7 63 oc/w t j junction temperature 150 t s storage temperature 55 150 t l lead temperature (soldering, 10 seconds) 300 oc ? all supplies are tested at 25 v. an internal 20 v clamp exists for each supply. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 7 recommended operating conditions for proper operation, the device should be used wit hin the recommended conditions. all voltage parame ters are absolute voltages referenced to v ss unless otherwise stated in the table. the offset rating is tested with supplies of (v cc com) = (v b v s ) = 15 v. symbol definition min max units irs2336(d) 10 20 v cc lowside supply voltage irs23364d 11.5 20 irs2336(d) v ss +5 v in hin, lin, & en input voltage irs23364d v ss v cc irs2336(d) v s +10 v s +20 v b highside floating well supply voltage irs23364d v s +11.5 v s +20 v s highside floating well supply offset voltage ? com8 600 v s (t) transient highside floating supply voltage ?? 50 600 v ho floating gate drive output voltage v s v b v lo lowside output voltage com v cc com power ground 5 5 v flt fault output voltage v ss v cc v rcin rcin input voltage v ss v cc v itrip itrip input voltage v ss v ss +5 v t a ambient temperature 40 125 oc ? logic operation for v s of C8 v to 600 v. logic state held for v s of C8 v to Cv bs . please refer to design tip dt973 for more details. ?? operational for transient negative v s of v ss 50 v with a 50 ns pulse width. guaranteed by design. ref er to the application information section of this datashe et for more details. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 8 static electrical characteristics (v cc com) = (v b v s ) = 15 v. t a = 25 o c unless otherwise specified. the v in and i in parameters are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to respective v s and com and are applicable to the respective output leads ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . symbol definition min typ max units test conditions irs2336(d) 8 8.9 9.8 v ccuv + v cc supply undervoltage positive going threshold irs23364d 10.4 11.1 11.6 irs2336(d) 7.4 8.2 9 v ccuv v cc supply undervoltage negative going threshold irs23364d 10.2 10.9 11.4 irs2336(d) 0.3 0.7 v ccuvhy v cc supply undervoltage hysteresis irs23364d 0.2 irs2336(d) 8 8.9 9.8 v bsuv+ v bs supply undervoltage positive going threshold irs23364d 10.4 11.1 11.6 irs2336(d) 7.4 8.2 9 v bsuv v bs supply undervoltage negative going threshold irs23364d 10.2 10.9 11.4 irs2336(d) 0.3 0.7 v bsuvhy v bs supply undervoltage hysteresis irs23364d 0.2 v na i lk highside floating well offset supply leakage 50 v b = v s = 600 v i qbs quiescent v bs supply current 70 120 a irs2336 2 3 i qcc quiescent v cc supply current ir2336(4)d 3 4 ma all inputs are in the off state v oh high level output voltage drop, v bias v o 0.90 1.4 v v ol low level output voltage drop, v o 0.40 0.6 v i o = 20 ma i o+ output high short circuit pulsed current 120 200 v o =0 v,v in =0 v, pw 10 s i o output low short circuit pulsed current 250 350 ma v o =15 v,v in =5 v, pw 10 s logic 0 input voltage v ih logic 1 input voltage 2.5 logic 1 input voltage v il logic 0 input voltage 0.8 na v in,clamp input voltage clamp (hin, lin, itrip and en) irs2336(d) 4.8 5.2 5.65 v i in = 100 a irs2336(d) 150 200 v in = 0 v i hin+ input bias current (ho = high) irs23364d 120 165 irs2336(d) 110 150 v in = 4 v i hin input bias current (ho = low) irs23364d 1 irs2336(d) 150 200 v in = 0 v i lin+ input bias current (lo = high) irs23364d 120 165 irs2336(d) 110 150 v in = 4 v i lin input bias current (lo = low) irs23364d 1 a v in = 0 v v rcin,th rcin positive going threshold 8 v rcin,hy rcin hysteresis 3 v na i rcin rcin input bias current 1 a v rcin = 0 v or 15 v r on,rcin rcin low on resistance 50 100 i = 1.5 ma downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 9 static electrical characteristics (continued) symbol definition min typ max units test conditions v it,th+ itrip positive going threshold 0.37 0.46 0.55 v it,th itrip negative going threshold 0.4 v it,hys itrip hysteresis 0.07 v na irs2336(d) 5 20 i itrip+ high itrip input bias current irs23364d 5 40 v in = 4 v i itrip low itrip input bias current 1 a v in = 0 v v en,th+ enable positive going threshold 2.5 v en,th enable negative going threshold 0.8 v na irs2336(d) 5 20 i en+ high enable input bias current irs23364d 120 165 v in = 4 v i en low enable input bias current 1 a v in = 0 v r on,flt fault low on resistance 50 100 i = 1.5 ma r bs internal bs diode ron (irs233 6(4)d) 200 na downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 10 dynamic electrical characteristics v cc = v b = 15 v, v s = v ss = com, t a = 25 o c, and c l = 1000 pf unless otherwise specified. symbol definition min typ max units test conditions t on turnon propagation delay 400 530 750 t off turnoff propagation delay 400 530 750 t r turnon rise time 125 190 t f turnoff fall time 50 75 t fil,in input filter time ? (hin, lin, itrip) 200 350 510 v in = 0 v & 5 v t en enable low to output shutdown propagation delay 350 460 650 v in, v en = 0 v or 5 v t filter,en enable input filter time 100 200 ns na t fltclr fault clear time rcin: r = 2 m, c = 1 nf 1.3 1.65 2 ms v in = 0 v or 5 v v itrip = 0 v t itrip itrip to output shutdown propagation delay 500 750 1200 v itrip = 5 v t bl itrip blanking time 400 t flt itrip to fault propagation delay 400 600 950 v in = 0 v or 5 v v itrip = 5 v dt deadtime 190 275 420 mdt dt matching ?? 60 v in = 0 v & 5 v without external deadtime mt delay matching time (t on , t off ) ?? 50 v in = 0 v & 5 v with external deadtime larger than dt pm pulse width distortion ??? 75 ns pw input=10 s ? the minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of t he input filter is exceeded. ?? this parameter applies to all of the channels. ple ase see the application section for more details. ??? pm is defined as pw in pw out . downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 11 functional block diagram: irs2336(d) note: irs2336 is without the integrated bootfet downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 12 functional block diagram: irs23364d downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 13 input/output pin equivalent circuit diagrams: irs2336(d) downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 14 input/output pin equivalent circuit diagrams: irs23364d downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 15 lead definitions: irs2336(d) symbol description vcc lowside supply voltage vss logic ground vb1 highside gate drive floating supply (phase 1) vb2 highside gate drive floating supply (phase 2) vb3 highside gate drive floating supply (phase 3) vs1 high voltage floating supply return (phase 1) vs2 high voltage floating supply return (phase 2) vs3 high voltage floating supply return (phase 3) hin1/n logic inputs for highside gate driver outpu ts (phase 1); input is outofphase with output hin2/n logic inputs for highside gate driver outpu ts (phase 2); input is outofphase with output hin3/n logic inputs for highside gate driver outpu ts (phase 3); input is outofphase with output lin1/n logic inputs for lowside gate driver output s (phase 1); input is outofphase with output lin2/n logic inputs for lowside gate driver output s (phase 2); input is outofphase with output lin3/n logic inputs for lowside gate driver output s (phase 3); input is outofphase with output ho1 highside driver outputs (phase 1) ho2 highside driver outputs (phase 2) ho3 highside driver outputs (phase 3) lo1 lowside driver outputs (phase 1) lo2 lowside driver outputs (phase 2) lo3 lowside driver outputs (phase 3) com lowside gate drive return fault/n indicates overcurrent, overtemperature (itrip), o r lowside undervoltage lockout has occurred. this pin has negative logic and an opendrain outpu t. the use of overcurrent and over temperature protection requires the use of external components. en logic input to shutdown functionality. logic functi ons when en is high (i.e., positive logic). no effect on fault and not latched. itrip analog input for overcurrent shutdown. when active , itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive, f ault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). rcin an external rc network input used to define the fau lt clear delay (t fltclr ) approximately equal to r*c. when rcin > 8 v, the fault pin goes back into an opendrain highimpedance state. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 16 lead definitions: irs23364d symbol description vcc lowside supply voltage vss logic ground vb1 highside gate drive floating supply (phase 1) vb2 highside gate drive floating supply (phase 2) vb3 highside gate drive floating supply (phase 3) vs1 high voltage floating supply return (phase 1) vs2 high voltage floating supply return (phase 2) vs3 high voltage floating supply return (phase 3) hin1 logic inputs for highside gate driver outputs (phase 1); input is inphase with output hin2 logic inputs for highside gate driver outputs (phase 2); input is inphase with output hin3 logic inputs for highside gate driver outputs (phase 3); input is inphase with output lin1 logic inputs for lowside gate driver outputs (phase 1); input is inphase with output lin2 logic inputs for lowside gate driver outputs (phase 2); input is inphase with output lin3 logic inputs for lowside gate driver outputs (phase 3); input is inphase with output ho1 highside driver outputs (phase 1) ho2 highside driver outputs (phase 2) ho3 highside driver outputs (phase 3) lo1 lowside driver outputs (phase 1) lo2 lowside driver outputs (phase 2) lo3 lowside driver outputs (phase 3) com lowside gate drive return fault/n indicates overcurrent, overtemperature (itrip), o r lowside undervoltage lockout has occurred. this pin has negative logic and an opendrain outpu t. the use of overcurrent and over temperature protection requires the use of external components. en logic input to shutdown functionality. logic functi ons when en is high (i.e., positive logic). no effect on fault and not latched. itrip analog input for overcurrent shutdown. when active , itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive, f ault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). rcin an external rc network input used to define the fau lt clear delay (t fltclr ) approximately equal to r*c. when rcin > 8 v, the fault pin goes back into an opendrain highimpedance state. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 17 lead assignments
1 vs1 2 ho1 3 vb1 4 vcc 5 hin1 6 hin2 7 hin3 8 n.c. 28 n.c. 27 n.c. 26 n.c. 25 lo1 24 lo2 23 lo3 22 com 21 n.c. 20 vss 19 n.c. 34 vb2 33 ho2 32 vs2 31 vb3 30 ho3 29 vs3 18 n.c. 17 rcin 16 en 15 itrip 14 n.c. 13 fault 12 n.c. 11 lin3 10 lin2 9 lin1 34 lead mlpq downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 18 application information and additional details information regarding the following topics are incl uded as subsections within this section of the data sheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shootthrough protection ? enable input ? fault reporting and programmable fault clear timer ? overcurrent protection ? overtemperature shutdown protection ? truth table: undervoltage lockout, itrip, and enab le ? advanced input filter ? shortpulse / noise rejection ? integrated bootstrap functionality ? bootstrap power supply design ? separate logic and power grounds ? tolerant to negative v s transients ? pcb layout tips ? integrated bootstrap fet limitation ? additional documentation igbt/mosfet gate drive the irs2336xd hvics are designed to drive up to six mosfet or igbt power devices. figures 1 and 2 ill ustrate several parameters associated with the gate drive f unctionality of the hvic. the output current of th e hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the highside power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between th e highside or lowside output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 19 switching and timing relationships the relationship between the input and output signa ls of the irs2336(d) and irs23364d are illustrated below in figures 3 and 4. from these figures, we can see th e definitions of several timing parameters (i.e., p w in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms (irs2336(d)) figure 4: switching time waveforms (irs23364d) the following two figures illustrate the timing rel ationships of some of the functionality of the irs2 336xd; this functionality is described in further detail later in this document. during interval a of figure 5, the hvic has receive d the command to turnon both the high and lowsid e switches at the same time; as a result, the shootthrough prote ction of the hvic has prevented this condition and both the high and lowside output are held in the off state. interval b of figures 5 and 6 shows that the signal on the itrip input pin has gone from a low to a hi gh state; as a result, all of the gate drive outputs have been dis abled (i.e., see that hox has returned to the low s tate; lox is also held low), the voltage on the rcin pin has been pul led to 0 v, and a fault is reported by the fault ou tput transitioning to the low state. once the itrip inp ut has returned to the low state, the output will r emain disabled and the fault condition reported until the voltage on t he rcin pin charges up to v rcin,th (see interval c in figure 6); the charging characteristics are dictated by the rc net work attached to the rcin pin. during intervals d and e of figure 5, we can see th at the enable (en) pin has been pulled low (as is t he case when the driver ic has received a command from the contr ol ic to shutdown); this results in the outputs (ho x and lox) being held in the low state until the enable pin is pulled high. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 20 figure 5: input/output timing diagram for the irs23 36xd family 50% 90% 50% t fltclr t itrip t flt rcin itrip hox fault v rcin,th v it,th+ interval b interval c v it,th figure 6: detailed view of b & c intervals deadtime this family of hvics features integrated deadtime p rotection circuitry. the deadtime for these ics is fixed; other ics within irs hvic portfolio feature programmable dea dtime for greater design flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both th e high and lowside power switches are held off; t his is done to ensure that the power switch being turned off has f ully turned off before the second power switch is t urned on. this minimum deadtime is automatically inserted whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 7 illustrates the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the irs2336xd is matched with respect to the high and lowside outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. figure 7 defines the two deadtime parameters (i.e., dt 1 and dt 2 ) of a specific channel; the deadtime matching para meter (mdt) associated with the irs2336xd specifies the maximum difference between dt 1 and dt 2 . the mdt parameter also applies when comparing the dt of one channel of the irs2336xd to that of another. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 21 figure 7: illustration of deadtime matched propagation delays the irs2336xd family of hvics is designed with prop agation delay matching circuitry. with this featur e, the ics response at the output to a signal at the input req uires approximately the same time duration (i.e., t on , t off ) for both the lowside channels and the highside channels; t he maximum difference is specified by the delay mat ching parameter (mt). additionally, the propagation dela y for each lowside channel is matched when compare d to the other lowside channels and the propagation delays of the highside channels are matched with each oth er; the mt specification applies as well. the propagation tur non delay (t on ) of the irs2336xd is matched to the propagation turnon delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs2336xd family has bee n designed to be compatible with 3.3 v and 5 v logic level signals. the irs2336(d) features an integrat ed 5.2 v zener clamp on the hin, lin, itrip, and en pins; the irs2 3364d does not offer this input clamp. figure 8 il lustrates an input signal to the irs2336(d) and irs23364d, its i nput threshold values, and the logic state of the i c as a result of the input signal. figure 8: hin & lin input thresholds downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 22 undervoltage lockout protection this family of ics provides undervoltage lockout pr otection on both the v cc (logic and lowside circuitry) power supply and the v bs (highside circuitry) power supply. figure 9 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disabled. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs, and the fault pin will transit ion to the low state to inform the controller of the fault conditi on. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate drive ou tputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. wit hout this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power s witch conducting current while the channel impedanc e is high; this could result in very high conduction losses within the power device and could lead to power device fai lure. figure 9: uvlo protection shootthrough protection the irs2336xd family of highvoltage ics is equippe d with shootthrough protection circuitry (also kno wn as cross conduction prevention circuitry). figure 10 shows how this protection circuitry prevents both the hig h and lowside switches from conducting at the same time. table 1 illustrates the input/output relationship of the d evices in the form of a truth table. note that the irs2336(d) has inv erting inputs (the output is outofphase with its respective input) while the irs23364d has noninverting inputs (the o utput is inphase with its respective input). downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 23 figure 10: illustration of shootthrough protection circuitry irs2336(d) irs23364d hin lin ho lo hin lin ho lo 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 table 1: input/output truth table for irs2336d and irs23364d enable input the irs2336xd family of hvics is equipped with an e nable input pin that is used to shutdown or enable the hvic. when the en pin is in the high state the hvic is ab le to operate normally (assuming no other fault con ditions). when a condition occurs that should shutdown the hvic, t he en pin should see a low logic state. the enable circuitry of the irs2336xd features an input filter; the minimum input duration is specified by t filter,en . please refer to the en pin parameters v en,th+ , v en,th , and i en for the details of its use. table 2 gives a summar y of this pins functionality and figure 11 illustrates the outputs response to a shutdown command. enable input enable input high outputs enabled * enable input low outputs disabled en hox (or lox) 90% v en,th t en table 2: enable functionality truth table (*assumes no other fault condition) figure 11: output enable timing waveform downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 24 fault reporting and programmable fault clear timer the irs2336xd family provides an integrated fault r eporting output and an adjustable fault clear timer . there are two situations that would cause the hvic to report a fa ult via the fault pin. the first is an undervoltag e condition of v cc and the second is if the itrip pin recognizes a fau lt. once the fault condition occurs, the fault pin is internally pulled to v ss and the fault clear timer is activated. the fault output stays in the low state until the fault cond ition has been removed and the fault clear timer expires; onc e the fault clear timer expires, the voltage on the fault pin will return to v cc . the length of the fault clear time period (t fltclr ) is determined by exponential charging characteris tics of the capacitor where the time constant is set by r rcin and c rcin . in figure 12 where we see that a fault condition has occurred (uvlo or itrip), rcin and fault are pulled to v ss , and once the fault has been removed, the fault cl ear timer begins. figure 13 shows that r rcin is connected between the v cc and the rcin pin, while c rcin is placed between the rcin and v ss pins. figure 12: rcin and fault pin waveforms figure 13: programming the fault clear timer the design guidelines for this network are shown in table 3. 1 nf c rcin ceramic 0.5 m to 2 m r rcin >> r on,rcin table 3: design guidelines the length of the fault clear time period can be de termined by using the formula below. c (t) = v f (1e t/rc ) t fltclr = (r rcin c rcin )ln(1v rcin,th /v cc ) downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 25 overcurrent protection the irs2336xd hvics are equipped with an itrip inpu t pin. this functionality can be used to detect ov ercurrent events in the dc bus. once the hvic detects an ov ercurrent event through the itrip pin, the outputs are shutdown, a fault is reported through the fault pin , and rcin is pulled to v ss . the level of current at which the overcurrent prot ection is initiated is determined by the resistor n etwork (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 14, and the itrip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc bus and select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the overcurrent threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc (r 1 /(r 1 +r 2 )) figure 14: programming the overcurrent protection for example, a typical value for resistor r 0 could be 50 m. the voltage of the itrip pin shou ld not be allowed to exceed 5 v; if necessary, an external voltage clamp may be used. overtemperature shutdown protection the itrip input of the irs2336xd can also be used t o detect overtemperature events in the system and initiate a shutdown of the hvic (and power switches) at that t ime. in order to use this functionality, the circui t designer will need to design the resistor network as shown in fig ure 15 and select the maximum allowable temperature . this network consists of a thermistor and two stand ard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node v x . the resistor values should be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the maximum allowable temperature is reached. the voltage of the itrip pin should not be allowed to e xceed 5 v. when using both the overcurrent protection and ov ertemperature protection with the itrip input, or ing diodes (e.g., dl4148) can be used. this network is shown in figure 16; the oring diodes have been labeled d 1 and d 2 . downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 26 figure 15: programming overtemperature protection figure 16: using overcurrent protection and over temperature protection truth table: undervoltage lockout, itrip, and enabl e table 4 provides the truth table for the irs2336xd. the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive output s have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance st ate. the second case shows that the uvlo for v bs has been tripped and that the highside gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new falling (irs2336(d)) or rising (irs23364d) transition of hi n. the third case shows the normal operation of th e hvic. the fourth case illustrates that the itrip trip thresho ld has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. in the last case, the hvic has received a command through the en input to shutdown; as a result, the gate drive outputs have been disabled. vcc vbs itrip en rcin fault lo ho uvlo v cc < v ccuv high 0 0 0 uvlo v bs 15 v < v bsuv 0 v 5 v high high impedance lin 0 normal operation 15 v 15 v 0 v 5 v high high impedance lin hin itrip fault 15 v 15 v >v itrip 5 v low 0 0 0 en command 15 v 15 v 0 v 0 v high high impedance 0 0 table 4: irs2336xd uvlo, itrip, en, rcin, & fault t ruth table advanced input filter the advanced input filter allows an improvement in the input/output pulse symmetry of the hvic and hel ps to reject noise spikes and short pulses. this input filter h as been applied to the hin, lin, and en inputs. th e working principle of the new filter is shown in figures 17 and 18. figure 17 shows a typical input filter and the asym metry of the input and output. the upper pair of w aveforms (example 1) show an input signal with a duration mu ch longer then t fil,in ; the resulting output is approximately the difference between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . figure 18 shows the advanced input filter and the s ymmetry between the input and output. the upper pa ir of waveforms (example 1) show an input signal with a d uration much longer then t fil,in ; the resulting output is approximately the same duration as the input signal . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the same du ration as the input signal. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 27 figure 17: typical input filter figure 18: advanced input filter shortpulse / noise rejection this devices input filter provides protection agai nst shortpulses (e.g., noise) on the input lines. if the duration of the input signal is less than t fil,in , the output will not change states. example 1 of figure 19 shows the input and output in the low state with positive noise spikes of duratio ns less than t fil,in ; the output does not change states. example 2 of figure 19 shows the input and output in the high st ate with negative noise spikes of durations less th an t fil,in ; the output does not change states. example 1 example 2 figure 19: noise rejecting input filters figures 20 and 21 present lab data that illustrates the characteristics of the input filters while rec eiving on and off pulses. the input filter characteristic is shown in figure 20; the left side illustrates the narrow pulse on ( short positive pulse) characteristic while the left shows the narrow puls e off (short negative pulse) characteristic. the x axis of figure 20 shows the duration of pw in , while the yaxis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the inp ut signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the symmetry improving as the du ration increases. to ensure proper operation of th e hvic, it is suggested that the input pulse width for the highs ide inputs be 500 ns. the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 21; the careful reader will note the scale o f the yaxis. the xaxis of figure 21 shows the du ration of pw in , while the yaxis shows the resulting pw out Cpw in duration. this data illustrates the performance a nd near symmetry of this input filter. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 28 time (ns) figure 20: irs2336xd input filter characteristic figure 21: difference between the input pulse and t he output pulse integrated bootstrap functionality the new irs2336xd family features integrated highv oltage bootstrap mosfets that eliminate the need of the external bootstrap diodes and resistors in many app lications. there is one bootstrap mosfet for each highside ou tput channel and it is connected between the v cc supply and its respective floating supply (i.e., v b1 , v b2 , v b3 ); see figure 22 for an illustration of this intern al connection. the integrated bootstrap mosfet is turned on only d uring the time when lo is high, and it has a limi ted source current due to r bs . the v bs voltage will be charged each cycle depending on th e ontime of lo and the value of the c bs capacitor, the drainsource (collectoremitter) dr op of the external igbt (or mosfet), and the lowsi de free wheeling diode drop. the bootstrap mosfet of each channel follows the st ate of the respective lowside output stage (i.e., the bootstrap mosfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 110% of v cc . in that case, the bootstrap mosfet is designed to remain off until v b returns below that threshold; this concept is illustrated in figure 23. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 29 v cc v b1 v b2 v b3 figure 22: internal bootstrap mosfet connection fig ure 23: bootstrap mosfet state diagram a bootstrap mosfet is suitable for most of the pwm modulation schemes and can be used either in parall el with the external bootstrap network (i.e., diode and resisto r) or as a replacement of it. the use of the integr ated bootstrap as a replacement of the external bootstrap network may have some limitations. an example of this limitati on may arise when this functionality is used in noncomplementar y pwm schemes (typically 6step modulations) and at very high pwm duty cycle. in these cases, superior performanc es can be achieved by using an external bootstrap d iode in parallel with the internal bootstrap network. bootstrap power supply design for information related to the design of the bootst rap power supply while using the integrated bootstr ap functionality of the irs2336xd family, please refer to applicatio n note 1123 (an1123) entitled bootstrap network a nalysis: focusing on the integrated bootstrap functionality. this application note is available at www.irf.com . for information related to the design of a standard bootstrap power supply (i.e., using an external di screte diode) please refer to design tip 044 (dt044) entitled using monolithic high voltage gate drivers. this design tip is available at www.irf.com . separate logic and power grounds the irs2336xd has separate logic and power ground p in (v ss and com respectively) to eliminate some of the noi se problems that can occur in power conversion applica tions. current sensing shunts are commonly used in many applications for power inverter protection (i.e., o vercurrent protection), and in the case of motor d rive applications, for motor current measurements. in these situations, i t is often beneficial to separate the logic and pow er grounds. figure 24 shows a hvic with separate v ss and com pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and o vercurrent circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the com pin is the reference point for the lowside gate drive circuitry. the output voltage used to drive the lowside gate is v lo com; the gateemitter voltage (v ge ) of the lowside switch is the output voltage of the driver minus the drop across r g,lo . downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 30 v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + v ge2 + v ge3 + itrip v x + figure 24: separate v ss and com pins tolerant to negative v s transients a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3phase inverter circuit is shown in figure 25; here we define the power switch es and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 26 and 27) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs fro m highside switch (q1) to the diode (d2) in parall el with the low side switch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 25: three phase inverter downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 31 q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 26: q1 conducting figure 27: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 28 and 2 9), and q4 igbt switches on, the current commutation occurs fr om d3 to q4. at the same instance, the voltage node , v s2 , swings from the positive dc bus voltage to the nega tive dc bus voltage. figure 28: d3 conducting figure 29: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 30 depicts one leg of t he three phase inverter; figures 31 and 32 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped togeth er in l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops asso ciated with the power switch and the parasitic elem ents of the circuit. when the highside power switch turns off , the load current momentarily flows in the lowsid e freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the com pin of the h vic) to the load and a negative voltage between v s1 and the dc bus is induced (i.e., the com pin of the hvic i s at a higher potential than the v s pin). downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 32 figure 30: parasitic elements figure 31: v s positive figure 32: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. the irs2336xd has been seen to withs tand large negative v s transient conditions on the order of 50 v for a period of 50 ns. an illustration of the irs2 336ds performance can be seen in figure 33. this experiment was conducted using various loads to create this condit ion; the curve shown in this figure illustrates the successful operation of the irs2336d under these stressful con ditions. in case of v s transients greater then 20 v for a period of time greater than 100 ns; the hvic is designed t o hold the highside outputs in the off state for 4 .5 s in order to ensure that the high and lowside power switches a re not on at the same time. figure 33: negative v s transient results for an international rectifier h vic even though the irs2336xd has been shown able to ha ndle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. the irs2336xd in the plcc44 package has had some unused pins removed in order to maximize the distance between the high vol tage and low voltage pins. please see the case outline plcc44 information in this datasheet for the detai ls. downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 33 ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 34). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, curr ent can be injected inside the gate drive loop via the igbt collectortogate parasitic capacitance. the parasi tic autoinductance of the gate loop contributes to developing a voltage across the gateemitter, thus increasing th e possibility of a self turnon effect. figure 34: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 f c eramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. v cc hin (x3) rcin en itrip v ss fault com lin (x3) lo (x3) ho (x3) v b (x3) v s (x3) c in figure 35: supply capacitor downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 34 routing and placement : power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the pha se voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the highside emitter to lowside collector distance, and 2) minimize th e lowside emitter to negative bus rail stray inductance. how ever, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes pl acing a resistor (5 or less) between the v s pin and the switch node (see figure 36), and in some cases using a cla mping diode between v ss and v s (see figure 37). see dt044 at www.irf.com for more detailed information. figure 36: v s resistor figure 37: v s clamping diode integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: ? vcc pin voltage = 0v and ? vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, as illustrated in fig.38 below, resulting in power loss and possible damage to the hvic. figure 38: current conduction path between vcc and vb pin downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 35 relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: ? in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. in this condition, back emf is generated at a motor terminal which causes high voltage bias on vs nodes resulting unwanted current flow to vcc. ? potential situations in other applications where vs /vb node voltage potential increases before the vcc voltage is available (for example due to sequen cing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.39) prevents current conduction outof vcc pin of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode sele ction is based on 25v rating or above & current cap ability aligned to icc consumption of ic 100ma should cov er most application situations. as an example, part number # ll4154 from diodes inc (25v/150ma standard diode) can be used. figure 39: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode ( ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements.

. additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these docum ents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 36 parameter temperature trends figures 4061 provide information on the experiment al performance of the irs2336xd hvic. the line plo tted in each figure is generated from actual lab data. a sm all number of individual samples were tested at thr ee temperatures (40 oc, 25 oc, and 125 oc) in order t o generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data point at eac h of the tested temperatures) that have been connec ted together to illustrate the understood temperature trend. th e individual data points on the curve were determin ed by calculating the averaged experimental value of the parameter (for a given temperature). 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) t on (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) t off (ns) exp. figure 40: t on vs. temperature figure 41: t off vs. temperature 0 150 300 450 600 50 25 0 25 50 75 100 125 temperature ( o c) dt (ns) exp. 0 300 600 900 1200 1500 50 25 0 25 50 75 100 125 temperature ( o c) t itrip (ns) exp. figure 42: dt vs. temperature figure 43: t itrip vs. temperature downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 37 0 200 400 600 800 1000 1200 50 25 0 25 50 75 100 125 temperature ( o c) t flt (ns) exp. 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) t en (ns) exp. figure 44: t flt vs. temperature figure 45: t en vs. temperature 0 20 40 60 50 25 0 25 50 75 100 125 temperature ( o c) mt (ns) exp. 0 20 40 60 50 25 0 25 50 75 100 125 temperature ( o c) mdt (ns) exp. figure 46: mt vs. temperature figure 47: mdt vs. temperature 0 20 40 60 50 25 0 25 50 75 100 125 temperature ( o c) pm (ns) exp. 0 4 8 12 16 50 25 0 25 50 75 100 125 temperature ( o c) i trip+ (a) exp. figure 48: pm vs. temperature figure 49: i itrip+ vs. temperature downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 38 0 1 2 3 4 5 50 25 0 25 50 75 100 125 temperature ( o c) i qcc (ma) exp. 0 20 40 60 80 100 120 50 25 0 25 50 75 100 125 temperature ( o c) i qbs (a) exp. figure 50: i qcc vs. temperature figure 51: i qbs vs. temperature 0.00 0.20 0.40 0.60 50 25 0 25 50 75 100 125 temperature ( o c) i o+ (a) exp. p. 0.00 0.20 0.40 0.60 50 25 0 25 50 75 100 125 temperature ( o c) i o (a) exp. figure 52: i o+ vs. temperature figure 53: i o vs. temperature 0 2 4 6 8 10 12 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv+ (v) exp. 0 2 4 6 8 10 12 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv (v) exp. figure 54: v ccuv+ vs. temperature figure 55: v ccuv vs. temperature downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 39 5 6 7 8 9 10 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv+ (v) exp. 5 6 7 8 9 10 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv (v) exp. figure 56: v bsuv+ vs. temperature figure 57: v bsuv vs. temperature 200 400 600 800 50 25 0 25 50 75 100 125 temperature ( o c) v it,th+ (mv) exp. p. 0 200 400 600 800 50 25 0 25 50 75 100 125 temperature ( o c) v it,th (mv) exp. figure 58: v it,th+ vs. temperature figure 59: v it,th vs. temperature 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) r on,rcin () exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) r on,flt () exp. figure 60: r on,rcin vs. temperature figure 61: r on,flt vs. temperature downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 40 package details: pdip28 downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 41 package details: soic28w downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 42 package details: plcc44 downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 43 case outline drawing for: mlpq7x7 downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 44 tape and reel details: soic28w carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 45 tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 46 tape and reel details: mlpq7x7 carrier tape dimension for 48mlpq7x7 metric imperial code min max min max a 11.90 12.10 0.474 0.476 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 7.15 7.35 0.281 0.289 f 7.15 7.35 0.281 0.289 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 reel dimensions for 48mlpq7x7 metric imperial code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.4 n/a 0.881 g 18.5 21.1 0.728 0.83 h 16.4 18.4 0.645 0.724 e f a c d g a b h note : controlling dimension in mm loaded tape feed direction a h f e g d b c downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 47 part marking information downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 48 ordering information standard pack base part number package type form quantity complete part number tube/bulk 52 irs2336dmpbf mlpq7x7 48l tape and reel 3000 irs2336dmtrpbf pdip28 tube/bulk 13 irs2336dpbf tube/bulk 25 irs2336dspbf soic28w tape and reel 1000 irs2336dstrpbf tube/bulk 27 irs2336djpbf irs2336d plcc44 tape and reel 500 irs2336djtrpbf pdip28 tube/bulk 13 irs2336pbf tube/bulk 25 irs2336spbf soic28w tape and reel 1000 irs2336strpbf tube/bulk 27 irs2336jpbf irs2336 plcc44 tape and reel 500 irs2336jtrpbf pdip28 tube/bulk 13 irs23364dpb f tube/bulk 25 irs23364dspbf soic28w tape and reel 1000 irs23364dstrpbf tube/bulk 27 irs23364djpbf irs23364d plcc44 tape and reel 500 IRS23364DJTRPBF downloaded from: http:///
irs2336x(d) family www.irf.com ? 2009 international rectifier 49 the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information . international rectifier assumes no responsibilit y for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is grante d by implication or otherwise under any patent or patent rights of international rectifier. the specifications mentioned in this document are subject to change without notice. this document supersedes and replaces all information pr eviously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 revision history date comment 09/17/07 original document. 01/15/08 typo correction 01/31/08 added mlpq7x7 package style 02/26/08 corrected esd & latchup classification, added note for cdm classification, added ordering information for mlpq7x7 4/24/08 added nond version (not done) 5/7/08 added nond version in ordering information (p47) 5/9/08 reviewed and updated all specifications in a ccordance with dr3 limits tables. 16/10/09 pag 17: irs2336dmpbf pin assignment changed pag 42: irs2336dmpbf package drawing changed 26/04/11 updated esd hbm downloaded from: http:///

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