1 of 7 111899 features converts full cmos ram into nonvolatile memory unconditionally write protects when v cc is out of tolerance automatically switches to battery when power-fail occurs 4 to 16 decoder provides control for up to 16 cmos rams consumes less than 100 na of battery current tests battery condition on power-up provides for redundant batteries power fail signal can be used to interrupt processor on power failure optional 5% or 10% power-fail detection optional 28-pin plcc surface mount package optional industrial temperature range of -40c to +85c pin description a, b, c, d - address inputs ce - chip enable ce0 - ce15 - chip enable outputs gnd - ground v bat1 - + battery 1 v bat2 - + battery 2 tol - power supply tolerance v cci - +5v supply v cco - ram supply pf - power fail pin assignment description the ds1212 nonvolatile controller x16 chip is a cmos circuit that solves the application problem of converting cmos rams into nonvolatile memories. incoming power is monitored for an out-of- tolerance condition. when such a condition is detected, the chip enables are inhibited to accomplish write protection and the battery is switched on to supply the rams with uninterrupted power. special circuitry uses a low-leakage cmos process that affords precise voltage detection at extremely low battery consumption. ds1212 nonvolatile controller x 16 chip www.dalsemi.com vbat1 vcco tol pf ce15 ce14 ce13 ce12 ce11 d c b a gnd vcci vbat2 ce ce0 ce1 ce2 ce3 ce4 ce5 ce6 ce7 ce8 ce9 ce10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin dip (600-mil) see mech. drawings section 28-pin plcc see mech. drawings section ce15 ce14 ce13 ce12 ce11 d c pf tol vcco vbat1 vcci vbat2 ce 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 ce0 ce1 ce2 ce3 ce4 ce5 ce6 b a gnd ce10 ce9 ce8 ce7
ds1212 2 of 7 by combining the ds1212 nonvolatile controller chip and lithium batteries, nonvolatile ram operation can be achieved for up to 16 cmos memories. operation the ds1212 performs six circuit functions required to decode and battery back up a bank of up to 16 rams. first, the 4-to-16 decoder provides selection of one of 16 rams. second, a switch is provided to direct power from the battery or v cci supply, depending on which is greater. this switch has a voltage drop of less than 0.2v. the third function the ds1212 provides is power-fail detection. it constantly monitors the v cci supply. when v cci falls below 4.75 volts or 4.5 volts, depending on the level of tolerance pin 3, a precision comparator outputs a power-fail detect signal to the decoder/chip enable logic and the pf signal is driven low. the pf signal will remain low until v cci is back in normal limits. the fourth function of write protection is accomplished by holding all chip enable outputs ( ce0 - ce15 ) to within 0.2 volts of v cci or battery supply. if ce is low at the time power fail detection occurs, the chip enable outputs are kept in their present state until ce is driven high. the delay of write protection until the current memory cycle is completed prevents corruption of data. power-fail detection occurs in the range of 4.75 volts to 4.5 volts with tolerance pin 3 grounded. if pin 3 is connected to v cco , then power- fail occurs in the range of 4.5 volts to 4.25 volts. during nominal supply conditions the chip enable outputs follow the logic of a 4-to-16 decoder, shown in figure 1. the fifth function the ds1212 performs is a battery status warning so that data loss is avoided. each time the circuit is powered up, the battery voltage is checked with a precision comparator. if the battery voltage is less than 2 volts, the second memory cycle is inhibited. battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. a subsequent write cycle can then be executed to the same memory location, altering the data. if the next read cycle fails to verify the written data, then the batteries are less than 2.0 volts and data is in danger of being corrupted. the sixth function of the ds1212 provides for battery redundancy. in many applications, data integrity is paramount. in these applications it is often desirable to use two batteries to ensure reliability. the ds1212 provides an internal isolation switch which allows the connection of two batteries during battery backup operation. the battery with the highest voltage is selected for use. if one battery should fail, the other will then assume the load. the switch to a redundant battery is transparent to circuit operation and the user. a battery status warning will only occur if both batteries are less than 2.0 volts. for single battery applications the unused battery input must be grounded.
ds1212 3 of 7 nonvolatile controller/decoder figure 1 inputs outputs ce dcba ce0 ce1 ce2 ce3 ce4 ce5 ce6 ce7 ce8 ce9 ce10 ce11 ce12 ce13 ce14 ce15 pf hxxxx hhhhhhhhhhhhhhhhh xxxxx hhhhhhhhhhhhhhhhl llllll hhhhhhhhhhhhhhhh llllhhlhhhhhhhhhhhhhhh lllhlhhlhhhhhhhhhhhhhh lllhhhhhlhhhhhhhhhhhhh llhllhhhhlhhhhhhhhhhhh llhlhhhhhhlhhhhhhhhhhh llhhlhhhhhhlhhhhhhhhhh llhhhhhhhhhhlhhhhhhhhh lhlllhhhhhhhhlhhhhhhhh lhllhhhhhhhhhhlhhhhhhh lhlhlhhhhhhhhhhlhhhhhh lhlhhhhhhhhhhhhhlhhhhh lhhllhhhhhhhhhhhhlhhhh lhhlhhhhhhhhhhhhhhlhhh lhhhlhhhhhhhhhhhhhhlhh lhhhh hhhhhhhhhhhhhhhlh h = high level l = low level x = irrelevant note: v cci input is 250 mv lower when tol pin3 = v cco .
ds1212 4 of 7 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes pin 3 = gnd supply voltage v cci 4.75 5.0 5.5 v 1 pin 3 = v cco supply voltage v cco 4.5 5.0 5.5 v 1 logic 1 input v ih 2.2 v cc +0.3 v 1 logic 0 input v il -0.3 +0.8 v 1 battery input v bat1 , v bat2 2.0 4.0 v 1, 2 (0 c to 70 c; v cci = 4.75 to 5.5v pin 3 = gnd) (0 c to 70 c; v cci = 4.5 to 5.5v, pin 3 = v cco ) dc electrical characteristics parameter symbol min typ max units notes supply current i cci 5ma3 supply current @ v cco = v cci -0.2 i cco1 80 ma 1, 4 ,10 input leakage i il -1.0 +1.0 a output leakage i lo -1.0 +1.0 a ce0 - ce15 , pf output @ 2.4v i oh -1.0 ma 5 ce0 - ce15 , pf output @ 0.4v i ol 4.0 ma 5 v cc trip point (tol=gnd) v cctp 4.50 4.62 4.74 v 1 v cc trip point (tol=v cco )v cctp 4.25 4.37 4.49 v 1 (0c to 70c; v cci < v bat ) parameter symbol min typ max units notes ce0 -ce15 output v ohl v bat -0.2 v 3, 7 battery current i bat 0.1 a 2, 3 battery backup current @ v cco = v bat1 ? 0.5v i cc2 100 a 6, 10, 11
ds1212 5 of 7 capacitance (t a = 25c) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf (0c to 70c; v cci = 4.75 to 5.5v, pin 3 = gnd) (0c to 70c; v cci = 4.5 to 5.5v, pin 3 = v cco ) ac electrical characteristics parameter symbol min typ max units notes ce propagation delay t pd 51020ns5 ce high to power-fail t pf 0ns address setup t as 20 ns 9 (0c to 70c; v cci < 4.75v, pin 3 = gnd) (0c to 70c; v cci < 4.5v, pin 3 = v cco ) parameter symbol min typ max units notes recovery at power-up t rec 2 80 125 ms v cc slew rate power-down t f 300 s v cc slew rate power-down t fb 10 s v cc slew rate power-up t r 0s ce pulse width t ce 1.5 s 7, 8 power fail to pf low t pfl 300 s
ds1212 6 of 7 timing diagram: decoder timing diagram: power-up timing diagram: power-down
ds1212 7 of 7 typical application figure 2 output load figure 3 notes: 1. all voltages referenced to ground. 2. only one battery input is required. 3. measured with v cco and ce0 - ce15 open. 4. i cc01 is the maximum average load which the ds1212 can supply to the memories. 5. measured with a load as shown in figure 3. 6. i cc02 is the maximum average load current which the ds1212 can supply to the memories in the battery backup mode. 7. chip enable outputs ce0 - ce15 can only sustain leakage current in the battery backup mode. 8. t ce max. must be met to ensure data integrity on power loss. 9. t as is only required to keep the decoder outputs glitch-free. while ce is low, the outputs ( ce0 - ce15 ) will be defined by inputs a through d with a propagation delay of t pd from an a through d input change. 10. for applications where higher currents are required, please see the battery manager chip data sheet (ds1259). 11. the ds1212 has a 5 kohm resistor in series with the battery input. as current from the battery increases over 100 a, the voltage drop will increase proportionately. the device cannot be damaged by higher currents in the battery path.
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