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june 2002 msp usb data manual slls519b designing with this device may require extensive support. before incorporating this device into a design, customers should contact ti or an authorized ti distributor. note
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 controller description 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 main features 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 usb features 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 general features 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 enhanced uart features 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 pinout information 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 detailed controller description 3?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 operating modes 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 usb interface configuration 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 external memory case 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 host download case 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 usb data movement 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 serial port setup 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 serial port data modes 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 rs-232 data mode 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 rs-485 data mode 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 irda data mode 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 mcu memory map (internal operation) 4?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 miscellaneous registers 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 roms: rom shadow configuration register (addr:ff90) 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 boot operation (mcu firmware loading) 4 ? 2 . . . . . . . . . . . . . . 4.1.3 wdcsr: watchdog timer, control, and status register (addr:ff93) 4 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 buffers + i/o ram map 4 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 endpoint descriptor block (edb ? 1 to edb ? 3) 4 ? 5 . . . . . . . . . . . . . . . . . . . 4.3.1 oepcnf_n: output endpoint configuration (n = 1 to 3) (addr:ff08, ff10, ff18) 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 oepbbax_n: output endpoint x-buffer base address (n = 1 to 3) 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 oepbctx_n: output endpoint x byte count (n = 1 to 3) 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 oepbbay_n: output endpoint y-buffer base address (n = 1 to 3) 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 oepbcty_n: output endpoint y-byte count (n = 1 to 3) 4 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 oepsizxy_n: output endpoint x-/y-buffer size (n =1 to 3) 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 4.3.7 iepcnf_n: input endpoint configuration (n = 1 to 3) (addr:ff48, ff50, ff58) 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 iepbbax_n: input endpoint x-buffer base address (n = 1 to 3) 4 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 iepbctx_n: input endpoint x-byte count (n = 1 to 3) 4 ? 9 . . . 4.3.10 iepbbay_n: input endpoint y-buffer base address (n = 1 to 3) 4 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.11 iepbcty_n: input endpoint y-byte count (n = 1 to 3) 4 ? 9 . . . 4.3.12 iepsizxy_n: output endpoint x-/y-buffer size (n = 1 to 3) 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 endpoint-0 descriptor registers 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 iepcnfg_0: input endpoint-0 configuration register (addr:ff80) 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 iepbcnt_0: input endpoint-0 byte count register (addr:ff81) 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 oepcnfg_0: output endpoint-0 configuration register (addr:ff82) 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 oepbcnt_0: output endpoint-0 byte count register (addr:ff83) 4 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 usb 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 usb registers 5 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 funadr: function address register (addr:ffff) 5 ? 1 . . . . . . 5.1.2 usbsta: usb status register (addr:fffe) 5 ? 1 . . . . . . . . . . . 5.1.3 usbmsk: usb interrupt mask register (addr:fffd) 5 ? 2 . . . . 5.1.4 usbctl: usb control register (addr:fffc) 5 ? 3 . . . . . . . . . . . 5.1.5 modecnfg: mode configuration register (addr:fffb) 5 ? 4 5.1.6 vendor id/product id 5 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.7 sernum7: device serial number register (byte 7) (addr:ffef) 5 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.8 sernum6: device serial number register (byte 6) (addr:ffee) 5 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.9 sernum5: device serial number register (byte 5) (addr:ffed) 5 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.10 sernum4: device serial number register (byte 4) (addr:ffec) 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.11 sernum3: device serial number register (byte 3) (addr:ffeb) 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.12 sernum2: device serial number register (byte 2) (addr:ffea) 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.13 sernum1: device serial number register (byte 1) (addr:ffe9) 5 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.14 sernum0: device serial number register (byte 0) (addr:ffe8) 5 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.15 function reset and power-up reset interconnect 5 ? 7 . . . . . . 5.1.16 pullup resistor connect/disconnect 5 ? 8 . . . . . . . . . . . . . . . . . .
v 6 dma controller 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 dma controller registers 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 dmacdr1: dma channel definition register (uart transmit channel) (addr:ffe0) 6 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 dmacsr1: dma control and status register (uart transmit channel) (addr:ffe1) 6 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 dmacdr3: dma channel definition register (uart receive channel) (addr:ffe4) 6 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.4 dmacsr3: dma control and status register (uart receive channel) (addr:ffe5) 6 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 bulk data i/o using the edb 6 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 in transaction (TUSB3410 to host) 6 ? 5 . . . . . . . . . . . . . . . . . . . 6.2.2 out transaction (host to TUSB3410) 6 ? 6 . . . . . . . . . . . . . . . . . 7 uart 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 uart registers 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 rdr: receiver data register (addr:ffa0) 7 ? 1 . . . . . . . . . . . . . 7.1.2 tdr: transmitter data register (addr:ffa1) 7 ? 1 . . . . . . . . . . . 7.1.3 lcr: line control register (addr:ffa2) 7 ? 2 . . . . . . . . . . . . . . . 7.1.4 fcrl: uart flow control register (addr:ffa3) 7 ? 3 . . . . . . . . 7.1.5 transmitter flow control 7 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6 mcr: modem-control register (addr:ffa4) 7 ? 5 . . . . . . . . . . . . 7.1.7 lsr: line-status register (addr:ffa5) 7 ? 6 . . . . . . . . . . . . . . . . 7.1.8 msr: modem-status register (addr:ffa6) 7 ? 7 . . . . . . . . . . . . 7.1.9 dll: divisor register low byte (addr:ffa7) 7 ? 8 . . . . . . . . . . . 7.1.10 dlh: divisor register high byte (addr:ffa8) 7 ? 8 . . . . . . . . . . . 7.1.11 baud-rate calculation 7 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.12 xon: xon register (addr:ffa9) 7 ? 9 . . . . . . . . . . . . . . . . . . . . . . 7.1.13 xoff: xoff register (addr:ffaa) 7 ? 9 . . . . . . . . . . . . . . . . . . . . . 7.1.14 mask: uart interrupt-mask register (addr:ffab) 7 ? 10 . . . . . 7.2 uart data transfer 7 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 receiver data flow 7 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 hardware flow control 7 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 auto rts (receiver control) 7 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 auto cts (transmitter control) 7 ? 11 . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 xon/xoff receiver flow control 7 ? 12 . . . . . . . . . . . . . . . . . . . . . . . 7.2.6 xon/xoff transmit flow control 7 ? 12 . . . . . . . . . . . . . . . . . . . . . . . 8 expanded gpio port 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 input/output and control registers 8 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 pur_3: gpio pullup register for port 3 (addr:ff9e) 8 ? 1 . . . 9 interrupts 9 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 8052 interrupt and status registers 9 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 8052 standard interrupt enable (sie) register 9 ? 1 . . . . . . . . . 9.1.2 additional interrupt sources 9 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 vecint: vector interrupt register (addr:ff92) 9 ? 2 . . . . . . . . . 9.1.4 logical interrupt connection diagram (internal/external) 9 ? 3 .
vi 10 i2c-port 10 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 i2c registers 10 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 i2csta: i2c status and control register (addr:fff0) 10 ? 1 . . . 10.1.2 i2cadr: i2c address register (addr:fff3) 10 ? 2 . . . . . . . . . . . . 10.1.3 i2cdai: i2c data-input register (addr:fff2) 10 ? 2 . . . . . . . . . . 10.1.4 i2cdao: i2c data-output register (addr:fff1) 10 ? 2 . . . . . . . . 10.2 random-read operation 10 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 current-address read operation 10 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 sequential-read operation 10 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 byte-write operation 10 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 page-write operation 10 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TUSB3410 bootcode flow 11 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 introduction 11 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 bootcode programming flow 11 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 default bootcode settings 11 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 device descriptor 11 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 configuration descriptor 11 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 interface descriptor 11 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 endpoint descriptor 11 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 string descriptor 11 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 external device header format 11 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 product signature 11 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 descriptor block 11 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2.1 descriptor prefix 11 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2.2 descriptor content 11 ? 7 . . . . . . . . . . . . . . . . . . . . . . 11.5 checksum in descriptor block 11 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 header examples 11 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.1 TUSB3410 bootcode supported descriptor block 11 ? 7 . . . . . 11.6.2 usb descriptor header 11 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.3 autoexec binary firmware 11 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 host driver downloading header format 11 ? 10 . . . . . . . . . . . . . . . . . . . . . 11.8 built-in vendor specific usb requests 11 ? 11 . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 reboot 11 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.2 force execute firmware 11 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.3 external memory read 11 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.4 external memory write 11 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.5 i 2 c memory read 11 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.6 i 2 c memory write 11 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.7 internal rom memory read 11 ? 12 . . . . . . . . . . . . . . . . . . . . . . . 11.9 bootcode programming consideration 11 ? 13 . . . . . . . . . . . . . . . . . . . . . . . 11.9.1 usb requests 11 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9.2 hardware reset introduced by firmware 11 ? 16 . . . . . . . . . . . . 11.10 file listings 11 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 electrical specifications 12 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii 12.1 absolute maximum ratings 12 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 commercial operating condition (3.3 v) 12 ? 1 . . . . . . . . . . . . . . . . . . . . . . . 12.3 electrical characteristics ta = 255c, vcc = 3.3 v +5%, vss = 0 v 12 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 application notes 13 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 crystal selection 13 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 external circuit required for reliable bus powered suspend operation 13 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 mechanical 14 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii list of illustrations figure title page 1 ? 1 controller block diagram 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ? 2 usb-to-serial (single channel) controller 1 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 rs-232 and ir mode select 3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 usb-to-serial implementation (rs-232) 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 rs-485 bus implementation 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 mcu memory map 4 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 1 reset diagram 5 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ? 2 pullup resistor connect/disconnect circuit 5 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 transaction time-out diagram 6 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 1 msr and mcr registers in loop-back mode 7 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 2 receiver/transmitter data flow 7 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 3 auto flow control interconnect 7 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ? 1 internal vector interrupt 9 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 1 control read transfer 11 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 2 control write transfer without data stage 11 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . 13 ? 1 crystal selection 13 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ? 2 external circuit 13 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix list of tables table title page 2 ? 1 terminal functions 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 rom/ram size definition table 4 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 xdata space 4 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 memory mapped registers summary 4 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 edb memory locations 4 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 5 edb entries in ram 4 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 6 input/output edb-0 registers 4 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 dma controller registers 6 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 dma out-termination condition 6 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 dma in-termination condition 6 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 1 uart registers summary 7 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 2 transmitter flow-control modes 7 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 3 receiver flow-control possibilities 7 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 4 dll/dlh values and resulted baud rates 7 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ? 1 8052 interrupt location map 9 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ? 2 vector interrupt values 9 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 1 device descriptor 11 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 2 configuration descriptor 11 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 3 interface descriptor 11 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 4 output endpoint1 descriptor 11 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 5 string descriptor 11 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 6 usb descriptors header 11 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 7 autoexec binary firmware 11 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 8 host driver downloading format 11 ? 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ? 9 bootcode response to control read transfer 11 ? 14 . . . . . . . . . . . . . . . . . . . . . . 11 ? 10 bootcode response to control write without data stage 11 ? 14 . . . . . . . . . . . 11 ? 11 vector interrupt values and sources 11 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
1 ? 1 1 introduction 1.1 controller description the TUSB3410 provides bridging between a usb port and an enhanced uart serial port. the TUSB3410 contains all the necessary logic to communicate with the host computer using the usb bus. it contains an 8052 microcontroller unit (mcu) with 16k bytes of ram that can be loaded from the host or from external on-board memory via an i 2 c bus. it also contains 10k bytes of rom that allow the mcu to configure the usb port at boot time. the rom code also contains an i 2 c boot loader. all the device functions such as the usb command decoding, uart setup, and error reporting are managed by the internal mcu firmware under the auspices of the pc host. the TUSB3410 can be used to build an interface between a legacy serial peripheral device and a pc with usb ports, such as a legacy-free pc. once configured, data flows from the host to the TUSB3410 via usb out commands and then out from the TUSB3410 on the sout line. conversely, data flows into the TUSB3410 on the sin line and then into the host via usb in commands. host (pc or otg drd) usb out in TUSB3410 sout sin legacy serial peripheral figure 1 ? 1. data flow
1 ? 2 8052 core clock oscillator 12 mhz pll and dividers 10k 8 rom 8 8 2 16-bit timers 16k 8 ram 8 8 4 port 3 2k 8 sram 8 8 i 2 c controller 8 uart ? 1 cpu-i/f susp./res. 8 ubm usb buffer manager 8 8 usb sie usb txr tdm control logic p3.(4, 3,1,0) i 2 c bus dp, dm 8 dma-1 dma-3 rts cts dtr dsr m u x ir encoder sout/ir_so m u x ir encoder sin/ir_sin 24 mhz sin sout figure 1 ? 2. usb-to-serial (single channel) controller block diagram
2 ? 1 2 main features 2.1 usb features ? fully compliant with usb 2.0 full speed specifications ? supports 12-mbps usb data rate (full speed) ? supports usb suspend, resume, and remote wakeup operations ? supports two power source modes: ? bus-powered mode ? self-powered mode ? can support a total of 3-input and 3-output (interrupt, bulk) endpoints 2.2 general features ? integrated 8052 microcontroller with ? 256 8 ram for internal data ? 10k 8 rom (with usb and i 2 c boot loader) ? 16k 8 ram for code space loadable from host or i 2 c port ? 2k 8 shared ram used for data buffers and endpoint descriptor blocks (edb) ? four gpio pins from 8052 port 3 ? master i 2 c controller for eeprom device access ? mcu operates at 24 mhz providing 2 mips operation ? 128-ms watchdog timer ? built-in two-channel dma controller for usb/uart bulk i/o ? operates from a 12-mhz crystal ? supports usb suspend and resume ? supports remote wake-up ? available in 32-pin lqfp ? 3.3-v operation with 1.8-v core operating voltage provided by on-chip 1.8-v voltage regulator 2.3 enhanced uart features ? software/hardware flow control: ? programmable xon/xoff characters ? programmable auto-rts /dtr and auto-cts /dsr ? automatic rs485-bus transceiver control, with and without echo ? selectable irda mode for up to 115.2 kbps transfer ? software selectable baud rate from 50 to 921.6 k baud ? programmable serial-interface characteristics ? 5-, 6-, 7-, or 8-bit characters ? even, odd, or no parity-bit generation and detection ? 1-, 1.5-, or 2-stop bit generation ? line break generation and detection
2 ? 2 ? internal test and loop-back capabilities ? modem-control functions (cts , rts , dsr , dtr , ri , and dcd ) ? internal diagnostics capability ? loopback control for communications link-fault isolation ? break, parity, overrun, framing-error simulation 2.4 pinout information vf package (top view) 23 22 21 20 19 12 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 ri /cp dcd dsr cts wakeup scl sda reset vcc x2 x1/clk1 gnd p3.4 p3.3 p3.1 p3.0 24 18 3 4 5 6 7 8 17 test1 test0 clkout dtr rts sout/ir_sout gnd sin/ir_sin vregen suspend vcc vdd18 pur dp dm gnd
2 ? 3 table 2 ? 1. terminal functions terminal i/o description name no. i/o description clkout 22 o clock output (controlled by clkouten and clkslct in modecnfg register (see section 5.1.5 and note 1) cts 13 i uart: clear to send (see note 4) dcd 15 i uart: data carrier detect (see note 4) dm 7 i/o upstream usb port differential data minus dp 6 i/o upstream usb port differential data plus dsr 14 i uart: data set ready (see note 4) dtr 21 o uart: data terminal ready (see note 1) gnd 8, 18, 28 gnd digital ground p3.0 32 i/o port-3.0 (see notes 3, 4, 5, and 8) p3.1 31 i/o port-3.1 (see notes 3, 4, 5, and 8) p3.3 30 i/o port-3.3 (see notes 3, 4, 5, and 8) p3.4 29 i/o port-3.4 (see notes 3, 4, 5, and 8) pur 5 o pull-up resistor connection (see note 2) reset 9 i controller master reset signal (see note 4) ri /cp 16 i uart: ring indicator (see note 4) rts 20 o uart: request to send (see note 1) scl 11 o master i 2 c controller: clock signal (see note 1) sda 10 i/o master i 2 c controller: data signal (see notes 1 and 5) sin/ir_sin 17 i uart: serial input data / ir serial data input (see note 6) sout/ir_sout 19 o uart: serial output data / ir serial data output (see note 7) suspend 2 o suspend condition signal (see note 3) test0 23 i test input (for factory test only) (see note 5) test1 24 i test input (for factory test only) (see note 5) vcc 3, 25 pwr 3.3 v vdd18 4 pwr 1.8-v supply. an internal voltage regulator generates this supply voltage when terminal vregen is asserted. when vregen is deasserted, 1.8 v must be supplied externally. vregen 1 i this active-low terminal is used to enable the 3.3-v to 1.8-v voltage regulator in the core. wakeup 12 i remote wake-up request pin. when low, wakes up system (see note 5) x1/clki 27 i 12-mhz crystal input or clock input x2 26 o 12-mhz crystal output notes: 1. 3-state cmos output ( 4-ma drive/sink) 2. 3-state cmos output ( 8-ma drive/sink) 3. 3-state cmos output ( 12-ma drive/sink) 4. ttl-compatible, hysteresis input 5. ttl-compatible, hysteresis input, with internal 100- a active pullup 6. ttl-compatible input without hysteresis, with internal 100- a active pullup 7. normal or ir mode: 3-state cmos output ( 4-ma drive/sink) 8. the mcu treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is tristated.
2 ? 4
3 ? 1 3 detailed controller description 3.1 operating modes the TUSB3410 controls its usb interface in response to usb commands, and this action remains the same independent of the serial port mode selected. on the other hand, the serial port can be set up in three modes. as with any interface device, data movement is the TUSB3410 ? s main function, but typically the initial configuration and error handling consume most of the support code. the following sections describe the various modes the device can be used in and the means of setting up the device. 3.2 usb interface configuration the TUSB3410 contains onboard rom microcode, which enables the mcu to enumerate the device as a usb peripheral. the rom microcode can also load application code into internal ram from either external memory via the i 2 c bus or from the host via the usb. 3.2.1 external memory case after reset, the TUSB3410 is disconnected from the usb because the pullup resistor cont bit is cleared. the TUSB3410 checks the i 2 c port for the existence of valid code, if it finds valid code, it uploads the code from the external memory device into the ram program space. once loaded, the TUSB3410 connects to the usb by setting the cont bit and enumeration and configuration are performed. this is the most likely use of the device. 3.2.2 host download case if the valid code is not found at the i 2 c port, the TUSB3410 connects to the usb by setting the cont bit, and then an enumeration and default configuration are performed. the host can then download additional microcode into ram to tailor the application. then, the mcu causes a disconnect and reconnect by using the pullup resistor cont bit in the usbctl register, which causes the TUSB3410 to be re-enumerated with a new configuration. 3.3 usb data movement from the usb perspective, the TUSB3410 looks like a usb peripheral device. it uses endpoint 0 as its control endpoint, as do all usb peripherals. it also configures up to three input and three output endpoints, although most applications use one bulk input endpoint for data in, one bulk output endpoint for data out, and one interrupt endpoint for status updates. the usb configuration likely remains the same regardless of the serial port configuration. most data is moved from the usb side to the uart side and vice versa using on-chip dma transfers. some special cases may use programmed io under control of the mcu. 3.4 serial port setup the serial port requires a few control registers to be written to configure its operation. this configuration likely remains the same regardless of the data mode used. these registers include the line control register that controls the serial word format and the divisor registers that control the baud rate. these registers are usually controlled by the host application. 3.5 serial port data modes the serial port can be configured in three different, although similar, data modes. similar to the usb mode, once configured for a specific application, it is unlikely that the mode would be changed. the different modes affect the timing of the serial input and output or the use of the control signals. however, the basic serial-to-parallel conversion
3 ? 2 of the receiver and parallel-to-serial conversion of the transmitter remain the same in all modes. some features are available in all modes, but are only applicable in certain modes. for instance, software flow control via xoff/xon characters can be used in all modes, but would usually only be used in rs-232 or irda mode because the rs-485 mode is half-duplex communication. similarly, hardware flow control via rts /cts (or dtr /dsr ) handshaking is available in rs-232 or irda mode. however, this would probably be used only in rs-232 mode, since in irda mode only the sin and sout paths are optically coupled. 3.5.1 rs-232 data mode the default mode is called the rs-232 mode, and is usually used for full duplex communication on sout and sin. in this mode, the modem control outputs (rts and dtr ) are used to communicate to a modem or as general outputs. the modem control inputs (cts , dsr , dcd , and ri ) are used for modem communication or as general inputs. alternatively, rts and cts (or dtr and dsr ) can be used to throttle the data flow on sout and sin to prevent receive fifo overruns. finally, software flow control via xoff/xon characters can be used for the same purpose. this mode represents the most general-purpose applications, and the other modes are subsets of this mode. 3.5.2 rs-485 data mode the rs-485 mode is very similar to the rs-232 mode in that the sout and sin formats remain the same. since rs-485 is a bus architecture, it is inherently a single duplex communication system. the TUSB3410 in rs-485 mode controls the rts and dtr signals such that either can be used to enable an rs-485 driver or rs-485 receiver. when in rs-485 mode, the enable signals for transmitting are automatically asserted whenever the dma is set up for outbound data. the receiver can be left enabled while the driver is enabled to allow an echo if desired, but when receive data is expected, the driver must be disabled. note that this precludes use of hardware flow control, since this is a half duplex operation, it would not be effective anyhow. software flow control is supported, but may be of limited value. the rs-485 mode is enabled by setting the 485e bit in the fcrl register, and a receiver enable (rcve) bit in the mcr allows the receiver to eavesdrop while in 485 mode. 3.5.3 irda data mode the irda mode encodes sout and decodes sin in the manner prescribed by the irda standard, up to 115.2 kbps. connection to an external irda transceiver is required. communications is usually full duplex. generally in an irda system only the sout and sin paths are connected, so hardware flow control is usually not an option. software flow control is supported. the irda mode is enabled by setting the iren bit in the usb control register. the ir encoder and decoder circuitry work with the uart to change the serial bit stream into a series of pulses and back again. for every zero bit in the outbound serial stream, the encoder sends a low-to-high-to-low pulse with the duration of 3/16 of a bit frame at the middle of the bit time. for every one bit in the serial stream, the output remains low for the entire bit time. the decoding process consists of receiving the signal from the irda receiver and converting it to a series of zeroes and ones. as the converse to the encoder, the decoder converts a pulse to a zero bit and the lack of a pulse to a one bit.
3 ? 3 from uart m u x ir encoder sout/ir_sou t 1 0 ir_tx sout uart baudout clock iren m u x 1 0 softsw txcntl m u x 1 0 clkout pin clkouten 3.556 mhz m u x 1 0 clkslct to uart receiver ir decoder ir_rx sin/ir_sin pin 3.3 v sout sin figure 3 ? 1. rs-232 and ir mode select
3 ? 4 4 7 1 6 8 3 2 transceivers dtr rts dcd dsr cts sout sin p3.0 p3.1 p3.3 serial port gpio pins for other onboard control function TUSB3410 12 mhz usb-0 db9 connector ri p3.4 figure 3 ? 2. usb-to-serial implementation (rs-232) 12 mhz usb-0 rs-485 transceiver rts dtr sout sin TUSB3410 rs-485 bus 2-bits time 1-bit max receiver is disabled if rcve = 0 sout dtr rts figure 3 ? 3. rs-485 bus implementation
4 ? 1 4 mcu memory map (internal operation) figure 4 ? 1 illustrates the mcu memory map under boot and normal operation. for more information regarding the integrated 8052, see the tusbxxxx microcontroller reference guide (sllu044). note: the internal 256 bytes of ram are not shown, since they are assumed to be in the standard 8052 location (0000 to 00ff). the shaded areas represent the internal rom/ram. when sdw bit = 0 (boot mode): the 10k rom is mapped to address (0x0000 ? 0x27ff) and is duplicated in location (0x8000 ? 0xa7ff) in code space. the internal 16k ram is mapped to address range (0x0000 ? 0x3fff) in data space. buffers, mmr, and i/o are mapped to address range (0xf800 ? 0xffff) in data space. when sdw bit = 1 (normal mode): the 10k rom is mapped to (0x8000 ? 0xa7ff) in code space. the internal 166k ram is mapped to address range (0x0000 ? 0x3ffff) in code space. buffers, mmr, and i/o are mapped to address range (0xf800 ? 0xffff) in data space. normal mode (sdw = 1) 0000 code xdata 16k code ram read only 2k data mmr 10k boot rom boot mode (sdw = 0) code xdata 10k boot rom 2k data mmr 10k boot rom (16k) read/write 27ff 3fff 8000 a7ff f800 ff7f ff80 ffff figure 4 ? 1. mcu memory map
4 ? 2 4.1 miscellaneous registers 4.1.1 roms: rom shadow configuration register (addr:ff90) this register is used by the mcu to switch from boot mode to normal operation mode (boot mode is set on power-on reset only). in addition, this register provides the device revision number and the rom/ram configuration. 765 4 32 1 0 roa s1 s0 r3 r2 r1 r0 sdw r/o r/o r/o r/o r/o r/o r/o r/w bit name reset function 0 sdw 0 this bit enables/disables boot rom. (shadow the rom). sdw = 0 when clear, the mcu executes from the 10k boot-rom space. the boot rom appears in two locations: 0000 and 8000h. the 16k ram is mapped to xdata space; therefore, read/write operation is possible. this bit is set by the mcu after the ram load is completed. mcu cannot clear this bit; it is cleared on power-up reset or watchdog time-out reset. sdw = 1 when set by the mcu, the 10k boot-rom maps to location 8000h, and the 16k ram is mapped to code space, starting at location 0000h. at this point, the mcu executes from ram, and the write operation is disabled (no write operation is possible in code space). 4 ? 1 r[3:0] no effect these bits reflect the device revision number. 6 ? 5 s[1:0] no effect code space size. these bits define the rom or ram code-space size (roa bit defines rom or ram). these bits are permanently set and are not affected by reset (see table 4 ? 1). 00 = 4k bytes code space size 01 = 8k bytes code space size 10 = 16k bytes code space size 11 = 32k bytes code space size 7 roa no effect rom or ram version. this bit indicates whether the code space is ram or rom based. this bit is permanently set and is not affected by reset (see table 4 ? 1). roa = 0 code space is rom roa = 1 code space is ram table 4 ? 1. rom/ram size definition table roms register boot rom ram code rom code roa s1 s0 boot rom ram code rom code 0 0 0 none none 4k 0 0 1 none none 8k 0 1 0 none none 16k (reserved) 1 1 1 none none 32k (reserved) 1 0 0 10k 4k none 1 0 1 10k 8k none 1 1 0 10k 16k none 1 1 1 10k 32k (reserved) none 4.1.2 boot operation (mcu firmware loading) since the code space is in ram (with the exception of the boot rom), the TUSB3410 firmware must be loaded from an external source. two sources are available for booting: one from an external serial e 2 prom connected to the i 2 c bus and the other from the host via the usb. on device reset, the sdw bit (in roms register) and cont bit (in usbctl: usb control register) are cleared. this configures the memory space to boot mode (see memory map) and keeps the device disconnected from the host. the first instruction is fetched from location 0000h (which is in the 10k rom). the 16k ram is mapped to xdata space (location 0000h). the mcu executes a read from an external e 2 prom and tests whether it contains the code (by testing for boot signature). if it contains the code, the mcu reads from e 2 prom and writes to the 16k ram in xdata space. if it does not contain the code, the mcu proceeds to boot from the usb.
4 ? 3 once the code is loaded, the mcu sets sdw = 1. this switches the memory map to normal mode; i.e. the 16k ram is mapped to code space, and the mcu starts executing from location 0000h. once the switch is done, the mcu sets cont = 1 (in the usbctl register). this connects the device to the usb and results in normal usb device enumeration. 4.1.3 wdcsr: watchdog timer, control, and status register (addr:ff93) a watchdog timer (wdt) with 1-ms clock is provided. if this register is not accessed for a period of 128 ms, the wdt counter resets the mcu. (see figure 5 ? 1). the watchdog timer is enabled by default and can be disabled by writing a pattern of 101010 into the wdd[5:0] bits. 765 4 32 1 0 roa s1 s0 r3 r2 r1 r0 sdw r/w r/w r/w r/w r/w r/w r/w w/o bit name reset function 0 wdt 0 mcu must write a 1 to this bit to prevent the wdt from resetting the mcu. if mcu does not write a 1 in a period of 128 ms, the wdt resets the device. writing a 0 has no effect on the wdt. (wdt is a 7-bit counter using a 1-ms clk). this bit is read as 0. 5 ? 1 wdd[5:1] 00000 these bits are used to disable the watchdog timer. for the timer to be disabled these bits must be set to 10101 and wdd[0] must also be set to 0. if any other pattern is present, the watchdog timer is in operation. 6 wdr 0 watchdog reset indication bit. this bit indicates if the reset occurred due to power-on reset or watchdog timer reset. wdr = 0 a power-up reset occurred wdr = 1 a usb reset or watchdog time-out reset occurred. to clear this bit, the mcu must write a 1. writing a 0 has no effect. 7 wdd[0] 1 this bit is one of the disable bits for the watchdog timer. this bit must be cleared in order for the watchdog timer to be disabled. 4.2 buffers + i/o ram map the address range from f800 to ffff (2k bytes) is reserved for data buffers, setup packet, endpoint descriptors block (edb), and all i/o. there are 128 locations reserved for mmr (memory mapped registers). table 4 ? 2 represents the xdata space allocation and access restriction for the dma, ubm, and mcu. table 4 ? 2. xdata space description address range ubm access dma access mcu access internal mmrs (memory mapped registers) ffff ff80 no (only edb-0) no (only data reg. and edb-0) yes edb (endpoint descriptors block) ff7f ff08 only for edb update only for edb update yes setup packet ff07 ff00 yes no yes input endpoint-0 buffer feff fef8 yes yes yes output endpoint-0 buffer fef7 fef0 yes yes yes data buffers feef f800 yes yes yes
4 ? 4 table 4 ? 3. memory mapped registers summary (xdata range = ff80 ffff) address register description ffff funadr function address register fffe usbsta usb status register fffd usbmsk usb interrupt mask register fffc usbctl usb control register fffb modecnfg mode configuration register fffa devvidh device custom vid high byte register fff9 devvidl device custom vid low byte register fff8 devpidh device custom pid high byte register fff7 devpidl device custom pid low byte register fff6 devrevh device custom revision number high byte register fff5 devrevl device custom revision number low byte register reserved fff3 i2cadr i 2 c-port address register fff2 i2cdati i 2 c-port data input register fff1 i2cdato i 2 c-port data output register fff0 i2csta i 2 c-port status register ffef sernum7 serial number byte 7 register ffee sernum6 serial number byte 6 register ffed sernum5 serial umber byte 5 register ffec sernum4 serial number byte 4 register ffeb sernum3 serial number byte 3 register ffea sernum2 serial number byte 2 register ffe9 sernum1 serial number byte 1 register ffe8 sernum0 serial number byte 0 register reserved ffe5 dmacsr3 dma ? 3: control and status register ffe4 dmacdr3 dma ? 3: channel definition register reserved ffe1 dmacsr1 dma ? 1: control and status register ffe0 dmacdr1 dma ? 1: channel definition register reserved ffab mask uart: interrupt mask register ffaa xoff uart: xoff register ffa9 xon uart: xon register ffa8 dlh uart: divisor high-byte register ffa7 dll uart: divisor low-byte register ffa6 msr uart: modem status register ffa5 lsr uart: line status register ffa4 mcr uart: modem control register ffa3 fcrl uart: flow control register ffa2 lcr uart: line control registers ffa1 tdr uart: transmitter data registers ffa0 rdr uart: receiver data registers ff9e pur_3 gpio: pullup register for port 3
4 ? 5 table 4 ? 3. memory mapped registers summary (xdata range = ff80 ffff) (continued) address register description ff93 reserved wdcsr watchdog timer control and status register ff92 vecint vector interrupt register reserved ff90 roms rom shadow configuration register reserved ff83 oepbcnt_0 output endpoint_0: byte count register ff82 oepcnfg_0 output endpoint_0: configuration register ff81 iepbcnt_0 input endpoint_0: byte count register ff80 iepcnfg_0 input endpoint_0: configuration register table 4 ? 4. edb memory locations address register description reserved ff58 iepcnf_3 input endpoint_3: configuration ff50 iepcnf_2 input endpoint_2: configuration ff48 iepcnf_1 input endpoint_1: configuration ff47 reserved ff20 ff18 oepcnf_3 output endpoint_3: configuration ff10 oepcnf_2 output endpoint_2: configuration ff08 oepcnf_1 output endpoint_1: configuration ff07 (8 bytes) setup packet block ff00 feff (8 bytes) input endpoint-0 buffer fef8 fef7 (8 bytes) output endpoint-0 buffer fef0 feef topbuff top of buffer space buffer space 4.3 endpoint descriptor block (edb ? 1 to edb ? 3) data transfers between the usb, the mcu, and external devices that are defined by an endpoint descriptor block (edb). three input- and three output-edbs are provided. with the exception of edb ? 0 (i/o endpoint ? 0), all edbs are located in sram as per table 4 ? 3. each edb contains information describing the x- and y-buffers. in addition, each edb provides general status information. table 4 ? 5 illustrates the edb entries for edb ? 1 to edb ? 3. edb ? 0 registers are described separately.
4 ? 6 table 4 ? 5. edb entries in ram (n = 1 to 3) offset entry name description 07 epsizxy_n i/o endpoint_n: x/y-buffer size 06 epbcty_n i/o endpoint_n: y-byte count 05 epbbay_n i/o endpoint_n: y-buffer base address 04 spare not used 03 spare not used 02 epbctx_n i/o endpoint_n: x-byte count 01 epbbax_n i/o endpoint_n: x-buffer base address 00 epcnf_n i/o endpoint_n: configuration 4.3.1 oepcnf_n: output endpoint configuration (n = 1 to 3) (addr:ff08, ff10, ff18) 765 4 32 1 0 ubme iso=0 togle dbuf stall usbie rsv rsv r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 1 ? 0 rsv x reserved = 0 2 usbie x usb interrupt enable on transaction completion. set/cleared by the mcu usbie = 0 no interrupt usbie = 1 interrupt on transaction completion 3 stall 0 usb stall condition indication. set/cleared by the mcu stall = 0 stall = 1 no stall usb stall condition. if set by the mcu, a stall handshake is initiated and the bit is cleared by the mcu. 4 dbuf x double-buffer enable. set/cleared by the mcu dbuf = 0 primary buffer only (x-buffer only) dbuf = 1 toggle bit selects buffer 5 togle x usb toggle bit. this bit reflects the toggle sequence bit of data0, data1 6 iso x iso = 0 nonisochronous transfer. this bit must be cleared by the mcu since only nonisochronous transfer is supported 7 ubme x ubm enable/disable bit. set/cleared by the mcu ubme = 0 ubm cannot use this endpoint ubme = 1 ubm can use this endpoint 4.3.2 oepbbax_n: output endpoint x-buffer base address (n = 1 to 3) 765 4 32 1 0 a10 a9 a8 a7 a6 a5 a4 a3 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 a[10:3] x a[10:3] of x-buffer base address (padded with 3 lsb of zeros for a total of 11 bits). this value is set by the mcu. the ubm or dma uses this value as the start-address of a given transaction. note that the ubm or dma does not change this value at the end of a transaction.
4 ? 7 4.3.3 oepbctx_n: output endpoint x byte count (n = 1 to 3) 765 4 32 1 0 nak c6 c5 c4 c3 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x x-buffer byte count: x000.0000b count = 0 x000.0001b count = 1 byte : : x011.1111b count = 63 bytes x100.0000b count = 64 bytes any value 100.0001b may result in unpredictable results. 7 nak x nak =0 nak = 1 no valid data in buffer. ready for host out buffer contains a valid packet from host (gives nak response to host out request) 4.3.4 oepbbay_n: output endpoint y-buffer base address (n = 1 to 3) 765 4 32 1 0 a10 a9 a8 a7 a6 a5 a4 a3 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 a[10:3] x a[10:3] of y-buffer base address (padded with 3 lsb of zeros for a total of 11 bits). this value is set by the mcu. the ubm or dma uses this value as the start-address of a given transaction. furthermore, ubm or dma does not change this value at the end of a transaction. 4.3.5 oepbcty_n: output endpoint y-byte count (n = 1 to 3) 765 4 32 1 0 nak c6 c5 c4 c3 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x y-byte count: x000.0000b count = 0 x000.0001b count = 1 byte : : x011.1111b count = 63 bytes x100.0000b count = 64 bytes any value 100.0001b may result in unpredictable results. 7 nak x nak =0 nak = 1 no valid data in buffer. ready for host out buffer contains a valid packet from host (gives nak response to host out request)
4 ? 8 4.3.6 oepsizxy_n: output endpoint x-/y-buffer size (n =1 to 3) 765 4 32 1 0 rsv s6 s5 s4 s3 s2 s1 s0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x x- and y-buffer size: 0000.0000b size = 0 0000.0001b size = 1 byte : : 0011.1111b size = 63 bytes 0100.0000b size = 64 bytes any value 100.0001b may result in unpredictable results. 7 rsv x reserved = 0 4.3.7 iepcnf_n: input endpoint configuration (n = 1 to 3) (addr:ff48, ff50, ff58) 765 4 32 1 0 ubme iso=0 togle dbuf stall usbie rsv rsv r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 1 ? 0 rsv x reserved = 0 2 usbie x usb interrupt enable on transaction completion usbie = 0 no interrupt usbie = 1 interrupt on transaction completion 3 stall 0 usb stall condition indication. set by the ubm but can be set/cleared by the mcu stall = 0 no stall stall = 1 usb stall condition. if set by the mcu a stall handshake is initiated and the bit is cleared automatically. 4 dbuf x double buffer enable dbuf = 0 primary buffer only (x-buffer only) dbuf = 1 toggle bit selects buffer 5 togle x usb toggle bit. this bit reflects the toggle sequence bit of data0, data1 6 iso x iso = 0 nonisochronous transfer. this bit must be cleared by the mcu since only nonisochronous transfer is supported 7 ubme x ubm enable/disable bit. set/cleared by the mcu ubme = 0 ubm cannot use this endpoint ubme = 1 ubm can use this endpoint 4.3.8 iepbbax_n: input endpoint x-buffer base address (n = 1 to 3) 765 4 32 1 0 a10 a9 a8 a7 a6 a5 a4 a3 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 a[10:3] x a[10:3] of x-buffer base address (padded with 3 lsb of zeros for a total of 11 bits). this value is set by the mcu. the ubm or dma uses this value as the start-address of a given transaction, but note that the ubm or dma does not change this value at the end of a transaction.
4 ? 9 4.3.9 iepbctx_n: input endpoint x-byte count (n = 1 to 3) 765 4 32 1 0 nak c6 c5 c4 c3 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x x-buffer byte count: x000.0000b count = 0 x000.0001b count = 1 byte : : x011.1111b count = 63 bytes x100.0000b count = 64 bytes any value 100.0001b may result in unpredictable results. 7 nak x nak = 0 nak = 1 buffer contains a valid packet for host-in transaction buffer is empty (gives nak response to host-out request) 4.3.10 iepbbay_n: input endpoint y-buffer base address (n = 1 to 3) 765 4 32 1 0 a10 a9 a8 a7 a6 a5 a4 a3 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 a[10:3] x a[10:3] of y-buffer base address (padded with 3 lsb of zeros for a total of 11 bits). this value is set by the mcu. the ubm or dma uses this value as the start-address of a given transaction, but note that the ubm or dma does not change this value at the end of a transaction. 4.3.11 iepbcty_n: input endpoint y-byte count (n = 1 to 3) 765 4 32 1 0 nak c6 c5 c4 c3 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x y-byte count: x000.0000b count = 0 x000.0001b count = 1 byte : : x011.1111b count = 63 bytes x100.0000b count = 64 bytes any value 100.0001b may result in unpredictable results. 7 nak x nak =0 nak = 1 buffer contains a valid packet for host-in transaction buffer is empty (gives nak response to host-in request)
4 ? 10 4.3.12 iepsizxy_n: output endpoint x-/y-buffer size (n = 1 to 3) 765 4 32 1 0 rsv s6 s5 s4 s3 s2 s1 s0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 c[6:0] x x- and y-buffer size: 0000.0000b size = 0 0000.0001b size = 1 byte : : 0011.1111b size = 63 bytes 0100.0000b size = 64 bytes any value 100.0001b may result in unpredictable results. 7 rsv x reserved = 0 4.4 endpoint-0 descriptor registers unlike registers edb ? 1 to edb ? 3, which are defined as memory entries in sram, endpoint ? 0 is described by a set of four registers (two for output and two for input). the registers and their respective addresses, used for edb ? 0 description, are defined in table 4 ? 6. edb ? 0 has no base-address register, since these addresses are hardwired into fef8 and fef0. note that the bit positions have been preserved to provide consistency with edb ? n (n = 1 to 3). table 4 ? 6. input/output edb-0 registers address register name description base address ff83 ff82 oepbcnt_0 oepcnfg_0 output endpoint_0: byte count register output endpoint_0: configuration register fef0 ff81 ff80 iepbcnt_0 iepcnfg_0 output endpoint_0: byte count register output endpoint_0: configuration register fef8 4.4.1 iepcnfg_0: input endpoint-0 configuration register (addr:ff80) 765 4 32 1 0 ubme rsv togle rsv stall usbie rsv rsv r/w r/o r/o r/o r/w r/w r/o r/o bit name reset function 1 ? 0 rsv 0 reserved = 0 2 usbie 0 usb interrupt enable on transaction completion. set/cleared by the mcu. usbie = 0 no interrupt usbie = 1 interrupt on transaction completion 3 stall 0 usb stall condition indication. set/cleared by the mcu stall = 0 no stall stall = 1 usb stall condition. if set by the mcu a stall handshake is initiated and the bit is cleared automatically by the next setup transaction. 4 rsv 0 double buffer enable dbuf = 0 primary buffer only (x-buffer only) dbuf = 1 toggle bit selects buffer 5 togle 0 usb toggle bit. this bit reflects the toggle sequence bit of data0, data1. 6 rsv 0 reserved = 0 7 ubme 0 ubm enable/disable bit. set/cleared by the mcu ubme = 0 ubm cannot use this endpoint ubme = 1 ubm can use this endpoint 4.4.2 iepbcnt_0: input endpoint-0 byte count register (addr:ff81) 765 4 32 1 0
4 ? 11 nak rsv rsv rsv c3 c2 c1 c0 r/w r/o r/o r/o r/w r/w r/w r/w bit name reset function 3 ? 0 c[3:0] 0h byte count: 0000b count = 0 : : 1111b count = 7 1000b count = 8 1001b to 1111b are reserved. (if used, they default to 8) 6 ? 4 rsv 0 reserved = 0 7 nak 1 nak =0 nak = 1 buffer contains a valid packet for host-in transaction buffer is empty (gives nak response to host-in request) 4.4.3 oepcnfg_0: output endpoint-0 configuration register (addr:ff82) 765 4 32 1 0 ubme rsv togle rsv stall usbie rsv rsv r/w r/o r/o r/o r/w r/w r/o r/o bit name reset function 1 ? 0 rsv 0 reserved = 0 2 usbie 0 usb interrupt enable on transaction completion. set/cleared by the mcu. usbie = 0 no interrupt usbie = 1 interrupt on transaction completion 3 stall 0 usb stall condition indication. set/cleared by the mcu stall = 0 no stall stall = 1 usb stall condition. if set by the mcu, a stall handshake is initiated and the bit is cleared automatically. 4 rsv 0 reserved = 0 5 togle 0 usb \toggle bit. this bit reflects the toggle sequence bit of data0, data1. 6 rsv 0 reserved = 0 7 ubme 0 ubm enable/disable bit. set/cleared by the mcu ubme = 0 ubm cannot use this endpoint ubme = 1 ubm can use this endpoint 4.4.4 oepbcnt_0: output endpoint-0 byte count register (addr:ff83) 765 4 32 1 0 nak rsv rsv rsv c3 c2 c1 c0 r/w r/o r/o r/o r/o r/o r/o r/o bit name reset function 3 ? 0 c[3:0] 0h byte count: 0000b count = 0 : : 1111b count = 7 1000b count = 8 1001b to 1111b are reserved 6 ? 4 rsv 0 reserved = 0 7 nak 1 nak =0 nak = 1 no valid data in buffer. ready for host out buffer contains a valid packet from host (gives nak response to host-in request).
4 ? 12
5 ? 1 5 usb 5.1 usb registers 5.1.1 funadr: function address register (addr:ffff) this register contains the device function address. 765 4 32 1 0 rsv fa6 fa5 fa4 fa3 fa2 fa1 fa0 r/o r/w r/w r/w r/w r/w r/w r/w bit name reset function 6 ? 0 fa[6:0] 0 these bits define the current device address assigned to the function. the mcu writes a value to this register because of the set-address host command. 7 rsv 0 reserved = 0 5.1.2 usbsta: usb status register (addr:fffe) all bits in this register are set by the hardware and are cleared by the mcu when writing a 1 to the proper bit location (writing a 0 has no effect). in addition, each bit can generate an interrupt if its corresponding mask bit is set (r/c notation indicates read and clear only by the mcu). 765 4 32 1 0 rstr susr resr rsv urri setup wakeup stpow r/c r/c r/c r/o r/c r/c r/c r/c bit name reset function 0 stpow 0 setup overwrite bit. set by hardware when setup packet is received while there is already a packet in the setup buffer. stpow = 0 stpow = 1 mcu can clear this bit by writing a 1 (writing 0 has no effect). setup overwrite 1 wakeup 0 remote wakeup bit wakeup = 0 wakeup = 1 the mcu can clear this bit by writing a 1 (writing 0 has no effect). remote wakeup request from wakeup pin 2 setup 0 setup transaction received bit. as long as setup is 1, in and out on endpoint ? 0 are naked, regardless of their real nak bits value. setup = 0 setup = 1 mcu can clear this bit by writing a 1 (writing 0 has no effect). setup transaction received 3 urri 0 uart ri status bit ? a rising edge causes this bit to be set. urri = 0 urri = 1 urri = 0 the mcu can clear this bit by writing a 1 (writing 0 has no effect). urri = 1 ring detected, which is used to wake the chip up (bring it out of suspend). 4 rsv 0 reserved 5 resr 0 function resume request bit resr = 0 resr = 1 the mcu can clear this bit by writing a 1 (writing 0 has no effect). function resume is detected 6 susr 0 function suspended request bit. this bit is set in response to a global or selective suspend condition. fsusp = 0 fsusp = 1 the mcu can clear this bit by writing a 1 (writing 0 has no effect). function suspend is detected 7 rstr 0 function reset request bit. this bit is set in response to host initiating a port reset. this bit is not affected by the usb function reset. frst = 0 frst = 1 the mcu can clear this bit by writing a 1 (writing 0 has no effect). function reset is detected
5 ? 2 5.1.3 usbmsk: usb interrupt mask register (addr:fffd) 765 4 32 1 0 rstr susr resr rsv ur1ri setup wakeup stpow r/w r/w r/w r/o r/w r/w r/w r/w bit name reset function 0 stpow 0 setup overwrite interrupt-enable bit stpow = 0 stpow = 1 stpow interrupt disabled stpow interrupt enabled 1 wakeup 0 remote wakeup interrupt enable bit wakeup = 0 wakeup = 1 wakeup interrupt disable wakeup interrupt enable 2 setup 0 setup interrupt enable bit setup = 0 setup = 1 setup interrupt disabled setup interrupt enabled 3 ur1ri 0 uart 1 r1 interrupt enable bit urri = 0 urri = 1 ur1ri interrupt disable ur1ri interrupt enable 4 rsv 0 reserved 5 resr 0 function resume interrupt enable bit resr = 0 resr = 1 function resume interrupt disabled function resume interrupt enabled 6 susr 0 function suspend interrupt enable fsusp = 0 fsusp = 1 function suspend interrupt disabled function suspend interrupt enabled 7 rstr 0 function reset interrupt bit. this bit is not affected by usb function reset. frst = 0 frst = 1 function reset interrupt disabled function reset interrupt enabled
5 ? 3 5.1.4 usbctl: usb control register (addr:fffc) unlike the rest of the registers, this register is cleared by the power-up reset signal only. the usb reset cannot reset this register (see figure 5 ? 1 ) . 765 4 32 1 0 r/w r/o r/w r/w r/w r/o r/w r/w bit name reset 0 dir 0 as a response to a setup packet, the mcu decodes the request and sets/clears this bit to reflect the data transfer direction. dir = 0 dir = 1 usb data-out transaction (from host to TUSB3410) usb data-in transaction (from TUSB3410 to host) 1 sir 0 setup interrupt-status bit. this bit is controlled by the mcu to indicate to the hardware when the setup interrupt is being served. sir = 0 sir = 1 setup interrupt is not served. the mcu clears this bit before exiting the setup interrupt routine. setup interrupt is in progress. the mcu sets this bit when servicing the setup interrupt. 2 rsv 0 reserved = 0 3 rsv 0 reserved = 0 4 frste 1 function reset-connection bit. this bit connects/disconnects the usb function reset to/from the mcu reset. frste = 0 frste = 1 function reset is not connected to mcu reset function reset is connected to mcu reset 5 rwup 0 device remote wakeup request. this bit is set by the mcu and is cleared automatically. rwup = 0 rwup = 1 writing a 0 to this bit has no effect when mcu writes a 1, a remote-wakeup pulse is generated. 6 iren 0 ir mode enable. this bit is set and cleared by firmware. iren = 0 iren = 1 ir encoder/decoder is disabled, uart mode is selected ir encoder/decoder is enabled, uart mode is deselected 7 cont 0 connect/disconnect bit cont = 0 cont = 1 upstream port is disconnected. pullup disabled. upstream port is connected. pullup enabled.
5 ? 4 5.1.5 modecnfg: mode configuration register (addr:fffb) this register is cleared by the power-up reset signal only. the usb reset cannot reset this register. 765 4 32 1 0 rsv rsv rsv rsv clkslct clkouten softsw txcntl r/o r/o r/o r/o r/w r/w r/w r/w bit name reset function 0 txcntl 0 transmit output control: hardware or firmware switching select for 3-state serial output buffer. txcntl = 0 txcntl = 1 hardware automatic switching is selected firmware toggle switching is selected 1 softsw 0 soft switch: firmware controllable 3-state output buffer enable for serial output pin. softsw = 0 softsw = 1 serial output buffer is enabled serial output buffer is disabled 2 clkouten 0 clock output enable: enable/disable the clock output at clkout terminal. clkouten = 0 clkouten = 1 clock output is disabled. device drives low at clkout terminal. clock output is enabled 3 clkslct 0 clock output source select: select between 3.556-mhz fixed clock or uart baud out clock as output clock source. clkslct = 0 clkslct = 1 uart baud out clock is selected as clock output fixed 3.556-mhz free running clock is selected as clock output 4 ? 7 rsv 0 reserved clock output control the clkouten bit in the mode configuration register (modecnfg) is used to enable or disable the clock output at the clkout terminal of the TUSB3410. the power up default of clkout is disabled to ensure the clock is not applied to the smart card until it is powered. firmware can write a 1 to enable the clock output if needed. the clkslct bit in the modecnfg register is used to select the output clock source from either a fixed 3.556-mhz free-running clock or the uart baudout clock. 5.1.6 vendor id/product id usb ? if and microsoft whql certification requires that end equipment makers use their own unique vendor id and product id for each product (model). oems cannot use silicon vendor ? s (for instance, ti ? s default) vid/pid in their end products. a unique vid/pid combination will avoid potential driver conflicts and enable logo certification. see www.usb.org for more information. 5.1.7 sernum7: device serial number register (byte 7) (addr:ffef) each TUSB3410 chip has a unique 64-bit serial die id number, which is generated during manufacturing. the die id is incremented sequentially, however there is no assurance without skip in the die id number. the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum7) contains the most significant byte (byte 7) of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d63 d62 d61 d60 d59 d58 d57 d56 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 7 value device serial number byte 7 value
5 ? 5 procedure to load device serial number value in shared ram: ? after power-up reset, boot code copies the predefined usb descriptors to shared ram. as a result, the default serial number hard-coded in the boot code (0x00 hex) is copied to the shared ram data space. ? once the boot code finishes copying descriptors, it performs a read to the sernum7 to sernum0 registers and overwrites the device serial number value stored in the shared ram with the one found in the sernum7 to sernum0 registers. ? once the boot code finishes the read to sernum7 ? sernum0 registers, it then checks if eeprom is present on the i 2 c port. if the eeprom is present and contains a valid device serial number as part of the usb device descriptor information stored in eeprom, the boot code overwrites the serial number value stored in shared ram with the one found in eeprom. otherwise, the device serial number value stored in shared ram stays unchanged from previous step. ? in summary, the serial number value in external eeprom has the highest priority to be loaded into shared ram data space. the serial number value stored in shared ram is used as part of the valid device descriptor information during normal operation. 5.1.8 sernum6: device serial number register (byte 6) (addr:ffee) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum6) contains byte 6 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d55 d54 d53 d52 d51 d50 d49 d48 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 6 value device serial number byte 6 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram. 5.1.9 sernum5: device serial number register (byte 5) (addr:ffed) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum5) contains byte 5 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d47 d46 d45 d44 d43 d42 d41 d40 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 5 value device serial number byte 5 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram.
5 ? 6 5.1.10 sernum4: device serial number register (byte 4) (addr:ffec) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum4) contains byte 4 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d39 d38 d37 d36 d35 d34 d33 d32 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 4 value device serial number byte 4 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram. 5.1.11 sernum3: device serial number register (byte 3) (addr:ffeb) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum3) contains byte 3 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d31 d30 d29 d28 d27 d26 d25 d24 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 3 value device serial number byte 3 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram. 5.1.12 sernum2: device serial number register (byte 2) (addr:ffea) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum2) contains byte 2 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d23 d22 d21 d20 d19 d18 d17 d16 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] 0 device serial number byte 2 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram. 5.1.13 sernum1: device serial number register (byte 1) (addr:ffe9) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum1) contains byte 1 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d15 d14 d13 d12 d11 d10 d9 d8 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 1 value device serial number byte 1 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram.
5 ? 7 5.1.14 sernum0: device serial number register (byte 0) (addr:ffe8) the device serial number register utilizes (mirrors) this unique 64-bit serial die id number. after power-up reset, this read-only register (sernum0) contains byte 0 of the complete 64-bit device serial number. the usb reset cannot reset this register. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] device serial number byte 0 value device serial number byte 0 value note: see the same procedure described in sernum7 register for procedure to load device serial number into the shared ram. 5.1.15 function reset and power-up reset interconnect figure 5 ? 1 represents the logical connection of the usb-function reset (usbr ) and power-up reset (reset ) pins. the internal reset signal is generated from the reset pin (purs signal) or from the usb reset (usbr signal). the usbr can be enabled or disabled by the frste bit in the usbctl register (on power up, frste = 0). the internal reset is used to reset all registers and logic, with the exception of the usbctl and globctl registers which are cleared by the purs signal only. usbctl register globctl register purs usbr reset mcu frste usb function reset to internal mmrs reset g2 wdd[4:0] wdt reset figure 5 ? 1. reset diagram
5 ? 8 5.1.16 pullup resistor connect/disconnect the TUSB3410 enumeration can be activated by the mcu (there is no need to disconnect the cable physically). figure 5 ? 2 represents the implementation of the TUSB3410 connect and disconnect from a usb up-stream port. when cont = 1 in the usbctl register, the cmos driver sources v dd to the pullup resistor (pur pin) presenting a normal connect condition to the usb hub (high speed). when cont = 0, the pur pin is driven low. in this state, the 1.5-k ? resistor is connected to gnd, resulting in the device disconnection state. the pur driver is a cmos driver that can provide (v dd ? 0.1 v) minimum at 8-ma source current. hub d+ d ? 15 k ? TUSB3410 1.5 k ? cmos pur cont-bit dp0 dm0 figure 5 ? 2. pullup resistor connect/disconnect circuit
6 ? 1 6 dma controller table 6 ? 1 outlines the dma channels and their associated transfer directions. two channels are provided for data transfer between the host and the uart. table 6 ? 1. dma controller registers dma channel transfer direction comments dma ? 1 host to uart dma writes to uart tdr register dma ? 3 uart to host dma reads from uart rdr register 6.1 dma controller registers each dma channel can point to one of three edbs (edb[3:1]) and transfer data to/from the uart channel. the dma can move data from a given out-point buffer (defined by edb) to the destination port. similarly, the dma can move data from a port to a given input-endpoint buffer. two modes of dma transfers are supported: burst and continuous. ? burst (cnt = 0) mode the dma stops at the end of a block-data transfer (or if an error condition occurred) and interrupts the mcu. it is the responsibility of the mcu to update the x/y bit and the nak bit in the edb. ? continuous (cnt = 1) mode at the end of a block transfer the dma updates the byte count and nak bit in the edb when receiving. in addition, it uses the x/y bit to switch automatically, without interrupting the mcu (the x/y bit toggle is performed by the ubm). the dma stops only when a time-out or error condition occurs. when the dma is transmitting (from the x/y buffer) it continues alternating between x/y buffers until it detects a byte count smaller than the buffer size (buffer size is typically 64 bytes). at that point it completes the transfer and stops.
6 ? 2 6.1.1 dmacdr1: dma channel definition register (uart transmit channel) (addr:ffe0) these registers are used to define the edb number that the dma uses for data transfer to the uarts. in addition, these registers define the data transfer direction and selects x or y as the transaction buffer. 765 4 32 1 0 en ine cnt xy t/r e2 e1 e0 r/w r/w r/w r/w r/o r/w r/w r/w bit name reset function 2 ? 0 e[2:0] 0 endpoint descriptor pointer. this field points to a set of edb registers that is to be used for a given transfer. 3 t/r 0 this bit is always zero, indicating that the dma data transfer is from sram to the uart tdr register. (the mcu cannot change this bit.) 4 xy 0 x/y buffer select bit. valid only when cnt = 0 xy = 0 xy = 1 next buffer to transmit/receive is the x buffer next buffer to transmit/receive is the y buffer 5 cnt 0 dma continuous transfer control bit. this bit defines the mode of the dma transfer. cnt = 0 burst mode: the dma stops the transfer when the byte count is zero or when a partial packet has been received (byte count < 64). at the end of transfer, the high-to-low transition of en interrupts the mcu (if enabled). in this mode, the x/y bit is set by the mcu to define the current buffer (x or y). cnt = 1 continuous mode: in this mode, the dma and ubm alternate between the x- and y-buffers. the dma sets the x/y bit and the ubm uses it for the transfer. the dma alternates between the x-/y-buffers and continues transmitting (from x-/y-buffer) without mcu intervention. the dma terminates, and interrupts the mcu, under the following conditions: 1. when the ubm byte count < buffer size (in edb), the dma transfers the partial packet and interrupt the mcu on completion. 2. transaction timer expires. the dma interrupts the mcu. 6 ine 0 dma interrupt enable/disable bit. this bit is used to enable/disable the interrupt on transfer completion. ine = 0 interrupt is disabled. in addition, ppkt and txft do not clear the en-bit and the dmac is not disabled. ine = 1 enables the en interrupt. when this bit is set, the dma interrupts the mcu on a 1 to 0 transition of the en bit. (when transfer is completed, en = 0) 7 en 0 dma channel enable bit. the mcu sets this bit to start the dma transfer. when the transfer completes, or when it is terminated due to error, this bit is cleared. the 1 to 0 transition of this bit generates an interrupt (if interrupt is enabled). en = 0 dma is halted. the dma is halted when the byte count reaches zero or transaction time-out occurs. when halted, the dma updates the byte count, sets nak = 0 in oedb, and interrupts the mcu (if ine = 1). en = 1 setting this bit starts the dma transfer.
6 ? 3 6.1.2 dmacsr1: dma control and status register (uart transmit channel) (addr:ffe1) this register is used to define the transaction time-out value. in addition, it contains a completion code that reports any errors or a time-out condition. 765 4 32 1 0 ten c4 c3 c2 c1 c0 txft ppkt r/w r/w r/w r/w r/w r/w r/c r/c bit name reset function 0 ppkt 0 partial packet condition bit. this bit is set by the dma and cleared by the mcu (see table 6 ? 2). ppkt = 0 no partial-packet condition ppkt = 1 partial-packet condition detected. when ien = 0, this bit does not clear the en bit in dmacdr; therefore, the dmac stays enabled, ready for the next transaction. clears when mcu writes a 1. writing a 0 has no effect. 1 txft 0 transfer time-out condition (see table 6 ? 2) txft = 0 dma stopped transfer without time-out txft = 1 dma stopped due to transaction time-out. when ien = 0, this bit does not clear the en bit in dmacdr; therefore, the dmac stays enabled, ready for the next transaction. dma clears when the mcu writes a 1. writing a 0 has no effect. 6 ? 2 c[4:0] 0 this field is used to define the transaction time-out value in 1-ms increments. this value is loaded to a down counter every time a byte transfer occurs. the down counter is decremented every sof pulse (1 ms). if the counter decrements to zero it sets txft = 1 (in dmacsr register) and halts the dma transfer. the counter starts counting only when ten = 1 and en = 1 (in dmacdr ) and the first byte has been transmitted (see figure 6 ? 1). 00000 = 0-ms time-out : : 11111 = 31-ms time-out 7 ten 0 transaction time-out counter enable/disable bit. ten = 0 ten = 1 counter is disabled (does not time-out) counter is enabled table 6 ? 2. dma out-termination condition out termination txft ppkt comments uart partial packet 0 1 this condition occurs when the host sends a partial packet. uart time-out 1 0 this condition occurs when x- and y-output buffers are full and the uart transmitter cannot transmit (due to flow-control restriction) or if host has no data to transmit. counter c[4:0] txft load sof ten en figure 6 ? 1. transaction time-out diagram
6 ? 4 6.1.3 dmacdr3: dma channel definition register (uart receive channel) (addr:ffe4) these registers are used to define the edb number that the dma uses for data transfer from the uarts. in addition, these registers define the data transfer direction and selects x or y as the transaction buffer. 765 4 32 1 0 en ine cnt xy t/r e2 e1 e0 r/w r/w r/w r/w r/o r/w r/w r/w bit name reset function 2 ? 0 e[2:0] 0 endpoint descriptor pointer. this field points to a set of edb registers that are used for a given transfer. 3 t/r 1 this bit is always 1. this indicates that the dma data transfer is from uart rdr register to sram. (the mcu cannot change this bit.) 4 xy 0 xy buffer select bit. valid only when cnt = 0. xy = 0 xy = 1 next buffer to transmit/receive is x next buffer to transmit/receive is y 5 cnt 0 dma continuous transfer control bit. this bit defines the mode of the dma transfer. cnt = 0 burst mode: dma stops the transfer when the byte count = 0 or when a receiver error occurs. at the end of transfer, the high-to-low transition of en interrupts the mcu (if enabled). in this mode, the xy bit is set by the mcu to define the current buffer (x or y). cnt = 1 continuous mode: in this mode, the dma and ubm alternate between the x- and y-buffers. the ubm sets the xy bit and the dma uses it for the transfer. the dma alternates between the x-/y-buffers and continues receiving (to x-/y-buffer) without mcu intervention. the dma terminates the transfer and interrupts the mcu, under the following conditions: 1. transaction time-out expired: dma updates edb and interrupts the mcu. ubm transfers the partial packet to the host. 2. uart receiver error condition: dma updates edb and does not interrupt the mcu. ubm transfers the partial packet to the host. 6 ine 0 dma interrupt enable/disable bit. this bit is used to enable/disable the interrupt on transfer completion. ine = 0 interrupt is disabled. in addition, ovrun and txft do not clear the en bit and the dmax is not disabled. ine = 1 enables the en interrupt. when this bit is set, the dma interrupts the mcu on a 1 to 0 transition of the en bit. (when transfer is completed, en = 0). 7 en 0 dma channel enable bit. the mcu sets this bit to start the dma transfer. when transfer completes, or when terminated due to error, this bit is cleared. the 1 to 0 transition of this bit generates an interrupt (if interrupt is enabled). en = 0 dma is halted. the dma is halted when transaction time-out occurs, or under a uart receiver-error condition. when halted, the dma updates the byte count and sets nak = 0 in iedb. if the termination is due to transaction time-out, the dma generates an interrupt. however, if the termination is due to a uart error condition, the dma does not generate an interrupt. (the uart generates the interrupt.) en = 1 setting this bit starts the dma transfer.
6 ? 5 6.1.4 dmacsr3: dma control and status register (uart receive channel) (addr:ffe5) this register is used to define the transaction time-out value. in addition, it contains a completion code that reports any errors or a time-out condition. 765 4 32 1 0 ten c4 c3 c2 c1 c0 txft ovrun r/w r/w r/w r/w r/w r/w r/c r/c bit name reset function 0 ovrun 0 overrun condition bit. this bit is set by dma and cleared by the mcu (see table 6 ? 3) ovrun = 0 no overrun condition ovrun = 1 overrun condition detected. when ien = 0, this bit does not clear the en bit in dmacdr; therefore, the dmac stays enabled, ready for the next transaction. clears when the mcu writes a 1. writing a 0 has no effect. 1 txft 0 transfer time-out condition bit (see table 6 ? 3) txft = 0 dma stopped transfer without time-out txft =1 dma stopped due to transaction time-out. when ien = 0, this bit does not clear the en bit in dmacdr; therefore, the dmac stays enabled, ready for the next transaction. clears when the mcu writes a 1. writing a 0 has no effect. 6 ? 2 c[4:0] 00000b this field is used to define the transaction time-out value in 1-ms increments. this value is loaded to a down counter every time a byte transfer occurs. the down counter is decremented every sof pulse (1 ms). if the counter decrements to zero it sets txft = 1 (in dmacsr register) and halts the dma transfer. the counter starts counting only when ten = 1 and en = 1 (in dmacdr ) and the first byte has been received (see figure 6 ? 1). 00000 = 0-ms time-out : : 11111 = 31-ms time-out 7 ten 0 transaction time-out counter enable/disable bit ten = 0 ten = 1 counter is disabled (does not time-out) counter is enabled table 6 ? 3. dma in-termination condition in termination txft ovrun comments uart error 0 0 uart error condition detected uart partial packet 1 0 this condition occurs when uart receiver has no more data for the host (data starvation). uart overrun 1 1 this condition occurs when x- and y-input buffers are full and the uart fifo is full (host is busy). 6.2 bulk data i/o using the edb the ubm (usb buffer manager) and the dmac (dma controller) access the edb to fetch buffer parameters for in and out transactions (in and out are with respect to host). in this discussion, it is assumed that (a) the mcu initialized the edbs, (b) dma-continuous mode is being used, (c) double buffering is being used, and (d) the x/y toggle is controlled by the ubm. note: the in and out transfers apply to uart. 6.2.1 in transaction (TUSB3410 to host) 1. the mcu initializes the iedb (64-byte packet, and double buffering is used) and the following dma registers: ? dmacsr: defines the transaction time-out value. ? dmacdr: defines the iedb being used and the dma mode of operation (continuous mode). once this register is set with en = 1, the transfer starts.
6 ? 6 2. the dma transfers data from the uart to the x buffer. when a block of 64 bytes is transferred, the dma updates the byte count and sets nak = 0 in iedb (indicating to the ubm that the x buffer is ready to be transferred to host). the ubm starts x-buffer transfer to host using the byte-count value in iedb and toggles the x/y bit. the dma continues transferring data from a device to y-buffer. at the end of the block transfer, the dma updates the byte count and sets nak = 0 in iedb (indicating to the ubm that the y-buffer is ready to be transferred to host). the dma continues the transfer from the device to host, alternating between x-and y-buffers without mcu intervention. 3. transfer termination: as mentioned, the dma/ubm continues the data transfer, alternating between the x- and y-buffers. termination of the transfer can happen under the following conditions: ? stop transfer: the host notifies the mcu (via control-end-point) to stop the transfer. under this condition, the mcu sets en = 0 in the dmacdr register. ? partial packet: the device receiver has no data to be transferred to host. under this condition, the byte-count value is less than 64 when the transaction timer time-out occurs. when the dma detects this condition, it sets txft = 1 and ovrun = 0, updates the byte count and nak bit (partial packet) in the iedb, and interrupts the mcu. ubm transfers the partial packet to host. ? buffer overrun: the host is busy, x- and y-buffers are full (x nak = 0 and y ? nak = 0) and the dma cannot write to these buffers. the transaction time-out stops the dma transfer, the dma sets txft = 1 and ovrun = 1, and interrupts the mcu. ? uart error condition: when receiving from a uart, a receiver-error condition stops the dma and sets txft = 1 and ovrun = 0, but the en bit remains set at 1. therefore, the dma does not interrupt the mcu. however, the uart generates a status interrupt, notifying the mcu that an error condition has occurred. 6.2.2 out transaction (host to TUSB3410) 1. the mcu initializes the oedb (64-byte packet, and double buffering is used) and the following dma registers: ? dmacsr: defines the transaction time-out value. ? dmacdr: defines the oedb being used, and the dma mode of operation (continuous mode). once the en bit is set to 1 in this register, the transfer starts. 2. the ubm transfers data from host to x-buffer. when a block of 64 bytes is transferred, the ubm updates the byte count and sets nak = 1 in oedb (indicating to dma that the x-buffer is ready to be transferred to the uart). the dma starts x-buffer transfer using the byte-count value in oedb. the ubm continues transferring data from host to y-buffer. at the end of the block transfer, the ubm updates the byte count and sets nak = 1 in oedb (indicating to dma that the y-buffer is ready to be transferred to device). the dma continues the transfer from the x-/y-buffers to the device, alternating between x- and y-buffers without mcu intervention. 3. transfer termination: the dma/ubm continues the data transfer alternating between x- and y-buffers. the termination of the transfer can happen under the following conditions: ? stop transfer: the host notifies the mcu (via control-end point) to stop the transfer. under this condition, the mcu sets en = 0 in the dmacdr register. ? partial-packet: ubm receives a partial packet from host. under this condition, the byte-count value is less than 64 and the transaction timer does not time-out. when the dma detects this condition, it transfers the partial packet to the device, sets txft = 0 and ppkt = 1, updates nak = 0 in oedb, and interrupts the mcu. ? time-out: the device is busy, x- and y-buffers are full (x-nak = 1 and y-nak = 1) and the ubm cannot write to these buffers. under this condition the transaction timer time-out stops the dma transfer, sets txft = 1 and ovrun = 0, and interrupts the mcu.
7 ? 1 7 uart 7.1 uart registers table 7 ? 1 summarizes the uart registers. these registers are used for data i/o, control, and status information. uart setup is done by the mcu. data transfer is typically performed by the dmac. however, the mcu can perform data transfer without dma; this is useful when debugging the firmware. table 7 ? 1. uart registers summary register name access function comments rdr r/o uart receiver data register can be accessed by mcu or dma tdr w/o uart transmitter data register can be accessed by mcu or dma lcr r/w uart line control register fcrl r/w uart flow control register mcr r/w uart modem control register lsr r/o uart line status register can generate an interrupt msr r/o uart modem status register can generate an interrupt dll r/w uart divisor register (low byte) dlh r/w uart divisor register (high byte) xon r/w uart xon register xoff r/w uart xoff register mask r/w uart interrupt mask register can control three interrupt sources 7.1.1 rdr: receiver data register (addr:ffa0) the receiver data register consists of a 32-byte fifo. data received from the sin pin are converted from serial-to-parallel format and stored in this fifo. data transfer from this register to the ram buffer is the responsibility of the dma controller. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] 0 receiver byte 7.1.2 tdr: transmitter data register (addr:ffa1) the transmitter data register is double buffered. data written to this register is loaded into the shift register, and shifted out on sout. data transfer from the ram buffer to this register is the responsibility of the dma controller. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 w/o w/o w/o w/o w/o w/o w/o w/o bit name reset function 7 ? 0 d[7:0] 0 transmit byte
7 ? 2 7.1.3 lcr: line control register (addr:ffa2) this register controls the data communication format. the word length, number of stop bits, and parity type are selected by writing the appropriate bits to the lcr. 765 4 32 1 0 fen brk fpty eprty prty stp wl1 wl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 1:0 wl{1 ? 0] 0 specifies the word length for transmit and receive 00b = 5 bits 01b = 6 bits 10b = 7 bits 11b = 8 bits 2 stp 0 specifies the number of stop bits for transmit and receive stp = 0 stp = 1 stp = 1 1 stop bit (word length = 5, 6, 7, 8) 1.5 stop bits (word length = 5) 2 stop bits (word length = 6, 7, 8) 3 prty 0 specifies whether parity is used prty = 0 prty = 1 no parity parity is generated 4 eprty 0 specifies whether even or odd parity is generated eprty = 0 eprty = 1 odd parity is generated (if prty = 1) even parity is generated (if prty = 1) 5 fpty 0 selects the forced parity bit fpty = 0 fpty = 1 parity is not forced parity bit is forced. if [eprty = 0], the parity bit is forced to 1 6 brk 0 this bit is the break-control bit brk = 0 brk = 1 normal operation forces sout into break condition (logic 0) 7 fen 0 fifo enable. this bit is used to disable/enable the fifo. to reset the fifo, the mcu clears and then sets this bit. fen = 0 fen = 1 the fifo is cleared and disabled. when disabled the selected receiver flow control is activated. the fifo is enabled and it can receive data.
7 ? 3 7.1.4 fcrl: uart flow control register (addr:ffa3) this register provides the flow-control modes of operation (see table 7 ? 3 for more details). 765 4 32 1 0 485e dtr rts rxof dsr cts txoa txof r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 0 txof 0 this bit controls the transmitter xon/xoff flow control. txof = 0 txof = 1 disable transmitter xon/xoff flow control enable transmitter xon/xoff flow control 1 txoa 0 this bit controls the transmitter xon-on-any/xoff flow control txoa = 0 txoa = 1 disable the transmitter xon-on-any/xoff flow control enable the transmitter xon-on-any/xoff flow control 2 cts 0 transmitter cts flow-control enable bit cts = 0 cts = 1 disables transmitter cts flow control cts flow control is enabled, i.e., when cts input pin is high, transmission is halted; when the cts pin is low, transmission resumes. 3 dsr 0 transmitter dsr flow-control enable bit dsr = 0 dsr = 1 disables transmitter dsr flow control dsr flow control is enabled, i.e., when dsr input pin is high, transmission is halted; when the dsr pin is low, transmission resumes. 4 rxof 0 this bit controls the receiver xon/xoff flow control. rxof = 0 rxof = 1 receiver does not attempt to match xon/xoff characters receiver searches for xon/xoff characters 5 rts 0 receiver rts flow control enable bit rts = 0 rts = 1 disables receiver rts flow control receiver rts flow control is enabled. rts output pin goes high when the receiver fifo halt trigger level is reached; it goes low, when the receiver fifo resume receiving trigger level is reached. 6 dtr 0 receiver dtr flow-control enable bit dtr = 0 dtr = 1 disables receiver dtr flow control receiver dtr flow control is enabled. dtr output pin goes high when the receiver fifo halt trigger level is reached; it goes low, when the receiver fifo resume receiving trigger level is reached. 7 485e 0 rs485 enable bit. this bit is used to configure the uart to control external rs485 transceivers. when configured in half-duplex mode (485e=1), rts or dtr can be used to enable the rs485 driver or receiver. see figure 5. 485e = 0 485e = 1 uart is in normal operation mode (full duplex) the uart is in half duplex rs485 mode. in this mode rts and dtr are active with opposite polarity (when rts = 0, dtr = 1). when the dma is ready to transmit, it drives rts = 1 (and dtr = 0) 2 ? bit ? time before transmission starts. when dma terminates the transmission, it drives rts = 0 (and dtr = 1) after transmission stops. when 485e is set to 1, the dtr and rts bits in the mcr register have no effect. also, see the rcve bit in mcr: modem-control register .
7 ? 4 7.1.5 transmitter flow control on reset (power up, usb or soft reset) the transmitter defaults to the xon state and the flow control is set to mode ? 0 (flow control is disabled). table 7 ? 2. transmitter flow-control modes mode 3 2 1 0 mode dsr cts txoa txof 0 all flow control is disabled 0 0 0 0 1 xon/xoff flow control is enabled 0 0 0 1 2 xon on any/ xoff flow control 0 0 1 0 3 not permissible (see note 1) x x 1 1 4 cts flow control 0 1 0 0 5 combination flow control (see note 2) 0 1 0 1 6 combination flow control 0 1 1 0 7 dsr flow control 1 0 0 0 9-e combination flow control notes: 1. this is a nonpermissible combination. if used, txoa and txof are cleared. 2. combination example: transmitter stops when either cts or xoff is detected. transmitter resumes when both cts is negated and xon is detected. table 7 ? 3. receiver flow-control possibilities mode 6 5 4 mode dtr rts rxof 0 all flow control is disabled 0 0 0 1 xon/xoff flow control is enabled 0 0 1 2 rts flow control 0 1 0 3 combination flow control (see note 3) 0 1 1 4 dtr flow control 1 0 0 5 combination flow control 1 0 1 6 combination flow control (see note 4) 1 1 0 7 combination flow control 1 1 1 notes: 3. combination example: both rts is asserted and xoff transmitted when fifo is full. both rts is deasserted and xon is tra nsmitted when fifo is empty. 4. combination example: both dtr and rts are asserted when fifo is full. both dtr and rts are deasserted when fifo is empty.
7 ? 5 7.1.6 mcr: modem-control register (addr:ffa4) this register provides control for modem interface i/o and definition of the flow control mode. 765 4 32 1 0 lcd lri rts dtr sen loop rcve urst r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 0 urst 0 uart soft reset. this bit can be used by the mcu to reset the uart. urst = 0 normal operation. writing a 0 by mcu has no effect. urst = 1 when the mcu writes a 1 to this bit, a uart reset is generated (ored with hard reset). when the uart exits the reset state, urst is cleared. the mcu can monitor this bit to determine if the uart completed the reset cycle. 1 rcve 0 receiver enable bit. this bit is valid only when 485e in fcrl is 1 (rs485 mode). when 485e = 0, this bit has no effect on the receiver. rcve = 0 when 485e = 1, the uart receiver is disabled when rts = 1, i.e., when data is being transmitted, the uart receiver is disabled. rcve = 1 when 485e = 1, the uart receiver is enabled regardless of the rts state, i.e., uart receiver is enabled all the time. this mode can be used to detect collisions on the rs-485 bus when received data does not match transmitted data. 2 loop 0 this bit controls the normal-/loop-back mode of operation (see figure 7 ? 1). loop = 0 normal operation loop = 1 enable loop-back mode of operation. in this mode the following occur: sout is set high sin is disconnected from the receiver input. the transmitter serial output is looped back into the receiver serial input. the four modem-control inputs: cts , dsr , dcd , and ri are disconnected. dtr, rts, lri and lcd are internally connected to the four modem-control inputs, and read in the msr register as follows: dtr is reflected in msr[4] bit rts is reflected in msr[5] bit lri is reflected in msr[6] bit lcd is reflected in msr[7] bit 3 rsv 0 reserved 4 dtr 0 this bit controls the state of the dtr output pin (see figure 7 ? 1). this bit has no effect when auto-flow control is used or when 485e = 1 (in fcrl register). dtr = 0 forces the dtr output pin to inactive (high) dtr = 1 forces the dtr output pin to active (low) 5 rts 0 this bit controls the state of the rts output pin (see figure 7 ? 1). this bit has no effect when auto-flow control is used or when 485e = 1 (in fcrl register). rts = 0 forces the rts output pin to inactive (high) rts = 1 forces the rts output pin to active (low)
7 ? 6 6 lri 0 this bit is used for loop-back mode only. when in loop-back mode, this bit is reflected in msr[6]-bit (see figure 7 ? 1). lri = 0 clears msr[6] = 0 lri = 1 sets msr[6] = 1 7 lcd 0 this bit is used for loop-back mode only. when in loop-back mode, this bit is reflected in msr[7]-bit (see figure 7 ? 1). lcd = 0 clears msr[7] = 0 lcd = 1 sets msr[7] = 1 7.1.7 lsr: line-status register (addr:ffa5) this register provides the status of the data transfer. dma transfer is halted when any of ovr, pte, fre, brk, or exit is 1. 765 4 32 1 0 rsv temt txe rxf brk fre pte ovr r/o r/o r/o r/o r/c r/c r/c r/c bit name reset function 0 ovr 0 this bit indicates the overrun condition of the receiver. if set, it halts the dma transfer and generates a status interrupt (if enabled). ovr = 0 ovr = 1 no overrun error overrun error has occurred. clears when the mcu writes a 1. writing a 0 has no effect. 1 pte 0 this bit indicates the parity condition of the received byte. if set, it halts the dma transfer and generates a status interrupt (if enabled). pte = 0 pte = 1 no parity error in data received parity error in data received. clears when the mcu writes a 1. writing a 0 has no effect. 2 fre 0 this bit indicates the framing condition of the received byte. if set, it halts the dma transfer and generates a status interrupt (if enabled). fre = 0 fre = 1 no framing error in data received framing error in data received. clears when mcu writes a 1. writing a 0 has no effect. 3 brk 0 this bit indicates the break condition of the received byte. if set, it halts the dma transfer and generates a status interrupt (if enabled). brk = 0 brk = 1 no break condition a break condition in data received was detected. clears when the mcu writes a 1. writing a 0 has no effect. 4 rxf 0 this bit indicates the condition of the receiver data register. typically, the mcu does not monitor this bit since data transfer is done by the dma controller. rxf = 0 rxf = 1 no data in the rdr rdr contains data. generates rx interrupt (if enabled). 5 txe 1 this bit indicates the condition of the transmitter data register. typically, the mcu does not monitor this bit since data transfer is done by the dma controller. txe = 0 txe = 1 tdr is not empty tdr is empty. generates tx interrupt (if enabled). 6 temt 1 this bit indicates the condition of both transmitter data register and shift register is empty. temt = 0 temt = 1 either tdr or tsr is not empty both tdr and tsr are empty 7 rsv 0 reserved = 0
7 ? 7 cts msr mcr (4) lcts (5) ldsr (6) lri (7) lcd (5) rts (4) dtr (6) lri (7) lcd (2) loop dsr ri dcd rts dtr figure 7 ? 1. msr and mcr registers in loop-back mode 7.1.8 msr: modem-status register (addr:ffa6) this register provides information about the current state of the control lines from the modem. 765 4 32 1 0 lcd lri ldsr lcts ? cd tri ? dsr ? cts r/o r/o r/o r/o r/c r/c r/c r/c bit name reset function 0 ? cts 0 this bit indicates that the cts input has changed state. cleared when the mcu writes a 1 to this bit. writing a 0 has no effect. ? cts = 0 ? cts = 1 indicates no change in the cts input indicates that the cts input has changed state since the last time it was read. clears when the mcu writes a 1. writing a 0 has no effect. 1 ? dsr 0 this bit indicates that the dsr input has changed state. cleared when the mcu writes a 1 to this bit. writing a 0 has no effect. ? dsr = 0 ? dsr = 1 indicates no change in the dsr input indicates that the dsr input has changed state since the last time it was read. clears when the mcu writes a 1. writing a 0 has no effect. 2 tri 0 trailing edge of the ring indicator. this bit indicates that the ri input has changed from low to high. this bit is cleared when the mcu writes a 1 to this bit. writing a 0 has no effect. tri = 0 tri = 1 indicates no applicable transition on the ri input indicates that an applicable transition has occurred on the ri input. 3 ? cd 0 this bit indicates that the cd input has changed state. cleared when the mcu writes a 1 to this bit. writing a 0 has no effect. ? cd = 0 ? cd = 1 indicates no change in the cd input indicates that the cd input has changed state since the last time it was read. 4 lcts 0 during loopback, this bit reflects the status of mcr[1] (see figure 7 ? 1) lcts = 0 lcts = 1 cts input is high cts input is low 5 ldsr 0 during loop back, this bit reflects the status of mcr[0] (see figure 7 ? 1). ldsr = 0 ldsr= 1 dsr input is high dsr input is low 6 lri 0 during loop back, this bit reflects the status of mcr[2] (see figure 7 ? 1). lri = 0 lri = 1 r i input is high r i input is low
7 ? 8 bit function reset name 7 lcd 0 during loopback, this bit reflects the status of mcr[3] (see figure 7 ? 1). lcd = 0 lcd = 0 cd input is high cd input is low 7.1.9 dll: divisor register low byte (addr:ffa7) this register contains the low byte of the baud-rate divisor. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 d[7:0] 08h low-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator. 7.1.10 dlh: divisor register high byte (addr:ffa8) this register contains the high byte of the baud-rate divisor. 765 4 32 1 0 d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 d[15:8] 00h high-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator. 7.1.11 baud-rate calculation the following formulas are used to calculate the baud-rate clock and the divisors. the baud-rate clock is derived from the 96-mhz master clock (dividing by 6.5). the table below presents the divisors used to achieve the desired baud rates, together with the associate rounding errors. baud clk 96 mhz 6.5 14.76923077 mhz divisor 14.76923077 10 6 baud rate 16
7 ? 9 table 7 ? 4. dll/dlh values and resulted baud rates desired baud dll/dlh value actual baud error % desired baud dec. hex. actual baud error % 1 200 769 0301 1 200.36 0.03 2 400 385 0181 2 397.60 0.01 4 800 192 00c0 4 807.69 0.16 7 200 128 0080 7 211.54 0.16 9 600 96 0060 9 615.38 0.16 14 400 64 0040 14 423.08 0.16 19 200 48 0030 19 230.77 0.16 38 400 24 0018 38 461.54 0.16 57 600 16 0010 57 692.31 0.16 115 200 8 0008 115 384.62 0.16 230 400 4 0004 230 769.23 0.16 460 800 2 0002 461 538.46 0.16 921 600 1 0001 923 076.92 0.16 note: the TUSB3410 does support baud rates lower than 1200 bps, which are not listed due to less interest. 7.1.12 xon: xon register (addr:ffa9) this register contains a value that is compared to the received data stream. detection of a match interrupts the mcu (only if the interrupt enable bit is set). this value is also used for xon transmission. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 d[7:0] 0000 xon value to be compared to the incoming data stream 7.1.13 xoff: xoff register (addr:ffaa) this register contains a value that is compared to the received data stream. detection of a match halts the dma transfer, and interrupts the mcu (only if the interrupt enable bit is set). this value is also used for xoff transmission. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 7 ? 0 d[7:0] 0000 xoff value to be compared to the incoming data stream
7 ? 10 7.1.14 mask: uart interrupt-mask register (addr:ffab) this register controls the uarts interrupt sources. 765 4 32 1 0 rsv rsv rsv rsv rsv rrie sie mie r/o r/o r/o r/o r/o r/w r/w r/w bit name reset function 0 mie 0 this bit controls the uart-modem interrupt. mie = 0 mie = 1 modem interrupt is disabled modem interrupt is enabled 1 sie 0 this bit controls the uart-status interrupt. sie = 0 mie = 1 status interrupt is disabled status interrupt is enabled 2 tri 0 this bit controls the uart-txe/rxf interrupts trie = 0 trie = 1 txe/rxf interrupts are disabled txe/rxf interrupts are enable 7 ? 3 rsv 0 reserved = 0 7.2 uart data transfer figure 7 ? 2 illustrates the data transfer between the uart and the host using the dma controller and the usb buffer manager (ubm). a buffer of 512 bytes is reserved for buffering the uart channel (transmit and receive buffers). the uart channel has 64 bytes of double-buffer space (x- and y-buffer). when the dma writes to the x-buffer, the ubm reads from the y-buffer. similarly, when the dma reads from the x-buffer, the ubm writes to the y-buffer. the dma channel is configured to operate in the continuous mode (by setting dmacdr[cnt] = 1). once the mcu enables the dma, data transfer toggles between the umb and the dma without mcu intervention. see in transaction (TUSB3410 to host) for dma transfer-termination condition. 7.2.1 receiver data flow the uart receiver has a 32-byte fifo. the receiver fifo has two trigger levels. one is the high-level mark (halt), which is set to 28 bytes, and the other is the low-level mark (resume), which is set to 4 bytes. when the halt mark is reached, either the rts pin goes high or xoff is transmitted (depending on the auto setting). when the fifo reaches the resume mark, then either the rts pin goes low or xon is transmitted.
7 ? 11 64-byte y-buffer 64-byte x-buffer dma dmacdr ubm x/y 48 receiver halt on error or time-out rdr: 32-byte fifo rts /dtr = 1 or xoff transmitted rts /dtr = 0 or xon transmitted xoff/xon cts /dtr = 1/0 64-byte y-buffer 64-byte x-buffer dma dmacdr sin sout tdr pause/run host figure 7 ? 2. receiver/transmitter data flow 7.2.2 hardware flow control figure 7 ? 3 illustrates the connection necessary to achieve hardware flow control. the cts and rts signals are provided for this purpose. auto cts and auto rts (and xon/xoff) can be enabled/disabled independently by programming the fcrl register. TUSB3410 sin rts sout cts external device sout cts sin rts figure 7 ? 3. auto flow control interconnect 7.2.3 auto rts (receiver control) in this mode, the rts output pin signals the receiver-fifo status to an external device. the rts output signal is controlled by the high- and low-level marks of the fifo. when the high-level mark is reached, rts goes high, signaling to an external sending device to halt its transfer. conversely, when the low-level mark is reached, rts goes low, signaling to an external sending device to resume its transfer. data transfer from the fifo to the x-/y-buffer is performed by the dma controller. see out transaction (TUSB3410 to host) for dma transfer-termination condition. 7.2.4 auto cts (transmitter control) in this mode, the cts input pin controls the transfer from internal buffer (x or y) to the tdr. when the dma controller transfers data from the y-buffer to the tdr and the cts input pin goes high, the dma controller is suspended until cts goes low. meanwhile, the ubm is transferring data from the host to the x-buffer. when cts goes low, the dma resumes the transfer. data transfer continues alternating between the x- and y-buffers, without mcu intervention. see out transaction (TUSB3410 to host) for dma transfer-termination condition.
7 ? 12 7.2.5 xon/xoff receiver flow control to enable xon/xoff flow control, certain mcr bits must be set as follows: mcr[5] = 1 and mcr[7:6] = 0. in this mode, the xon/xoff bytes are transmitted to an external sending device to control the device ? s transmission. when the high-level mark (of the fifo) is reached, the xoff byte is transmitted, signaling to an external sending device to halt its transfer. conversely, when the low-level mark is reached, the xon byte is transmitted, signaling to an external sending device to resume its transfer. the data transfer from the fifo to x-/y-buffer is performed by the dma controller. 7.2.6 xon/xoff transmit flow control to enable xon/xoff flow control, certain mcr bits must be set as follows: mcr[5] = 1 and mcr[7:6] = 0. in this mode, the incoming data are compared to the xon and xoff registers. if a match to xoff is detected, the dma is paused. if a match to xon is detected, the dma resumes. meanwhile, the ubm is transferring data from the host to the x-buffer. the mcu does not switch the buffers unless the y-buffer is empty and the x-buffer is full. when xon is detected, the dma resumes the transfer.
8 ? 1 8 expanded gpio port 8.1 input/output and control registers the TUSB3410 has four general-purpose i/o pins (p3.0, p3.1, p3.3, p3.4) that are controlled by firmware running on the mcu. each pin can be controlled individually and each is implemented with a 12-ma push/pull cmos output with tristate control plus input. the mcu treats the outputs as open drain types in that the output can be driven low continuously, but a high output is driven for two clock cycles and then the output is tristated. an input pin can be read using the mov instruction. for example, mov c,p3.3 reads the input on p3.3. as a precaution, be certain the associated output is tristated before reading the input. an output can be set high (and then tristated) using the setb instruction. for example, setb p3.1 sets p3.1 high. an output can be set low using the clr instruction, as in clr p3.4, which sets p3.4 low (driven continuously until changed). each gpio pin has an associated internal pullup resistor. it is strongly recommended that the pullup resistor remain connected to the pin to prevent oscillations in the input buffer. the only exception is if an external source always drives the input. 8.1.1 pur_3: gpio pullup register for port 3 (addr:ff9e) 765 4 32 1 0 rsv rsv rsv rsv pin3 rsv pin1 pin0 r/o r/o r/o r/w r/w r/o r/w r/w bit name reset function 0 ? 7 pin n (n = 0 to 7) 0 the mcu may write to this register. if the mcu sets this bit to 1, the pullup resistor is disconnected from the pin. if the mcu clears this bit to 0, the pullup resistor is connected to the pin. the pullup resistor is connected to the v cc power supply.
8 ? 2
9 ? 1 9 interrupts 9.1 8052 interrupt and status registers all 8052 standard, five interrupt sources are preserved. sie is the standard interrupt-enable register that controls the five interrupt sources. all the additional interrupt sources are ored together to generate ex0. the xinto signal is provided to interrupt an external mcu (see figure 9 ? 1). table 9 ? 1. 8052 interrupt location map interrupt source description start address comments es uart interrupt 0023h et1 timer-1 interrupt 001bh ex1 external interrupt-1 0013h et0 timer-0 interrupt 000bh ex0 external interrupt-0 0003h used for all internal peripherals reset 0000h 9.1.1 8052 standard interrupt enable (sie) register 765 4 32 1 0 ea x x es et1 ex1 et0 ex0 r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 0 ex0 0 enable or disable external interrupt-0 ex0 = 1 ex0 = 1 external interrupt-0 is disabled external interrupt-0 is enabled 1 et0 0 enable or disable timer-0 interrupt et0 = 0 et0 = 1 timer-0 interrupt is disabled timer-0 interrupt is enabled 2 ex1 0 enable or disable external interrupt-1 ex1 = 0 ex1 = 1 external interrupt-1 is disabled external interrupt-1 is enabled 3 et1 0 enable or disable timer-1 interrupt et1 = 0 ex1 = 1 timer-1 interrupt is disabled timer-1 interrupt is enabled 4 es 0 enable or disable serial port interrupts es = 0 es = 1 serial-port interrupt is disabled serial-port interrupt is enabled 5, 6 rsv 0 reserved 7 ea 0 enable or disable all interrupts (global disable) ea = 0 ea = 1 disable all interrupts each interrupt source is individually controlled 9.1.2 additional interrupt sources all nonstandard 8052 interrupts (dma, i 2 c, etc.) are ored to generate an internal int0. note, the external int0 is not used. furthermore, the int0 must be programmed as an active low-level interrupt (not edge triggered). a vector interrupt register is provided to identify all interrupt sources (see vecint: vector-interrupt register ). up to 64 interrupt vectors are provided. it is the responsibility of the mcu to read the vector and dispatch to the proper interrupt routine.
9 ? 2 9.1.3 vecint: vector interrupt register (addr:ff92) this register contains a vector value, which identifies the internal interrupt source that trapped to location 0003h . writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is pending). note: the vector value is offset; therefore, its value is in increments of two (bit 0 is set to 0). when no interrupt is pending, the vector is set to 00h (see table 9 ? 2). as shown, the interrupt vector is divided to two fields: i[2:0] and g[3:0]. the i field defines the interrupt source within a group (on a first-come-first-served basis). in the g field, which defines the group number, group g0 is the lowest, and g15 is the highest priority. 765 4 32 1 0 g3 g2 g1 g0 i2 i1 i0 0 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 3 ? 1 i[2:0] 0h this field defines the interrupt source in a given group. see table 9 ? 2. bit 0 = 0 always; therefore, vector values are offset by two. 7 ? 4 g[3:0] 0h this field defines the interrupt group. i[2:0] and g[3:0] combine to produce the actual interrupt vector. table 9 ? 2. vector interrupt values g[3:0] (hex) i[2:0] (hex) vector (hex) interrupt source 0 0 00 no interrupt 1 0 10 not used 1 1 1 1 2 3 12 14 16 output endpoint-1 output endpoint-2 output endpoint-3 2 0 20 not used 2 2 2 3 3 3 3 3 3 3 3 1 2 3 0 1 2 3 4 5 6 7 22 24 26 30 32 34 36 38 3a 3c 3e input endpoint-1 input endpoint-2 input endpoint-3 stpow packet received setup packet received reserved reserved resr interrupt susr interrupt rstr interrupt reserved 4 4 4 4 0 1 2 3 40 42 44 46 i 2 c txe interrupt i 2 c rxf interrupt input endpoint-0 output endpoint-0 4 4 ? 7 48 4e not used 5 5 5 0 1 4 ? 7 50 52 58 5e uart status interrupt uart modem interrupt not used 6 6 6 7 0 1 4 ? 7 5 ? 7 60 62 68 6e 70 7e uart rxf interrupt uart txe interrupt not used not used 8 8 8 0 2 5 ? 7 80 84 88 ? 8e dma1 interrupt dma3 interrupt not used 9 ? 15 x 90 fe not used
9 ? 3 9.1.4 logical interrupt connection diagram (internal/external) figure 9 ? 1 shows the logical connection of the interrupt sources and its relation with xinto . the priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). the interrupt priorities are hard wired. vector 0x88 is the highest and 0x12 is the lowest. priority encoder interrupts ieo (int0) xinto ieo vector figure 9 ? 1. internal vector interrupt
9 ? 4
10 ? 1 10 i 2 c-port 10.1 i 2 c registers 10.1.1 i2csta: i 2 c status and control register (addr:fff0) this register is used to control the stop condition for read and write operations. in addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits. 765 4 32 1 0 rxf rie err 1/4 txe tie srd swr r/o r/w r/c r/w r/o r/w r/w r/w bit name reset function 0 swr 0 stop write condition. this bit determines if the i 2 c controller generates a stop condition when data from the i2cdao register is transmitted to an external device. swr = 0 stop condition is not generated when data from the i2cdao register is shifted out to an external device. swr = 1 stop condition is generated when data from the i2cdao register is shifted out to an external device. 1 srd 0 stop read condition. this bit determines if the i 2 c controller generates a stop condition when data is received and loaded into the i2cdai register. srd = 0 stop condition is not generated when data from the sda line is shifted into the i2cdai register. srd = 1 stop condition is generated when data from the sda line are shifted into the i2cdai register. 2 tie 0 i 2 c transmitter empty interrupt enable tie = 0 tie = 1 interrupt disable interrupt enable 3 txe 1 i 2 c transmitter empty. this bit indicates that data can be written to the transmitter. it can be used for polling or it can generate an interrupt. txe = 0 transmitter is full. this bit is cleared when the mcu writes a byte to the ii2cdao register. txe = 1 transmitter is empty. the i 2 c controller sets this bit when the contents of the i2cdao register are copied to the sda shift register. 4 1/4 0 bus speed selection 1/4 = 0 1/4 = 1 100-khz bus speed 400-khz bus speed 5 err 0 bus error condition. this bit is set by the hardware when the device does not respond. it is cleared by the mcu. err = 0 no bus error err = 1 bus error condition has been detected. clears when the mcu writes a 1. writing a 0 has no effect. 6 rie 0 i 2 c receiver ready interrupt enable rie = 0 rie = 1 interrupt disable interrupt enable 7 rxf 0 i 2 c receiver full. this bit indicates that the receiver contains new data. it can be used for polling or it can generate an interrupt. rxf = 0 receiver is empty. this bit is cleared when the mcu reads the i2cdai register. rxf = 1 receiver contains new data. this bit is set by the i 2 c controller when the received serial data has been loaded into the i2cdai register.
10 ? 2 10.1.2 i2cadr: i 2 c address register (addr:fff3) this register holds the device address and the read/write command bit. 765 4 32 1 0 a6 a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name reset function 0 r/w 0 read/write command bit r/w = 0 r/w = 1 write operation read operation 7 ? 1 a[6:0] 0h seven address bits for device addressing 10.1.3 i2cdai: i 2 c data-input register (addr:fff2) this register holds the received data from an external device. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 r/o r/o r/o r/o r/o r/o r/o r/o bit name reset function 7 ? 0 d[7:0] 0 8-bit input data from an i 2 c device 10.1.4 i2cdao: i 2 c data-output register (addr:fff1) this register holds the data to be transmitted to an external device. writing to this register starts the transfer on the sda line. 765 4 32 1 0 d7 d6 d5 d4 d3 d2 d1 d0 w/o w/o w/o w/o w/o w/o w/o w/o bit name reset function 7 ? 0 d[7:0] 0 8-bit output data to an i 2 c device 10.2 random-read operation a random read requires a dummy byte-write sequence to load in the data word address. once the device-address word and the data-word address are clocked out and acknowledged by the device, the mcu starts a current-address sequence. the following describes the sequence of events to accomplish this transaction. device address + eprom [high byte] ? the mcu sets i2csta[srd] = 0. this forces the i 2 c controller not to generate a stop condition after the contents of the i2cdai register are received. ? the mcu sets i2csta[swr] = 0. this forces the i 2 c controller not to generate a stop condition after the contents of the i2cdao register are transmitted. ? the mcu writes the device address (r/w bit = 0) to the i2cadr register (write operation) ? the mcu writes the high byte of the e2prom address into the i2cdao register (this starts the transfer on the sda line). ? the txe bit in the i2csta register is cleared (indicates busy). ? the content of the i2cadr register is transmitted to e2prom (preceded by start condition on sda).
10 ? 3 ? the contents of the i2cdao register are transmitted to e2prom. (eprom address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register has been transmitted. ? a stop condition is not generated. eprom [low byte] ? the mcu writes the low byte of the e2prom address into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cdao register are transmitted to the device (e2prom address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register has been transmitted. ? this completes the dummy write operation. at this point, the e2rom address is set and the mcu can do either a single- or a sequential-read operation. 10.3 current-address read operation once the e 2 prom address is set, the mcu can read a single byte by executing the following steps: ? the mcu sets i2csta[srd] = 1. this forces the i 2 c controller to generate a stop condition after the i2cdai-register contents are received. ? the mcu writes the device address (r/w bit = 1) to the i2cadr register (read operation). ? the mcu writes a dummy byte to the i2cdao register (this starts the transfer on sda line). ? the rxf bit in the i2csta register is cleared. ? the contents of the i2cadr register are transmitted to the device (preceded by start condition on sda). ? the data from e2prom are latched into the i2cdai register (stop condition is transmitted). ? the rxf bit in the i2csta register is set and interrupts the mcu, indicating that the data are available. ? the mcu reads the i2cdai register. this clears the rxf bit (i2csta[rxf] = 0). ? end 10.4 sequential-read operation once the e 2 prom address is set, the mcu can execute a sequential read operation by executing the following (this example illustrates a 32-byte sequential read): device address ? the mcu sets i2csta[srd] = 0. this forces the i 2 c controller not to generate a stop condition after the i2cdai register contents are received. ? the mcu writes the device address (r/w bit = 1) to the i2cadr register (read operation). ? the mcu writes a dummy byte to the i2cdao register (this starts the transfer on the sda line). ? the rxf bit in the i2csta register is cleared. ? the contents of the i2cadr register are transmitted to the device (preceded by start condition on sda). n-byte read (31 bytes) ? the data from the device are latched into the i2cdai register (stop condition is not transmitted). ? the rxf bit in the i2csta register is set and interrupts the mcu, indicating that data are available. ? the mcu reads the i2cdai register. this clears the rxf bit (i2csta[rxf] = 0). ? this operation repeats 31 times. last-byte read (byte 32) ? mcu sets i2csta[srd] = 1. this forces the i 2 c controller to generate a stop condition after the i2cdai register contents are received.
10 ? 4 ? the data from the device is latched into the i2cdai register (stop condition is transmitted). ? the rxf bit in the i2csta register is set and interrupts the mcu, indicating that data are available. ? the mcu reads the i2cdai register. this clears the rxf bit (i2csta[rxf] = 0) ? end 10.5 byte-write operation the byte-write operation involves three phases: device address + eprom [high byte] phase , eprom [low byte] phase, and eprom [data] phase. the following describes the sequence of events to accomplish the byte-write transaction. device address + eprom [high byte] ? the mcu sets i2csta[swr] = 0. this forces the i 2 c controller to not generate a stop condition after the contents of the i2cdao register are transmitted. ? the mcu writes the device address (r/w bit = 0) to the i2cadr register (write operation). ? the mcu writes the high byte of the e2prom address into the i2cdao register (this starts the transfer on the sda line). ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cadr register are transmitted to the device (preceded by start condition on sda). ? the contents of the i2cdao register are transmitted to the device (e2prom high address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. eprom [low byte] ? the mcu writes the low byte of the e2prom address into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicating busy). ? the contents of the i2cdao register are transmitted to the device (e2prom address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. eprom [data] ? the mcu sets i2csta[swr] = 1. this forces the i 2 c controller to generate a stop condition after the contents of i2cdao register are transmitted. ? the the data to be written to e2prom is written by the mcu into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cdao register are transmitted to the device (e2prom data). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. ? the i 2 c controller generates a stop condition after the contents of the i2cdao register are transmitted. ? end
10 ? 5 10.6 page-write operation the page-write operation is initiated in the same way as byte write, with the exception that a stop condition is not generated after the first eprom [data] is transmitted. the following describes the sequence of writing 32 bytes in page mode. device address + eprom [high byte] ? the mcu sets i2csta[swr] = 0. this forces the i 2 c controller not to generate a stop condition after the contents of the i2cdao register are transmitted. ? the mcu writes the device address (r/w bit = 0) to the i2cadr register (write operation). ? the mcu writes the high byte of the e2prom address into the i2cdao register ? the txe bit in the i2csta register is cleared (indicating busy). ? the contents of the i2cadr register are transmitted to the device (preceded by start condition on sda). ? the contents of the i2cdao register are transmitted to the device (e2prom address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. eprom [low byte] ? the mcu writes the low byte of the e2prom address into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cdao register are transmitted to the device (e2prom address). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. eprom [data] ? 31 bytes ? the data to be written to the e2prom are written by the mcu into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cdao register are transmitted to the device (e2prom data). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. ? this operation repeats 31 times. eprom [data] ? last byte ? the mcu sets i2csta[swr] = 1. this forces the i 2 c controller to generate a stop condition after the contents of the i2cdao register are transmitted. ? the mcu writes the last date byte to be written to the e2prom, into the i2cdao register. ? the txe bit in the i2csta register is cleared (indicates busy). ? the contents of the i2cdao register are transmitted to e2prom (e2prom data). ? the txe bit in the i2csta register is set and interrupts the mcu, indicating that the i2cdao register contents have been transmitted. ? the i 2 c controller generates a stop condition after the contents of the i2cdao register are transmitted. ? end of 32-byte page-write operation.
10 ? 6
11 ? 1 11 TUSB3410 bootcode flow 11.1 introduction TUSB3410 bootcode is a program embedded within TUSB3410 device. this program is designed to load application firmware from either external memory device or usb host bootloader device driver. after finished downloading, bootcode releases its control to the application firmware. this document describes how the bootcode initializes the TUSB3410 device in detail. in addition, the default usb descriptor, i 2 c device header format, usb host driver firmware downloading format, and supported built-in usb vendor specific requests are listed for reference. users should carefully follow the appropriate format to interface with the bootcode. all unsupported formats might cause unexpected results. the bootcode source code is also provided for programming reference. 11.2 bootcode programming flow after power-on reset, the bootcode initializes the i 2 c and usb registers along with internal variables. the bootcode then checks to see if the i 2 c device contains a valid signature. if the i 2 c device has a valid signature, the bootcode continues searching for descriptor blocks and then processes them if the checksum is correct. if application firmware was found, the bootcode downloads it and releases the control to the application firmware. otherwise, the bootcode connects to the usb and waits for host driver to download application firmware. once firmware downloading is finished, the bootcode releases the control to the firmware. the following is the bootcode step-by-step operation. ? check if bootcode is in the application mode. if the bootcode is in the application mode, the bootcode releases the control to the application firmware. otherwise, the bootcode continues. ? initialize all the default settings. ? call copydefaultsettings() routine. set i 2 c to 400-khz speed. ? call usbdatainitialization() routine. set bfunadr = 0 disconnect from usb (busbctl = 0x00) bootcode handles usb reset copy predefined device, configuration, and string descriptors to ram disable all endpoints and enable usb interrupt(setup, rstr, suspr, and resu) ? search for product signature ? check if valid signature is in i 2 c. if not, skip i 2 c process. read 2 bytes from address 0x0000 with type iii and device address 0. stop searching if valid signature is found. read 2 bytes from address 0x0000 with type ii and device address 4. stop searching if valid signature is found. ? load customized device, configuration and string descriptors from i 2 c eeprom. ? process each descriptor block from i 2 c until end of header is found if descriptor block is device, configuration or string descriptors, the bootcode overwrites the default descriptors. if descriptor block is binary firmware, the bootcode makes a note and loads the firmware later on.
11 ? 2 if descriptor block is auto-execution firmware, the bootcode loads it and releases the control to the firmware. if descriptor block is end of header , the bootcode stops searching. ? set header pointer to the beginning of the binary firmware in i 2 c eeprom. ? enable global and usb interrupts and set connection bit to 1. ? set global interrupt bit. ea = 1. ? set internal interrupt bit. ex0 = 1. ? set connection bit. cont = 1. ? wait for any interrupt events until get device desciptor setup packet arrives. ? suspend interrupt set idle = 1 to enter suspend mode. usb reset wakes up the microcontroller. ? resume interrupt bootcode wakes up and waits for new usb requests. ? reset interrupt call usbreset() routine. ? setup interrupt bootcode process the request. ? reboot if reboot=1, disconnect from usb and restart at address 0x0000. ? download firmware from i 2 c eeprom ? disable global interrupt. reset ea = 0. ? load firmware to xdata space if available. ? download firmware from usb. ? if no firmware in i 2 c eeprom, host downloads firmware via output endpoint 1. ? in the first data packet to output endpoint 1, host driver add 3 bytes before the application firmware in binary format. these three bytes are lsb and msb of firmware size and then arithmetic checksum of binary firmware. ? release control to firmware. ? update usb configuration and interface number. ? release control to application firmware. ? application firmware ? either disconnect from bus or continue responding to usb requests. 11.3 default bootcode settings the bootcode has its own predefined device, configuration, and string descriptors. these default descriptors should be used in evaluation only. they should not be used in end-user product.
11 ? 3 11.3.1 device descriptor device descriptor describes the usb version that the device supports, device class, protocol, vendor, product identifications, strings, and number of configuration. the os (operation system like windows, mac, or linux) reads this descriptor to decide which device driver should be used to communicate to this device. the bootcode uses 0x0451(texas instruments) as vendor id and 0x3410(TUSB3410) as product id. it also supports three different strings and one configuration. table 11 ? 1 lists the device descriptor. table 11 ? 1. device descriptor offset field size value description 0 blength 1 0x12 size of this descriptor in bytes 1 bdescriptortype 1 1 device descriptor type 2 bcdusb 2 0x0110 usb spec 1.1 4 bdeviceclass 1 0xff device class is vendor ? specific 5 bdevicesubclass 1 0 we have no subclasses. 6 bdeviceprotocol 1 0 we use no protocols. 7 bmaxpacketsize0 1 8 max. packet size for endpoint zero 8 idvendor 2 0x0451 usb ? assigned vendor id = ti 10 idproduct 2 0x3410 ti part number = TUSB3410 12 bcddevice 2 0x100 device release number = 1.0 14 imanufacturer 1 1 index of string descriptor describing manufacturer 15 iproducct 1 2 index of string descriptor describing product 16 iserialnumber 1 3 index of string descriptor describing device ? s serial number 17 bnumconfigurations 1 1 number of possible configurations: 11.3.2 configuration descriptor the configuration descriptor describes the number of interfaces supported by this configuration, power configuration, and current consumption. the bootcode declares only one interface running in bus-powered mode. it consumes up to 100 ma at boot time. table 11 ? 2 lists the configuration descriptor. table 11 ? 2. configuration descriptor offset field size value description 0 blength 1 9 size of this descriptor in bytes. 1 bdescriptor type 1 2 configuration descriptor type 2 wtotallength 2 25 = 9 + 9 + 7 total length of data returned for this configuration. includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. 4 bnuminterfaces 1 1 number of interfaces supported by this configuration 5 bconfigurationvalue 1 1 value to use as an argument to the setconfiguration() request to select this configuration. 6 iconfiguration 1 0 index of string descriptor describing this configuration. 7 bmattributes 1 0x80 configuration characteristics d7: reserved (set to one) d6: self-powered d5: remote wakeup is supported d4 ? 0: reserved (reset to zero) 8 bmaxpower 1 0x32 this device consumes 100 ma.
11 ? 4 11.3.3 interface descriptor the interface descriptor describes the number of endpoints supported by this interface as well as interface class, subclass, and protocol. the bootcode supports only one endpoint and use its own class. table 11 ? 3 lists the interface descriptor. table 11 ? 3. interface descriptor offset field size value description 0 blength 1 9 size of this descriptor in bytes 1 bdescriptortype 1 4 interface descriptor type 2 binterfacenumber 1 0 number of interface. zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. 3 balternatesetting 1 0 value used to select alternate setting for the interface identified in the prior field 4 bnumendpoints 1 1 number of endpoints used by this interface (excluding endpoint zero). if this value is zero, this interface only uses the default control pipe. 5 binterfaceclass 1 0xff the interface class is vendor specific. 6 binterfacesubclass 1 0 7 binterfaceprotocol 1 0 8 iinterface 1 0 index of string descriptor describing this interface 11.3.4 endpoint descriptor the endpoint descriptor describes the type and size of communication pipe supported by this endpoint. the bootcode supports only one output endpoint with the size of 64 bytes in addition to control endpoint 0 (required by all usb devices). table 11 ? 4 lists the endpoint descriptor. table 11 ? 4. output endpoint1 descriptor offset field size value description 0 blength 1 7 size of this descriptor in bytes 1 bdescriptortype 1 5 endpoint descriptor type 2 bendpointaddress 1 0x01 bit 3 0: the endpoint number bit 7: direction 0 = out endpoint 1 = in endpoint 3 bmattributes 1 2 bit 1 0: transfer type 10 = bulk 11 = interrupt 4 wmaxpacketsize 2 64 maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. 6 binterval 1 0 interval for polling endpoint for data transfers. expressed in milliseconds.
11 ? 5 11.3.5 string descriptor the string descriptor contains string in the unicode format. it is used to show the manufacturers name, product model, and serial number in human readable format. the bootcode supports three strings. the first string is the manufacturers name, the second string is the product name, and the last string is the serial number. table 11 ? 5 lists the string descriptor. table 11 ? 5. string descriptor offset field size value description 0 blength 1 4 size of string 0 descriptor in bytes 1 bdescriptortype 1 0x03 string descriptor type 2 wlangid[0] 2 0x0409 english 4 blength 1 36 size of string 1 descriptor in bytes 5 bdescriptortype 1 0x03 string descriptor type 6 bstring 2 ? t ? ,0x00 unicode, t is the first byte 8 2 ? e ? ,0x00 texas instruments 10 2 ? x ? ,0x00 12 2 ? a ? ,0x00 14 2 ? s ? ,0x00 16 2 ? ? ,0x00 18 2 ? i ? ,0x00 20 2 ? n ? ,0x00 22 2 ? s ? ,0x00 24 2 ? t ? ,0x00 26 2 ? r ? ,0x00 28 2 ? u ? ,0x00 30 2 ? m ? ,0x00 32 2 ? e ? ,0x00 34 2 ? n ? ,0x00 36 2 ? t ? ,0x00 38 2 ? s ? ,0x00 40 blength 1 42 size of string 2 descriptor in bytes 41 bdescriptortype 1 0x03 string descriptor type 42 bstring 2 ? t ? ,0x00 unicode, t is first byte 44 2 ? u ? ,0x00 TUSB3410 boot device 46 2 ? s ? ,0x00 48 2 ? b ? ,0x00 50 2 ? 3 ? ,0x00 52 2 ? 4 ? ,0x00 54 2 ? 1 ? ,0x00 56 2 ? 0 ? ,0x00 58 2 ? ? ,0x00 60 2 ? b ? ,0x00 62 2 ? o ? ,0x00 64 2 ? o ? ,0x00 66 2 ? t ? ,0x00 68 2 ? ? ,0x00 70 2 ? d ? ,0x00
11 ? 6 table 11 ? 5. string descriptor (continued) offset field size value description 72 2 ? e ? ,0x00 74 2 ? v ? ,0x00 76 2 ? i,0x00 78 2 ? c ? ,0x00 80 2 ? e ? ,0x00 82 blength 1 34 size of string 3 descriptor in bytes 84 bdescriptortype 1 0x03 string descriptor type 86 bstring 2 r0,0x00 unicode 88 2 r1,0x00 r0 to rf are bcd of sernum0 to 90 2 r2,0x00 sernum7 registers. 16 digit hex 92 2 r3,0x00 16 digit hex numbers are created from 94 2 r4,0x00 sernum0 to sernum7 registers 96 2 r5,0x00 98 2 r6,0x00 100 2 r7,0x00 102 2 r8,0x00 104 2 r9,0x00 106 2 ra,0x00 108 2 rb,0x00 110 2 rc,0x00 112 2 rd,0x00 114 2 re,0x00 116 2 rf,0x00 11.4 external device header format the header can be restored in various storage devices such as rom, parallel/serial eeprom, i 2 c, or flash rom. a valid header should contain a product signature and one or more descriptor blocks. the descriptor block contains the descriptor prefix and content. in the descriptor prefix, the data type, size, and checksum are specified to describe the content. the descriptor content contains the necessary information for the bootcode to process. the header processing routine always counts from the first descriptor block until the desired block number is reached. the header reads in descriptor prefix with the size of 4 bytes. this prefix contains the type of block, size, and checksum. for example, if the bootcode would like to find the position on third descriptor block, it reads in the first descriptor prefix, calculates the position on the second descriptor prefix based on the size specified in the prefix. bootcode, then repeats the same calculation to find out the position of the third descriptor block. note that the header-processing routine of the TUSB3410 only supports the i 2 c device. no other storage device should be used to store header information. 11.4.1 product signature the product signature should be stored at the first 2 bytes of storage device. these 2 bytes should match the product number. the order of these 2 bytes should be the lsb first and then the msb. for example, ump (tusb5152) is 0x5152. therefore, the first byte should be 0x52 and the second byte should be 0x51. the TUSB3410 bootcode searches the first 2 bytes of the i 2 c device. if the first 2 bytes are not 0x10 and 0x34, the bootcode skips the header processing.
11 ? 7 11.4.2 descriptor block each descriptor block contains prefix and content. the size of the prefix is always 4 bytes. it contains the data type, size, and checksum for data integrity. the descriptor content contains the corresponding information specified in the prefix. it could be as small as 1 byte or as large as 65535 bytes. the next descriptor immediately follows the previous descriptor. if there are no more descriptors, an extra byte with a value of zero should be added to indicate the end of header. 11.4.2.1 descriptor prefix the first byte of the descriptor prefix is the data type. this tells the bootcode how to process the data in the descriptor content. the second and third bytes are the size of descriptor content. the second byte is the low byte of the size and the third byte is the high byte. the last byte is the 8-bit arithmetic checksum of descriptor content. 11.4.2.2 descriptor content information stored in the descriptor content can be the usb information, firmware, or other type of data. the size of the content should be from 1 byte to 65535 bytes. 11.5 checksum in descriptor block each descriptor prefix contains one checksum of the descriptor content. if the checksum is wrong, the bootcode simply ignores the descriptor block. 11.6 header examples the header can be specified in different ways. the following descriptors show examples of the header format and the supported descriptor block. 11.6.1 TUSB3410 bootcode supported descriptor block the TUSB3410 bootcode supports the following descriptor blocks. ? usb device descriptor ? usb configuration descriptor ? usb string descriptor ? binary firmware 1 ? autoexec binary firmware 2 1 binary firmware is loaded when the bootcode receives the first get device descriptor request from host. downloading the firmware should either continue that request in the data stage or disconnect from the usb and then reconnect to the usb as a new device. 2 the bootcode loads this autoexec binary firmware before it connects to the usb. the firmware should connect to the usb once it is loaded.
11 ? 8 11.6.2 usb descriptor header table 11 ? 6 contains the usb device, configuration, and string descriptors for the bootcode. the last byte is zero to indicate the end of header. table 11 ? 6. usb descriptors header offset type size value description 0 signature0 1 0x10 function_pid_l 1 signature1 1 0x34 function_pid_h 2 data type 1 0x03 usb device descriptor 3 data size (low byte) 1 0x12 the device descriptor is 18 bytes. 4 data size (high byte) 1 0x00 5 check sum 1 0xcc checksum of data below 6 blength 1 0x12 size of device descriptor in bytes 7 bdescriptortype 1 0x01 device descriptor type 8 bcdusb 2 0x0110 usb spec 1.1 10 bdeviceclass 1 0xff device class is vendor-specific 11 bdevicesubclass 1 0x00 we have no subclasses. 12 bdeviceprotocol 1 0x00 we use no protocols 13 bmaxpacketsize0 1 0x08 maximum packet size for endpoint zero 14 idvendor 2 0x0451 usb ? assigned vendor id = ti 16 idproduct 2 0x3410 ti part number = TUSB3410 18 bcddevice 2 0x0100 device release number = 1.0 20 imanufacturer 1 0x01 index of string descriptor describing manufacturer 21 iproducct 1 0x02 index of string descriptor describing product 22 iserialnumber 1 0x03 index of string descriptor describing device ? s serial number 23 bnumconfigurations 1 0x01 number of possible configurations: 24 data type 1 0x04 usb configuration descriptor 25 data size (low byte) 1 0x19 25 bytes 26 data size (high byte) 1 0x00 27 check sum 1 0xc6 checksum of data below 28 blength 1 0x09 size of this descriptor in bytes 29 bdescriptortype 1 0x02 configuration descriptor type 30 wtotallength 2 25(0x19) = 9 + 9 + 7 total length of data returned for this configuration. includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. 32 bnuminterfaces 1 0x01 number of interfaces supported by this configuration 33 bconfigurationvalue 1 0x01 value to use as an argument to the setconfiguration() request to select this configuration 34 iconfiguration 1 0x00 index of string descriptor describing this configuration. 35 bmattributes 1 0xe0 configuration characteristics d7: reserved (set to one) d6: self ? powered d5: remote wakeup is supported d4 ? 0: reserved (reset to zero) 36 bmaxpower 1 0x64 this device consumes 100 ma. 37 blength 1 0x09 size of this descriptor in bytes 38 bdescriptortype 1 0x04 interface descriptor type 39 binterfacenumber 1 0x00 number of interface. zero-based value identifying the index in the array of concurrent interfaces supported by this configuration.
11 ? 9 table 11 ? 6. usb descriptors header (continued) offset type size value description 40 balternatesetting 1 0x00 value used to select alternate setting for the interface identified in the prior field 41 bnumendpoints 1 0x01 number of endpoints used by this interface (excluding endpoint zero). if this value is zero, this interface only uses the default control pipe. 42 binterfaceclass 1 0xff the interface class is vendor specific. 43 binterfacesubclass 1 0x00 44 binterfaceprotocol 1 0x00 45 iinterface 1 0x00 index of string descriptor describing this interface 46 blength 1 0x07 size of this descriptor in bytes 47 bdescriptortype 1 0x05 endpoint descriptor type 48 bendpointaddress 1 0x01 bit 3 0: the endpoint number bit 7: direction 0 = out endpoint 1 = in endpoint 49 bmattributes 1 0x02 bit 1 0: transfer type 10 = bulk 11 = interrupt 50 wmaxpacketsize 2 0x0040 maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. 52 binterval 1 0x00 interval for polling endpoint for data transfers. expressed in milliseconds. 53 data type 1 0x05 usb string descriptor 54 data size (low byte) 1 0x1a 26(0x1a) = 4 + 6 + 6 + 10 55 data size (high byte) 1 0x00 56 check sum 1 0x50 checksum of data below 57 blength 1 0x04 size of string 0 descriptor in bytes 58 bdescriptortype 1 0x03 string descriptor type 59 wlangid[0] 2 0x0409 english 61 blength 1 0x06 size of string 1 descriptor in bytes 62 bdescriptortype 1 0x03 string descriptor type 63 bstring 2 ? t ? ,0x00 unicode, ? t ? is the first byte. 65 2 ? i ? ,0x00 ti = 0x54, 0x49 67 blength 1 0x06 size of string 2 descriptor in bytes 68 bdescriptortype 1 0x03 string descriptor type 69 bstring 2 ? u ? ,0x00 unicode, ? u ? is the first byte. 71 2 ? c ? ,0x00 ? uc ? = 0x75, 0x43 73 blength 1 0x0a size of string 3 descriptor in bytes 74 bdescriptortype 1 0x03 string descriptor type 75 bstring 2 ? 3 ? ,0x00 unicode, ? t ? is the first byte. 77 2 ? 4 ? ,0x00 ? 3410 ? = 0x33, 0x34, 0x31, 0x30 79 2 ? 1 ? ,0x00 81 2 ? 0 ? ,0x00 83 data type 1 0x00 end of header
11 ? 10 11.6.3 autoexec binary firmware if the application requires firmware loaded prior to usb connection, the following header can be used. the bootcode loads the firmware and release the control to the firmware directly without connecting to the usb. however, per the usb specification requirement, any usb device should connect to the bus and respond to the host within the first 100 ms. therefore, if downloading time is more than 100 ms, the usb and header speed descriptor blocks should be added before the autoexec binary firmware. table 11 ? 7 shows an example of autoexec binary firmware header. table 11 ? 7. autoexec binary firmware offset type size value description 0x0000 signature0 1 0x10 function_pid_l 0x0001 signature1 1 0x34 function_pid_h 0x0002 data type 1 0x07 autoexec binary firmware 0x0003 data size (low byte) 1 0x67 0x4567 bytes of application code 0x0004 data size (high byte) 1 0x45 0x0005 check sum 1 0xnn checksum of the following firmware 0x0006 program 0x4567 binary application code 0x456d data type 1 0x00 end of header 11.7 host driver downloading header format if firmware downloading from the host driver is desired, the host driver should follow the format in table 11 ? 8. the texas instruments bootloader driver generates the proper format. therefore, users only need to provide the binary image of the application firmware for the bootloader. if the checksum is wrong, the bootcode disconnects from the usb and waits before it reconnects to the usb. table 11 ? 8. host driver downloading format offset type size value description 0x0000 firmware size (low byte) 1 0xxx application firmware size 0x0001 firmware size (low byte) 1 0xyy 0x0002 checksum 1 0xzz checksum of binary application code 0x0003 program 0xyyxx binary application code
11 ? 11 11.8 built-in vendor specific usb requests the bootcode supports several vendor specific usb requests. these requests are primarily for internal testing only. these functions should not be used in normal operation. 11.8.1 reboot the reboot command forces the bootcode to reboot. the bootcode starts over. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_out 01000000b brequest btc_reboot 0x85 wvalue none 0x0000 windex none 0x0000 wlength none 0x0000 data none 11.8.2 force execute firmware the force execute firmware command requests the bootcode to execute the downloaded firmware unconditionally. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_out 01000000b brequest btc_force_execute_firmware 0x8f wvalue none 0x0000 windex none 0x0000 wlength none 0x0000 data none 11.8.3 external memory read the bootcode returns the content of the specified address. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_in 11000000b brequest btc_exeternal_memory_read 0x90 wvalue none 0x0000 windex data address 0xnnnn (from 0x0000 to 0xffff) wlength 1 byte 0x0001 data byte in the specified address 0xnn 11.8.4 external memory write the external memory write command tells the bootcode to write data to the specified address. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_out 01000000b brequest btc_exeternal_memory_write 0x91 wvalue hi: 0x00 lo: data 0x00nn windex data address 0xnnnn (from 0x0000 to 0xffff) wlength none 0x0000 data none
11 ? 12 11.8.5 i 2 c memory read the bootcode returns the content of the specified address in i 2 c eeprom. in the wvalue field, the i 2 c device number is from 0x00 to 0x07 in high filed. the memory type is from 0x01 to 0x03 for cat i to cat iii devices. if bit 7 of bvaluel is set, then 400 khz is used. otherwise, 100 khz is used. this request is also used to set the device number and speed before the i 2 c write request. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_in 11000000b brequest btc_i2c_memory_read 0x92 wvalue hi: i 2 c device number lo: memory type bit[1:0] speed bit[7] 0xxxyy windex data address 0xnnnn (from 0x0000 to 0xffff) wlength 1 byte 0x0001 data byte in the specified address 0xnn 11.8.6 i 2 c memory write the i 2 c memory write command tells the bootcode to write data to the specified address. the spi mode setting is done in the spi read command. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_out 01000000b brequest btc_i2c_memory_write 0x93 wvalue hi: should be zero lo: data 0x00nn windex data address 0xnnnn (from 0x0000 to 0xffff) wlength none 0x0000 data none 11.8.7 internal rom memory read the bootcode returns the byte of the specified address in rom. that is, the binary code of the bootcode. bmrequesttype usb_req_type_device | usb_req_type_vendor | usb_req_type_out 01000000b brequest btc_internal_rom_memory_read 0x94 wvalue none 0x0000 windex data address 0xnnnn (from 0x0000 to 0xffff) wlength 1 byte 0x0001 data byte in the specified address 0xnn
11 ? 13 11.9 bootcode programming consideration 11.9.1 usb requests for each usb request, the bootcode follows the steps below to ensure proper operation of the hardware. 1. determine the direction of the request by checking the msb of the bmrequesttype field and set the usbctl_dir bit accordingly. 2. decode the command 3. if another setup is pending, then return. otherwise, serve the request. 4. check again, if another setup is pending then go to step 2. 5. clear the interrupt source and then the vecint register. 6. exit the interrupt routine. 11.9.1.1 usb requests the usb request consist of three types of transfers. they are control-read-with-data-stage, control-write- without-data-stage, and control-write-with-data-stage transfer. in each transfer, arrows indicate interrupts generated after receiving the setup packet, in or out token. figure 11 ? 1 and figure 11 ? 2 show the usb data flow and how the hardware and firmware respond to the usb requests. table 11 ? 9 and table 11 ? 10 lists the bootcode reposes to the standard usb requests. setup (0) in(1) in(0) in(0/1) out(1) int int int int more packets setup stage data stage statusstage 1.hardware generates interrupt to mcu. 2.hardware sets nak on both endpoints. 3.set dir bit in usbctl to indicate the data directory. 3.decode the setup packet 4.if another setup packet arrives, abandon this one. 5.executes appropriate routines. a) clear nak bit in out endpoint. b) copy data to in endpoint buffer and set byte count. 1.hardware generates interrupt to mcu. 2.copy data to in buffer. 3.clear the nak bit. 4.if all data has been sent out, stall input endpoint. 1.hardware does not generate interrupt to mcu. figure 11 ? 1. control read transfer
11 ? 14 table 11 ? 9. bootcode response to control read transfer control read action in bootcode get status of device return power and remote wakeup settings get status of interface return 2 bytes of zeros get status of endpoint return endpoint status get descriptor of device return device descriptor get descriptor of configuration return configuration descriptor get descriptor of string return string descriptor get descriptor of interface stall get descriptor of endpoint stall get configuration return bconfigurednumber value get interface return binterfacenumber value setup (0) in(1) int setup stage status stage 1.hardware generates interrupt to mcu. 2.hardware sets nak on both endpoints. 3.set dir bit in usbctl to indicate the data directory. 3.decode the setup packet 4.if another setup packet arrives, abandon this one. 5.executes appropriate routines. a) clear nak bit in in endpoint. b) keep a note so in interrupt routine can take proper action to the request. 1.hardware does not generates interrupt to mcu. figure 11 ? 2. control write transfer without data stage table 11 ? 10. bootcode response to control write without data stage control write without data stage action in bootcode clear feature of device stall clear feature of interface stall clear feature of endpoint clear endpoint stall set feature of device stall set feature of interface stall set feature of endpoint stall endpoint set address set device address set descriptor stall set configuration set bconfigurednumber set interface setbinterfacenumber sync. frame stall
11 ? 15 11.9.1.2 interrupt handling routine the higher-vector number has a higher priority than the lower-vector number. table 11 ? 11 lists all the interrupts and source of interrupts. table 11 ? 11. vector interrupt values and sources g[3:0] (hex) i[2:0] (hex) vector (hex) interrupt source interrupt source should be cleared 0 0 00 no interrupt no source 1 1 10 output ? endpoint ? 1 vecint register 1 2 12 output ? endpoint ? 2 vecint register 1 3 14 output ? endpoint ? 3 vecint register 1 4 16 output ? endpoint ? 4 vecint register 2 4 ? 7 18 1e not used 2 1 20 input ? endpoint ? 1 vecint register 2 2 22 input ? endpoint ? 2 vecint register 2 3 24 input ? endpoint ? 3 vecint register 2 4 26 input ? endpoint ? 4 vecint register 2 4 ? 7 28 2e not used 3 0 30 stpow packet received usbsta/ vecint registers 3 1 32 setup packet received usbsta/ vecint registers 3 2 34 psof interrupt usbsta/ vecint registers 3 3 36 resr interrupt usbsta/ vecint registers 3 4 38 fspr interrupt usbsta/ vecint registers 3 5 3a rtsr interrupt usbsta/ vecint registers 3 6 3c hstl interrupt usbsta/ vecint registers 3 7 3e not used 4 0 40 i2c txe interrupt vecint register 4 1 42 i2c txe interrupt vecint register 4 2 44 input ? endpoint ? 0 vecint register 4 3 46 output ? endpoint ? 0 vecint register 4 4 ? 7 48 4e not used 5 0 50 uart1 status interrupt lsr/vecnt register 5 1 52 uart1 modern interrupt lsr/vecint register 5 3 ? 7 54 5e not used 6 0 60 uart1 rxf interrupt lsr/vecnt register 6 1 62 uart1 txe interrupt lsr/vecint register 6 2 ? 7 64 6e not used 7 0 ? 7 70 7e not used 8 0 80 dma1 interrupt dmacsr/vecnt register 8 1 82 not used 8 2 84 dma3 interrupt dmacsr/vecnt register 8 3 ? 7 86 7e not used 9 ? 15 0 ? 7 90 fe not used
11 ? 16 11.9.2 hardware reset introduced by the firmware this feature can be used in firmware upgrade. once the upgrade is done, the application firmware disconnects from the usb for at least 200 ms to ensure os has unloaded the device driver. the firmware then enables the watchdog timer (enabled by default after power-on reset) and enters an endless loop without resetting the watchdog timer. once the watchdog timer times out, it resets the chip as if the chip gets the power-on reset. the bootcode takes over control and starts the power-on sequence again. 11.10 file listings the bootload code can be obtained from the ti website under slls519.code.zip. the list shown below are the names of the files that can be downloaded. ? types.h ? usb.h ? TUSB3410.h ? bootcode.h ? watchdog.h ? bootcode.c ? bootlsr.c ? bootusb.c ? header.h ? header.c ? i2c.h ? i2c.c
12 ? 1 12 electrical specifications 12.1 absolute maximum ratings ? supply voltage, v cc ? 0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage, v o ? 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 12.2 commercial operating condition (3.3 v) parameter min typ max unit v cc supply voltage 3 3.3 3.6 v v i input voltage 0 v cc v v high level input voltage ttl 2 v cc v v ih high-level input voltage cmos 0.7 v cc v cc v v low level input voltage ttl 0 0.8 v v il low-level input voltage cmos 0 0.2 v cc v t a operating temperature 0 70 c 12.3 electrical characteristics t a = 25 c, v cc = 3.3 v 5%, v ss = 0 v parameter test conditions min typ max unit v high level output voltage ttl i 4ma v cc ? 0.5 v v oh high-level output voltage cmos i oh = ? 4 ma v cc ? 0.5 v v low level output voltage ttl i 4ma 0.5 v v ol low-level output voltage cmos i ol = 4 ma 0.5 v v positive threshold voltage ttl vv 1.8 v v it+ positive threshold voltage cmos v i = v ih 0.7 v cc v v negative threshold voltage ttl vv 0.8 1.8 v v it ? negative threshold voltage cmos v i = v ih 0.2 v cc v v hysteresis (v v ) ttl vv 0.3 0.7 v v hys hysteresis (v it+ ? v it ? ) cmos v i = v ih 0.17 v cc 0.3 v cc v i high level input current ttl vv 20 a i ih high-level input current cmos v i = v ih 1 a i low level input current ttl vv 20 a i il low-level input current cmos v i = v il 1 a i oz output leakage current (hi-z) v i = v cc or v ss 20 a i ol output low drive current 0.1 ma i oh output high drive current 0.1 ma clock duty cycle ? 50% jitter specification ? 100 ppm c i input capacitance 18 pf c o output capacitance 10 pf ? applies to all clock outputs
12 ? 2
13 ? 1 13 application notes 13.1 crystal selection the TUSB3410 requires a 12-mhz clock source to work properly. this clock source can be a crystal placed across the x1 and x2 terminals. a parallel resonant crystal is recommended. most parallel resonant crystals are specified at a frequency with a load capacitance of 18 pf. this load can be realized by placing 33-pf capacitors from each end of the crystal to ground. together with the input capacitance of the TUSB3410 and stray board capacitance, this provides close to two 36-pf capacitors in series to emulate the 18-pf load requirement. note, that when using a crystal, it takes about 2 ms after power up for a stable clock to be produced. TUSB3410 x1 33 pf 12 mhz x2 33 pf figure 13 ? 1. crystal selection 13.2 external circuit required for reliable bus powered suspend operation ti has found a potential problem with the action of the suspend output pin immediately after power on. in some cases the suspend pin can power up asserted high. when used in a bus powered application this can cause a problem because the vregen# input is usually connected to the suspend output. this in turn causes the internal 1.8-v voltage regulator to shut down, which means an external crystal may not have time to begin oscillating, thus the device will not initialize itself correctly. ti has determined an on-chip fix for this problem, but has not determined a schedule on when the fix will be implemented. in the meantime, the components r2 and d1 (rated to 25 ma) in the circuit shown below can be used as a workaround. note that r1 and c1 are required components for proper reset operation, unless the reset signal is provided by another means. r2 and d1 can be left in place or removed once the silicon is modified. note that use of an external oscillator (1.8-v output) versus a crystal would avoid this situation, but it is not expected that many applications would use an oscillator. also note that self-powered applications would probably not see this problem because the vregen# input would likely be tied low, enabling the internal 1.8-v regulator at all times.
13 ? 2 TUSB3410 suspend d1 vregen reset r2 32 k ? c1 1 f 3.3 v r1 15 k ? figure 13 ? 2. external circuit 13.3 wakeup timing from wakeup or ri pin the TUSB3410 can be brought out of the suspended state, or woken up, by a command from the host. the TUSB3410 also supports remote wakeup and can be awakened by either of two input signals. a low pulse on the wakeup pin or a low-to-high transition on the ri pin wakes the device up. note that for reliable operation, either condition must persist for approximately 3 ms minimum. this allows time for the crystal to power up since in the suspend mode the crystal interface is powered down. the state of the wakeup or ri pin is then sampled by the clock to verify there was a valid wakeup event.
14 ? 1 14 mechanical vf (s-pqfp-g32) plastic quad flatpack 4040172 / c 10/96 0,13 nom 0,25 0,45 0,75 0,05 min gage plane 0,30 0,45 16 17 9 8 sq 25 24 7,20 6,80 32 1 5,60 typ sq 8,80 9,20 1,45 1,35 1,60 max seating plane 0,10 0 ? 7 m 0,22 0,80 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
14 ? 2

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