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automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 evaluation kit available 19-5571; rev 3; 10/14 general description the max16927 is a highly integrated power supply for automotive tft-lcd applications. the device integrates one buck converter, one boost converter, one cuk converter, two gate-voltage controllers, and two vcom buffers, one of which supports negative output voltages. the device is designed to operate from a supply voltage between 4.5v and 16v, making it ideal for automotive tft-lcd applications. alternatively, the device can operate from an available 3v to 5.5v supply. the device uses an integrated spi interface for control and diagnostics. the spi interface adjusts the vcom buffer output through an internal 7-bit dac up to +1v. the startup and shutdown sequences can be controlled through spi or using one of the three preset stand-alone modes. the device is optimized for low emi. peak interference is reduced by using the spread-spectrum feature. spread- spectrum is always enabled for the buck converter but enabled through an external input (ssen) for the boost and cuk converters. additional emi enhancement is achieved by running the boost and cuk converters 180 degrees out-of-phase. the device includes a control output for an nmos switch to enable flexible sequencing of the negative vsl output. a drive output is also included for a series pmos switch for the boost converter allowing true shutdown?. the device is available in a 48-lead tqfn package with an exposed pad, and operates over the -40 n c to +105 n c temperature range. applications automotive dashboardsautomotive central information displays automotive navigation systems features s operating voltage range of 4.5v to 16v (in3) or 3v to 5.5v (ina) s 16v input, 2a buck converter provides 3.3v output to tft bias-supply circuitry and/or other external circuitry s flexible configuration allows single high-power positive output (18v/200ma) or positive output (18v, 100ma) and negative output (-12v/100ma) s one positive gate-voltage regulator s one negative gate-voltage controller s dac-controlled vcom buffers with offset of 0v to +1v s high-frequency operation 2.1mhz (buck converter) 1.2mhz (boost and cuk converters) s converters run out-of-phase for lower emi s externally controlled spread-spectrum switching for boost and cuk s very flexible sequencing in both stand-alone and spi-controlled modes s true shutdown boost converter s low-current shutdown mode (< 10a) s spi control interface s internal soft-start s overtemperature shutdown s -40c to +105c operation s aec-q100 qualified ordering information true shutdown is a trademark of maxim integrated products, inc. block diagram and typical operating circuits appear at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part.* ep = exposed pad. part temp range pin-package max16927gtm/v+ -40 n c to +105 n c 48 tqfn-ep* for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
2 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in3, lxn, lxp, lx3, vcomp, en3 to gnd .......... -0.3v to +20v bst to gnd ........................................................... -0.3v to +26v bst to lx3 ............................................................... -0.3v to +6v vcp, vgh to gnd ................................................. -0.3v to +24v drvn to gnd ........................................................ -25v to +0.3v flt , ina to gnd ..................................................... -0.3v to +6v cs , clk, din, en1, en2, enp, ref, fbp, fbgh, gate to gnd.................... ....... -0.3v to (v ina + 0.3v) fb gl, fbn, dout, ssen, compp, compn to gnd?????. ................ -0.3v to (v ina + 0.3v) fb3 to gnd ........................................................... -0.3v to +12v vcomh, vcinh to gnd ....................................... -0.3v to +20 v vcoml, vcinl to gnd (note 1) ......................... -1.5v to +1.5 v vcomn to gnd ................................................... -7.5 v to +0.3 v vcomp to gnd ..................................................... -0.3v to +20 v vsls to gnd ......................................................... -20v to +0.3v pgood, sync, avl to gnd .................................. -0.3v to +6v gnd to pgnd3, pgndp, pgndn ....................... -0.3v to +0.3v continuous power dissipation (t a = +70 n c) tqfn (derate 38.5mw/ n c above +70 n c)..................3076mw operating temperature range ........................ -40 n c to +105 n c junction temperature range ........................... -40 n c to +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) absolute maximum ratings note 1: pin protection is temperature dependent. temperature behavior t j = -40 n c, q 1.8v; t j = +150 n c, q 0.9v. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 2) tqfn junction-to-ambient thermal resistance ( q ja ) .......... 26 c/w junction-to-case thermal resistance ( q jc ) ................. 1 c/w parameter symbol conditions min typ max units buck convertersupply-voltage range v in3 v out = 3.3v 4.5 16 v supply current i in3 v en3 = 0v 10 m a v en3 = v in3 , no load 5.3 ma undervoltage lockout (uvlo) avl rising 2.7 3 v hysteresis 0.1 avl voltage 6v p v in3 p 16v 5 v avl voltage (skip mode) 6v p v in3 p 16v, v sync = 0v, i load = 0a 3.3 v spread-spectrum range 6 % switching frequency f sw internally generated 1.925 2.1 2.275 mhz sync input frequency range 1.8 2.6 mhz output voltage v out3 4.75v p v in3 p 16v, i load < 2a continuous mode 3.2% 3.3 3.36% v skip mode (note 4) 3.17% 3.3 3.43% high-side dmos on-resistance r ds_on(3) i lx = 1000ma, v in3 = v avl = 5v 100 250 m i dmos current-limit threshold 2.72 3.4 4.08 a soft-start ramp time t ss 0.25 0.419 0.65 ms guraranteed output current i out3(min) 4.75v p v in3 p 16v 2 a duty-cycle range 15 99 % downloaded from: http:///
3 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 electrical characteristics (continued)(v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) parameter symbol conditions min typ max units power good (pgood)pgood threshold rising 92 % falling 88 90 92 pgood debounce time 10 f s pgood high leakage current t a = +25 c 0.2 f a pgood low level sinking 1ma 0.4 v en3/syncen3 threshold high 2.4 v en3 threshold low 0.6 v en3 internal pulldownresistance value 500 k i sync high switching threshold 1.4 v sync low switching threshold 0.4 v sync internal pulldownresistor value 200 k i ina power inputina input-supply range 3 5.5 v ina undervoltage-lockout threshold v ina rising, hysteresis = 200mv 2.5 2.7 2.9 v ina supply current i ina v fbp = v fbgh = 1.3v, v fbn = v fbgl = 0v, lxn and lxp not switching, vcomh/l = off 0.6 3.0 ma ina supply current,shutdown mode i ina_shdn v enp = 0v 1.2 f a duration-to-triggerfault condition v fbp , v fbn , v fbgh , or v fbgl below their pgood thresholds 218 ms referenceref output voltage v ref no load 1.238 1.25 1.262 v ref load regulation 0 < i load < 80 f a (load sink) -0.6 +0.3 % ref undervoltage-lockout threshold rising edge, hysteresis = 200mv 1.15 v oscillator frequency f osc 4320 4800 5280 khz spread-spectrum modulation frequency f ss 1200 khz spread-spectrum factor ssr as a percentage of f osc +8 % boost and cuk converters?common parametersswitching frequency f sw f osc /4 khz switching frequency maximum duty cycle 93 % downloaded from: http:///
4 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 electrical characteristics (continued)(v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) parameter symbol conditions min typ max units lxp, lxn current limit i lim v vsh = 16v, v vsl = -12v, vshlim[1:0] = vsllim[1:0] = 00, default; see the applications information section for spi programming of other values 1.3 1.56 1.87 a lxp, lxn on-resistance r ds_on i lx_ = 100ma 340 500 m i lxp, lxn leakage current i leak_lx v lx_ = 20v, t a = +25 n c 10 20 f a soft-start current v vsh = 16v, v vsl = -12v, vshlim66 = vsllim66 = 0, default; see the applications information section for spi programming of other values 1.3 1.56 1.87 a soft-start voltage ramp time 13.5 ms fbp/fbn to compp/compn transconductance d i = 2.5 f a at compp/compn 400 f s internal slope compensation 1.5 a/ f s boost converter (vsh)output-voltage range v vsh v ina 18 v fbp regulation voltage v fbp v ina = 3v to 5.5v 0.77 x v ref 0.80 x v ref 0.83 x v ref v pgood threshold pgtsh measured on fbp 850 mv fbp load regulation 0 < i load < full load -1 % fbp line regulation v ina = 3v to 5.5v 0.1 %/v fbp input-bias current v fbp = 1v, t a = +25 n c 1 f a cuk converter (vsl)vsl output-voltage range v vsl using cuk topology -12 -4.5 v fbn regulation voltage v fbn voltage that appears across feedback resistors connected between ref and fbn, v ina = 3v to 5.5v -0.77 x v ref -0.80 x v ref -0.83 x v ref v pgood threshold pgtsl measured on fbn, value referred to gnd 400 mv fbn load regulation 1 % fbn line regulation v ina = 3v to 5.5v 0.3 %/v fbn input-bias current v fbn = 0.25v, t a = +25 n c 1 f a fbn threshold voltage for high-power boost mode v fbn lxn and lxp connected together for 2x output current capability 2.5 v vgh linear regulatoroutput-voltage range v vgh v vcp = 23v, i load = 20ma 5 21 v vgh output current i vgh v vcp - v vgh = 2v 20 ma fbgh regulation voltage v fbgh i vgh = 1ma 0.77 x v ref 0.80 x v ref 0.83 x v ref v pgood threshold pgtgh measured on fbgh, v vgh rising 850 mv downloaded from: http:///
5 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 electrical characteristics (continued)(v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) parameter symbol conditions min typ max units fbgh line regulation v vcp = 12v to 20v at v vgh = 10v, i vgh = 10ma 2 % fbgh load regulation i vgh = 0 to 20ma 2 % fbgh input-bias current v fbgh = 1v, t a = +25 n c 1 f a vgh current limit i limvgh t a = +25 n c 25 40 ma vgh soft-start time vghstt[1:0] = 00, default 6.78 ms vghstt[1:0] = 10 13.6 vghstt[1:0] = 01 27.1 vghstt[1:0] = 11 54.3 vgl linear regulatorfbgl regulation voltage v fbgl voltage that appears across feedback resistors connected between ref and fbgl, i drvn = 100 f a 0.77 x v ref 0.8 x v ref 0.83 x v ref v output-voltage range drvn -21 -2 v fbgl pgood threshold pgtgl measured on fbgl, value referred to gnd 400 mv fbgl input-bias current v fbgl = 0.25v, t a = +25 n c 1 f a drvn source current v fbgl = 0.5v, v drvn = -10v 2 ma drvn source current limit t a = +25 n c 2.5 4 ma vgl soft-start time vglstt[1:0] = 00, default 6.78 ms vglstt[1:0] = 10 13.6 vglstt[1:0] = 01 27.1 vglstt[1:0] = 11 54.3 vcomh buffervcomp supply range 6 18 v vcomp supply current buffer configuration, no load, no input,t a = +25 n c 3 5 ma vcinh resistive divider value internal 1m i pullup to vcomp and 1m i pulldown to ground 500 k i input/output-voltage range 2 v vcomp - 2v v large-signal voltage gain v vcomh = 2v to v vsh - 2v 80 db slew rate v vsh = 12v, c l < 30pf 45 v/ f s -3db bandwidth v vsh = 12v, c l < 30pf 20 mhz current limit sourcing, t a = +25 n c 90 ma sinking, t a = +25 n c 90 vcoml buffervcomn supply range -7 -4.5 v vcomn supply current buffer configuration, no input, no load, t a = +25 n c 3 5 ma downloaded from: http:///
6 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 electrical characteristics (continued)(v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) parameter symbol conditions min typ max units vcinl resistance resistor internally connected to ground 1000 k i input common-modevoltage range t a = -40 n c to +85 n c q 1 q 1.25 v t a = +85 n c to +105 n c q 0.8 large-signal voltage gain v coml = -1v to +1v 80 db slew rate c l < 30pf 28 v/ f s -3db bandwidth c l < 30pf 20 mhz current limit sourcing 11 ma sinking 11 ma vcom dacvoltage resolution 7 bits differential nonlinearity monotonic over temperature (note 5) -1 +1 lsb zero-scale error includes v comh or v coml buffer input offset voltage -2 +2 lsb full-scale error -12 +12 lsb vcom voltage step size 7.8 mv input and output series switch controlp-channel fet gate-driver sink current v gate = v ina 36 53 70 f a p-channel gate-drivervoltage threshold measured at gate; below this voltage, the external p-channel fet is conducting 1.25 v vsls gate-driversource current v vsls = -5v 38 50 58 f a digital inputscs input pullup resistor value r pu 500 k i ssen, enp input pulldown resistor value r pd 500 k i enp, en1, en2, clk, cs , din, ssen input voltage low v il 0.8 v enp, en1, en2, clk, cs , din, ssen input voltage high v ih 2.4 v digital outputsdout output voltage low 0.4 v dout output voltage high 2.8 v flt output voltage low v flt i sink = 2ma 0.4 v spi interface (note 6)clock frequency f clk 4 mhz falling edge of cs to rising edge of clk required setup time t lead input rise/fall time < 10ns 100 ns falling edge of clk to rising edge of cs required hold time t lag input rise/fall time < 10ns 100 ns setup time din-to-clkfalling edge t din(su) 30 ns downloaded from: http:///
7 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 electrical characteristics (continued)(v in3 = 12v, v ina = 3.3v, t a = t j = -40 n c to +105 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 3) note 3: all devices are 100% tested at t a = +25c. limits over temperature are guaranteed by design. note 4: guaranteed by design; not production tested. note 5: design guaranteed by ate characterization. limits are not production tested. note 6: guaranteed by design. figure 1 shows the spi timing characteristics. figure 1. spi timing characteristics cs clk din msb in msb out lsb out t dout(dis) t valid t dout(en) t lead dout t lag t din(su) t din(hold) parameter symbol conditions min typ max units din hold time after fallingedge of clk t din(hold) 20 ns time from rising edge ofclk-to-dout data valid t valid c dout = 50pf 70 ns time from falling edge of cs to dout low t dout(en) 55 ns time from rising edge of cs to dout high impedance t dout(dis) 55 ns dout leakage current inhigh-impedance state i dout(hi-z) v cs = v ina , v dout = v ina /2, t a = +25 n c 1 f a flt leakage current in high-impedance state i flt (hi-z) v flt = 5v, t a = +25 n c 1 f a en1/en2/clk leakage current i in_leak 3.3v < v ina p 5.0v , t a = +25 n c 1 f a din input pulldown resistor value r pd,din 50 k w thermal shutdown thermal-shutdown temperature temperature rising 165 n c thermal-shutdown hysteresis 15 n c downloaded from: http:///
8 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating characteristics (v in3 = 12v, v ina = 3.3v, v vgh = 12v, v vgl = -12v, v vsh = 6.9v, v vsl = -6.9v, t a = +25 n c, unless otherwise noted.) efficiency vs. load current (buck) max16927 toc02 load current (a) efficiency (%) 1.6 1.2 0.8 0.4 10 20 30 40 50 60 70 80 90 100 0 0 2.0 line regulation (buck) max16927 toc03 input voltage (v) error (%) 14 12 10 8 6 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 -2.0 41 6 load regulation (buck) max16927 toc04 load current (a) error (%) 1.8 1.6 1.2 1.4 0.4 0.6 0.8 1.0 0.2 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 -6 0 2.0 100ma to 2a load transient response (buck) max16927 toc06 v out3 (ac-coupled) 50mv/div i out3 1a/div 20s/div startup behavior (buck) max16927 toc05 v lx3 10v/vv out3 2v/vi out3 2a/div v en3 5v/v 100s/div 10v to 16v line transient response (buck) max16927 toc07 v out3 (ac-coupled) 50mv/div v in3 5v/div 20s/div shutdown supply current (buck) max16927 toc01 supply voltage (v) supply current (a) 14 12 10 8 6 2 4 6 8 10 12 14 0 41 6 downloaded from: http:///
9 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating characteristics (continued) (v in3 = 12v, v ina = 3.3v, v vgh = 12v, v vgl = -12v, v vsh = 6.9v, v vsl = -6.9v, t a = +25 n c, unless otherwise noted.) short-circuit behavior (buck) max16927 toc08 i lx3 2a/divv pg00d3 5v/div v out3 2v/div 1ms/div ina shutdown supply current max16927 toc09 supply voltage (v) supply current (a) 5.0 4.5 4.0 3.5 1 2 3 4 50 3.0 5.5 switching frequency vs. supply voltage max16927 toc10 input voltage (v) error (%) 5.0 4.5 4.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 3.0 5.5 boost and cukf sw = 1.2mhz spectrum (spread-spectrum mode) max16927 toc11 frequency (mhz) magnitude (dbv) 10 -70 -60 -50 -40 -30 -20 -10 0 10 -80 1 100 lxp nodemeasurement bandwidth = 1khz v ssen = v ina spectrum (fixed-frequency mode) max16927 toc12 frequency (mhz) magnitude (dbv) 10 -70 -60 -50 -40 -30 -20 -10 0 10 -80 1 100 lxp nodemeasurement bandwidth = 1khz v ssen = 0v efficiency vs. load current (boost) max16927 toc13 load current (ma) efficiency (%) 700 600 400 500 200 300 100 10 20 30 40 50 60 70 80 90 100 0 0 800 v ina = 3.3v v ina = 5v load regulation (boost) max16927 toc14 load current (ma) error (%) 700 600 400 500 200 300 100 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 800 v ina = 3.3v v ina = 5v line regulation (boost) max16927 toc15 input voltage (v) error (%) 5.0 4.5 4.0 3.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 3.0 5.5 i load = 200ma downloaded from: http:///
10 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating characteristics (continued) (v in3 = 12v, v ina = 3.3v, v vgh = 12v, v vgl = -12v, v vsh = 6.9v, v vsl = -6.9v, t a = +25 n c, unless otherwise noted.) 100ma to 450ma load transient response max16927 toc22 v vsl (ac-coupled) 200mv/div i vsl 200ma/div 100s/div startup behavior (cuk) max16927 toc21 v ina 5v/divv lxn 10v/divv vsl 5v/divi vsl 200ma/div 4ms/div line regulation (cuk) max16927 toc20 5.0 4.5 4.0 3.5 3.0 5.5 input voltage (v) error (%) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 i load = 200ma load regulation (cuk) max16927 toc19 load current (ma) error (%) 500 400 300 200 100 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 600 v ina = 3.3v v ina = 5v efficiency vs. load current (cuk) max16927 toc18 load current (ma) efficiency (%) 500 400 300 200 100 10 20 30 40 50 60 70 80 90 100 0 0 600 v ina = 3.3v v ina = 5v 100ma to 500ma load transient response max16927 toc17 v vsh (ac-coupled) 100mv/div i vsh 200ma/div 20s/div startup behavior (boost) max16927 toc16 v lxp 5v/divv vsh 5v/divi vsh 200ma/div v ina 5v/div 10ms/div downloaded from: http:///
11 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating characteristics (continued) (v in3 = 12v, v ina = 3.3v, v vgh = 12v, v vgl = -12v, v vsh = 6.9v, v vsl = -6.9v, t a = +25 n c, unless otherwise noted.) supply sequencing (stand-alone mode 2) max16927 toc29 v vsl 5v/div v vsl_sw 5v/div v vgh 5v/divv vgl 5v/div v vsh 5v/div 10ms/div v en1 = v ina , v en2 = v ina supply sequencing (stand-alone mode 1) max16927 toc28 v vsl 5v/div v vgh 5v/divv vgl 5v/div v vsh 5v/div 10ms/div v en1 = v ina , v en2 = 0v supply sequencing (stand-alone mode 0) max16927 toc27 v vsl 5v/div v vgh 5v/divv vgl 5v/div v vsh 5v/div 10ms/div v en1 = 0v, v en2 = v ina load regulation (vgl linear regulator) max16927 toc26 load current (ma) error (%) 18 16 12 14 4 6 8 10 2 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 02 0 v vcn = v vgl - 2v line regulation (vgl linear regulator) max16927 toc25 vcn voltage (v) error (%) -13 -14 -16 -15 -18 -17 -19 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0 -0.20 -20 -12 i load = 20ma i load = 10ma load regulation (vgh linear regulator) max16927 toc24 load current (ma) error (%) 18 16 12 14 4 6 8 10 2 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 02 0 v vcp = v vgh + 2v line regulation (vgh linear regulator) max16927 toc23 vcp voltage (v) error (%) 20 19 17 18 14 15 16 13 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 12 21 i load = 10ma i load = 20ma downloaded from: http:///
12 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating characteristics (continued) (v in3 = 12v, v ina = 3.3v, v vgh = 12v, v vgl = -12v, v vsh = 6.9v, v vsl = -6.9v, t a = +25 n c, unless otherwise noted.) reference load regulation max16927 toc33 load current (a) error (%) 70 60 40 50 20 30 10 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 08 0 ramped dac response max16927 toc32 v vcoml 500mv/div 20ms/div vcoml transient response max16927 toc31 v vcoml 500mv/div 10ms/div magnitude response vs. frequency (vcom buffer) max16927 toc30 frequency (mhz) magnitude (db) 10 1 -40 -30 -20 -10 0 10 20 30 -50 0.1 100 z l = 1k i + 220nf vcoml vcomh downloaded from: http:///
13 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 pin description pin configuration top view max16927 tqfn 13 14 15 16 17 18 19 20 21 22 23 24 fb3 pgood gnd ssen flt din dout cs clk enp en1 en2 48 47 46 45 44 43 42 41 40 39 38 37 1 2 34 56 78 91 0 11 12 fbn ep compp fbp pgndn lxn lxn lxp lxp pgndp gate vcp vgh sync pgnd3 en3 in3 lx3 lx3 in3 bst gnd avl ina compn 36 35 34 33 32 31 30 29 28 27 26 25 ref fbgh fbgl gnd vcinl vcoml vcomn vsls vcinh vcomh vcomp drvn + pin name function 1 compn cuk converter error-amplifier compensation. connect the compensation network from compn to gnd. 2 ina boost and cuk power supply. connect to the output of the buck converter or to a supply between 3v and 5.5v. 3 avl buck-converter internal 5v regulator. connect a 1 f f capacitor between avl and pgnd3. do not use avl to power external circuitry. 4, 15, 28 gnd analog ground 5 bst buck-converter bootstrap capacitor connection. connect a 0.1 f f capacitor between bst and lx3. 6, 9 in3 buck-converter power supply. connect to a 4.5v to 16v supply. connect a 1 f f or larger ceramic capacitor in parallel with a 47 f f capacitor from in3 to pgnd3. connect both in3 power inputs together. 7, 8 lx3 buck-converter inductor connection. connect the inductor, boost capacitor, and catch diode at this node. 10 en3 buck-converter enable input. en3 is a high-voltage, 5v- and 3.3v-compatible input. connect to in3 for normal operation and connect to pgnd3 to disable the buck converter. 11 pgnd3 buck-converter power ground 12 sync buck-converter sync input. sync allows the buck converter to be synchronized to other dc-dc converters. when connected to an external clock source, the buck converter is synchronized. when sync is not used, connect to gnd. downloaded from: http:///
14 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 pin description (continued) pin name function 13 fb3 buck-converter feedback input. connect fb3 to the output-voltage node, out3, as shown in the typical operating circuits . 14 pgood buck converter open-drain power-good output. connect a 10k i pullup resistor to any low-voltage supply. 16 ssen spread-spectrum enable input. connect ssen to ina to place the boost and cuk in spread-spectrum mode. connect ssen to gnd for fixed-frequency pwm operation. ssen has an internal 500k i pulldown resistor. 17 flt open-drain fault output. when low, flt indicates that one or more of the output voltages (except the buck-converter output) is less than 85% of their regulated values. connect a 10k i pullup resistor from flt to ina. the flt output is cleared on the rising edge of the cs signal or when enp is toggled. 18 din spi interface data input. data is clocked in on the falling edge of the clk input. din has an internal 50m w (typ) pulldown resistor. 19 dout spi interface data output. data is stable on the falling edge of the clk input. 20 cs spi interface active-low chip-select input. pull cs low to enable the spi interface. a new 32-bit data word is latched into the input register on the rising edge of cs . when cs is high, dout is high impedance. cs has an internal pullup resistor of value of 500k i . 21 clk spi interface clock input 22 enp active-high enable input. enp enables the device, with the exception of the buck converter, which is controlled by en3. enp has an internal 500k i pulldown resistor. to enable the boost converter, take enp high when ina > 2.9v. connect enp to gnd to place everything in shutdown except the buck converter. 23 en1 enable input 1. en1 and en2 determine the supply sequencing of the regulators. when en1 and en2 are low, the spi interface is enabled. see the soft-start and supply sequencing (en3, enp, en1, en2) section. 24 en2 enable input 2 25 ref 1.25v reference output. connect a 100nf capacitor between ref and gnd. 26 fbgh positive gate-voltage linear regulator-feedback input. fbgh is regulated to 1v. 27 fbgl negative gate-voltage linear regulator-controller-feedback input. fbgl is regulated to 0.25v. 29 vcinl vcoml adder input. the voltage on vcinl is added to the vcom dac voltage and buffered to the vcoml output. 30 vcoml low-range vcom buffer output. the output range of this buffer can be dac from 0v to 1v around the vcinl voltage. 31 vcomn vcoml buffer negative supply. the positive supply for this buffer is ina. if v vsl is set lower than -7v, an external regulator is needed to limit v vcomn to -7v. 32 vsls external n-channel fet gate drive. vsls sources a current to turn on the external fet when the envsls bit is set to 1 through spi. 33 vcinh vcomh adder input. the voltage on vcinh is added to the vcom dac voltage and buffered to the vcomh output. 34 vcomh high-range vcom buffer output. the output range of this buffer can be dac from 0v to 1v around the vcinh voltage. 35 vcomp vcomh buffer positive supply. the negative supply for this buffer is gnd. connect vcomp to the output of the boost converter even if the vcomh buffer is unused. downloaded from: http:///
15 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 detailed description the max16927 is a highly integrated power supply for automotive tft-lcd applications. the device integrates one buck converter to generate 3.3v from a 4.5v to 16v supply, one boost converter, one cuk converter, two gate-voltage controllers, and two vcom buffers, one of which supports an active q 1v drive referred to gnd. an spi interface provides diagnostics and host control.the buck converter operates independently from the boost and cuk converters and the linear regulators. use the buck converter to generate a 3.3v output to power the other four regulators from a 4.5v to 16v supply. alternatively, power the four regulators from an available 3v to 5.5v supply and ground all pins for the buck con - verter: bst, in3, lx3, fb3, en3, avl, pgood, sync, and pgnd3. 3.3v buck converter the device features a current-mode buck converter with an integrated high-side fet, which requires no external compensation network. the device regulates the output voltage to 3.3v. the buck converter delivers a minimum of 2a of output current. the high 2.1mhz (typ) switch - ing frequency allows for small external components, reduced output ripple, and guarantees no am interfer - ence.a power-good (pgood) indicator is available to monitor output-voltage quality. shutting down the buck converter reduces the supply current to 10a. enable (en3) the buck converter is activated by driving en3 high. en3 is compatible with +3.3v logic levels but is also high-voltage compatible up to 20v. the en3 input has a 500k pulldown resistor. pin description (continued) pin name function 36 drvn negative gate-voltage linear regulator base drive output. open drain of an internal n-channel fet. connect drvn to the base of an external npn pass transistor. 37 vgh positive gate-voltage linear regulator output 38 vcp positive gate-voltage linear regulator power input. connect vcp to the positive output of the external charge pump. 39 gate external p-channel fet gate drive. gate sinks a current to turn on the external fet when the boost converter is enabled and goes into high impedance during a fault condition or when the boost is disabled. 40 pgndp boost converter power ground 41, 42 lxp boost converter switching node. connect the inductor and diode to this node. 43, 44 lxn cuk converter switching node. connect the inductor and coupling capacitor to this node. 45 pgndn cuk converter power ground 46 fbp boost converter feedback input. fbp is regulated to 1v. 47 compp boost converter error-amplifier compensation. connect the compensation network from compp to gnd. 48 fbn cuk converter feedback input. fbn is regulated to 0.25v. connect fbn to ina when lxn and lxp are connected together to double the output power of the boost. ? ep exposed pad. connect the exposed pad to the ground plane for optimal heat dissipation. do not use the exposed pad as the only electrical ground connection. downloaded from: http:///
16 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 undervoltage lockout (uvlo) when the device is enabled, an internal bias generator turns on. lx begins switching after v avl has exceeded the internal uvlo level v uvlo = 2.7v (typ). soft-start the buck converter goes into soft-start after four current-limit events have been detected. upon detecting the fourth current-limit event, the device starts the soft-start timer and attempts to ramp the output to its final value in 1024 clock cycles (t ss = 0.49ms typ). if the output does not reach its final value before the soft-start timer expires, the buck converter stops switching for 576 clock cycles before reattempting to regulate the output. the process repeats until the source of output undervoltage is removed. oscillator/synchronization (sync) the buck converter has an integrated oscillator that pro - vides a switching frequency of 2.1mhz (typ). the sync pin can be used to synchronize the internal clock with an external source. use an external clock frequency range between 1.8mhz and 2.6mhz. connect sync to gnd if not used. spread-spectrum mode the buck converter features spread-spectrum operation, which varies the internal operating frequency of the buck converter by +6% relative to the internally generated operating frequency of 2.1mhz (typ). this function does not apply to an externally applied clock signal. power-good (pgood) the buck converter features an open-drain power-good output. pgood is an active-high output that pulls low when the buck output voltage is below 90% of its nominal value and is high impedance when the output voltage is above 92% of its nominal value. connect a 10k i pullup resistor from pgood to any low-voltage supply. overcurrent protection the buck converter limits its output current to i max = 2.72a (min). if a short-circuit condition is detected for four clock cycles, the controller stops switching for 512 clock cycles and attempts to soft-start the output. this process is repeated until the short-circuit condition is removed. in the event the internal fet overheats, the device enters thermal-overload protection. internal 5v regulator (avl) the device features a 5v regulator whose function is to charge the boost capacitor through the internal boost diode and to power the circuitry of the buck converter. bypass avl to gnd with a 1f capacitor. do not use avl to power external circuitry. oscillator and spread-spectrum mode (boost and cuk) the boost and cuk converters run from a 1.2mhz oscil - lator. connect ssen to ina to enable spread-spectrum clocking, in which the clock frequency varies +8% above 1.2mhz. connect ssen to gnd for fixed-frequency 1.2mhz clocking. boost converter the boost converter employs a current-mode, fixed- frequency pwm architecture to maximize loop bandwidth and provide fast-transient response to pulsed loads typi - cal of tft-lcd panel source drivers. the 1.2mhz switch - ing frequency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the integrated high-efficiency mosfet and the ic?s built-in digital soft-start functions reduce the number of external components required while control - ling inrush currents. the output voltage can be set from v ina to 18v with an external resistive voltage-divider. the regulator controls the output voltage by modulat - ing the duty cycle (d) of the internal power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: vsh ina vsh v -v d v = figure 2 shows the functional diagram of the boost regulator. an error amplifier compares the signal at fbp to 1v and changes the compp output. the voltage at compp sets the peak inductor current. as the load varies, the error amplifier sources or sinks current to the compp output accordingly to produce the inductor peak current necessary to service the load. to main - tain stability at high duty cycles, a slope-compensation signal is summed with the current-sense signal. on the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel mosfet and apply - ing the input voltage across the inductor. the current downloaded from: http:///
17 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the current-feedback signal and the slope compensation exceeds the compp voltage, the controller resets the flip-flop and turns off the mosfet. the inductor current then flows through the diode to the output. the mosfet remains off for the rest of the clock cycle. the external p-channel fet controlled by gate protects the output during fault conditions and makes possible true shutdown of the converter. during startup, vsh is slightly prebiased to detect any shorts on the boost out - put. under normal operation, the p-channel fet is turned on, connecting the supply to the input of the boost con - verter. under a fault condition or in shutdown, the fet is turned off, disconnecting the supply from the input and preventing current from charging the output through the inductor and diode from the supply. cuk converter the cuk converter produces a negative output using a controller architecture similar to that of the boost. the network?ln1, c1, and schottky diode?allow a boosted voltage to be stored on c1 (see figure 3). ignoring para - sitic voltage drops, the relationship between v c1 and v ina is given by: c1 ina v 1 v 1- d = during the on-time, energy is stored in ln1 and during the off-time it is released to storage capacitor c1. the network?c1, schottky diode, ln2, and c2?performs the inverting function. ignoring parasitic voltage drops, the relationship between the output of the cuk converter and v c1 is given by: vsl c1 v -d v = during the on-time, c1 delivers energy to c2, the load, and ln1. during the off-time, ln1 releases the energy stored during the on-time to c2 and the load. the rela - tionship between input and output voltages is: vsl ina v d - v 1- d = during startup, depending on the configuration of en1 and en2, the n-channel fet gating the cuk output is turned off to allow the charge-pump voltages to settle to their final values. the charge pumps power the positive and negative gate-voltage regulators, vgh and vgl. turn on the n-channel fet and connect the cuk output to vsl by setting the en_vsls bit to 1. when vcomn is connected to the output of the cuk con - verter, v vsl must be limited to -7v. if v vsl is set lower than -7v, an external regulator is needed to limit the volt - age on vcomn to -7v. high-power boost converter figure 10 shows an alternative use of the cuk converter power stage. disabling the cuk by connecting fbn to ina and using the boost and cuk power stages in parallel provides a boost converter output capable of twice the power by doubling the inductor current limit. in this appli - cation, connect lxn and lxp together and leave vsls unconnected. figure 2. boost converter functional diagram logic and driver lxp clock pgndp v limit fbpcompp error amp 1v 0.85v fault comparator to fault logic 1.2mhz oscillator pwm comparator slope comp ilim comparator soft- start current sense downloaded from: http:///
18 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 current limit (boost and cuk) the effective current limit is reduced by the internally injected slope compensation by an amount dependent on the duty cycle of the converter. the effective current limit is given by: lim(eff) lim_dc_0% d i i -1.16 93% = for i lim_dc_0% , dependence on spi bits vsxlim<66,1,0> (table 1). the vsxlim[66] bit determines whether during soft-start the current limit is reduced one level down. after soft-start is finished, the vsxlim[66] bit has no influence. the cuk converter exhibits a similar reduc - tion in current limit dependent on its duty cycle. with the cuk converter current limit bits set to 0 (i.e., vsllim1 = vsllim0 = 0), the effective current limit is given by the same equation where d is the duty cycle of the cuk con - verter in percent. estimate the duty cycle of each con - verter using the formulas shown in the design procedure section. figure 4 shows the dependence of the current limit on the duty cycle of the boost and cuk converters. emi reduction the device reduces the emi of the boost and cuk converters in two ways. in spread-spectrum mode, the switching frequency of the boost and cuk converters varies randomly to +8% of 1.2mhz. additional emi reduction is achieved by running the boost and cuk converters 180 degrees out of phase. in a high-power boost converter as described in the previ - ous section, the boost and cuk converters run in phase. table 2 summarizes the phase relationship between the boost and cuk converters. figure 3. cuk converter figure 4. effective current limit vs. duty cycle table 2. phase relationship between converters table 1. boost and cuk current limit settings note: codes with bit <66> high are applicable in soft-start only. vsl c2 pgndn vsls fbn ref ln2 ln1 -4.5v to -12v cuk c 1 compn lxn ina effective current limit vs. duty cycle duty cycle (%) ab c d effective current limit (a) 90 80 70 60 50 40 30 20 10 0.5 1.0 1.5 2.0 2.5 3.0 0 0 100 e a: vsxlim<66,1,0> = 000b: vsxlim<66,1,0> = 001 or 100 c: vsxlim<66,1,0> = 010 or 101 d: vsxlim<66,1,0> = 011 or 110 e: vsxlim<66,1,0> = 111 spi bits vsxlim<66,1,0> i lim_dc_0% (a) 000 2.66 001 or 100 1.78 010 or 101 1.11 011 or 110 0.79 111 0.46 application phase relationship between boost and cuk converters one positive output,one negative output 180 degrees out of phase one higher powerpositive output in phase downloaded from: http:///
19 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 positive gate-voltage linear regulator (vgh) the positive gate-voltage linear-regulator includes a p-channel fet output stage to generate a regulated +5v to +22v output. the regulator maintains accuracy over wide line and load conditions. it is capable of at least 20ma of output current and includes current-limit protec - tion. vgh is typically used to provide the tft lcd gate drivers? gate-on voltage. the vgh linear regulator derives its positive supply volt - age from a noninverting charge pump, a single-stage example of which is shown in the typical operating circuits (figures 9 and 10). a higher voltage using a multistage charge pump is possible as described in the charge pumps section. negative gate-voltage linear-regulator controller (vgl) the negative gate-voltage linear-regulator controller is an analog gain block with an open-drain p-channel output. it drives an external npn pass transistor with a 6.8k base-to-emitter resistor (see the pass transistor selection section). its guaranteed base drive-source cur - rent is at least 2ma. vgl is typically used to provide the tft lcd gate-drivers? gate-off voltage. the vgl linear regulator derives its negative supply volt - age from an inverting charge pump, a single-stage exam - ple of which is shown in the typical operating circuits . a more negative voltage using a multistage charge pump is possible as described in the charge pumps section. vcom buffers the vcom buffers, vcomh and vcoml, hold their out - put voltage stable while providing the ability to source and sink a high current quickly into a capacitive load such as the backplane of a tft lcd panel. in stand-alone mode, the spi interface is not used. the vcomh and vcoml output voltages are set by applying voltages to the vcinh and vcinl inputs. vcinh is inter - nally biased to midrail (v vcomp/2 ) using internal 1m i pullup and pulldown resistors. vcinl is internally pulled to ground through a 1m resistor. its voltage is adjust - able using a single external resistor typically connected to vcomn. alternatively, to avoid drift in the voltage due to the difference in thermal coefficients between the internal and external resistors, set the voltage on vcinl using two lower value external resistors. only one vcom buffer is active at a time. the vcoml buf - fer is active only when the cuk converter is running while the vcomh buffer is active only when the cuk converter is disabled or paralleled with the boost converter to provide a high-power boosted output (i.e., fbn is connected to ina). always connect vcomp to the output of the boost converter even when the vcomh buffer is inactive. the max16927 features a +7-bit vcom digital-to-analog converter (dac) whose output polarity and magnitude is controlled through spi (see the vcom dac section). the resolution of the dac is 7.8mv for a 0v to +1v output range. the output of the dac is buffered to the vcomh and vcoml outputs. further offset is possible by apply - ing a voltage to vcinh or vcinl. the vcomh buffer is powered between vcomp and gnd while the vcoml buffer is powered between ina and vcomn. always connect vcomp to the output of the boost converter even when the vcomh buffer is inactive. ensure that the voltage on vcomn never falls below -7v. driving purely capacitive loads in general, the lcd backplane (vcom) consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. however, if the operational amplifier is used in an appli - cation with a purely capacitive load, steps must be taken to ensure stable operation. as the operational amplifier?s capacitive load increases, the amplifier?s bandwidth decreases and gain peaking increases. a 5 i to 50 i resistor placed between the buf - fer output and the capacitive load reduces peaking but also reduces the gain. an alternative method of reducing peaking is to place a series rc network (snubber) in par - allel with the capacitive load. the rc network does not continuously load the output or reduce the gain. typical values of the resistor are between 100 i and 200 i , and the typical value of the capacitor is 10nf. soft-start and supply sequencing (en3, enp, en1, en2) the device provides flexible supply-sequencing schemes. the order in which the switching and linear regulators turn on is determined either by the external enable inputs (enp, en3, en1, and en2) or through spi. table 3 shows the various supply-sequencing options available on the device. do not connect enp directly to ina; enp should not transition from low to high until ina > 2.9v when enabled, the regulator ramps the output voltage toward its set voltage. the soft-start period of the boost and cuk converters is a fixed 13.56ms. the soft-start period of the linear regulators is spi controlled and is 6.784ms by default. each regulator turns on immediately after the previous regulator?s internal pgood indicator signals that its output is within regulation (i.e., within 85% downloaded from: http:///
20 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 of its set voltage). for the boost and cuk converters after the ramp-up time of 13.56ms, there is a further 13.56ms delay before other regulators are enabled. fault indicator ( flt ) the active-low fault indicator pulls low when any of the switching or linear regulator output voltages (except for the buck converter) are out of regulation. an internal voltage monitor is available for each regulator. when the output voltage falls and stays below 85% of the set voltage for a duration of 218ms, flt asserts. the fault- blanking time of 218ms prevents false triggering. there are pgood indicators for each regulator than can be read out through spi so that the fault can be traced back to the failing supply. an overvoltage condition on either lxn, lxp, the cuk out - put, or the boost output causes flt to assert immediately and the device to shut down. once this fault condition is cleared, toggle enp low for 1ms and then high to return the device to reinitiate the startup sequence. the device turns on the switching and linear regulators in the order shown in table 3. in the event of a thermal fault (i.e., the junction tempera - ture t j exceeds +165 n c), flt asserts immediately and the device shuts down. once the device cools by 15 n c, the device turns on the switching and linear regulators in the order shown in table 3. spi-compatible serial interface the device has an spi interface consisting of three inputs and one output: the clock signal (clk), data input (din), chip-select input ( cs ), and data output (dout). use a clock frequency of 4mhz or less to communicate with the device. the serial interface works with the clock polarity (cpol) set to 0 and the clock phase (cpha) set to 1 (figure 5). the device may also be used without the spi interface (see the stand-alone mode section). initiate a write to the device by pulling cs low and setting the msb bit to 0. data is written msb first and is clocked in on the falling edge of each clock pulse. each write to the device consists of 32 bits (1 word). pull cs high after the 32nd bit has been clocked in to latch the data. the internal register is not updated if cs is pulled high before the falling edge of the 32nd clock pulse. the spi interface only accepts data inputs of 32 bits or a multiple of 32 bits. to read from the spi register, write a word to the spi inter - face with the msb bit set to 1. the 31 remaining bits are don?t cares. data output is available on the falling edge of each clock pulse. dout goes into a high- impedance state as soon as cs is pulled high. tables 5 and 6 show the formats of the write and read words, respectively. as shown in table 5, some of the bits written to the spi register are ignored and can be figure 5. spi timing diagram (cpol = 0, cpha = 1) table 3. supply sequencing clk din dout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 cs enable input supply-sequencing order en3 enp en1 en2 1st 2nd 3rd 4th 5th 0 0 x x device is in shutdown. 1 0 x x buck converter is outputting 3.3v. all other blocks are in shutdown. 0 1 x x buck converter is in shutdown. an external 3.3v to 5v supply powers ina. x 1 0 0 spi determines which regulator is on. x 1 0 1 vsh vsl vgh vgl ? x 1 1 0 vsl vsh vgl vgh ? x 1 1 1 vsl vgl vsh vgh vsl switch downloaded from: http:///
21 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 set to either 0 or 1. the bit description table (table 7) describes each bit in the data input and output and indi - cates whether it is a read-only or read/write bit. enable when enp is pulled high with en1 and en2 low, the device allows spi to independently enable and disable each switching and linear regulator. status and power-good indicators a number of status-monitoring circuits detect and indi - cate irregular conditions. the spi output data includes information about the device thermal shutdown status and undervoltage conditions on the switching and linear regulator outputs. specifically, flags are set to indicate if the device junction temperature exceeds +165 n c and if the output voltages of the switching and linear regulators fall below 85% of their set values. soft-start the soft-start time of the linear regulators, defined as the amount of time it takes for the regulator output to ramp from 0v to the set voltage, is programmable between 6.78ms, 13.6ms, 27.1ms, and 54.3ms. current limit (boost and cuk) the current limit (i lim ) of the switching converters is pro - grammable based on table 1. current limit during soft-start the current limit of the switching converters during soft- start is programmable based on table 1. after the soft- start period, the current limit is reset to the programmed current limit. vcom dac an integrated 7-bit dac provides offset to the vcinh and vcinl inputs in increments of 7.8mv in a positive direction. the size of the offset is given as: vcom offset = n x 7.8mv where n is the numeric value of the digital code stored in dac[6:0]. table 4 shows the relationship of the vcom dac offset and selected digital codes. table 4. vcom dac offsettable 5. write format (r/ w = 0) note: ??? is ignored by the spi register and can be set to either 0 or 1. table 6. read format (r/ w = 1) note: ?x? reflects the r/ w bit from the previous write sequence. spi control bits for dac vcom dac offset (mv) dacu dac[6:0] 1 111 1111 +998.4 1 100 0000 +499.2 1 000 0000 0 bit name r/ w ?? ? ? envsls envsh vshlim1vshlim0 vshlim66 ? envsl vsllim1vsllim0 vsllim66 ? envgh vghstti1vghstti0 ? envgl vglstti1vglstti0 ? dacu dac6dac5 dac4 dac3 dac2 dac1 dac0 bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name x vsls_on t vcomh vcoml pgvsh envsh vshlim1vshlim0 vshlim66 pgvsl envsl vsllim1vsllim0 vsllim66 pgvgh envgh vghstti1vghstti0 pgvgl envgl vglstti1vglstti0 pgvin dacu dac6dac5 dac4 dac3 dac2 dac1 dac0 bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 downloaded from: http:///
22 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 table 7. bit description bit number bit name read/ write function 31 r/ w w 0 = write to the spi register and read out the current contents.1 = read out the contents of the spi register. the remaining 31 bits are don?t cares and are not written to the register. 30 vsls_on r vsl switch status:0 = vsl switch is off. 1 = vsl switch is on. 29 t r thermal-shutdown indicator:0 = die temperature is not over +165 n c. 1 = die temperature exceeds +165 n c. 28 vcomh r positive vcom buffer status:0 = positive vcom buffer is inactive. 1 = positive vcom buffer is active. 27 vcoml r negative vcom buffer status:0 = negative vcom buffer is inactive. 1 = negative vcom buffer is active. 26 pgvsh r vsh boost converter power-good indicator:0 = vsh is out of regulation. 1 = vsh is within regulation. envsls w vsl switch enable:0 = turn off vsl switch. 1 = turn on vsl switch. 25 envsh r/w boost converter enable:0 = disable the converter (default). 1 = enable converter. 24 vshlim1 r/w boost converter current limit:00 = see table 1 and the current limit equation. 01 = see table 1 and the current limit equation. 10 = see table 1 and the current limit equation. 11 = see table 1 and the current limit equation. 23 vshlim0 r/w 22 vshlim66 r/w boost converter startup current limit:0 = set the current limit during startup to i lim (default). 1 = reduce the current limit during soft-start. 21 pgvsl r vsl cuk converter power-good indicator:0 = vsl is out of regulation. 1 = vsl is within regulation. 20 envsl r/w cuk converter enable:0 = disable the converter (default). 1 = enable converter. 19 vsllim1 r/w cuk converter current limit:00 = see table 1 and the current limit equation. 01 = see table 1 and the current limit equation. 10 = see table 1 and the current limit equation. 11 = see table 1 and the current limit equation. 18 vsllim0 downloaded from: http:///
23 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 stand-alone mode the device can be used in stand-alone mode without the spi interface. when unused, connect the data and clock inputs, din and clk, to gnd. the chip-select input, cs , is internally pulled up to ina and can either be left unconnected or connected to ina. in this mode, the default current-limit and soft-start values are used and sequencing is controlled using the en1 and en2 inputs as illustrated in table 3. since the dac value cannot be changed, use the vcinh and vcinl inputs to set the vcomh or vcoml output levels. table 7. bit description (continued) bit number bit name read/ write function 17 vsllim66 r/w cuk converter startup current limit:0 = set the current limit during startup to i lim (default). 1 = reduce the current limit during soft-start. 16 pgvgh r vgh positive voltage-linear regulator power-good indicator:0 = vgh is out of regulation. 1 = vgh is within regulation. 15 envgh r/w vgh positive voltage-linear regulator enable:0 = disable the regulator (default). 1 = enable the regulator. 14 vghstti1 r/w vgh linear regulator soft-start timing:00 = set the soft-start time to 6.78ms (default). 10 = set the soft-start time to 13.6ms. 01 = set the soft-start time to 27.1ms. 11 = set the soft-start time to 54.3ms. 13 vghstti0 r/w 12 pgvgl r vgl negative voltage-linear regulator power-good indicator:0 = vgl is out of regulation. 1 = vgl is within regulation. 11 envgl r/w vgl negative voltage-linear regulator enable:0 = disable the regulator (default). 1 = enable the regulator. 10 vglstti1 r/w vgl linear regulator soft-start timing:00 = set the soft-start time to 6.78ms (default). 10 = set the soft-start time to 13.6ms. 01 = set the soft-start time to 27.1ms. 11 = set the soft-start time to 54.3ms. 9 vglstti0 8 pgvin r ina input supply power-good indicator:0 = v ina is below uvlo. 1 = v ina is above uvlo. 7 dacu r/w reserved bit: always set to 1. 6 dac6 r/w vcom dac digital input bits. use dac[6:0] to adjust the vcom dac output from 0 to 1v in 7.8mv increments. see the vcom dac section to determine the relationship between the output voltage and digital input. 5 dac5 r/w 4 dac4 r/w 3 dac3 r/w 2 dac2 r/w 1 dac1 r/w 0 dac0 r/w downloaded from: http:///
24 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 design procedure buck converter inductor selection three key inductor parameters must be specified for operation with the device: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dc ). to determine the inductance value, select the ratio of induc - tor peak-to-peak ac current to dc average current (lir) first. for lir values that are too high, the rms currents are high, and therefore i 2 r losses are high. use high- valued inductors to achieve low lir values. typically, inductance is proportional to resistance for a given pack - age type, which again makes i 2 r losses high for very low lir values. a good compromise between size and loss is to select a 30% to 60% peak-to-peak ripple current to average-current ratio. if extremely thin high-resistance inductors are used, as is common for lcd-panel appli - cations, the best lir can increase between 0.5 and 1.0. the value of the inductor is determined as follows: in3 out3 out3 sw (v -v ) d l lir i f = and: out3 in3 v d v = ? where v in3 is the input voltage, v out3 is the output volt - age, i out3 is the output current, is the efficiency of the buck converter, d is the duty cycle, and f sw is 2.1mhz (the switching frequency of the buck converter). the efficiency of the buck converter can be estimated from the typical operating characteristics and accounts for losses in the internal switch, catch diode, inductor r dc , and capacitor esr. the exact inductor value is not critical and can be adjust - ed to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. on the other hand, higher induc - tance increases efficiency by reducing the rms current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the satura - tion current rating (i sat ) must be high enough to ensure that saturation can occur only above the maximum current-limit value. if the buck output must withstand short-circuit conditions, an inductor with saturation cur - rent of 6a must be used. capacitor selection the input and output filter capacitors should be of a low esr type (tantalum, ceramic, or low-esr electrolytic) and should have i rms ratings greater than: 2 in(rms) o lir i i d (1-d ) 12 = + for the input capacitor: o out(rms) lir i i 12 = for the output capacitor where d is the duty cycle given above. the output voltage contains a ripple component whose peak-to-peak value depends on the value of the esr and capacitance of the output capacitor, and is approxi - mately given by: d v ripple = d v esr + d v cap d v esr = lir x i o x r esr o cap sw lir i v 8cf ?= diode selection the catch diode should be a schottky type to minimize its voltage drop and maximize efficiency. the diode must be capable of withstanding a reverse voltage of at least v in3(max) , the maximum value of the input voltage. the diode should have an average forward-current rating greater than: i d = i o x (1-d) where d is the duty cycle given above. in addition, ensure that the peak-current rating of the diode is greater than: out lir i1 2 ?? + ???? boost converter inductor selection considerations used in selecting an inductor for the buck converter are equally applicable in selecting an inductor for the boost converter. use the following equations to determine an appropriate inductor value: in in sw vd lp lir i f = downloaded from: http:///
25 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 and : oo in in vi i v = v in d1 v o = ? where v in is the input voltage, v o is the output volt - age, i o is the output current, is the efficiency of the boost converter, d is the duty cycle, and f sw is 1.2mhz (the switching frequency of the boost converter). the efficiency of the boost converter can be estimated from the typical operating characteristics and accounts for losses in the internal switch, catch diode, inductor r dc , and capacitor esr. capacitor selection the input and output filter capacitors should be of a low esr type (tantalum, ceramic, or low-esr electrolytic) and should have i rms ratings greater than: in in(rms) lir i i 12 = for the input capacitor: 2 out(rms) o lir d 12 ii 1- d + = for the output capacitor, where i in and d are the input current and duty cycle given above.the output voltage contains a ripple component whose peak-to-peak value depends on the value of the esr and capacitance of the output capacitor, and is approxi - mately given by: d v ripple = d v esr + d v cap esr in esr lir v i (1 ) r 2 ? = + o cap sw id v cf ?= where i in and d are the input current and duty cycle given above. rectifier diode the catch diode should be a schottky type to minimize its voltage drop and maximize efficiency. the diode must be capable of withstanding a reverse voltage of at least v vsh . the diode should have an average forward cur - rent rating greater than: i d = i in x (1 - d) where i in and d are the input current and duty cycle given above. in addition, ensure that the peak-current rating of the diode is greater than: in lir i1 2 ?? + ???? output-voltage selection the output voltage of the boost converter can be adjusted by using a resistive voltage-divider formed by r top and r bottom . connect r top between the output and fbp and connect r bottom between fbp and gnd. select r bottom in the 10k i to 50k i range. calculate r top with the following equation: vsh top bottom fbp v r r ( -1) v = where v fbp , the boost converter?s feedback set point, is 1v. place both resistors as close to the device as pos - sible. connect r bottom to the analog ground plane and route this connection away from the power traces. loop compensation choose r comp to set the high-frequency integrator gain for fast-transient response. choose c comp to set the integrator pole to maintain loop stability. for low-esr output capacitors, use table 8 to select initial values for r comp and c comp . use a 15pf capacitor in parallel to r comp and c comp . table 8. boost example compensation values v vsh (v) 5 7 13 15 i vsh (a) 0.6 0.6 0.1 0.3 p out (w) 3 4.2 1.3 4.5 inductor value ( f h) 3.3 3.3 15 4.7 r comp (k w ) 47 56 31 56 c comp (pf) 220 270 680 390 downloaded from: http:///
26 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 to further optimize transient response, vary r comp in 20% steps and c comp in 50% steps while observ - ing transient-response waveforms. the ideal transient response is achieved when the output settles quickly with little or no overshoot. connect the compensation network to the analog ground plane and route this con - nection away from the power traces. p-channel fet selection the p-channel fet used to gate the boost-converter?s input should have low on-resistance as it affects overall efficiency of the boost converter. the fet must be rated to the full current rating of boost inductor. connect a resistor (r sg ) between the source and gate of the fet. under normal operation, r sg carries a gate drive current of 53a (typ) and 36a (min) and the resulting gate-source voltage (v gs ) turns on the fet. when the gate drive is removed under a fault condition or in shutdown, r sg bleeds off charge to turn off the fet. size r sg to produce the v gs needed to turn on the fet. cuk converter inductor selection considerations used in selecting an inductor for the buck converter are equally applicable in selecting an inductor for the cuk converter. use the same value and type of inductor for ln1 and ln2. use the following equation to determine their value: ina in sw vd ln1 ln2 lir i f = = the input current and duty cycle are calculated as fol - lows: vsl o in ina |v | | i | i v = vsl schottky ina vsl schottky |v | v d v |v | v + = ++ in the equations above, v ina is the input voltage, v vsl is the output voltage, i in is the input current, i o is the output current, is the efficiency of the cuk converter, d is the duty cycle, and f sw is 1.2mhz (the switching fre - quency of the cuk converter). the efficiency of the cuk converter can be estimated from the typical operating characteristics and accounts for losses in the internal switch, catch diode, inductor r dc , and capacitor esr. capacitor selection the value of the cuk coupling capacitor, c 1 , can be calculated as follows: in vsl sw |i | d cvr (v |v |) f + where cvr is the capacitor voltage-ripple ratio and is the ratio of the capacitor?s voltage ripple to the average voltage across the coupling capacitor. a good starting value for cvr is 0.05. it is important that a low-esr type is used as all the output power flows through this capaci - tor. the voltage rating of the coupling capacitor must be at least v ina + |v vsl |. the input and output filter capacitors should be of a low esr type (tantalum, ceramic, or low-esr electrolytic) and should have i rms ratings greater than: in in(rms) lir i i 12 = for the input capacitor: o out(rms) lir | i | i 12 = for the output capacitor, where i in is the input current given above.the output voltage contains a ripple component whose peak-to-peak value depends on the value of the esr and capacitance of the output capacitor, and is approxi - mately given by: d v ripple = d v esr + d v cap d v esr = lir x |i o | x r esr rectifier diode the catch diode should be a schottky type to minimize its voltage drop and maximize efficiency. the diode must be capable of withstanding a reverse voltage of at least (v ina + |v vsl |). the diode should have an average for - ward current rating greater than: i d = (i in + |i o |) x (1 - d) where i in and d are the input current and duty cycle given above. in addition, ensure that the peak-current rating of the diode exceeds i in + |i o |. downloaded from: http:///
27 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 output-voltage selection the output voltage of the cuk converter can be adjusted by using a resistive voltage-divider formed by r top and r bottom . connect r top between ref and fbgl and connect r bottom between fbgl and the output of the cuk converter. select r top greater than 20k i to avoid loading down the reference output. calculate r bottom with the following equation: fbn vsl bottom top ref fbn v |v | rr v -v + = where v vsl is the desired output voltage, v ref = 1.25v, and v fbn = 0.2 x v ref = 0.25v (the regulated feedback voltage of the converter). note that ref can only source up to 80a total (for cuk and vgl feedback). loop compensation see table 9 to select the compensation components for the cuk converter. selection of the n-channel fet for vsl output an n-channel fet can be used to delay the on switch of the vsl output when the charge pumps use the vsl output voltage and vgh and/or vgl are required to be present before vsl (see table 3 and specifically the mode for en1 = en2 = 1). the n-channel fet, connect - ed in series with the cuk converter?s output, should have low on-resistance. connect a resistor (r gs ) between the gate and source of the fet. under normal operation, r gs carries a gate-drive current of 50a, typ (38a min) and the resulting gate-source voltage (v gs ) turns on the fet. size r gs to produce the v gs needed to turn on the fet.when this fet is not used, leave vsls unconnected. charge pumps selecting the number of charge-pump stages for most applications, a single-stage charge pump suf - fices as shown in the typical operating circuits . the flying capacitor can be connected to either lxn or lxp. in the lxn case, the output voltages are: v vcp = v ina + |v vsl | + v schottky + v vsh - 2 x v d v vcn = - (v ina + 2 x |v vsl | + v schottky - 2 x v d ) in the lxp case, the output voltages are: v vcp = 2 x v vsh - v schottky - 2 x v d v vcn = - (|v vsl | + v v sh - v schottky - 2 x v d ) the equations above assume that the inverting charge pump is connected to the cuk output (figure 9). in the case where the cuk converter is unused or operates in parallel with the boost converter, connect the invert - ing charge pump to ground (figure 10 ) , make lxp the switching node, use the equations for the lxp case, and set |v vsl | to 0v in those equations. figure 6. multistage noninverting charge pump for positive output (cuk is active; if cuk is inactive, make lxp the switching node) figure 7. multistage inverting charge pump for negative output (cuk is active) figure 8. multistage inverting charge pump for negative output (cuk is inactive) table 9. cuk example compensation values lxp or lxn vsh vcp lxp or lxn vsl vcn lxp vcn v vsl (v) -5 -7 -12 i vsl (a) +0.6 +0.6 +0.1 p out (w) +3 +4.2 +1.2 inductor value ( f h) +3.3 +3.3 +15 r compn (k i ) +47 +56 +31 c compn (pf) +220 +270 +680 downloaded from: http:///
28 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 if larger output voltages are needed, use multistage charge pumps (however, the maximum charge-pump voltage is limited by the absolute maximum ratings of vcp and drvn). figures 6, 7, and 8 show the configura - tion of a multistage charge pump for both positive and negative outputs. for multistage charge pumps with lxn as the switching node, the output voltages are given by: v vcp = n x (v ina + |v vsl | + v schottky + v vsh - 2 x v d ) v vcn = -n x (v ina + 2 x |v vsl | + v schottky - 2 x v d ) for those with lxp as the switching node, the output voltages are: v vcp = n x (2xv vsh - v schottky - 2 x v d ) v vcn = -n x (|v vsl| + v vsh - v schottky - 2 x v d ) the equations above assume that the inverting charge pump is connected to the cuk output (figures 6 and 7). in the case where the cuk converter is unused or operates in parallel with the boost converter, connect the inverting charge pump to ground (figure 8), make lxp the switch - ing node, use the equations for the lxp case, and set |v vsl | to 0v in those equations. flying capacitors increasing the flying-capacitor value lowers the effec - tive source impedance and increases the output-current capability. however, increasing the capacitance indefi - nitely has a negligible effect on output-current capability because the internal switch resistance and the diode impedance place a lower limit on the source impedance. a 0.1f ceramic capacitor works well in most low-current applications. the voltage rating of the flying capacitors for the noninverting charge pump should exceed v cp while that for the negative-charge pump should exceed the magnitude of vcn. charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output-ripple voltage and the peak- to-peak transient voltage. with ceramic capacitors, the output-voltage ripple is dominated by the capacitance value. use the following equation to approximate the required output capacitance for the noninverting charge pump connected to vcp: load_vcp out_vcp sw ripple_vcp di c fv where d is the duty cycle of the switching node to which the flying capacitor is connected, c out_vcp is the output capacitor of the noninverting charge pump, i load_vcp is the load current of the noninverting charge pump, f sw is the switching frequency of the boost and cuk converters, and v ripple_vcp is the peak-to-peak value of the output ripple.for the inverting charge pump connected to vcn, use the following equation to approximate the required out - put capacitance: load_vcn out_vcn sw ripple_vcn (1-d) i c fv where d is the duty cycle of the switching node to which the flying capacitor is connected, c out_vcn is the out - put capacitor of the inverting charge pump, i load_vcn is the load current of the inverting charge pump, f sw is the switching frequency of the boost and cuk convert - ers, and v ripple_vcn is the peak-to-peak value of the output ripple. charge-pump rectifier diodes use high-speed silicon switching diodes with a current rating equal to or greater than two times the average charge-pump input current. if it helps to avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with an equivalent current rating. positive gate-voltage linear regulator output-voltage selection the output voltage of the positive gate-voltage linear regulator can be adjusted by using a resistive voltage- divider formed by r top and r bottom . connect r top between the output and fbgh and connect r bottom between fbgh and gnd. select r bottom in the 10k to 50k range. calculate r top with the following equation: vgh top bottom fbgh v r r ( - 1) v = where v vgh is the desired output voltage and v fbgh = 1v (the regulated feedback voltage for the regulator). place both resistors as close to the device as possible. avoid excessive power dissipation within the internal pmos device of the linear regulator by paying attention to the voltage drop across the drain and source. the amount of power dissipation is given by: p diss = (v vcp - v vgh ) x i load(max) where v vcp is the noninverting charge-pump output volt - age applied to the drain, v vgh is the regulated output downloaded from: http:///
29 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 voltage, as well as the source voltage, and i load(max) is the maximum load current. stability requirements the positive gate-voltage linear regulator (vgh) requires a minimum output capacitance for stability. for an output voltage of 5v to 22v and an output current of 10ma to 15ma, use a minimum capacitance of 0.47f. negative gate-voltage linear-regulator controller output-voltage selection the output voltage of the negative gate-voltage linear regulator can be adjusted by using a resistive voltage- divider formed by r top and r bottom . connect r top between ref and fbgl and connect r bottom between fbgl and the collector of the external npn transistor. select r top greater than 20k i to avoid loading down the reference output: calculate r bottom with the fol - lowing equation: fbgl v gl bottom top ref fbgl v -v rr v -v = where v vgl is the desired output voltage, v ref = 1.25v, and v fbgl = 0.8 x v ref = 1v (the regulated feedback voltage of the regulator). pass transistor selection the pass transistor must meet specifications for current gain (h fe ), input capacitance, collector-emitter saturation voltage, and power dissipation. the transistor?s current gain limits the guaranteed maximum output current to: be load(max) drvn fe(min) be v i (i - ) h r = where i drvn is the minimum guaranteed base-drive cur - rent, v be is the transistor?s base-to-emitter forward-volt - age drop, and r be is the pulldown resistor connected between the transistor?s base and emitter. furthermore, the transistor?s current gain increases the linear regula - tor?s dc loop gain (see the stability requirements sec - tion), so excessive gain destabilizes the output.the transistor?s saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator can support. also, the package?s power dissipation limits the usable maximum input-to-output voltage differential. the maximum power- dissipation capability of the transistor?s package and mounting must exceed the actual power dissipated in the device. the power dissipated equals the maximum load current (i load(max)_lr ) multiplied by the maximum input-to-output voltage differential: p diss = (v vgl - v vcn ) x i load(max) where v vgl is the regulated output voltage on the collec - tor of the transistor, v vcn is the inverting charge-pump output voltage applied to the emitter of the transistor, and i load(max) is the maximum load current. stability requirements the vgl linear-regulator controller uses an internal transconductance amplifier to drive an external pass transistor. the transconductance amplifier, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. the transconductance amplifier regulates the output voltage by controlling the pass transistor?s base current. the total dc loop gain is approximately: bias fe v_lr ref t load ih 4 a1 v vi ?? ?? ? + ?? ???? ?? where v t is 26mv at room temperature, and i bias is the current through the base-to-emitter resistor (r be ). for the device, the bias current for the negative voltage- linear regulator is 0.1ma. therefore, the base-to-emitter resistor should be chosen to set 0.1ma bias current: be be v 0.7v r 6.8k 0.1ma 0.1ma = = = w the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, pass transistor?s input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capacitor?s esr generates a zero. for proper operation, use the fol - lowing equations to verify the linear regulator is properly compensated: 1) first, determine the dominant pole set by the linear regulator?s output capacitor and the load resistor: load(max)_lr pole_lr out_lr out_lr i f 2c v = the unity-gain crossover of the linear regulator is: f crossover = a v_lr x f pole_lr downloaded from: http:///
30 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 2) the pole created by the internal amplifier delay is approximately 1mhz: f pole_amp = 1mhz 3) next, calculate the pole set by the transistor?s input capacitance, the transistor?s input resistance, and the base-to-emitter pullup resistor: pole_in in be in 1 f 2 c (r //r ) = where: m fe in in tm gh c ,r 2f g = = g m is the transconductance of the pass transistor, and f t is the transition frequency. both parameters can be found in the transistor?s data sheet. because r be is much greater than r in , the above equation can be simplified: pole_in in in 1 f 2c r = substituting for c in and r in yields: t pole fe f f h = 4) next, calculate the pole set by the linear regulator?s feedback resistance and the capacitance between fb and agnd (including stray capacitance): pole_fb fb top bottom 1 f 2 c (r //r ) = where c fb is the capacitance between fbgl node and gnd (approximately 30pf), r top is the upper resistor of the linear regulator?s feedback divider, and r bottom is the lower resistor of the divider. 5) next, calculate the zero caused by the output capaci - tor?s esr: zero_esr out_lr esr 1 f 2c r = where r esr is the esr of c out_lr . to ensure stabil - ity, make c out_lr large enough so the crossover occurs well before the poles and zero calculated in steps 2 to 5. the poles in steps 3 and 4 gener - ally occur at several megahertz, and using ceramic capacitors ensures the esr zero occurs at sev - eral megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move one of the other poles or the zero below 1mhz. table 10 is a list of recommended minimum output capacitances for the vgl linear regulator and are appli - cable for output currents in the 10ma to 15ma range. applications information power dissipation an ic?s maximum power dissipation depends on the thermal resistance from the die to the ambient environ - ment and the ambient temperature. the thermal resis - tance depends on the ic package, pcb copper area, other thermal mass, and airflow. more pcb copper, cool - er ambient air, and more airflow increase the possible dissipation, while less copper or warmer air decreases the ic?s dissipation capability. the major components of power dissipation are the power dissipated in the buck converter, boost converter, cuk converter, vgh linear regulator, vgl linear regulator controller, and the power dissipated by the vcom buffers. buck converter in the buck converter, conduction and switching losses in the internal mosfet are dominant. estimate these losses using the following formula: 2 lx3 in(dc, max) ds_on in3 in(dc,max) r f sw p (i d) r 0.5 v i (t t ) f ?? ???? ?? + + ?? where r ds_on is the on-resistance of the buck convert - er?s internal fet, t r = 5ns, t f = 5ns, and f sw = 2.1mhz. table 10. minimum output capacitance vs. output voltage range for vgl linear regulator (i out = 10ma to 15ma) output voltage range (v) minimum output capacitance (f) -2 r v vgl r -4 2.2 -5 r v vgl r -7 1.5 -8 r v vgl r -13 1 downloaded from: http:///
31 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 boost converter in the boost converter, conduction and switching losses in the internal mosfet are dominant. estimate these losses using the following formula: 2 lxp in(dc,max) ds_on vsh in(dc,max) r f sw p (i d) r 0.5 v i (t t ) f ?? ?? ?? ?? + + ?? where r ds_on is on-resistance of the boost converter?s internal fet, t r = 7ns, t f = 16ns, and f sw = 1.2mhz. cuk converter a similar analysis applies to the cuk converter. the power dissipation in the integrated low-side fet is: ( ) 2 lxn in(dc,max) ds_on vsl ina in(dc,max) r f sw p (i d) r 0.5 |v | + v i (t t ) f ?? ???? ?? + + ?? where r ds_on is on-resistance of the boost converter?s internal fet, t r = 7ns, t f = 16ns, and f sw = 1.2mhz. positive gate-voltage linear regulator use the lowest number of charge-pump stages possible in supplying power to the positive voltage-linear regula - tor. doing so minimizes the drain-source voltage of the integrated pmos switch and power dissipation. the power dissipated in the switch is given as: vgh vcp vgh load(max) p (v - v ) i = negative gate-voltage linear-regulator controller use the lowest number of charge-pump states possible to provide the negative voltage to the vgl linear regu - lator. estimate the power dissipated in the vgl linear-regulator controller using the following: p vgl = (v ina + |v vcn | - v be ) x i drvn where v be is the base-emitter voltage of the external npn bipolar transistor and i drvn is the current sourced from drvn to the r be bias resistor and to the base of the transistor. vcom buffers the power dissipated in the vcom buffers depends on the output current, the output voltage, and the supply voltages. the two vcom buffers, vcomh and vcoml, use separate supply rails. vcomh is powered between vcomp and gnd while vcoml is powered between ina and vcomn. the power dissipated in vcomh is given by: p vcomh(source) = (v vcomp - v comh ) x i out_source p vcomh(sink) = v comh x i out_sink where i out_source is the output current sourced by the buffer and i out_sink is the output current that the buf - fer sinks. similarly, the power dissipated in the vcoml buffer is given by: p vcoml(source) = (v ina - v coml ) x i out_source p vcoml(sink) = (v coml - v vcomn ) x i out_sink total power dissipation the total power dissipated in the package is the sum of the losses calculated above and the power due to the quiescent current consumed in the device (i in3 in con - tinuous mode for the buck converter and i ina for the rest of the device). therefore, total power dissipation can be estimated as follows: p t = p lx3 + p lxp + p lxn + p vgh + p vgl + p vcomh + p vcoml + (v in3 x i in3 ) + (v ina x i ina ) achieve maximum heat transfer by connecting the exposed pad to a thermal landing pad and connecting the thermal landing pad to a large ground plane through thermal vias. layout considerations careful pcb layout is critical in achieving stable and optimized performance. follow the following guidelines for good pcb layout: u place decoupling capacitors as close to the ic as possible. connect the power ground planes and the analog ground plane together at one point close to the device. u connect input and output capacitors to the power ground planes; connect all other capacitors to the signal ground plane. u keep the high-current paths as short and wide as possible. keep the path of switching currents short. u place the feedback resistors as close to the ic as possible. connect the negative end of the resistive divider, as well as compensation rc, to the analog ground plane and keep the center tap away from switching nodes. u route digital i/os and high-speed switching nodes (lx3, lxn, and lxp) away from sensitive analog nodes (fb3, fbp, fbn, compp, compn, and ref). refer to the max16927 evaluation kit data sheet for a recommended pcb layout. downloaded from: http:///
32 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 block diagram fbgh drvnfbgl fbp pgndp vgh in3 vcinh fbn lxp vcp lxn lx3fb3 bst pgndn en3 ina vcomn vcomh vcomp vcinl pgnd3 avl pgood compp compn gate vsls sync refgnd -4.5v to -12v cuk 3.3v buck oscillator dac 7 positive gate- voltage linear regulator negative gate- voltage linear regulator controller spi and logic control bandgap reference flt dout ssen din cs clk enp en1 en2vcoml + + 4.5v to 18v boost max16927 downloaded from: http:///
33 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating circuits figure 9. typical operating circuit fbgh drvn vcn vgl fbgl fbp pgndp vsh vgh in3 6v to 16v vgh out3 vcinh fbn lxp lp vcp lxn l n1 l n2 c 1 lx3 l bst pgndn fb3 ina to out3 or separate 3v to 5v supply 1 positive output1 negative output vcomn vcomh vcomp vcinl sync en3avl pgnd3 compp compn gate vsls ref pgood refgnd -4.5v to -12v cuk 3.3v buck oscillator dac positive gate- voltage linear regulator negative gate- voltage linear regulator controller spi and logic control bandgap reference flt dout ssen din cs clk enp en1 en2vcoml + + 4.5v to 18v boost 7 max16927 vsh vcp vcn v sl_sw vsl downloaded from: http:///
34 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 typical operating circuits (continued) figure 10. typical high-power operating circuit fbgh drvn vcn vgl fbgl fbp pgndp vsh vgh in3 6v to 16v l vgh out3 vcinh fbn ina lxp lp vcp lxn lx3 bst pgndn fb3 ina to out3 or separate 3v to 5v supply high-power positive output vcomn vcomh vcomp vcinl sync en3avl pgnd3 compp compn gate vsls pgood refgnd -4.5v to -12v cuk 3.3v buck oscillator dac positive gate- voltage linear regulator negative gate- voltage linear regulator controller spi and logic control bandgap reference flt dout ssen din cs clk enp en1 en2vcoml + + 4.5v to 18v boost 7 max16927 vsh vcp vcn dac downloaded from: http:///
35 maxim integrated automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos package type package code outline no. land pattern no. 48 tqfn-ep t4877+7 21-0144 90-0133 downloaded from: http:///
automotive tft-lcd power supply with boost, buck, and cuk converters, vcom buffers, gate drivers, and spi interface max16927 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 36 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2014 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/10 initial release ? 1 12/10 added ?measurement bandwidth = 1khz? to toc 11 and toc 12 9 2 9/13 removed short ina to enp, added description on how to enable boost converter, clarified ina > 2.9v then en from low to go high 14, 19 3 10/14 updated general description , features , pin description , vcom buffers , vcom dac sections, and toc 32, table 4, and table 7 to match vcoml buffer performance, and updated vgh and vgl soft-start time 1, 5, 12, 14, 19, 21, 23 downloaded from: http:///

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