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73s8010r low cost smart card interface simplifying system integration ? data sheet ds_80 10r_022 august 2009 rev. 1.6 ? 2009 teridian semiconductor corporation 1 description the teridian 73s8010r is a single smart card interface ic that provide s full electrical compliance with iso - 7816 - 3 and emv 4.0 (emv2000) specifications. interfacing with the host is done through the two - wire i 2 c bus and one interrupt output to inform the system controller of the card presence and faults. the card clock signal can be generated by an on - chip oscillator using an external crystal, or by connection to a clock signal. the teridian 73s8010r incorporates an iso - 7816 - 3 acti vation/deactivation sequencer that controls the card signals. level - shifters drive the card signals with the selected card voltage (3 v or 5 v), coming from an internal low drop - out (ldo) voltage regulator. this ldo regulator is powered by a dedicated po wer supply input , v pc . digital circuitry is separately powered by a digital power supply , v dd . with its embedded ldo regulator, the teridian 73s8010r is a cost - effective solution for any application where a 5 v (typically - 5% +10%) power supply is avail able. hardware support for auxili ary i/o lines, c4 / c8 contacts is provided. emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. the fault can be a card over - current, a v dd (digital p ower supply), a v pc (regulator power supply), a v cc (card power supply) or an over - heating fault. the card over - current circu itry is a true current detect function, as opposed to v cc voltage drop detection, as usually implemented in icc interface ics. th e v dd voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. it allows automated card deactivation at a customized v dd voltage threshold value. it can be used, for instance, to match the system controlle r operating voltage range. applications ? set - top - box conditional access and pay - per - view ? point of sales & transaction terminals ? control access & identification ? multiple card and sam reader configurations advantages ? single smart card interface ? ic firmware compatible with tda8020 ? traditional step - up converter is replaced by an ldo regulator ? greatly reduced power dissipation ? fewer external components are required ? better noise performance ? high current capability (90 ma supplied to the card ) ? small for mat (5x5x0.8 mm) qfn32 package option ? true card over - current detection features ? c ard interface ? complies with iso - 7816 - 3 and emv 4.0 ? an ldo voltage regulator provides 3 v / 5 v to the card from an external power supply input ? iso - 7816 - 3 activation / deactiv ation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry ? protection includes 3 voltage supervisors that detect voltage drops on v cc card and on power supplies v dd and v pc ? over - current detection 150 ma max ? 1 card detection input ? auxiliary i/o lines, for c4 / c8 contact signals ? host interface ? fast mode, 400 kbps i 2 c slave bus ? 8 possible devices in parallel ? one control register and one status register ? interrupt output to the host for fault detection ? cr ystal oscillator or host clock, up to 27 mhz ? 6 kv esd protection on the card interface ? so28 or qfn32 package downloaded from: http:///
73s8010r data sheet ds_8010r_022 rev. 1.6 2 functional diagram pin numbers reference the so28 package [pin numbers] reference the qfn32 package figure 1 : 73s80 10 r block diagram [2 ] 5 gnd icc i / o buffers vdd voltage supervisor voltage reference i 2 c digital & fault logic vdd fault vcc fault int _clk vdd vpc rst clk pres temp fault [3 ] 6 [7 ] 10 [8 ] 11 [ 10 ] 12 [ 11 ] 13 [ 13 ] 15 [ 14 ] 16 [ 20 ] 21 [ 17 ] 18 [ 26 ] 26 [ 28 ] 28 [ 27 ] 27 [ 21 ] 22 iso - 7816 sequencer r-c osc . ldo regulator & voltage supervisors icc reset buffer icc clock buffer over temp i/o aux 1 aux 2 iouc aux 1 uc aux 2 uc gnd vddf _ adj xtal osc clock generation xtalin xtalout [ 24 ] 25 [ 23 ] 24 nc [4 , 5 , 6 , 9 , 16 , 25 , 32 ] 7 , 8 , 9 [ 31 ] 3 sad 2 [ 29 ] 1 sad 0 [ 30 ] 2 sad 1 vcc gnd [ 12 ] 14 [ 15 ] 17 gnd [1 ] 4 [ 22 ] 23 int [ 19 ] 20 sda [ 18 ] 19 scl vpc fault downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 3 table of contents 1 pinout ............................................................................................................................................. 5 2 electrical specifications ................................................................................................................ 8 2.1 absolute maximum ratings ..................................................................................................... 8 2.2 recommended operating conditions ...................................................................................... 8 2.3 smart card interface requirements ........................................................................................ 9 2.4 digital signals characteristics ............................................................................................... 11 2.5 dc characteristics ................................................................................................................ 11 2.6 i 2 c inte rface characteristics .................................................................................................. 12 2.7 voltage / temperature fault detection circuits ...................................................................... 12 3 applications information ............................................................................................................. 13 3.1 example 73s8010r schematics ........................................................................................... 13 3.2 system controller interface (i 2 c bus) .................................................................................... 14 3.3 power supply and voltage supervision ................................................................................. 17 3.4 card power supply ............................................................................................................... 18 3.5 over - temperature monitor ..................................................................................................... 18 3.6 on - chip oscillator and card clock ......................................................................................... 18 3.7 activation sequence ............................................................................................................. 19 3.8 deactivation sequence ......................................................................................................... 19 3.9 interrupt ................................................................................................................................ 20 3.10 warm reset .......................................................................................................................... 21 3.11 i/o circuitry and ti ming ......................................................................................................... 21 4 mechanical drawings .................................................................................................................. 22 4.1 32 - pin qfn ........................................................................................................................... 22 4.2 28 - pin so ............................................................................................................................. 23 5 ordering information ................................................................................................................... 24 6 related documentation ............................................................................................................... 24 7 conta ct information ..................................................................................................................... 24 revision history .................................................................................................................................. 25 downloaded from: http:///
73s8010r data sheet ds_8010r_022 4 rev. 1.6 figures figure 1: 73s8010r block diagram ......................................................................................................... 2 figure 2: 73s8010r 32 - pin qfn pinout .................................................................................................. 5 figure 3: 73s8010r 28 - pin so pinout ..................................................................................................... 5 figure 4: typical 73s8010r application schematic ............................................................................... 13 figure 5: i 2 c bus write protocol ............................................................................................................ 15 figure 6: i 2 c bus read protocol ............................................................................................................ 16 figure 7: i 2 c bus timing diagram .......................................................................................................... 16 figure 8: activation sequence ............................................................................................................... 19 figure 9: deactivation sequence ........................................................................................................... 20 figure 10: interrupt operation due to fault and status conditions .......................................................... 20 figure 11: warm reset operatio n ......................................................................................................... 21 figure 12: i/o timing diagram ............................................................................................................... 21 figure 13: 32 - pin qfn package dimensions ......................................................................................... 22 figure 14: 28 - pin so package dimensions ........................................................................................... 23 tables table 1: 73s8010r pin definitions .......................................................................................................... 6 table 2: absolute maximum device ratings ............................................................................................ 8 table 3: recommended operating conditions ......................................................................................... 8 table 4: dc smart card interface requi rements ..................................................................................... 9 table 5: digital signals characteristics .................................................................................................. 11 table 6: dc characteristics ................................................................................................................... 11 table 7: i 2 c characteristics ................................................................................................................... 12 table 8: voltage / temperature fault detection circuits ......................................................................... 12 table 9: device address selection ........................................................................................................ 14 table 10: control register description ................................................................................................... 14 table 11: card clock rate selection ..................................................................................................... 14 table 12: status register description .................................................................................................... 15 table 13: i2c bus timing parameters ................................................................................................... 16 table 14: choice of vcc pin capacitor ................................................................................................ . 18 table 15: card clock divisor options .................................................................................................... 18 table 16: order numbers and packaging marks .................................................................................... 24 downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 5 1 pinout the 73s80 10r is supplied as a 32 - pin qfn package and as a 2 8- pin so package . 6 7 8 9 5 4 3 2 1 17 18 19 20 2423 22 21 1011 12 13 14 15 16 32 31 3029 28 27 26 25 gnd gnd vpc ncnc nc pres i/o xtalout xtalin int gnd vdd sda scl vddf_adj nc aux2 aux1 gnd clk rst vcc nc teridian 73s8010r nc nc sad2 sad1 sad0 aux2uc aux1uc i/ouc figure 2 : 73s80 10r 32 - pin qfn pinout 73s8010r 1 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 19 20 2827 26 25 24 23 22 21 sad0 sad1 sad2 gnd vpc nc pres i/o aux2 aux1 gnd aux2uc aux1uc i/ouc xtalin xtalout int vdd sda scl vcc rst clk nc gnd nc vddf_adj gnd figure 3 : 73s80 10r 28- pin so pinout downloaded from: http:///
73s8010r data sheet ds_8010r_022 6 rev. 1.6 table 1 describes the pin functions for the device. table 1 : 73s80 10r pin definitions pin name pin (so28) pin (qfn32) type description card interface i/o 11 8 io card i/o: data signal to/from card. includes a pull - up resistor to v cc. aux1 13 11 io aux1: auxiliary data signal to/from card. includes a pull - up resistor to v cc. aux2 12 10 io aux2: auxiliary data signal to/from card. includes a pull - up resistor to v cc. rst 16 14 o card reset: provides reset (rst) signal to card. clk 15 13 o card clock: provides clock signal (clk) to card. the crystal oscillator frequency and clksel bits in the control register determine the rate of this clock. pres 10 7 i card presence switch: active high indicates card is present. i ncludes a pull - down resistor . vcc 17 15 pso card power supply C logically controlled by the sequencer, output of ldo regulator. requires an external filter capacitor to gnd. gnd 14 12 gnd card ground. miscellaneous inputs and outputs xtalin 24 23 i crystal oscillator input: can be connected to crystal or driven as a source for the card clock. xtalout 25 24 o crystal oscillator output: connected to crystal. left open if xtalin is b eing used as an external clock input. vddf_adj 18 17 i v dd threshold adjustment input: this pin can be used to overwrite a higher vddf value (that controls deactivation of the card). must be left open if unused. nc 7, 8, 9 4,5,6,9, 16,25,32 C non - connec ted pin. power supply and ground vdd 21 20 system interface supply voltage and supply voltage for internal circuitry. vpc 6 3 ldo regulator power supply source. gnd 4 1 gnd ldo regulator ground. gnd 14 12 gnd smart card i/o ground. gnd 5, 22 2,21 g nd digital ground. downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 7 pin name pin (so28) pin (qfn32) type description microcontroller interface int 23 22 o interrupt output signal (negative assertion) to the processor. a 20 k pull up to v dd is provided internally . sad0 sad1 sad2 1 2 3 29 30 31 i i i serial device address bits. digital inputs for a ddress selection that allows for the connection of up to 8 devices in parallel. address selections is as follows: sad2 sad1 sad0 (7 bit) i 2 c address 0 0 0 0x40 0 0 1 0x42 0 1 0 0x44 0 1 1 0x46 1 0 0 0x48 1 0 1 0x4a 1 1 0 0x4c 1 1 1 0x4e pins sa d0 and sad1 are internally pulled down and sad2 is internally pulled up. the default address when unconnected is 0x48. scl 19 18 i i 2 c clock signal input. sda 20 19 i/o i 2 c bi - directional serial data signal. i/ouc 26 26 io system controller data i/o to /from the card. includes a n internal pull - up resistor to v dd. aux1uc 27 27 io system controller auxiliary data i/o to/from the card. includes an internal pull - up resistor to v dd. aux2uc 28 28 io system controller auxiliary data i/o to/from the card. includes an internal pull - up resistor to v dd. downloaded from: http:///
73s8010r data sheet ds_8010r_022 8 rev. 1.6 2 electrical specifications this section provides the following: ? absolute maximum ratings ? recommended operating conditions ? smart card interface requirements ? digital signals characteristics ? dc characteristics ? i2c interface characteristics ? voltage / temperature fault detection circuits 2.1 absolute maximum ratings table 2 lists the maximum operating conditions for the 73s8010r . permanent device damage may occur if absolute maximum ratings are exceeded. exposure to the extremes of the absolute maxi mum rating for extended periods may affect device reliability. table 2 : absolute maximum device ratings parameter rating supply v oltage v dd - 0.5 to 6.0 vdc supply v oltage v pc - 0.5 to 6.0 vdc input v oltage for d igital i nputs - 0.3 to (v dd +0.5) vdc storage t emperature - 60 c to + 150 c pin v oltage (except card interface) - 0.3 to (v dd + 0.5) vdc pin v oltage (card interface) - 0.3 to (v cc + 0. 5 ) vdc esd t olerance C card interface pins +/ - 6 kv esd t olerance C other pins +/ - 2 kv note: esd testing on smart card pins is hbm condition, 3 pulses, each polarity re ferenced to ground. 2.2 recommended operating conditions function operation should be restricted to the recommended operating conditions specified in table 3. table 3 : recommended operating conditions parameter rating supply v oltage v dd 2.7 to 5 .5 vdc supply v oltage v pc 4. 75 to 5.5 vdc ambient o perating temperature - 40 c to +85 c input voltage for digital inputs 0 v to v dd to +0.3 v downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 9 2.3 smart card interface requirements table 4 lists the 73s80 10r smart card interface requirements. table 4 : dc smart card interface requirements symbol parameter condition min nom max unit card power supply (v cc ) regulator general conditions: - 40 c < t < 85 c, 4.75 v < v pc < 5.5 v , 2.7 v < v dd < 5.5 v v cc card supply voltage including ripple and noise inactive mode - 0.1 C 0.1 v inactive mode i cc = 1 ma - 0.1 C 0.4 v active mode; i cc < 65 ma; 5 v 4.6 0 C 5.25 v active mode; i cc < 90 ma; 5 v 4.55 C v active mode; i cc < 90 ma; 3 v 2.80 C 3.2 v active mode; single pulse of 100 ma for 2 s; 5 v , fixed load = 25 ma 4.6 C 5.25 v active mode; single pulse of 100 ma for 2 s; 3 v, fixed load = 25 ma 2.76 C 3.2 v active mode; current pulses of 40 nas with peak |i cc | < 200 ma, t < 400 ns; 5 v 4.6 C 5.25 v active mode; current pulse s of 40 nas with peak |i cc | < 200 ma, t <400 ns; 3 v 2.76 C 3.2 v i ccmax maximum supply current to the card static load current, v cc >4.6 or 2.7 volts as selected 90 C C ma i ccf i cc fault current 100 C 150 ma v sr vcc slew rate, rise rate on activate c f = 3.3 f on v cc 0.02 0.05 0.08 v/s v sf vcc slew rate, fall rate on de - activate c f = 3.3 f on v cc 0.025 0.06 0.08 v/s c f external filter capacitor (v cc to gnd) 1 3.3 5 f downloaded from: http:///
73s8010r data sheet ds_8010r_022 10 rev. 1.6 symbol parameter condition min nom max unit interface requirements C data signals: i/o, aux1, aux2, and host interfaces : i/ouc, aux1uc, aux2uc. i shortl , i shorth , and v inact requirements do not pertain to i/ouc, aux1uc, aux2uc . v oh output level, high (i/o, aux1, aux2) i oh = 0 a 0.9 * v cc C v cc +0.1 v i oh = - 40 a 0.75 * v cc C v cc +0.1 v v oh output level, high (i/ouc, aux1uc, aux2uc) i oh = 0 a 0.9 * v cc C v dd +0.1 v i oh = - 40 a 0.75 * v cc C v dd +0.1 v v ol output level, low i ol = 1 ma C C 0.3 v v ih input level, high (i/o, aux1, aux2) 1.8 C v cc +0.30 v v ih input level, high (i/ouc, aux1uc, aux2uc) 1. 8 C v cc +0.30 v v il input level, low - 0. 3 C 0.8 v v in act output voltage when outside of session i ol = 0 C C 0.1 v i ol = 1 ma C C 0.3 v i leak input leakage v ih = v cc C C 10 a i il input current, low v il = 0 C C 0.65 ma i shortl short circuit output current for output low, shorted to v cc through 33 ? C C 15 ma i shorth short circuit output current for output high, shorted to ground through 33 ? C C 15 ma t r , t f output rise time, fall time for i/o, aux1, aux2, c l = 80 pf, 10% to 90%. for i/ouc, aux1uc, aux2uc, cl=50 pf , 10% to 90%. C C 100 ns t ir , t if input rise, fall times C C 1 s r pu internal pull - up resistor output stable for >200 ns 8 11 14 k ? fd max maximum data rate C C 1 mhz t fd io delay, i/o to i/ouc, i/ouc to i/o, aux1 to aux1uc, aux1uc to aux1, aux2 to aux2uc, aux2uc to aux2 falling e dge from master to slave measured at 50% point 60 100 200 ns t rd io delay, i/o to i/ouc, i/ouc to i/o, aux1 to aux1uc, aux1uc to aux1, aux2 to aux2uc, aux2uc to aux2 rising edge from master to slave measured at 50% point C 25 90 ns c in input capacitance C C 10 pf downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 11 symbol parameter condition min nom max unit reset and clock for card interface, rst, clk v oh output level, high i oh = - 200 a 0.9 * v cc C v cc v v ol output level, low i ol = 200 a 0 C 0.3 v v in act output voltage when outside of session i ol = 0 C C 0.1 v i ol = 1 ma C C 0.3 v i rst_lim output current limit, rst C C 30 ma i clk_lim output current limit, clk C C 70 ma t r , t f output rise time, fall time c l = 35 pf for clk, 10% to 90% C C 8 ns c l = 200 pf for rst, 10% to 90% C C 100 ns duty cycle for clk c l =35 pf, f clk 20mhz 45 C 55 % 2.4 digital signals characteristics table 5 lists the 73s80 10r digital signals characteristics. table 5 : digital signals characteristics symbol par ameter condition min nom max unit d ig it a l i / o e x c e p t f o r o s c i/o v il input l ow v oltage - 0.3 C 0.8 v v ih input h igh v oltage 0.7 * v dd C v dd + 0.3 v v ol output l ow v oltage i ol = 2 ma C 0.45 v v oh output h igh v oltage i oh = -1 ma v dd - 0.45 C v r out pull - up resistor; int C 20 C k ? |i il1 | input l eakage c urrent gnd < v in < v dd -5 C 5 a oscillator (xtalin) i/o v il xt al input l ow v oltage - xtalin - 0.3 C 0.5 v v ih xt al input h igh v oltage - xtalin 0.7*v dd C v dd + 0.3 v i il xt al input c urrent - xtalin gnd < v in < v dd - 30 C 30 a 2.5 dc characteristics table 6 lists the dc characteristics. table 6 : dc characteristics symbol parameter condition min nom max unit i dd supply c urrent on v dd C 1.5 3. 0 ma i pc supply c urrent on v pc v cc on, i cc = 0 i/o, aux1, aux2 = high C 0.45 0.65 ma downloaded from: http:///
73s8010r data sheet ds_8010r_022 12 rev. 1.6 2.6 i 2 c interface characteristics table 7 lists the i 2 c interface characteristics. table 7 : i 2 c characteristics symbol parameter condition min nom max unit v il input low voltage - 0.3 C 0. 3 * v dd v v ih input high voltage 0.7 * v dd C v dd +0.3 v v ol output low voltage i ol = 3 ma C C 0.40 v c in pin capacitance C C 10 pf i in output high voltage i oh = - 1 ma v dd - 0.45 C v t f output fall time c l = 0 to 400 pf 20 + 0.1*c l C 250 ns t sp pulse width of spikes that are suppressed transition from valid logic level to opposite level C C 50 ns 2.7 voltage / temperature fault detection circuits table 8 lists the voltage / temperature fault dete ction circuits. table 8 : voltage / temperature fault detection circuits symbol parameter condition min nom max unit v ddf v p over - current fault no external resistor on vddf_adj pin 2.15 C 2.4 v v pcf v pc fault (v pc voltage supervis or threshold) v pc < v cc , a transient event C v cc - 0.2 C v v ccf v cc fault (v cc voltage supervisor threshold) v cc = 5 v 4.20 C 4.55 v v cc = 3 v 2.5 C 2.7 v t f die over temperature fault 115 C 145 c downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 13 3 applications information this section provides ge neral usage information for the design and implementation of the 73s8010r. 3.1 example 73s8010r schematics figure 4 shows a typical application schematic for the implementation of the 73s8010r . note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact teridian for the latest infor mation so28 see note 4 vdd y1 crystal c2 22pf c1 iso7816=1uf, emv=3.3uf sda_to/from_uc sad1 clk track should be routed far from rst, i/o, c4 and c8. notes: 1) vdd = 2.7v to 5.5v dc. 2) vpc = 4.75v(emv, iso) to 5.5v dc 3) required if external clock from up is used. 4) required if crystal is used. y1, c2 and c3 must be removed if external clock is used. 5) optional. can be left open. 6) r1 and r3 are external resistors that adjust the vdd fault voltage. can be left open. i/ouc_to/from_uc r1 rext1 see note 1 card detection switch is normally closed vpc c6 100nf vdd external_clock_from uc c4 100nf c3 22pf aux1uc_to.from_uc see note 5 c510uf aux2uc_to/from_uc see note 3 see note 2 vdd low esr (<100mohms) c1 should be placed near the sc connecter contact sad0 sck_from_uc 73s8010r 1 2 3 4 5 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 28 27 25 24 26 sad0 sad1 sad2 gnd gnd vpc nc aux2 ncnc pres i/o aux1 gnd clk rst vcc vddf_adj scl sda vdd gnd int aux2uc aux1uc xtalout xtalin i/ouc sad2 int _interrupt_to_uc r3 rext2 - or - r2 20k see note 6 smart card connector 1 2 3 4 5 6 7 8 9 10 vcc rst clk c4 gnd vpp i/o c8 sw-1 sw-2 r4 r5 2k 2k 7) hardware to define address of device see note 7 figure 4 : typical 73s80 10r application schematic downloaded from: http:///
73s8010r data sheet ds_8010r_022 14 rev. 1.6 3.2 system controller interface (i 2 c bus) a fast - mode 400 khz i 2 c bus slave interface is used for controlling the 73s8010r device and reading the status of the device via the data pin sda and clock pin scl. the bus has 3 address select pins, sad0, sad1, and sad2. this allows up to 8 devices to be connected in parallel. table 9 lists the device address selections for the sad2:0 settings. table 9 : device address selection sad2 sad1 sad0 (7 bit) i 2 c address 0 0 0 0x40 0 0 1 0x42 0 1 0 0x44 0 1 1 0x46 1 0 0 0x48 1 0 1 0x4a 1 1 0 0x4c 1 1 1 0x4e bit 0 of the i 2 c address is the r/w bit. refer to figure 5 and figure 6 for usage. table 10 describes the control register bits. table 10 : control register description p ower - on - reset value = 0x00 name bit description start/stop 0 when set, initiates an activation and a cold reset procedure; when reset, initi ates a deactivation sequence . warm reset 1 when set, initiates a warm reset procedure; automatically reset by hardware when the card starts answering or when the card is declared mute . 5 v and 3 v 2 when set, v cc = 3 v ; when reset, v cc = 5 v . when de - ac tivating (setting bit 0 = 0) and operating with 3 v (bit 2 =1), do not simultaneously set bit 2 =0. clock stop 3 when set, the card clock is stopped. bit 4 determines the card clock stop level . clock stop level 4 when set, card clock stops high; when re set card clock stops low . clksel1 5 bits 5 and 6 determine the clock rate to the card . see table 11 for more details. clksel2 6 i/o enable 7 i/o enable bit. when set, i/o is transferred on i/ouc; when reset i/o to i/ouc is h igh impedance. table 11 : card clock rate selection bit clksel2 bit clksel1 card clock 0 0 clkin/8 0 1 clkin/4 1 0 clkin/2 1 1 clkin (xtalin) downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 15 i 2 c- bus write to control register the i 2 c- bus write command to the control register follows the format shown in figure 5 . after the start condition, the master sends a slave address . this address is seven bits long followed by an eighth bit which is an opcode bit (r/w) C a zero indicates the master will write data to the control register. after the r/w bit, the zero ack bit is sent to the master by the device. the master now starts sending the 8 bits of data to the control register during the data bits. after the data bits, the zero ack bit is sent to the master by the device. the master should send the stop condition after receiving this ack bit. 1-7 8 9 1-8 9 address bits r/ w bit ack bit data bits ack bit stop condition start condition scl sda msb msb lsb lsb figure 5 : i 2 c bus write protocol table 12 describes the status register bit s. table 12 : status register description power on reset = 0x04 name bit description pres 0 set when the card is present (pin pres is high); reset when the card is not present. presl 1 set when the pres pin changes state (rising/f alling edge); reset when the status register is read. generates an interrupt when set. i/o 2 set when i/o is high; reset when i/o is low. supl 3 set when a voltage fault is detected; reset when the status register is read. generates an interrupt when se t. prot 4 set when an over - current or over - heating fault has occurred during a card session; reset when the status register is read. generates an interrupt when set . mute 5 set during atr when the card has not answered during the iso 7816 - 3 time window (40000 card clock cycles); reset when the next session begins. early 6 set during atr when the card has answered before 400 card clock cycles; reset when the next session begins . active 7 set when the card is active (v cc is on); reset when the card is in active. i 2 c- bus read from status register the i 2 c- bus read command from the status register follows the format shown in figure 6 . after the start condition, the mast er sends a sl ave address . this address is s even bits long followed by an eighth bit which is an opcode bit (r/w) C a one indicates the master will read data from the status register. after the r/w bit, the zero ack bit is sent to the master by the device. the device now starts sending the 8 -b it status register data to the control register during the data bits. after the data bits, the one ack bit is sent to the device by the master. the master should send the stop condition after receiving the ack bit. downloaded from: http:///
73s8010r data sheet ds_8010r_022 16 rev. 1.6 1-7 8 9 1-8 9 address bits r/ w bit ack bit data bits ack bit stop condition start condition scl sda lsb msb lsb msb figure 6 : i 2 c bus read protocol scl sda thdsta tsudat thddat tsusto tbuf tlow thi figure 7 : i 2 c bus timing diagram table 13 : i2c bus timing parameters symbol parameter min. typ. max. unit fsclk clock freque ncy C C 400 khz tlow clock low 1.3 C C s thi clock high 0.6 C C s thdsta hold time start condition 0.6 C C s tsudat data set up time 100 C C ns thddat data hold time 5 C 900 ns tsusto set up time stop condition 0.6 C C s tbuf bus free time betwee n a stop and start condition 1.3 C C s downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 17 3.3 power supply and voltage supervision the teridian 73s8010r smart card interface ic incorporates a ldo voltage regulat or. the voltage output is controlled by the digital input 5v/ #v . this regulator is able to provide either 3 v or 5 v card voltage from the power supply applied on the vpc pin. digital circuitry is powered by the power supply applied on the vdd pin. v dd also defines the voltage range to interface with the system controller. three voltage supervisors constantly check the presence of the voltages v dd , v pc and v cc . a card deactivation sequence is forced upon fault of any of these voltage supervisors. the two voltage supervisors for v pc and v cc are linked so that a fault is generated to activate a deactivation sequence when the voltage v pc becomes lower than v cc . this allows the 73s8010r to operate at lower v pc voltage when using 3 v cards only. the voltage regulator can provide a current of at least 90 ma on v cc which easily complies with the emv 4.0 specification. the v pc voltage supervisor threshold values are defined from the emv 4.0 standard. a third voltage supervisor monitors the v dd voltage. it is used to initialize the iso - 7816 - 3 sequencer at power - on, and to deactivate the card at powe r- off or upon a fault. the voltage threshold of the v dd voltage supervisor is internally set by default to 2.3 v nominal. however, it may be desirable in some applications to modify this threshold value. the pin vddf_adj (pin 18 in the so package, pin 1 7 in the qfn package) is used to connect an external resistor r e xt to ground to raise the v dd fault voltage to another value v ddf . the resistor value is defined as follows: r ext = 56 k / (v ddf - 2.33) an alternative (more accurate) method of adjustin g the v dd fault voltage is to use a resistive network of r3 from the pin to supply and r1 from the pin to ground (see figure 4 ). in order to set the new threshold voltage, the equivalent resistance must be determi ned. this resistance value will be designated kx. kx is defined as r1/(r1+r3). kx is calculated as: kx = (2.789 / v th ) - 0.6125 where v th is the desired new threshold voltage. to determine the values of r1 and r3, use the following formulas. r3 = 24 000 / kx r1 = r3*(kx / (1 C kx)) taking the example above, where a v dd fault threshold voltage of 2.7 v is desired, solving for kx gives: ? kx = (2.789 / 2.7) - 0.6125 = 0.42046. solving for r3 gives: ? r3 = 24000 / 0.42046 = 57080. solving for r1 gives: ? r1 = 57080 *(0.42046 / (1 C 0.42046)) = 41412. using standard 1 % resistor values gives r3 = 57.6 k ? and r1 = 42.4 k ?. these values give an equivalent resistance of kx = 0.4228, a 0.6% error. if the 2.3 v default threshold is used, this pin must be left unconnected. downloaded from: http:///
73s8010r data sheet ds_8010r_022 18 rev. 1.6 3.4 card power supply the card power supply is provided by the ldo regulator, and controlled by the digital iso - 7816 - 3 sequencer. card voltage selection is carried out by bit 2 of the control register. choice of the v cc capacitor: depending on the application, the requirements in terms of both the v cc minimum voltage and the transient currents that the interface must be able to provide to the card are different. an external capacitor must be connected between the vcc pin and the card ground in order to guarantee stabil ity of the ldo regulator, and to handle the transient requirements. t he type and value of this capacitor can be optimized to meet the desired specification. table 14 shows the recommended capacitors for each v pc power supply configuration and applicable specification. table 14 : choice of vcc pin capacitor 3.5 over - temperature monitor a built - in detector monitors die temperature. when an over - temperature condition occurs (resulting from a heavily loaded card interface, including short circuits, for example), a card deactivati on sequence is initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and an interrupt is generated). 3.6 on - chip oscillator and card clock the teridian 73s8010r device has an on - chip oscillator that can generate the smart card clock using an external crystal connected between the xtalin and xtalout pins to set the oscillator fr equency. when the card clock signal is available from another source, it can be connect ed to the pin xtalin, and in this case, the xtalout pin should be left unconnected. the card clock frequency may be chosen from 4 different division rates, defined by the clksel2 and clksel1 bits (bits 5 and 6) of the i 2 c control register, as listed in table 15 . table 15 : card clock divisor options specification requirements system requirements specification min v cc voltage allowed during transient current max transient current charge min v pc power supply required capacitor type capacitor value emv 4.0 4.6 v 30 na ? s 4.75 v x5r/x7r with esr<100 m 3.3 f iso - 7816 -3 4.5 v 20 na ? s 4.75 v 1 f clksel2 clksel1 card clock 0 0 clkin / 8 0 1 clkin / 4 1 0 clkin / 2 1 1 clkin (xtalin) downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 19 3.7 activation sequence after power on reset, the signal int is low until the v dd is stable. when v dd has been stable for approximately 10 ms and the signal int is high, the system controller may read the status register to see if the card is present. if all the status bits are satisfied, the system controller can initiate the activation sequence by writing a '1' to the start/stop bit (bit 0) of the control register. the following steps and figure 8 show the activation sequence and the timing of the card control signals when the syst em controller initiates the start/stop bit (bit 0) of the control register: 1. voltage v cc to the card should be valid by the end of t 1 . if v cc is not valid for any reason, then the session is aborted. 2. turn i/o to reception mode at the end of t 1 . 3. clk is app lied to the card at the end of t 2 . 4. rst (to the card) is set high at the end of t 3 . start/stop vcc io clk rst t 1 t 2 t 3 t 1 = 0.510 ms (timing by 1.5mhz internal oscillator), i/o in reception mode t 2 =1.5 s, clk starts t 3 = >42000 card clock cycles, rst set high figure 8 : activation sequence 3.8 deactivation sequence deactivation is initiated either by the system controller by resetting the start/s top bit, or automatically in the event of hardware faults. hardware faults are over - current, over - temperature, v dd fault, v pc fault, v cc fault, and card extraction during the session. the following steps and figure 9 show the deactivation sequence and the timing of the card control signals when the system controller clears the start/stop bit: 1. rst goes low at the end of t 1 . 2. clk goes low at the end of t 2 . 3. i/o goes low at the end of t 3 . out of reception mode. 4. shut down v cc at the end of time t 4 . downloaded from: http:///
73s8010r data sheet ds_8010r_022 20 rev. 1.6 start/stop rst clk io vcc t 1 t 2 t 3 t 4 t 1 = > .5 s t 2 = > 7.5 s t 3 = > 0 .5 s t 4 = > 0 .5 s figure 9 : deactivation sequence 3.9 interrupt the interrupt is an active low interrupt. it is set low if any of the following interna l faults are detected: ? v cc fault ? v dd fault ? v pc fault the interrupt will also be set if one of t he following status bit condition s is detected: ? early atr ? mute atr ? card insert or card extract ? protection status from over - current or over - heating when the interrupt is set low by th e detection of one of the status bits, it is set high when the status bits are read. (read status done) figure 10 shows the interrupt operation resulting from the fault or status bit conditions. figure 10 : interrupt operation due to fault and status conditions a power - on - reset event will reset all of the control and status registers to their default states. a v dd fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates the interval t 1 , not clearing the interrupt until v dd is valid for at least t 1 . a v dd fault can be considered valid for v dd as low as 1.5 to 1.8 volts. at the lower range of v dd fault, por will be asserted. int any fault status bits read status done downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 21 3.10 warm reset the 73s8010r automatically asserts a warm reset to the card when instructed throu gh bit 1 of the i 2 c control register (bit warm reset). the warm reset length is automatically defined as 42,000 card clock cycles. the warm reset bit is automatically reset when the card starts answering or when the card is declared mute. figure 11 : warm reset operation 3.11 i/o circuitry and timing the states of the i/o, aux1, and aux2 pins are low after power - on - reset and they are high when the activation sequencer enables the i/o reception state. see section 3.7 activation sequence for more details on when the i/o reception is enabled. the states of t he i/ouc, aux1uc, and aux2uc are high after power on reset. when the control i/o enable bit (bit 7) of the control register is set, the first i/o line on which a falling edge is detected becomes the input i/o line and the other becomes the output i/o line. when t he input i/o line rising edge is detected , then both i/o lines return to their neutral state. the delay between these signals is shown in figure 12 . io iouc t io_hl t io_lh t iouc_hl t iouc_lh delay from i/o to i/ouc: t io_hl = 10 0ns t io_lh = 25ns delay from i/ouc to i/o: t iouc_hl = 100ns t iouc_lh = 25ns figure 12 : i/o timing diagram warm reset (bit 1) rst t 1 t 2 t 1 > 1.5s, warm reset starts t 2 = 42000 card clock cycles, end of warm reset t 3 t 3 = resets warm reset bit 1 when detected atr or mute io downloaded from: http:///
73s8010r data sheet ds_8010r_022 22 rev. 1.6 4 mechanical drawing s 4.1 32 - pin qfn 2.5 5 2.5 5 top view 1 2 3 figure 13 : 32 - pin qfn package dimensions 0.85 nom. / 0.9max. 0.00 / 0.005 0.20 ref. seating plane side view 0.2 min. 0.35 / 0.45 1.5 / 1.875 3.0 / 3.75 0.18 / 0.3 bottom view 1 2 3 0.25 0.5 0.5 0.25 3.0 / 3.75 1.5 / 1.875 0.35 / 0.45 chamfered 0.30 downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 23 4.2 28- pin so . 335 (8. 509 ) . 320 (8. 128 ) . 420 ( 10 . 668 ) . 390 (9. 906 ) . 050 typ . ( 1. 270 ) . 305 (7. 747 ) . 285 (7. 239 ) . 715 ( 18 . 161 ) . 695 ( 17 . 653 ) . 0115 (0. 29 ) . 003 (0. 076 ) . 016 nom (0. 40 ) . 110 (2. 790 ) . 092 (2. 336 ) pin no . 1 bevel figure 14 : 2 8- pin so package dimensions downloaded from: http:///
73s8010r data sheet ds_8010r_022 24 rev. 1.6 5 ordering information table 16 lists the order numbers and packaging marks used to identify 73s80 10r products. table 16 : order numbers and packaging marks part description order number packaging mark 73s8010r C sol, 28 - pin l ead -f ree so 73s8010r - il/f 73s8010r - il 73s8010r C sol, 28 - pin lead - free so tape / reel 73s8010r - ilr/f 73s8010r - il 73s8010r C qfn, 32 - pin lead - free qfn 73s8010r - im/f 73s8010r 73s8010r C qfn, 32 - pin lead - free qfn tape / reel 73s8010r - imr/f 73s8010r 6 related documentation the following 73s8010r document s are available from teridian semiconductor corporation: 73s8010r 28so demo board users guide 7 contact information for more information about teridian semiconductor products or to check the availabili ty of the 73s8010r , contact us at: 6440 oak canyon road suite 100 irvine, ca 9261 8- 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
ds_8010r_022 73s8010r data sheet rev. 1.6 25 revision history revision date description 1.0 7/1/2004 first publication. 1.1 11/10/2004 make revisions to all references of i/o as it relates to the pins for the smart card and microcontroller interfaces, i.e. io - > i/o and iouc - > i/ouc. this is done to insure consistency and follow the designations used in iso 7816. remove the mlp pin numbering in the pin description. correct the clock division table under card clock. change the value of r2 on the typical application schematic. the origi nal value is 100 k and the updated value is 10 k . the pres input has a high impedance pull down resistor and the 100 k for r2 is too high to insure a valid logic level on this input. 1.3 10/26/2005 remove nds references in application schematic. 1. 5 1/21/2008 removed leaded package option, replaced 32qfn punched with sawn, updated 28so dimension. changed dimension of bottom exposed pad on 32qfn mechanical package figure. 1.6 8/28 /2009 added section 6, related documentation and section 7, contact information. formatted to the corporate style. added document number. misc ellaneous editorial change s. teridian semiconductor corporation is a registered trademark of teridian semiconduc tor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. all other trademarks are the property of their respective owners. this data sheet is proprietary to teridian semiconductor corporation (tsc) and se ts forth design goals for the described product. the data sheet is subject to change. tsc assumes no obligation r egarding future manufacture, unless agreed to in writing. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. ter idian semiconductor corporation (tsc) reserves the right to make changes in specifications at any time without noti ce. accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. tsc assumes no l iability for applications assistance. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teridian.com downloaded from: http:///

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