powering the next generation of voice-assisted end nodes i.mx RT600 family of crossover processors combining a high-performance tensilica ? hi-fi 4 audio dsp core with added real-time functionality from the arm ? cortex ? -m33 core, the i.mx RT600 family of crossover processors is designed to unlock the potential of ml/ai end nodes with a secure, power-optimized embedded processor. the crossover processor market drawing on its expertise as a leading supplier of both applications processors and microcontrollers (mcus), nxp ? introduces the i.mx RT600 family, a unique new class of crossover processors that strikes the best balance between power optimization and high-performance capabilities. these processors, optimized for audio, voice and machine learning solutions, enable a wide range of consumer and iot applications. } greater performance } real-time operation } richer integration } hardened security target applications } audio subsystem } ml-based edge applications } voice recognition consumer electronics } voice ui-enabled iot devices i .mx RT600 family block diagram 4.5 mb shared sram arm ? cortex ? -m33 trustzone ? accelerator s fpu mpu etm cadenc e ? tensilica ? hi-fi 4 dsp debug interface fpu mpu 128 kb dsp tcm 96 kb dsp cache 8 kb qspi cache 2 kb sram puf 128 kb rom dma gint iocon frequency measur e gpio pint crc sdio/mmc/sd flexcomm spi i 3 c frac rate gen octal/qspi lpcac hs usb w/ phy otfa d dmic ctimers system timers rtc sct watch dog acmp adc/temp sram puf aes-256 rng sha-2 clock control pmc wd oscm essage unit ecrp pll, irc, fro reset rtc oscs emaphor e ostimer control processor core dsp processor core digital peripherals serial peripherals timers analog peripherals shared internal memory system control security
nxp and the nxp logo are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, cortex and trustzone are trademarks or registered trademarks of arm limited (or its subsidiaries) in the us and/or elsewhere. the related technology may be protected by any or all of patents, copyrights, designs and trade secrets. all rights reserved. ? 2018 nxp b.v. document number: imxRT600familyfs rev 3 release date: october 2018 www.nxp.com/imxRT600 mcu next-generation core + high-performance audio dsp integration } move fast, react fast with real-time microcontroller domain } create advanced audio and voice recognition systems with a breakthrough dsp engine } connect and protect with a high level of security performance highlights } highly optimized cadence tensilica hi-fi 4 audio dsp engine C featuring emerging multichannel object-based audio standards C ideal for dsp-intensive applications } high-performing cortex-m33 core C next-generation core based on the arm v8-m architecture C hardware co-processors provide accelerated support for additional dsp algorithms and cryptography } extensive memory resources C up to 4.5 mb accessible to both cores and both dma engines to simplify development complexity C 128 kb tightly-coupled memory (tcm) for the exclusive use of the dsp core usability highlights design flexibility } improved power efficiency C wide dynamic voltage and performance range C simplified power modes with fast wake-up and low leakage C configurable blocks of memory for individual power gating and retention } advanced audio subsystem interfaces C dmic interface supporting eight channels and voice activation detect C up to 8 x i 2 s interfaces for high-performance, multichannel audio } external memory interface options C octal/quad spi with cache and dynamic decryption } numerous connectivity and communication interfaces C sdio for wi-fi ? -enabled streaming C high-speed usb device/host and high-speed spi interfaces advanced security } arm trustzone ? -m for asset protection C system-wide, secure resource isolation for trusted hardware } secure boot mechanism with sram puf or otp-based unique key for hardware based root of trust } symmetric and asymmetric cryptography acceleration C aes-256, sha2-256 C ecc and rsa } octal/quad spi interface with a real-time decryption engine } secure debug authentication feature i.mx rt685 control processor core/speed arm ? cortex ? -m33 up to 300 mhz dsp processor core/speed tensilica ? hi-fi 4 up to 600 mhz on-chip ram up to 4.5 mb dsp tcm 128 kb dsp cache 96 kb sdio 2 x sdio, 1 supports emmc5.0 w/ hs400 octal/quad spi 1 x up to 100 mb per second dma engine 2 x with 35 channels each usb with phy 1 x high-speed host/device high-speed spi 1 x up to 50 mhz serial interfaces 8 x flexcomm interfaces with support up to 8 x spi, 8 x i 2 c, 8 x uart, 4 x i 2 s channels (total 8 instances) i3c 1 x master/slave dmic up to 8 channels gpio up to 228 security sram puf, rng, aes256, sha-2, secure boot, rng adc 1 x 12-bit 1 msamples/s acmp 4 cap touch / temperature sensor 1/1 sctimer multi-rate timer os event timer 1 x 32-bit 1 x 24-bit 1 x 64-bit gp timer / wdog 5/2 reduced-power modes sleep mode, deep-sleep mode and deep power-down mode package vfbga176 operating temperature 0 to 70 c
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