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lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 lm118qml operational amplifier check for samples: lm118qml 1 features description the lm118 is a precision high speed operational 2 ? 15 mhz small signal bandwidth amplifier designed for applications requiring wide ? ensured 50v/ s slew rate bandwidth and high slew rate. it features a factor of ? maximum bias current of 250 na ten increase in speed over general purpose devices without sacrificing dc performance. ? operates from supplies of 5v to 20v ? internal frequency compensation the lm118 has internal unity gain frequency compensation. this considerably simplifies its ? input and output overload protected application since no external components are ? pin compatible with general purpose op necessary for operation. however, unlike most amps internally compensated amplifiers, external frequency compensation may be added for optimum performance. for inverting applications, feed forward compensation will boost the slew rate to over 150v/ s and almost double the bandwidth. overcompensation can be used with the amplifier for greater stability when maximum bandwidth is not needed. further, a single capacitor can be added to reduce the 0.1% settling time to under 1 s. the high speed and fast settling time of this op amp makes it useful in a/d converters, oscillators, active filters, sample and hold circuits, or general purpose amplifiers. this device is easy to apply and offers an order of magnitude better ac performance than industry standards such as the lm709. fast voltage follower do not hard-wire as voltage follower (r1 5 k ) 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. connection diagram figure 1. cdip package figure 2. to-99 top view top view see package number j0014a see package number lmc pin connections shown on schematic diagram and typical applications are for to package. figure 3. cdip package figure 4. clga package top view top view see package number nab0008a see ns package number nac0010a 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml n/c bal/comp1 -in +in n/c comp2 v+ out 1 10 2 9 3 8 4 7 v- bal/comp3 5 6
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 schematic diagram copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com absolute maximum ratings (1) supply voltage 20v 8 ld to-99 750mw 8ld cdip 1000mw power dissipation (2) 14ld cdip 1250mw 10ld clga 600mw differential input current (3) 10 ma input voltage (4) 15v output short-circuit duration continuous operating temperature range ? 55 c t a +125 c thermal resistance 8 ld to-99 (still air @ 0.5w) 160 c/w 8 ld to-99 (500lf / min air flow @ 0.5w) 86 c/w 8ld cdip (still air @ 0.5w) 120 c/w 8ld cdip (500lf / min air flow @ 0.5w) 66 c/w ja 14ld cdip (still air @ 0.5w) 87 c/w 14ld cdip (500lf / min air flow @ 0.5w) 51 c/w 10ld clga (still air @ 0.5w) 198 c/w 10ld clga (500lf / min air flow @ 0.5w) 124 c/w 8 ld to-99 48 c/w 8ld cdip 17 c/w jc 14ld cdip 17 c/w 10ld clga 22 c/w storage temperature range ? 65 c t a +150 c lead temperature (soldering, 10 seconds) 300 c esd tolerance (5) 2000v (1) absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. for specifications and test conditions, see the electrical characteristics. the specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) the maximum power dissipation must be derated at elevated temperatures and is dictated by t jmax (maximum junction temperature), ja (package junction to ambient thermal resistance), and t a (ambient temperature). the maximum allowable power dissipation at any temperature is p dmax = (t jmax - t a )/ ja or the number given in the absolute maximum ratings, whichever is lower. (3) the inputs are shunted with back-to-back diodes for over voltage protection. therefore, excessive current will flow if a differential input voltage in excess of 1v is applied between the inputs unless some limiting resistance is used. (4) for supply voltages less than 15v, the absolute maximum input voltage is equal to the supply voltage. (5) human body model, 1.5 k in series with 100 pf. 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 quality conformance inspection mil-std-883, method 5005; group a subgroup description temp c 1 static tests at 25 2 static tests at 125 3 static tests at -55 4 dynamic tests at 25 5 dynamic tests at 125 6 dynamic tests at -55 7 functional tests at 25 8a functional tests at 125 8b functional tests at -55 9 switching tests at 25 10 switching tests at 125 11 switching tests at -55 12 settling time at 25 13 settling time at 125 14 settling time at -55 lm118/883 electrical characteristics dc parameters the following conditions apply, unless otherwise specified. dc v cc = 15v, v cm = 0v sub- symbol parameter conditions notes min max unit groups v io input offset voltage v cm = 11.5v, r s = 50 ? -4.0 +4.0 mv 1 -6.0 +6.0 mv 2, 3 v cc = 20v, r s = 50 ? -4.0 +4.0 mv 1 -6.0 +6.0 mv 2, 3 v cc = 20v, v cm = 15v, -4.0 +4.0 mv 1 r s = 50 ? -6.0 +6.0 mv 2, 3 v cc = 5v, r s = 50 ? -4.0 +4.0 mv 1 -6.0 +6.0 mv 2, 3 i io input offset current v cm = 11.5v, r s = 10k ? -50 +50 na 1 -100 +100 na 2, 3 v cc = 20v, r s = 10k ? -50 +50 na 1 -100 +100 na 2, 3 v cc = 5v, r s = 10k ? -50 +50 na 1 -100 +100 na 2, 3 i ib input bias current v cm = 11.5v, r s = 10k ? 1.0 250 na 1 1.0 500 na 2, 3 v cc = 20v, r s = 10k ? 1.0 250 na 1 1.0 500 na 2, 3 v cc = 5v, r s = 10k ? 1.0 250 na 1 1.0 500 na 2, 3 psrr power supply rejection ratio +v cc = 20v to 5v, r s = 50 ? 70 db 1, 2, 3 -v cc = -20v to -5v, r s = 50 ? 70 db 1, 2, 3 cmrr common mode rejection ratio v cc = 15v, v cm = 11.5v, r s = 80 db 1, 2, 3 50 ? +i os short circuit current t < 25ms -65 -5.0 ma 1, 2, 3 copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com lm118/883 electrical characteristics dc parameters (continued) the following conditions apply, unless otherwise specified. dc v cc = 15v, v cm = 0v sub- symbol parameter conditions notes min max unit groups -i os short circuit current t < 25ms 5.0 65 ma 1, 2 5.0 80 ma 3 i cc power supply current v cc = 20v 8.0 ma 1 7.0 ma 2 11 ma 3 v io adj. input offset voltage adjust v cc = 20v 4.0 -4.0 mv 1 r i input resistance see (1) 1.0 m ? 1 v i input voltage range v cc = 15v +11. see (2) -11.5 v 1, 2, 3 5 a vs large signal voltage gain r l = 2k ? , v o = 0 to -10v see (3) 50 v/mv 4 see (3) 25 v/mv 5, 6 r l = 2k ? , v o = 0 to +10v see (3) 50 v/mv 4 see (3) 25 v/mv 5, 6 v o output voltage swing r l = 2k ? +12 -12 v 4, 5, 6 (1) specified by design not tested (2) specified by cmrr (3) datalog in k = v/mv lm118/883 electrical characteristics ac parameters the following conditions apply parameters, unless otherwise specified. ac v cc = 15v, v cm = 0v, r s = 0 ? , r l = 2k ? ,, c l = 33pf sub- symbol parameter conditions notes min max unit groups s r slew rate v cc = 20v, v i = -5v to +5v, a v =1 50 v/ s 7 v cc = 20v, v i = +5v to -5v, a v =1 50 v/ s 7 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 typical performance characteristics input current voltage gain figure 5. figure 6. power supply rejection input noise voltage figure 7. figure 8. common mode rejection supply current figure 9. figure 10. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com typical performance characteristics (continued) closed loop output impedance current limiting figure 11. figure 12. input current unity gain bandwidth figure 13. figure 14. voltage follower slew rate inverter settling time figure 15. figure 16. 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 typical performance characteristics (continued) large signal frequency response open loop frequency response figure 17. figure 18. voltage follower pulse response large signal frequency response figure 19. figure 20. open loop frequency response inverter pulse response figure 21. figure 22. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com auxiliary circuits feedforward compensation for greater inverting slew rate compensation for minimum settling time slew and settling time to 0.1% for a 10v step change is 800 ns. slew rate typically 150v/ s. offset balancing isolating large capacitive loads overcompensation 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 typical applications fast voltage follower do not hard-wire as voltage follower (r1 5 k ) integrator or slow inverter c f = large (c f 50 pf) *do not hard-wire as integrator or slow inverter; insert a 10k-5 pf network in series with the input, to prevent oscillation. fast summing amplifier differential amplifier copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com fast sample and hold d/a converter using ladder network *optional ? reduces settling time. 12 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 four quadrant multiplier output zero. * ? y ? zero + ? x ? zero ? full scale adjust. d/a converter using binary weighted network *optional ? reduces settling time. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: lm118qml
lm118qml snosaj3a ? july 2005 ? revised march 2013 www.ti.com fast summing amplifier with low input current wein bridge sine wave oscillator instrumentation amplifier 14 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lm118qml
lm118qml www.ti.com snosaj3a ? july 2005 ? revised march 2013 revision history section date released revision section originator changes 07/12/05 a new release, corporate format l. lytle 1 mds data sheet, mnlm118 ? x rev 0a0 was converted into the corp. datasheet format. mds datasheet will be archived. 03/20/2013 a all sections changed layout of national data sheet to ti format copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: lm118qml
package option addendum www.ti.com 19-jul-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm118 md8 active diesale y 0 182 green (rohs & no sb/br) call ti level-1-na-unlim -55 to 125 lm118 mw8 active wafersale ys 0 1 green (rohs & no sb/br) call ti level-1-na-unlim -55 to 125 lm118h/883 active to-99 lmc 8 20 tbd call ti call ti -55 to 125 lm118h/883 q aco lm118h/883 q >t lm118j-8/883 active cdip nab 8 40 tbd call ti call ti -55 to 125 lm118j-8 /883 q aco /883 q >t (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 19-jul-2016 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
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