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this is information on a product in full production. september 2015 docid024898 rev 2 1/12 ESDALC14-1BF4 low clamping and low capacitance bidirectional single line esd protection datasheet - production data features ? low clamping voltage: v cl = 18 v ? bidirectional device ? low leakage current ? 0201 package ? ultra low pcb area: 0.18 mm 2 ? ecopack ? 2 compliant component complies with the following standards ? iec 61000-4-2: ? 15 kv (air discharge) ? 8 kv (contact discharge) applications where transient over voltage protection in esd sensitive equipment is required, such as: ? smartphones, mobile phones and accessories ? tablet, pc, netbooks and notebooks ? portable multimedia devices and accessories ? digital cameras and camcorders ? communication and highly integrated systems description the ESDALC14-1BF4 is a bidirectional single line tvs diode designed to protect the data line or other i/o ports against esd transients. the device is ideal for applications where both reduced line capacitance and board space saving are required. figure 1. functional diagram sdfndjh www.st.com
characteristics ESDALC14-1BF4 2/12 docid024898 rev 2 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings symbol parameter value unit v pp (1) peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 25 30 kv p pp (1) peak pulse power (8/20 s) 100 w i pp (1) peak pulse current (8/20 s) 5 a t j operating junction temperature range -40 to 150 c t stg storage temperature range -65 to +150 c t l maximum lead temperature for soldering during 10 s 260 c 1. for a surge greater than the maximum values, the diode will fail in short-circuit. r d = dynamic impedance t = voltage temperature coefficient v i v cl v cl v br v br v rm v rm i rm i pp slope: 1/r d symbol parameter v = breakdown voltage v = stand-off voltage v = clamping voltage i = peak pulse current br rm cl pp i = leakage current @ v rm rm c = parasitic capacitance table 2. electrical characteristics (values, t amb = 25 c) symbol test conditions value unit min. typ. max. v br i r = 1 ma 13 v i rm v rm = 12 v 100 na vcl 8 kv contact discharge after 30 ns iec 61000-4-2 18 c line v line = 0 v, f = 1 mhz, v osc = 30 mv 22 25 pf
docid024898 rev 2 3/12 ESDALC14-1BF4 characteristics 12 figure 3. leakage current versus junction temperature (typical values) figure 4. junction capacitance versus applied voltage (typical values) i r ( na) 0.1 1 10 100 25 50 75 100 125 150 v r =v rm =12v io/io t j c () c (pf) 0 5 10 15 20 25 30 0123456789101112 t j =25-c f=1mhz vosc=30mv io/io v r v () figure 5. dynamic resistance figure 6. attenuation measurement result i pp (a) 0 5 10 15 20 25 30 0 5 10 15 20 25 v cl (v) positive polarity negative polarity rd 0.22 100k 1m 10m 100m 1g 10g -5 4 -5 1 -4 8 -4 5 -4 2 -3 9 -3 6 -3 3 -3 0 -2 7 -2 4 -2 1 -1 8 -1 5 -1 2 -9 -6 -3 0 - s21 (db) f (hz)
characteristics ESDALC14-1BF4 4/12 docid024898 rev 2 figure 7. esd response to iec 61000-4-2 (+8 kv contact discharge) figure 8. esd response to iec 61000-4-2 (-8 kv contact discharge) 10 v/div 20 ns/div vcl: peak clamping voltage vcl: clamping voltage at 30 ns vcl: clamping voltage at 60 ns vcl: clamping voltage at 100 ns 1 2 2 2 17.2 v 1 35.2 v 15.0 v 3 3 4 4 16.4 v 10 v/div 20 ns/div vcl: peak clamping voltage vcl: clamping voltage at 30 ns vcl: clamping voltage at 60 ns vcl: clamping voltage at 100 ns 1 2 2 2 -18.2 v 1 -33.8 v -15.1 v 3 3 4 4 -17.0 v
docid024898 rev 2 5/12 ESDALC14-1BF4 package information 12 2 package information ? epoxy meets ul94, v0 ? lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 2.1 0201 package information figure 9. 0201 package outline top view bottom view side view d e a l2 l1 b1 b b2 e
package information ESDALC14-1BF4 6/12 docid024898 rev 2 note: the marking codes can be rotated by 90 or 180 to differentiate assembly location.in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. table 3. 0201 package dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.28 0.30 0.32 0.0110 0.0118 0.0126 b 0.19 0.21 0.23 0.0075 0.0082 0.0091 b1 0.125 0.14 0.155 0.0049 0.0055 0.0061 b2 0.125 0.14 0.155 0.0049 0.0055 0.0061 d 0.57 0.60 0.63 0.0224 0.0236 0.0257 e 0.33 0.35 0.37 0.0130 0.0138 0.0146 e 0.27 0.30 0.33 0.0106 0.0118 0.0130 l1 0.175 0.19 0.205 0.0069 0.0075 0.0081 l2 0.175 0.19 0.205 0.0069 0.0075 0.0081 figure 10. footprint in mm (inches) figure 11. marking 0.243 (0.0096) 0.170 (0.0067) 0.300 (0.0118) 0.243 (0.0096) 0.656 (0.0258) pin1 pin2 f
docid024898 rev 2 7/12 ESDALC14-1BF4 package information 12 2.2 packing information figure 12. tape and reel outline bar indicates pin 1 user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 + 0.03 - 0.01 2.0 0.05 1.75 0.1 3.5 0.05 ? 1.5 0.1 0.36 0.03 0.38 0.03 0.22 0.68 0.03 f f f f f f f
recommendation on pcb assembly ESDALC14-1BF4 8/12 docid024898 rev 2 3 recommendation on pcb assembly 3.1 stencil opening design 1. general recommendations on stencil opening design a) stencil opening dimensions: l (length), w (width), t (thickness). figure 13. stencil opening dimensions b) general design rule stencil thickness (t) = 75 ~ 125 m 2. recommended stencil window a) stencil opening thickness: 80 m b) other dimensions: see figure 14 figure 14. recommended stencil window position, stencil opening thickness: 80 m l t w aspect ratio w t ----- 1.5 = aspect area lw 2t l w + () --------------------------- - 0.66 = 0.230 (0.0091) 0.183 (0.0072) 0.170 (0.0067) 0.300 (0.0118) 0.285 (0.0112) 0.656 (0.0258) 0.643 (0.0253) footprint stencil window 0.007 (0.00027) 0.007 (0.00027) 0.008 (0.0003) 0.008 (0.0003) mm (inches)
docid024898 rev 2 9/12 ESDALC14-1BF4 recommendation on pcb assembly 12 3.2 solder paste 1. use halide-free flux, qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste recommended. 3. offers a high tack force to resist component displacement during pcb movement. 4. use solder paste with fine particles: type 4 (powder particle size 20-48 m per ipc j std-005). 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead rec ognition capabilities of th e placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 1.0 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks a nd open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
recommendation on pcb assembly ESDALC14-1BF4 10/12 docid024898 rev 2 3.5 reflow profile figure 15. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
docid024898 rev 2 11/12 ESDALC14-1BF4 ordering information 12 4 ordering information figure 16. ordering information scheme 5 revision history table 4. ordering information order code marking package weight base qty delivery mode ESDALC14-1BF4 f (1) 1. the marking codes can be rotated by 90 c or 180 c to differentiate assembly location 0201 0.116 mg 15000 tape and reel esda - 1 b lc 14 f4 esd array low capacitance breakdown voltage 14 = 13 v min number of lines directional b = bi-directional package = f4 0201 table 5. document revision history date revision changes 11-oct-2013 1 first issue 03-sep-2015 2 updated table 2 .
ESDALC14-1BF4 12/12 docid024898 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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