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| UP9508 1 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com 3/2/1+2/1-phase pwm controller with smbus digital interface control for imvp8 ? ? ? ? ? intel imvp8 compatible ? ? ? ? ? support s-line desktop cpu ? ? ? ? ? thermal sense with vrhot# indication ? ? ? ? ? rcot +tm control topology ? ? ? ? ? easy setting ? ? ? ? ? smooth mode transition ? ? ? ? ? fast transition response ? ? ? ? ? external mosfet driver enable control ? ? ? ? ? support operation phase disable function ? ? ? ? ? vcore: 3/2/1-phase pwm outputs ? ? ? ? ? vccgt: 2/1-phase pwm outputs ? ? ? ? ? build-in adc for platform parameter setting ? ? ? ? ? selectable svid vr address ? ? ? ? ? selectable smbus device address ? ? ? ? ? selectable vboot voltage ? ? ? ? ? operation phase extension function ? ? ? ? ? smbus interface for performance and efficiency optimization ? ? ? ? ? dynamic programmable vr parameters ? ? ? ? ? programmable protection thresholds ? ? ? ? ? vr output reporting ? ? ? ? ? programmable loop gain ? ? ? ? ? system input power monitor p sys adc ? ? ? ? ? enable control and vr_rdy indicator ? ? ? ? ? system thermal management ? ? ? ? ? differential remote voltage sense ? ? ? ? ? differential current balance sense amplifier ? ? ? ? ? ocp/ovp/uvp/thermal shutdown ? ? ? ? ? rohs compliant and halogen free general description features applications ? ? ? ? ? desktop pc cpu power supplies note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. rebmunredr oe gakca pk ramer w gqp8059p ul 25-6x6nfqv ordering information pin configuration the UP9508 is an imvp8 compliant desktop cpu voltage regulator controller that integrates a 3-phase pwm controller for vcore and a 2-phase pwm controller for vccgt. the vcore controller can be configured as 3/2/1- phase, and the vccgt controller can be configured as 2/1- phase for platform power design flexibility. this part outputs pwm signal to external mosfet driver to drive the buck power stage. the integrated smbus interface programmability makes this part with high performance and easy design. designer can define different power scenario for different current states to optimize the performance and efficiency. the UP9508 combines true differential output voltage sense, differential inductor dcr current sense, input voltage feedforward sense and adaptive voltage positioning to provide accurately regulated power for desktop cpu. it adopts upis proprietary rcot+tm (robust constant on-time) topology to have fast transient response and smooth mode transition. similar to digital based pwm controller, the loop gain is also programmable by smbus interface to achieve design flexibility. the UP9508 provides system input power monitor (psys) adc, vr_rdy indicator and selectable vr parameters, such as svid vr address, smbus device address and vboot voltage. it also provides complete fault protection functions, including over voltage, under voltage, over current, over temperature and under voltage lockout. the UP9508 is available in vqfn6x6 - 52l package. imon vr_rdy vcc sclk alert# sdio sda scl vrhot# en csp3 csp2 csn1 csp1 fbrtna compa csp dac eap tsense vinsen cspa comp csn1a csp1a fbrtn pwm1a 18 17 53 gnd 27 9 10 11 12 20 19 29 28 52 51 7 8 24 23 22 21 26 25 33 32 31 30 35 34 49 48 50 3 4 5 6 1 2 13 16 36 38 37 47 fb 46 sysfault# csn3 csn2 daca fba eapa tonset isum pwm3_imax pwm2_imaxa isuma prog1 tsensea imona csn drctrl csn2a csp2a prog2 csna psys 15 14 45 44 42 41 43 40 39 pwm2a prog3 pwm1 upi confidential
UP9508 2 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com typical application circuit 3+2 phase pwm2_imaxa csp1 tsense vr_rdy sclk alert# sdio vrhot# en prog2 prog1 tonset vcc 5v csn1 scl prog3 vinsen v in csp csn gnd vccgt csp1a csn1a cspa csna 1 1 1 1 fbrtna fba daca eapa vccgt_sense vssgt_sense imona compa isuma sysfault# tsensea csp2a csn2a 1 0.1 f 0.1 f 0.1 f 0.1 f vcore boot ug ph lg 0.1 f v in pwm en vccgnd 12v boot ug ph lg 0.1 f v in pwm en vccgnd 12v 1 f 1 f pwm3_imax drctrl 10kohm 0.1 f csp2 csn2 0.1 f csp3 csn3 0.1 f 0.1 f fbrtn fb dac eap vcc_sense vss_sense imon comp isum boot ug ph lg 0.1 f v in pwm en vccgnd 12v 1 f pwm1 boot ugph lg 0.1 f v in pwm en vcc gnd 12v 1 f boot ugph lg 0.1 f v in pwm en vcc gnd 12v 1 f pwm1a pwm2a psys sda upi confidential UP9508 3 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com typical application circuit 1+1 phase pwm2_imaxa csp1 tsense vr_rdy sclk alert# sdio vrhot# en csn1 csp csn vcore pwm3_imax 0.1 f csp2 csn2 csp3 csn3 0.1 f fbrtn fb dac eap vcc_sense vss_sense imon comp isum 1kohm vcc 1kohm vcc *note 1 *note 2: a 10kohm resistor must still be connected between drctrl to ground even if external mosfet driver is unused. *note 1: use 1kohm resistor to pull up csn2, csn3 and csn2a to vcc. connect csp2, csp3 and csp2a to ground. drctrl 10kohm boot ug ph lg 0.1 f v in pwm en vcc gnd 12v 1 f pwm1 prog2 prog1 tonset vcc 5v scl prog3 vinsen v in gnd vccgt csp1a csn1a cspa csna fbrtna fba daca eapa vccgt_sense vssgt_sense imona compa isuma sysfault# tsensea csp2a csn2a 0.1 f 0.1 f 0.1 f boot ugph lg 0.1 f v in pwm en vcc gnd 12v 1 f pwm1a pwm2a psys sda 1kohm vcc *note 1 upi confidential UP9508 4 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 1x ami_3m w p etercsidlanretxeroflangiscigolm w pastuptuoti.niplanoitcnuf-itlum asinipsiht .tnetnocretsigerdivserocvehttesotdesuoslasitidnalia rerocvrofrevirdtefsom .tuptuo m w p3esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc .erocvroftupnignittes xami divsehttesotdng otnipsihtmorfrotsiseratcennoc .liarerocvrofeulav)h12x0(retsigerxamcci 2a xami_2m w p etercsidlanretxeroflangiscigolm w pastuptuoti.niplanoitcnuf-itlum asinipsiht .tnetnocretsigerdivstgccvehttesotdesuoslasitidnalia rerocvrofrevirdtefsom .tuptuo m w p2esahp .revirdtefsomlanretxefotupnim w potnipsihttcennoc .tgccvroftupnignittesaxami divsehttesotdng otnipsihtmorfrotsiseratcennoc .liartgccvrofeulav)h12x0(retsigerxamcci 3y dr_rv .rotacidniydaer rv sihtpullup.hgihevitcasitidnaerutcurtsniardneponasin ipsiht seog(ydr_rvstressarellortnoceht.ecruosegatlovaotrot siserreporpahguorhtnip .dnam mocdivstpeccaotydaersirellortnocehttahtetacidniot)h gih 43 nsc .3esahperocvroftupniesnestnerruclaitnereffidevitage n s i3esahperocvnehw k1ahguorhtccvotnipsihthgihllup,desuton ? erocvtelot3m w pelbasidotrotsiser .noitarugifnocesahp-2nietareporv 53 psc .3esahperocvroftupniesnestnerruclaitnereffidevitiso p si3esahperocvnehw .noitarugifnocesahp-2niderugifnocsirverocvnehw dng otnipsihttrohs,desuton 62 nsc .2esahperocvroftupniesnestnerruclaitnereffidevitage n s i2esahperocvnehw k1ahguorhtccvotnipsihthgihllup,desuton ? erocvtelot2m w pelbasidotrotsiser .noitarugifnocesahp-elgnisnietareporv 72 psc .2esahperocvroftupniesnestnerruclaitnereffidevitiso p si2esahperocvnehw esahp-elgnisniderugifnocsirverocvnehw dng otnipsihttrohs,desuton .noitarugifnoc 81 nsc .1esahperocvroftupniesnestnerruclaitnereffidevitage n 91 psc .1esahperocvroftupniesnestnerruclaitnereffidevitiso p 0 1m usi .erocvrofgnisnesdnagnittesdlohserhtnoitcetorptnerru crevo atcennoc tcennoctonod.dlohserhtnoitcetorptnerrucrevoehttesot dng otnipsihtmorfrotsiser daollatotehtotlanoitroporpsinipsihtfotnerructuptuoe ht.nipsihtotroticapacyna sihtmorfrotsiseradna,nipsihtfotuoswolfdnadesnessitn errucdaollatoteht.tnerruc ehtnehw.tnerructuptuolatotehtotlanoitroporpegatlovm usiehtsekam dng otnip x amcciehteussiotwoldellupeblliw#trelaehtylno,v5.1sde ecxenip musinoegatlov fo %031(v59.1sdeecxenip musinoegatlovehtnehw.ecafretnidivshguorhttrela .rellortnocehtnwodtuhsotdeppirteblliwnoitcetorptner rucrevoeht,)tluafed,v5.1 1 1n sc .erocvrofreifilpmaesnestnerruclatotfotupnignitrevni 2 1p sc .erocvrofreifilpmaesnestnerruclatotfotupnignitrevni -non 3 1p moc .erocvrofreifilpmarorrepoollortnocfotuptuo ahtiwseiresnirotsiseratcennoc .noitasnepmocpoollortnocegatlovrofdng otnipsihtmorfroticapac 4 1b f .erocvrofreifilpmarorreehtfotupnignitrevni 5 1p ae .erocvrofreifilpmarorreehtfotupnignitrevni-non sihtneewtebrotsiseratcennoc .noitcnuf)enildaol(poordehttesotcaddnanip 6 1c ad .erocvroftuptuo cad ehtrofegatlovecnereferehtsinipsihtfoegatlovtuptuoeh t morfroticapacatcennoc.ntrbfottcepserhtiwderusaem siegatlovcad.liarerocv .ntrbfotnipsiht upi confidential UP9508 5 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 7 1n trbf .erocvrofnruterkcabdeefegatlovtuptuo egatlovlaitnereffidehtottupnignitrevni .tnemerusaem egatlovtuptuocadnitniopecnereferehtsintrbf.reifilpm aesnes ,tniopesnesnruterkcabdeefegatlovtuptuorossecorpehto tyltceridnipsihttcennoc .esnes_ssvyleman 8 1n omi .erocvrofrotinomtnerructuptuo otdng otnipsihtmorfrotsiseratcennoc sihtfotnerructuptuoeht.rverocvrofnoitcnufgnitropert nerructuptuolatigidtnemelpmi tuoswolfdnadesnessitnerrucdaollatoteht.tnerrucdaoll atotehtotlanoitroporpsinip ehtotlanoitroporpegatlovnomiehtsekam dng otnipsihtmorfrotsiseradna,nipsihtfo nomiehtstrevnoc)cda(retrevnoclatigid-ot-golanani-tl iubeht.tnerructuptuolatot nacroticapaca.ecafretnidivsaivgnitropertnerructuptu oroftnetnoclatigidotegatlov nomiehttahteton.nomifoemitesnopserehttsujdaotdng otnomimorfdetcennoceb lanoitcnufninoitcesdetalerehtees.gnitropertnerructu ptuolatigidrofylnodesusi .noitcelesroticapacnomirofnoitpircsed 9 1n esniv .esnesegatlovtupniegatsrewop tupniegatsrewopehtotnipsihttcennocyltcerid v ni vegatlovtupniegatsrewoprofnipsihtnoegatlovehtsesnes rellortnoceht. ni .noitaluclacemit-no m w profdesuoslasiegatlovnesniveht.noitceted 0 2c cv .tiucriclortnoccigolroftupniylppus naaivecruosegatlovv5aotnipsihttcennoc .tiucriclortnoccigolehtroftupniylppusehtsiccv.retli fcr 1 2l cs .tupnikcolcsubms .tupnilangiskcolcsublairesseviecernipsiht 2 2a ds .tupniatadsubms .langisatadsublairesfotuptuorotupnisinipsiht 3 2# tohrv .rotacidnilamreht divs eht.wolevitcasitidnaerutcurtsniardneponasinipsiht nahtrehgihsierutarepmetrvehttahtmroftalpehtetacidni ot#tohrvstressarellortnoc 601sinoitressa#tohrvfoeulaveht.dlohserhteht o lamrehtdivsfoeulavehtdna,c 301sitrela o .c 4 2k lcs .tupnikcolc divs 5 2# trela .enil#trela divs 6 2o ids .o/iatad divs 7 2n e tupnilortnocelbanepihc wolebnipsihtllup.pihcehtselbanev8.0evobanipsihtllup . l iarrewopegatlovttvehtfotuptuoehtotdetcennocyllacipy ts'ti.pihcehtelbasidotv3.0 .draobrehtom ehtno 8 2a nomi .tgccvrofrotinomtnerructuptuo otdng otnipsihtmorfrotsiseratcennoc sihtfotnerructuptuoeht.rvtgccvrofnoitcnufgnitropert nerructuptuolatigidtnemelpmi tuoswolfdnadesnessitnerrucdaollatoteht.tnerrucdaoll atotehtotlanoitroporpsinip otlanoitroporpegatlovanomiehtsekam dng otnipsihtmorfrotsiseradna,nipsihtfo anomiehtstrevnoc)cda(retrevnoclatigid-ot-golanani-t liubeht.tnerructuptuolatoteht nacroticapaca.ecafretnidivsaivgnitropertnerructuptu oroftnetnoclatigidotegatlov ehttahteton.anomifoemitesnopserehttsujdaotdng otanomimorfdetcennoceb l anoitcnufninoitcesdetalerehtees.gnitropertnerructup tuolatigidrofylnodesusianomi .noitcelesroticapacanomirofnoitpircsed 9 2a ntrbf .tgccvrofnruterkcabdeefegatlovtuptuo egatlovlaitnereffidehtottupnignitrevni .tnemerusaem egatlovtuptuoacadnitniopecnereferehtsiantrbf.reifil pmaesnes ,tniopesnesnruterkcabdeefegatlovtuptuorossecorpehto tyltceridnipsihttcennoc .esnes_tgssvyleman 0 3a cad .tgccvroftuptuo cad ehtrofegatlovecnereferehtsinipsihtfoegatlovtuptuoeh t roticapacatcennoc.antrbfottcepserhtiwderusaem siegatlovacad.liartgccv .antrbfotnipsihtmorf upi confidential UP9508 6 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 1 3a pae .tgccvrofreifilpmarorreehtfotupnignitrevni-non sihtneewtebrotsiseratcennoc .noitcnuf)enildaol(poordehttesotacaddnanip 2 3a bf .tgccvrofreifilpmarorreehtfotupnignitrevni 3 3a pmoc .tgccvrofreifilpmarorrepoollortnocfotuptuo ahtiwseiresnirotsiseratcennoc .noitasnepmocpoollortnocegatlovrofdng otnipsihtmorfroticapac 4 3a nsc tgccvrofreifilpmaesnestnerruclatotfotupnignitrevni 5 3a psc .tgccvrofreifilpmaesnestnerruclatotfotupnignitrevni -non 6 3a musi .tgccvrofgnisnesdnagnittesdlohserhtnoitcetorptnerru crevo atcennoc tcennoctonod.dlohserhtnoitcetorptnerrucrevoehttesot dng otnipsihtmorfrotsiser daollatotehtotlanoitroporpsinipsihtfotnerructuptuoe ht.nipsihtotroticapacyna sihtmorfrotsiseradna,nipsihtfotuoswolfdnadesnessitn errucdaollatoteht.tnerruc ehtnehw.tnerructuptuolatotehtotlanoitroporpegatlova musiehtsekam dng otnip ehteussiotwoldellupeblliw#trelaehtylno,v5.1sdeecxen ipamusinoegatlov v59.1sdeecxenipamusinoegatlovehtnehw.ecafretnidivsh guorhttrelaxamcci .rellortnocehtnwodtuhsotdeppirteblliwnoitcetorptner rucrevoeht,)v5.1fo %031( 7 3a 1psc .1esahptgccvroftupniesnestnerruclaitnereffidevitiso p sitgccvnehw .dng otnipsihttrohs,esahp-1saderugifnoc 8 3a 1nsc .1esahptgccvroftupniesnestnerruclaitnereffidevitage n sitgccvnehw .dng otnipsihttrohs,esahp-1saderugifnoc 9 3a 2psc .2esahptgccvroftupniesnestnerruclaitnereffidevitiso p tefsom ehtelbasidot ehtotrefer.dng otnipsihttrohs,)a2gl,a2hp,a2gu,a2toob(esahpsihtfore vird .liatedrofnoitamrofninoitacilppaninoitcesdetaler 0 4a 2nsc .2esahptgccvroftupniesnestnerruclaitnereffidevitage n ehtelbasidot ccvotnipsihthgihllup,)a2gl,a2hp,a2gu,a2toob(esahpsi htforevirdtefsom k1ahguorht ? noitacilppaninoitcesdetalerehtotrefer.esahpsihtelba sidotrotsiser .liatedrofnoitamrofni 1 4a esnest .tgccvroftupnignirotinomlamreht erutarepmetevitagendeificepsatcennoc erutarepmetrvtgccvrofdng otnipsihtmorfkrowtenrotsimreht)ctn(tneiciffeoc k001esuotdnem mocer.gnisnes ? / atarumybrotsimrehtctn0524= .liatedrofnoitamrofninoitacilppaninoitcesdetalereht ees.)cr30f401fw51pcn( 2 4t esnot .gnittesemit-no m w p .emit-no m w pehttesotdng otnipsihtmorfrotsiseratcennoc .gnittesemit-no m w pemasehterahsrvtgccvdnarverocveht 3 4e snest .erocvroftupnignirotinomlamreht erutarepmetevitagendeificepsatcennoc erutarepmetrverocvrofdng otnipsihtmorfkrowtenrotsimreht)ctn(tneiciffeoc atarumybrotsimrehtctn0524=]/[k001esuotdnem mocer.gnisnes .liatedrofnoitamrofninoitacilppaninoitcesdetalereht ees.)cr30f401fw51pcn( 4 4s ysp .tupnicdarotinomrewoptupnimetsys rewop metsysmroftalplatotrofsinipsiht otegatlovnipsyspehtstrevnoc)cda(retrevnoclatigid-ot -golanani-tliubeht.rotinom eht.ecafretnidivsaiv)hb1x0(rotinomrewop metsysmroftalplatotroftnetnoclatigid .noituloservm01htiw)hff=(v65.2ot)h00=(v0 morfsiegnartuptuodnatupnicda ecruostnerrucaotnipsihttcennocro,mroftalp morfecruosegatlovaotnipsihttcennoc a.noitcnufsihttnemelpmiotdng otnipsihtmorfrotsiserahtiwgnola mroftalp morf .emitesnopserehttsujdaotnipsihtotdeddaebnacroticapa c 5 4# tluafsys .rotacidni#tluafsys .tuptuoniard-neponasinipsiht upi confidential UP9508 7 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 6 4a 1m w p .tuptuo m w p1esahptgccv tefsomlanretxefotupnim w pehtotnipsihttcennoc rofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht.revird .liartgccv 7 4a 2m w p .tuptuo m w p2esahptgccv tefsomlanretxefotupnim w pehtotnipsihttcennoc rofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht.revird .liartgccv 8 43 gorp .3nipgnittesnoitcnuf rotsiseratcennoc.sretemaraprvowttesotdesusinipsiht egnahclliweulavh52x0(eulavh42x0retsigerdivsehttcele sotdng otnipsihtmorf dnarverocveht.elbasid/elbanenoitcnufnoisnetxeesahpn oitarepodna)ylgnidrocca hc0ottesebnaceulavh42x0retsigerdivseht.sgnittesemas ehterahsrvtgccv tidna,eulavretsigerdivsehtstesylnonipsihttahteton.) su/vm33=(h12ro)su/vm21=( lautcaeht.gnimittreladnaetarwelsnoitisnartegatlovtu ptuolautcaehttceffatonseod .hc1x0retsigersubmsybdellortnocsietarwelsnoitisnart egatlovtuptuo 9 4l rtcrd .tuptuolortnocelbanerevird tefsom otdesusiti.niplanoitcnuf-itlum asinipsiht sihtmorfrotsiser[k01atcennoc.srevirdtefsom etercsidlanretxellaelbasid/elbane rehtoynaesutonod.rellortnocehtotesolcrotsisersihtec alpdnadnuorgotnip fognituorecartbcp.nipsihtotyltceridroticapacynatcen noctonod.eulavecnatsiser noitamrofninoitacilppaninoitcesdetalerehtotrefer.no itaredisnoclaicepssahnipsiht .liatedrof 0 52 gorp .2nipgnittesnoitcnuf rotsiseratcennoc.sretemaraprvowttesotdesusinipsiht ecivedsubmsehtdna)toobv(egatlovputratslaitiniehttce lesotdng otnipsihtmorf dnaliarerocveht.v5.1rov2.1,v50.1,v8.0,v0ottesebnact oobveht.sserdda ottesebnacsserddaecivedsubmseht.gnittestoobvemaseht erahsliartgccv .hc8x0roha8x0,h88x0 1 51 gorp .1nipgnittesnoitcnuf rotsiseratcennoc.sserddarv divstesotdesusinipsiht eht.srotalugeregatlovowtehtrofsserddarv divsehttcelesotdng otnipsihtmorf .]30,10[ro]20,00[,]00,10[,]10,00[satesebnac]tgccv/e rocv[fosserddarv divs ehtwollofyltcirtsdnaliatedrofnoitamrofninoitacilppa ninoitcesdetalerehtotrefer .gnittesdednem mocer 2 51 m w p .tuptuo m w p1esahp .revirdtefsomlanretxefotupnim w pehtotnipsihttcennoc .liarerocvrofrevirdtefsom etercsidlanretxeroflangiscigolm w pastuptuonipsiht dapdesopxe .dnuorg l ortnoccigoldnasrevirdtefsom deddebmefodnuorgehtsidapdesopxeeht .dng otdetcennocdnabcpegralaotderedlosebtsumtidna,stiucr ic upi confidential UP9508 8 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional block diagram por svid/smbus/adc shutdown /calibration vr_rdy en vcc on time generation and pwm control logic ramp generation tonset pwm2/imaxa pwm3/imax fbrtn prog1 prog2 alert# sclk vrhot# csp1 csn1 dac vinsen gnd fbrtna tsensea eap imon csn csp fb comp uvp ovp eap + 400mv tsense eap - 400mv operation phase selection gm gm gm current balance gm per-phase ocp isum csp2 csn2 csp3 csn3 i csn i ofs i csn i csn i csn daca i csna pwm1 pwm1a pwm2a csp1a csn1a gm gm csp2a csn2a operation phase selection on time generation and pwm control logic current balance per-phase ocp eapa imona csna cspa fba compa uvp ovp eapa + 400mv eapa - 400mv gm isuma i csna i ofsa i csna tonset vinsen drctrl i csna d/a buf d/a buf imax imaxa ramp generation tonset sysfault# ocp & svid iccmax alert ocp & svid iccmax alert sda scl prog3 psys upi confidential UP9508 9 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description power input and power on reset the UP9508 has single power input vcc. vcc is the 5v supply input for control logic circuit of the controller. rc filter to vcc is required for locally bypassing this supply input. vcc has power on reset (por) function. vinsen is the power stage input voltage sense pin, and it also has power on reset function. the controller monitors the vinsen voltage for pwm on-time calculation. en is the chip enable input pin. logic high to this pin enables the controller, and logic low to this pin disables the controller. the above three inputs (vcc, vinsen and en) are monitored to determine whether the controller is ready for operation. figure 1 shows the power ready detection circuit. the vcc voltage is monitored for power on reset with typically 4.3v threshold at its rising edge. the vinsen voltage is monitored for power on reset with typically 6v threshold at its rising edge. when vcc and vinsen are all ready, the controller waits for en to start up. when en pin is driven above 0.8v, the controller begins its start up sequence. when en pin is driven below 0.3v, the controller will be turned off, and it will clear all fault states to prepare to next soft-start once the controller is re-enabled. note that only vcc or en toggle will clear all fault state, vinsen toggle is not used for clearing fault state. anytime any one of the three inputs falls below their power on reset level will shutdown the controller. vcc en vinsen 4.3v 0.8v 6v por figure 1. circuit for power ready detection controller start up sequence when vcc and vinsen inputs are all ready, the controller waits for the en signal to initiate the power on sequence. after en goes high, the controller waits for a delay time ta (<2.5ms) then vr_rdy goes high to indicate that the pwm controller is ready for accepting svid command. at the same time, the output voltage starts to ramp up to vboot with always slow slew rate for non-zero vboot case. after output voltage settled to vboot, the controller assert alert#. then the start up sequence is over. figure 2 shows the typical start up sequence for non-zero vboot case. time interval tb is determined by the vboot voltage and the slow slew rate. figure 3 shows the typical start up sequence of zero-vboot case. for the zero vboot case, the output voltage slew rate is determined by the setvid command. note that vr_rdy goes high after delay time ta in both cases. pvcc vinsen vcc en vtt (pullup bias rail) vr_rdy (open drain) t a vout (non-zero vboot) alert# (open drain) t b figure 2. start up sequence and enable timing with non-zero vboot t a svid bus 1st setvid command t b pvcc vinsen vcc en vtt (pullup bias rail) vr_rdy (open drain) vout (zero vboot) alert# (open drain) figure 3. start up sequence and enable timing with zero vboot upi confidential UP9508 10 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description initial parameter setting there are five essential vr initial parameters that need to be determined such as vcore svid register 0x21h value, vccgt svid register 0x21h value, svid vr address, output initial start up voltage vboot and smbus device address. they are programmed by pwm3_imax, pwm2_imaxa, prog1 and prog2 as shown in figure 4. each parameter setting is detailed in the following sections. prog1 pwm3_imax a/d converter prog2 pwm2_imaxa r imax r imaxa r 1 r 2 r 3 r 4 prog3 r 5 r 6 figure 4. initial parameter setting vcore svid register (iccmax) value setting (pwm3_imax) the pwm3_imax is a multi-functional pin, which is used to set specific svid register value and outputs pwm signal for external mosfet driver. refer to figure 4, a resistor r imax connected from this pin to ground sets the vcore svid register 0x21h (iccmax) value. during the initial setting period, a 10ua current source is turned on for a period of time to flow out of this pin through r imax to create voltage drop on this pin. this voltage is digitized by an internal 8- bit a/d converter and stored in vcore svid register 0x21h (iccmax). the a/d converter scales 2.56v into 256 levels, which means 10mv represents 1a. for example, if the svid register 0x21h (iccmax) value to be set to 100a (64h), the voltage should be 10mv x 100 = 1v. therefore the resistor r imax is 1v / 10ua = 100k. the programmable range is from 00h to ffh (0a to 256a). if the pin voltage is greater than 2.56v, the svid register 0x21h value will still be ffh. note that this setting is only for determining svid register value, and is not used for over current protection or svid iccmax alert function vccgt svid register (iccmax) value (pwm2_imaxa) the pwm2_imaxa is a multi-functional pin, which is used to set specific svid register value and outputs pwm signal for external mosfet driver. refer to figure 4, a resistor rimaxa connected from this pin to ground sets the vccgt svid register 0x21h (iccmax) value. during the initial setting period, a 10ua current source is turned on for a period of time to flow out of this pin through rimaxa to create voltage drop on this pin. this voltage is digitized by an internal 8- bit a/d converter and stored in vccgt svid register 0x21h (iccmax). the a/d converter scales 2.56v into 256 levels, which means 10mv represents 1a. for example, if the svid register 0x21h (iccmax) value to be set to 60a (3ch), the voltage should be 10mv x 60 = 0.6v. therefore the resistor rimaxa is 0.6v / 10ua = 60k[. the programmable range is from 00h to ffh (0a to 256a). if the pin voltage is greater than 2.56v, the svid register 0x21h value will still be ffh. note that this setting is only for determining svid register value, and is not used for over current protection or svid iccmax alert function. svid vr address (prog1) the up9507 features selectable svid vr address for maximized flexibility in platform design. prog1 is a function setting pin, which is used to set this essential parameter. refer to figure 4, resistors r 1 and r 2 connected in parallel from this pin to ground sets the svid vr address. the svid vr address of [vcore/ vccgt] can be set as [00, 01], [01, 00], [00, 02] or [01, 03]. this makes the svid vr address interchangeable/selectable, and provides more design flexibility per different power requirement. table 1 shows the recommended resistance value for prog1 function setting. strictly follows the recommended resistor value in prog1 setting. note that for the rail with svid address being set to 02h or 03h, its vboot voltage will be fixed at 1.05v, regardless of the prog2 pin setting. see initial start up voltage (vboot) (prog2) section for detail. table 1. svid vr address setting .on sserdda divs ,erocv( )tgccv dednem mocer1gorp k(eulavrotsiser ?? ? ?? l ellarapni) r 1 r 2 1h 10,h0 00n epo 2h 00,h1 03 12 1 3h 20,h0 04 24 2 4h 30,h1 07 43 4 oteulavrotsiserdednem mocerehtwollofyltcirts:eton .tluafmetsyscihportsatacdiova upi confidential UP9508 11 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description operation phase disable function the pwm2_imaxa is a multi-functional pin, which is used to set specific svid register value and outputs pwm signal for external mosfet driver. refer to figure 4, a resistor rimaxa connected from this pin to ground sets the vccgt svid register 0x21h (iccmax) value. during the initial setting period, a 10ua current source is turned on for a period of time to flow out of this pin through rimaxa to create voltage drop on this pin. this voltage is digitized by an internal 8- bit a/d converter and stored in vccgt svid register 0x21h (iccmax). the a/d converter scales 2.56v into 256 levels, which means 10mv represents 1a. for example, if the svid register 0x21h (iccmax) value to be set to 60a (3ch), the voltage should be 10mv x 60 = 0.6v. therefore the resistor rimaxa is 0.6v / 10ua = 60k[. the programmable range is from 00h to ffh (0a to 256a). if the pin voltage is greater than 2.56v, the svid register 0x21h value will still be ffh. note that this setting is only for determining svid register value, and is not used for over current protection or svid iccmax alert function table 2. operation phase number setting noitarugifnoc detroppus noitarepo esahp rebmun tegratotwol/hgihllup,noitcennocnip 2ps c2 ns c3 ps c3 ns ca 2ps ca 2ns ca 1ps ca 1nsc esahp-2+3 2+ 3- -- -- -- -- -- -- -- - 2+ 2- -- -d n gc c v- -- -- -- - 2+ 1d n gc c vd n gc c v- -- -- -- - 1+ 3- -- -- -- -d n gc cv lamron noitcennoc )2eton( lamron n oitcennoc )2eton( 1+ 2- -- -d n gc c vd n gc cv lamron noitcennoc )2eton( lamron n oitcennoc )2eton( 1+ 1d n gc c vd n gc c vd n gc cv lamron noitcennoc )2eton( lamron n oitcennoc )2eton( .noitcennoclamronsetoned"--":1eton .noitcennoclamronniebdluohsa1nscdnaa1psc,noitarepoe sahpelgnisnitgccvrof:2eton k01a:3eton ? .desunusirevirdtefsomlanretxefinevedngotlrtcrdneewt ebdetcennocebllitstsumrotsiser k1esu:4eton ? .ccvotpullupnehwrotsiserpullup esuaclliwnoitcennocnwod/pullupniptcerrocnidnagnitte s1gorptcerrocni.elbasidesahprofelbatehtwollofyltcir ts:5eton .putratsgnirudtluafcihportsatac upi confidential UP9508 12 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com slew rate and phase extension enable control (prog3) table 4. slew rate and phase extension enable control .on noisnetxeesahp divtes tsaf wels etar dednem mocer r otsiserlellarap k(epyt ?? ? ?? ) eroccc vt gcc vr 5 r 6 1e lbasi de lbasid 21 su/vm 0n epo 2e lbasi de lban e3 12 1 3e lban ee lbasi d4 24 2 4e lban ee lban e7 43 4 5e lban ee lbane 33 su/vm 01 10 11 6e lban ee lbasi d0 2 20 81 7e lbasi de lban e0 6 30 33 8e lbasi de lbasi dn ep on epo external mosfet driver control the drctrl pin is used for controlling the enable/disable of external mosfet drivers. ma ke sure to connect a 10k[ resistor from this pin to gnd and place this resistor close to the controller. this resistor is used to generate the reference current for thermal sense by tsense and tsensea. do not use any other resistance value. this 10k[ re sistor must still be connected between drctrl to ground even if external mosfet driver is unused. connect this pin to a resistor riso and then connect to the enable control pin of the external mosfet drivers as shown in figure 5. the recommended resistance value of riso is between 1k[ to 10k[. the drctrl is a noise sensitive pin, therefore the pcb trace routing should be kept away from other nets, especially the switching signals. it is required to keep at least 20mil space to other nets 10kohm drctrl r iso to mosfet driver enable pi n noise sensitive. keep trace routing away from other nets . figure 5. drctrl connection pwm on time setting the pwm on-time is set by an external resistor r ton con- nected between tonset pin and gnd. the controller senses vinsen voltage to obtain input voltage information initial start up voltage (vboot) and smbus device address. (prog2) the UP9508 features selectable initial start up voltage (vboot) and smbus device address for design flexibility. prog2 is a function setting pin, which is used to set the two essential parameters. refer to figure 4, resistors r3 and r4 connected in parallel from this pin to ground sets the initial start up voltage (vboot) and smbus device ad- dress. the vboot can be set to 0v, 0.8v, 1.05v, 1.2v or 1.5v. both the vcore rail and vccgt rail share the same vboot setting. the smbus device address can be set to 0x88h, 0x8a or 0x8ch. table 3 shows the recommended resistance value for prog2 function setting. although vcore and vccgt share the same vboot setting, there is an ex- ception for the rail with svid address being set to 02h and 03h. for the rail with svid address being set to 02h or 03h, its vboot voltage will be fixed at 1.05v, regardless of the prog2 pin setting. the vboot voltage of other rail (svid address=00h or 01h) still follows prog2 pin setting. in this case, the vboot voltage for svid address [00, 02], or [01, 03] will be different. for example, when vboot is set to 0v (prog2 pin short to gnd) and svid address is set to [00, 02], the vboot voltage for the rail with address=00 and address=01 is 0v and 1.05v, respectively. table 3. vboot and smbus device address setting .o n) v(toobv subms sserdda l ellarapdednem mocer k(epytrotsiser ?? ? ?? ) r 3 r 4 10 h88 0n epo 28 . 03 . 43 3 35 . 13 12 1 42 . 16 10 2 55 0. 14 24 2 60 ha8 3 33 3 78 . 07 43 4 85 . 18 66 5 92 . 12 82 8 0 15 0. 10 1 10 11 1 10 hc8 05 10 51 2 18 . 00 2 20 81 3 15 . 10 7 20 72 4 12 . 10 6 30 33 5 15 0. 1n ep on epo functional description upi confidential UP9508 13 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description for pwm on-time calculation. both the vcore rail and vccgt rail share the same pwm on-time setting. the pwm on-time can be calculated as below equation. 10 0 ) ( ? ? ? ? ? ? ? ? = ton in out on r v v ns t table 6 lists the switching frequency and the recommended resistor r ton value (with condition: v in = 12v, v out = 1.2v). for example, given v in = 12v, v out = 1.2v, r ton = 50k ? , t on is about 500ns by above equation. the pwm frequency is about 200khz. note that the resistance value of r ton value must be greater than 10k ? to ensure the pwm on-time calculation circuit in normaloperation. table 5. switching frequency and resistor r ton ycneuqerfgnihctiws )zhk( r otsiser dednem mocer r not k( ?? ? ?? ) 00 20 5 00 33 .33 00 45 2 00 50 2 00 67 .61 rrotsiserfo muminim eht:eton not k01sieulav ? . soft startthe slew rate of output voltage during soft start operation and dynamic vid voltage change is determined internally. place a mlcc c dac between dac and fbrtn (daca and fbrtna for vccgt). the recommended capacitance of c dac is 10nf. the slew rate during soft start operation is always slow for non-zero vboot case. the slow slew rate is determined by the processor in svid register 2ah. iccmax alert and total output over current protection (ocp) as shown in figure 8, the sensed current i csn is mirrored internally and fed to isum pin (isuma for vccgt) as i sum for svid iccmax alert function and total output over current protection (ocp). a resistor r isum is connected from isum pin to gnd. this current flows through the resistor r isum , creating voltage drop across it. as the total load current increases, the voltage on isum pin (v isum ) increases proportionally. when the isum pin voltage is greater than typically 1.5v, the svid iccmax alert will be triggered, dynamic vid change and slew rate the controller accepts setvid command via svid bus for output voltage change during normal operation. this allows the output voltage to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (vid otf). a vid otf event may occur under either light or heavy load condition. this voltage change direction can be upward or downward. per setvid command, the slew rate can be fast or slow. the slow slew rate is determined by the svid register 2ah, which can only be programmed by the processor. the default value of slow slew rate is 1/2 of fast slew rate. the fast slew rate of vcore and vccgt can be separately further progra mmed by the controller?|s smbus register 0x1ch. the fast slew rate can be set from 12mv/ us to 33mv/us with a total of 7 steps and 3mv/lsb resolution. the default value of fast slew rate is 12mv/us. output voltage differential sense the UP9508 uses differential sense by a high-gain low- offset error amplifier for output voltage differential sense as shown in figure 6. the cpu voltage is sensed by the fb and fbrtn pins (fba and fbrtna for vccgt). fb pin is connected to the positive remote sense pin vcc_sense of the cpu via the resistor rfb. fbrtn pin is connected to the negative remote sense pin vss_sense of cpu directly. (vccgt_sense and vssgt_sense for vccgt). the error amplifier compares the vfb with veap (= vdac - icsn x rdrp) to regulate the output voltage. gm r comp_int comp i csn fb r fb vcc_sense positive voltage remote sense pin of cpu csp csn eap dac r drp fbrtn c dac vss_sense negative voltage remote sense pin of cpu c comp r csn c csn reference voltage r comp figure 6. output voltage differential sense total load current sense the up9507 uses a low input offset current sense amplifier (csa) to sense the total load current flowing through inductors for droop function by csp and csn (cspa and csna for vccgt) as shown in figure 7. r ph1 r ph2 r ph3 1ohm ph1 ph2 ph3 1ohm 1ohm v core v core v cor e c csn r csn csp csn i csn figure 7. total load current sense upi confidential UP9508 14 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com and then the alert# will be pulled low to indicate the processor that the voltage regulator is in iccmax condition. the output current level of triggering svid iccmax alert is calculated as follows. dc csn isum iccmax out r r n r i = 5.1 _ i csn csp csn r csn c csn isum r isum imon r imon c imon a/d converter svid register ocp iccmax alert 1.5v smbus figure 8. iccmax alert and total output ocp when the isum pin voltage further increases to greater than the ocp threshold (default value is typically 130% of svid iccmax alert threshold of 1.5v) for a specific delay time, the total output current protection will be triggered. vr_rdy will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high- impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the total output ocp is a latch-off type protection, and it can only be reset by vcc or en toggling. avoid adding capacitor to the isum pin. additional capacitance to this pin will affect the current level of svid iccmax alert and the total output ocp. the default output current level of triggering total output ocp is calculated as follows. 3 .1 5.1 _ = dc csn isum ocp out r r n r i total output ocp and operating phase number the total output ocp level is usually designed for the voltage regulator that is operated in full phase condition by hardware setting. the actual operating phase number is controlled by the svid setps command or the smbus auto phase setting. when the operating phase number is decreased, the total output ocp level is decreased as well. the total output ocp level is changed per actual operating phase number. table 5 shows the total output ocp ratio per actual operating phase number and the hardware configuration. table 7. total output ocp and operating phase number functional description the voltage across c csn is proportional to the total load current, and the output current of csa (i csn ) is also proportional to the total load current of the voltage regulator. the sensed current i csn represents the total output current of the regulator, and it is directly used for droop function, and further internally mirrored for svid iccmax alert function, total output over current protection, and output current reporting. i csn is calculated as follows. csn dc out csn r n r i i = in this inductor current sensing topology, r ph and c csn must be selected according to the equation below: n c r r l k csn ph dc = where r dc is the dcr of the output inductor l, n is the operation phase number. theoretically, k should be equal to 1 to sense the instantaneous total load current. but in real application, k is usually between 1.2 to 1.8 for better load transient response. note that the resistance value of r csn must be less than 2k ? to ensure the current sensing circuit in normal operation.droop (load line) setting as shown in figure 6, the current i csn denotes the sensed total load current, which is mirrored to the eap pin. when load current increases, i csn also increases and creates a voltage drop across r drp , and makes v eap lower than the v dac as follows. dr p csn dc out dac drp csn dac eap r n r r i v r i v v ? ? ? ? ? ? ? ? = = where r dc is the dcr of output inductor, n is the operation phase number, and i out denotes the total load current. in steady state, the output voltage is regulated to v eap . as the total load current i out increases, i csn increases proportionally, making v eap decreases accordingly. this makes the output voltage also decreases linearly as the total output current increases, which is also known as active voltage positioning (avp). the slope of output voltage decrease to total load current increase is referred to as load line. the load line is defined as follows n r r r i v line l oad csn drp dc out out = ? ? = upi confidential UP9508 15 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description oitar pcotuptuolatot noitidnocgnitarepo esahp- 3e sahp-2 e sahp-1 erawdrah noitarugifnoc esahp- 31- -2 1/5 esahp- 2- -13 /2 esahp- 1- -- -1 output current reportingrefer to figure 8, the sensed current i csn is also sepa- rately mirrored and fed to imon pin (imona for vccgt) as i imon for svid output current reporting function. connect a resistor r imon from imon pin to gnd. the current i imon flows through the resistor r imon , creating voltage drop across it. as the total load current increases, the voltage on imon pin (v imon ) increases proportionally. an internal analog-to- digital converter (adc) converts v imon to a digital content for output current reporting through svid interface. as v imon voltage increases, the svid register 0x15h content in- creases. the imon voltage has typically 600mv offset, which means v imon =600mv and svid register 0x15h=00h. the adc input range is typically 1.5v, which means the svid register 0x15h=ffh when v imon =2100mv. further increase of v imon (>2.1v) is allowed, but the adc results will remain at ffh. capacitor can be added to the imon pin to adjust the response time of current reporting. the imon pin is for digital output current reporting only, not for svid iccmax alert function or ocp. the total output cur- rent level for svid register 0x15h=ffh is calculated as follows. dc csn imon ffh hx out r r n r . i svid = = 51 15 0 note that the resistance value of r imon must be between 10k ? to 60k ? to ensure the controller in normal operation. imon/imona capacitor selection the capacitor c imon connected from imon to gnd (c imona for imona) is used to adjust the response time of imon voltage change to load current change. it is recommended to add a capacitor to the imon pin. however, too large capacitance for c imon is improper, and will affect the accuracy in digital output current reporting. due to the embedded a/ d conversion circuit to the imon pin, the rc time constant (tau) should be adequate to ensure correct operation and where l is the output inductor, r dc is its parasitic resistance and k is a constant. theoretically, if k = 1, the sensed current signal i csnx can be expressed as follows. csnx dc lx csnx r r i i = digital current reporting accuracy. use 4 x tau = 160us as the rule of thumb to determine c imon . after resistor r imon is determined, the c imon is then calculated by imon imon r c 4 10 160 6 then choose a capacitance value that is closest to but not greater than the calculation for c imon . over voltage protection (ovp) the controller monitors the voltage on fb pin (fba for vccgt) for over voltage protection. the controller monitors the voltage on fb pin (fba for vccgt) for under voltage protection. after output voltage ramps up to vboot, the con- troller initiates ovp function. once v fb exceeds v eap + ovp threshold for a specific delay time, ovp is triggered. vr_rdy will be pulled low immediately, ugx will be held low, lgx will be held high, and pwm outputs will be low to let driver turns on low side mosfet and turns off high side mosfet to protect cpu. since the low side mosfet is turned on, the regulator output capacitor will be discharged and output voltage decreases as well. when fb pin voltage decreases to lower than typical 0.5v, lgx will be held low (pwm outputs turns to high impedance state) to turn off the low side mosfet to avoid negative output voltage. the other unaffected voltage regulator will also shut down. the ovp is a latch-off type protection, and it can only be reset by vcc or en toggling. the ovp detection circuit has a fixed delay time to prevent false trigger. the ovp threshold can be further programmed by the smbus register. under voltage protection (uvp) the controller monitors the voltage on fb pin (fba for vccgt) for under voltage protection. after output voltage ramps up to vboot, the controller initiates uvp function. once v fb is lower than v eap - uvp threshold for a specific delay time, ovp is triggered. vr_rdy will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high-impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the uvp is a latch-off type protection, and it can only be reset by vcc or en toggling. the uvp detection circuit has a fixed delay time to prevent false trigger. the uvp threshold can be further programmed by the smbus register. per-phase over current protection in addition to the total output current ocp, the controller provides per-phase current ocp to protect the voltage regulator. the controller uses dcr current sensing technique to sense the inductor current in each phase for per-phase over current protection and current balance as shown in figure 9. in this inductor current sensing topology, the time constant can expressed as follows csx cspx dc c r r l k = upi confidential UP9508 16 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com (tsensea for vccgt) pin voltage and the sensed temperature is shown in figure 11. either vcore or vccgt regulator can trigger the vrhot# as long as the temperature of any of the two regulators exceeds the maximum temperature threshold. the threshold of vrhot# assertion can be further programmed by smbus register, the svid thermal alert assertion point will move accordingly. it is highly recommended to use 7.32k as r p , and 100k/ ] =4250 ntc thermistor by murata (ncp15wf104f03rc). r s is reserved for fine tune. r s =0 r ntc =100kohm tsense r p =7.32k ohm i tsense vrhot svid thermal alert smbus figure 10. regulator temperature sense 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 90 100 110 120 130 140 150 sensed temperature ( o c) sense/tsensa pin voltage (mv) figure 11. tsense/tsensea pin voltage and sensed temperature control loopthe UP9508 adopts the upi proprietary rcot +tm control technology. the rcot uses the constant on-time modulator. the output voltage is sensed to compare with the internal high accurate reference voltage. the reference voltage is commanded by cpu through the svid interface. the amplified error signal v comp is compared to the internal ramp to initiate a pwm on-time. the rcot +tm features easy design, fast transient response and is smooth mode transition and especially suitable for powering the microprocessor. system input power monitor (psys) the UP9508 provides total platform system input power monitor function. for desktop application, it is processor intput power. figure 12 shows the implementation of this function. psys pin is connected to a source (silicon functional description v in lr dc v core r cspx c csx r csnx cspx csnx i csnx i lx figure 9. phase current sense the sensed current i csnx represents the current in each phase, and it is compared to a current source (default = 100ua, smbus programmable) for per-phase ocp. if the inductor current of any of the active operating phase exceeds the threshold for a specific delay time, the per-phase ocp is triggered. vr_rdy will be pulled low immediately, both ugx and lgx will be held low, and all pwm outputs will in high-impedance state to let driver turns off all mosfets to shutdown the regulator. the other unaffected voltage regulator will also shut down. the per-phase ocp is a latch- off type protection, and it can only be reset by vcc or en toggling. the per-phase ocp threshold and its delay time can be further programmed by the smbus register. note that the resistance value of r csnx must be less than 2k to ensure the current sensing circuit in normal operation. the resistance of r csnx and the default per-phase ocp level can be obtained using equation as follows. ua r i r dc perphase ocp csnx 100 _ = thermal monitoring and vrhot#the tsense pin (tsensea for vccgt) is used for voltage regulator thermal monitoring. connect a negative temperature coefficient (ntc) thermistor network from tsense pin to gnd to implement this function as shown in figure 10. the ntc thermistor is placed close to the hottest point of the regulator, normally close to the inductor and low-side mosfet of phase 1. a precision current source flows out of the tsense pin through the temperature sense network to create a voltage drop v tsense on this pin. as regulator temperature rises, the v tsense decreases. therefore the controller detects the v tsense to obtain regulator thermal information for svid thermal alert and vrhot# function. the controller asserts vrhot# when the sensed temperature is higher than the value of svid register 0x22h (temp_max), in which the default value is 6ah (106 o c). the temperature for svid thermal alert and vrhot# assertion is 103 o c and 106 o c, respectively. the curve of tsense upi confidential UP9508 17 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description sensor) that can deliver system input power information. a built-in analog-to-digital converter (adc) converts the psys pin voltage to digital content for total platform system power monitor (0x1bh) via svid interface. cpu can then get the system input power (processor input power) information through the svid interface. the UP9508 operates as a meter here. if the source is in current format, which means the current source is proportional to the system input power, connect a resistor from psys pin to gnd to transform it to voltage. the adc input and output range is from 0v (=00h) to 2.56v (=ffh) with 10mv resolution. i f the psys pin voltage is greater than 2.56v, the svid register 0x1bh value will still be ffh. silicon sensor psys svid atx power / adaptor cpu i sys i in a/d UP9508 p sys meter 0x1bh figure 12. system input power monitor upi confidential UP9508 18 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( 00x 00 00. 05 2x 00 34. 0a 4x 05 16. 0f 6x 00 08. 04 9x 05 89. 08 bx 05 61. 1c dx 05 43.1 10x 00 52. 06 2x 05 34. 0b 4x 00 26. 00 7x 05 08. 05 9x 00 99. 09 bx 00 71. 1d dx 00 53.1 20x 05 52. 07 2x 00 44. 0c 4x 05 26. 01 7x 00 18. 06 9x 05 99. 0a bx 05 71. 1e dx 05 53.1 30x 00 62. 08 2x 05 44. 0d 4x 00 36. 02 7x 05 18. 07 9x 00 00. 1b bx 00 81. 1f dx 00 63.1 40x 05 62. 09 2x 00 54. 0e 4x 05 36. 03 7x 00 28. 08 9x 05 00. 1c bx 05 81. 10 ex 05 63.1 50x 00 72. 0a 2x 05 54. 0f 4x 00 46. 04 7x 05 28. 09 9x 00 10. 1d bx 00 91. 11 ex 00 73.1 60x 05 72. 0b 2x 00 64. 00 5x 05 46. 05 7x 00 38. 0a 9x 05 10. 1e bx 05 91. 12 ex 05 73.1 70x 00 82. 0c 2x 05 64. 01 5x 00 56. 06 7x 05 38. 0b 9x 00 20. 1f bx 00 02. 13 ex 00 83.1 80x 05 82. 0d 2x 00 74. 02 5x 05 56. 07 7x 00 48. 0c 9x 05 20. 10 cx 05 02. 14 ex 05 83.1 90x 00 92. 0e 2x 05 74. 03 5x 00 66. 08 7x 05 48. 0d 9x 00 30. 11 cx 00 12. 15 ex 00 93.1 a0x 05 92. 0f 2x 00 84. 04 5x 05 66. 09 7x 00 58. 0e 9x 05 30. 12 cx 05 12. 16 ex 05 93.1 b0x 00 03. 00 3x 05 84. 05 5x 00 76. 0a 7x 05 58. 0f 9x 00 40. 13 cx 00 22. 17 ex 00 04.1 c0x 05 03. 01 3x 00 94. 06 5x 05 76. 0b 7x 00 68. 00 ax 05 40. 14 cx 05 22. 18 ex 05 04.1 d0x 00 13. 02 3x 05 94. 07 5x 00 86. 0c 7x 05 68. 01 ax 00 50. 15 cx 00 32. 19 ex 00 14.1 e0x 05 13. 03 3x 00 05. 08 5x 05 86. 0d 7x 00 78. 02 ax 05 50. 16 cx 05 32. 1a ex 05 14.1 f0x 00 23. 04 3x 05 05. 09 5x 00 96. 0e 7x 05 78. 03 ax 00 60. 17 cx 00 42. 1b ex 00 24.1 01x 05 23. 05 3x 00 15. 0a 5x 05 96. 0f 7x 00 88. 04 ax 05 60. 18 cx 05 42. 1c ex 05 24.1 11x 00 33. 06 3x 05 15. 0b 5x 00 07. 00 8x 05 88. 05 ax 00 70. 19 cx 00 52. 1d ex 00 34.1 21x 05 33. 07 3x 00 25. 0c 5x 05 07. 01 8x 00 98. 06 ax 05 70. 1a cx 05 52. 1e ex 05 34.1 31x 00 43. 08 3x 05 25. 0d 5x 00 17. 02 8x 05 98. 07 ax 00 80. 1b cx 00 62. 1f ex 00 44.1 41x 05 43. 09 3x 00 35. 0e 5x 05 17. 03 8x 00 09. 08 ax 05 80. 1c cx 05 62. 10 fx 05 44.1 51x 00 53. 0a 3x 05 35. 0f 5x 00 27. 04 8x 05 09. 09 ax 00 90. 1d cx 00 72. 11 fx 00 54.1 61x 05 53. 0b 3x 00 45. 00 6x 05 27. 05 8x 00 19. 0a ax 05 90. 1e cx 05 72. 12 fx 05 54.1 71x 00 63. 0c 3x 05 45. 01 6x 00 37. 06 8x 05 19. 0b ax 00 01. 1f cx 00 82. 13 fx 00 64.1 81x 05 63. 0d 3x 00 55. 02 6x 05 37. 07 8x 00 29. 0c ax 05 01. 10 dx 05 82. 14 fx 05 64.1 91x 00 73. 0e 3x 05 55. 03 6x 00 47. 08 8x 05 29. 0d ax 00 11. 11 dx 00 92. 15 fx 00 74.1 a1x 05 73. 0f 3x 00 65. 04 6x 05 47. 09 8x 00 39. 0e ax 05 11. 12 dx 05 92. 16 fx 05 74.1 b1x 00 83. 00 4x 05 65. 05 6x 00 57. 0a 8x 05 39. 0f ax 00 21. 13 dx 00 03. 17 fx 00 84.1 c1x 05 83. 01 4x 00 75. 06 6x 05 57. 0b 8x 00 49. 00 bx 05 21. 14 dx 05 03. 18 fx 05 84.1 d1x 00 93. 02 4x 05 75. 07 6x 00 67. 0c 8x 05 49. 01 bx 00 31. 15 dx 00 13. 19 fx 00 94.1 e1x 05 93. 03 4x 00 85. 08 6x 05 67. 0d 8x 00 59. 02 bx 05 31. 16 dx 05 13. 1a fx 05 94.1 f1x 00 04. 04 4x 05 85. 09 6x 00 77. 0e 8x 05 59. 03 bx 00 41. 17 dx 00 23. 1b fx 00 05.1 02x 05 04. 05 4x 00 95. 0a 6x 05 77. 0f 8x 00 69. 04 bx 05 41. 18 dx 05 23. 1c fx 05 05.1 12x 00 14. 06 4x 05 95. 0b 6x 00 87. 00 9x 05 69. 05 bx 00 51. 19 dx 00 33. 1d fx 00 15.1 22x 05 14. 07 4x 00 06. 0c 6x 05 87. 01 9x 00 79. 06 bx 05 51. 1a dx 05 33. 1e fx 05 15.1 32x 00 24. 08 4x 05 06. 0d 6x 00 97. 02 9x 05 79. 07 bx 00 61. 1b dx 00 43. 1f fx 00 25.1 42x 05 24. 09 4x 00 16. 0e 6x 05 97. 03 9x 00 89.0 table 8. imvp8 vid table upi confidential UP9508 19 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 9. supported svid data and configuration register xedn ie manretsige rs secc at luafe dn oitpircsed h0 0d iredne vo rh 7 2d irednev h1 0d itcudor po rh f 1d itcudorp h2 0n oisivertcudor po rh 1 0n oisivertcudorp h5 0d ilocotor po rh 50 rellortnocehtlocotorpdivsfonoisrevtahwseifitnedi .stroppus h6 0y tilibapa co rh 18 rv divsehtseifitnedi,retsigerdeppamtib erayrtemeletlanoitpoehtfohcihwdnaseitilibapac .detroppus h0 11 _sutat sm w p-w,m- rh 00 .detressasilangis#trelaehtretfadaerretsigeratad .rvehtfosutatsehtgniyevnoc h1 12 _sutat sm w p-w,m- rh 00 ehtgniyevnoc.atad2_sutatsgniwohsretsigeratad .subdivsehtfosutats h5 1t nerructuptu om w p-w,m- r- -. tnerructuptuodegareva hb 1r ewoptupn im w p-w,m- r- -. sysprorewoptupnidegareva hc 1d aertsal_2_sutat sm w p-w,m- rh 00 tahtatad2sutatsehtfoypocasniatnocretsigersiht .dnam moc)2sutats(gerteg ehthtiwdaertsalsaw h1 2x am_cc im roftalp o r- - mroftalpehtmumixam cciehtgniniatnocretsigeratad .stroppus h2 2x am_pme tm roftalp o rh a6 ehtxam erutarepmetehtgniniatnocretsigeratad .stressa#tohrvlevelehtdnatroppusmroftalp nitamrofyranib o 061=ha6.e.i,c o .c h4 2t saf_r so rh c0 welstsaffoytilibapacehtgniniatnocretsigeratad ,su/vm nitamrofyranib.niatsusnacmroftalpehtetar .su/vm21=hc0.e.i h5 2w ols_r so rh 60 welswolsfoytilibapacehtgniniatnocretsigeratad .su/vm6=h60.e.i,su/vm nitamrofyranib.etar h6 2t oob vm roftalp o r- -. spetsdivniegatlovtoobvgniniatnocretsigeratad ha 2r otceles wels wol sr etsam w rh 1 0. etarwelslautcatcelfertsumretsigeretarwels hb 2y cnetaltixe4s po rh 59 stneserpertahteulavdedocnenasdlohretsigersiht su061stneserperh59.ycnetaltixe4sp rveht hc 2y cnetaltixe3s po rh 54 stneserpertahteulavdedocnenasdlohretsigersiht su5stneserperh54.ycnetaltixe3sp rveht hd 2y daer divsotelban eo rh 9c stneserpertahteulavdedocnenasdlohretsigersiht su4032stneserperh9c.ydaerotelbane rveht h0 3x amtuo vr etsam w rh bf stesdnaretsam ehtybdem margorpsiretsigersiht .troppuslliw rvehtdiv mumixam eht upi confidential UP9508 20 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description xedn ie manretsige rs secc at luafe dn oitpircsed h1 3g nittes di vr etsam w rh 00 divdem margorpyltnerrucgniniatnocretsigeratad .egatlov h2 3e tatsrewo pr etsam w rh 00 rewopdem margorptnerrucehtgniniatnocretsiger .etats h3 3t esffo egatlo vr etsam w rh 00 rofgnittesdivehtotdeddaspetsdivnitesffotes .gninigram egatlov h4 3g ifnoc rvitlu mr etsam w rh 10 elpitlum serugifnochcihwretsigerataddeppamtib .subemasehtnoroivahebsrv h5 3r dagerte sr etsam w r- - ehtfoegarotsyraropmetrofretsigerdaphctarcs .retsigerretnioprdagertes h2 4d iv-1div iw / rh 00 i- 1divinidenifedtnerrucxam ehthtiwdetaicossadiv h3 4i -1div iw / rh ff t essidivehtnehwdetcepxe)tib/a1(tnerrucxam eht div-1divi:sa > div-2divi> div h4 4d iv-2div iw / rh 00 i- 2divinidenifedtnerrucxam ehthtiwdetaicossadiv h5 4i -2div iw / rh ff :satessidivehtnehwdetcepxetnerrucxam eht div-2divi > div-3divi> div h6 4d iv-3div iw / rh 00 i- 3divinidenifedtnerrucxam ehthtiwdetaicossadiv h7 4i -3div iw / rh ff :satessidivehtnehwdetcepxetnerrucxam eht div-3divi > div table 9. supported svid data and configuration register (cont.) > > > upi confidential UP9508 21 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description smbus interface the UP9508 features an smbus interface and data registers to allow user to adjust various platform operating parameters for vcore and vccgt. the supported operating parameters that can be adjusted through the smbus are summarized as table 8. the main function is to dynamically change the offset voltage, switching frequency, operating phase number, and loadline according to the total load current. this function is referred to as auto phase, and it provides user the maximal flexibility in the platform design to maxi mize voltage regulators eff iciency and the processor performance as well. for the 3-phase vcore regulator, there are three load current states (lcs) to set. the switching frequency, offset voltage, operating phase number and loadline in each lcs can be programmed independently. for the 2-phase vccgt regulator, there are two load current states (lcs) to set. the switching frequency, offset voltage and operating phase number in each lcs can also be programmed independently. vm0, vm1 ( svm0 for vccgt ): define the thresholds for three load current states (lcs0, lcs1 and lcs2) for vcore. the vcore controller converts isum pin voltage v isum to a digital content, which represents the total output current. the vm0 and vm1 setting is defined as the ratio of isum pin voltage to 1.5v (1.5v denotes when vcore output current reaches its iccmax). it takes 1.5v as the full scale, and 6- bits means that there are 64 steps for user to choose from. each load current state register has 6-bits to set the level of output current that the load current state is entered. the controller compares the vm0 and vm1 content and 1.5v (i out_iccmax , refer to the section of iccmax alert and total output over current protection ) to determine which load current state should be entered and executes the corresponding operating parameter settings (frequency, offset and operating phase number). lcs0: v isum > vm0, highest load current state. lcs1: vm0 > v isum > vm1 lcs2: vm1 > v isum , lowest load current state. vm0_hys, vm1_hys (svm0_hys for vccgt) : define the hyteresis of vm0 and vm1. the hysteresis is also defined as the ratio of isum pin voltage to 1.5v (1.5v denotes when vcore output current reaches its iccmax). vofs0, vofs1, vofs2 (svofs0, svofs1 for vccgt) : define the offset voltage in each load current state. 8-bits content setting with 5mv/step. iicf0, iicf1, iicf2 (siicf0, siicf1 for vccgt): define the switching frequency in each load current state. the switching frequency is defined as the ratio to current setting per r tonset and vin. iicp0, iicp1, iicp2 (siicp0, siicp1 for vccgt): define the operating phase number in each load current state. the operating phase number can be full-phase to single- phase. iicll0, iicll1, iicll2 (siicll0, siicll1 for vccgt): define the loadline value in each load current state. the loadline adjustment is defined as the ratio to current droop setting. rcomp1, rcomp2 (srcomp1, srcomp2 for vccgt): define the compensation resistor value. the compensation resistor value for the regulator operating in single-phase operation and multi-phase operation can be adjusted separately. gcomp (sgcomp for vccgt): for ota transconductance setting for voltage control loop. it is defined as the ratio to the default value of 2020ua/v. imonovr/oc/uv/ov (simonovr/soc/suv/sov for vccgt): imonovr controls the overwrite for svid register 0x15h. oc/uv/ov is used for the threshold adjustment of per-phase ocp, uvp and ovp, respectively. total ocp (stotal ocp for vccgt): used to adjust the total output current ocp threshold.lchvid (slchvid for vccgt): this register stores the 8-bits vid code. when latch vid function is enabled, controller will ignore the setvid command from cpu and move output voltage to the targeted value. iout (siout for vccgt): this register reports real iout value (00h when v imon = 0.6v, ffh when v imon = 2.1v). vout (svout for vccgt): this register reports the output voltage that is converted by the internal adc with 10mv/ lsb. the data source can be selected (in specific register) from either the a/d result of actual output voltage or a copy of svid register 0x21h (vid_setting). upi confidential UP9508 22 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 10x 0e roc v] 2:7[0m vw / rh 00 0levelegatlovmusilanretnites )etatstnerructsehgih(0scl>=0level> musiv otegatlovnip musiotoitarehtsadenifedsignittes0mv .)xamccistisehcaertnerructuptuoerocvnehw(v5.1 xamccix)46/]2:7[tib(=0mv eract'nod]0:1[tib 20x 0e roc v] 2:7[1m vw / rh 00 1levelegatlovmusilanretnites 1scl>=1level> musiv>0level 2scl>=1level< musiv otegatlovnip musiotoitarehtsadenifedsignittes1mv .)xamccistisehcaertnerructuptuoerocvnehw(v5.1 xamccix)46/]2:7[tib(=1mv eract'nod]0:1[tib 30x 0t gcc v] 2:7[2mv sw / rh 00 0levelegatlovamusilanretnites )etatstnerructsehgih(0scls>=0level>amusiv )etatstnerructsewol(1scls>=0level UP9508 24 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed c0x 0e roc v] 4:7[2fci iw / rh 88 =tluafed,2sclerocvfoycneuqerfgnitarepo:]4:7[2fcii %001 ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%051=0101,%521=1001;)tluafed(%001=0001 ;%522=1011;%002=0011;%571=1101 %572=1111;%052=0111 eract'nod:]0:3[tib d0x 0e rocv ]4:7[0llcii ]0:3[1llcii w/ rh 88 ,0sclerocvfognittesenildaol:]4:7[0llcii %001=tluafed )pets/%5.21,%5.781=xam,%0=nim( ,1sclerocvfognittesenildaol:]0:3[1llcii %001=tluafed )pets/%5.21,%5.781=xam,%0=nim( e0x 0e roc v] 4:7[2llci iw / rh 88 ,2sclerocvfognittesenildaol:]4:7[2llcii %001=tluafed )pets/%5.21,%5.781=xam,%0=nim( eract'nod:]0:3[tib f0x 0e rocv ]7[ne_bc ]4:6[niagi_1hp ]0:2[niagi_2hp w/ rh 44 ecnalabtnerrucerocvfolortnocffo/no:]7[ne_bc ,no =tluafed,noitcnuf )delbanesinoitcnufecnalabtnerruc(no =0 )delbasidsinoitcnufecnalabtnerruc(ffo =1 niagecnalabtnerruc1esahperocv:]4:6[niagi_1hp %001=tluafed,tnemtsujda ;%5.78=110;%57=010;%5.26=100;%05=000 ;%521=011;%5.211=101;)tluafed(%001=001 %5.731=111 eract'nod:]3[tib niagecnalabtnerruc2esahperocv:]0:2[niagi_2hp %001=tluafed,tnemtsujda ;%5.78=110;%57=010;%5.26=100;%05=000 ;%521=011;%5.211=101;)tluafed(%001=001 %5.731=111 upi confidential UP9508 25 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 01x 0e roc v] 4:6[niagi_3h pw / rh 44 eract'nod:]7[tib niagecnalabtnerruc3esahperocv:]4:6[niagi_3hp %001=tluafed,tnemtsujda ;%5.78=110;%57=010;%5.26=100;%05=000 ;%521=011;%5.211=101;)tluafed(%001=001 %5.731=111 eract'nod:]0:3[tib 11x 0e rocv ]4:6[soi_1hp ]0:2[soi_2hp w/ rh 00 eract'nod:]7[tib tesffoecnalabtnerruc1esahperocv:]4:6[soi_1hp au0=tluafed,tnemtsujda ;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101;au8=001 eract'nod:]3[tib tesffoecnalabtnerruc2esahperocv:]0:2[soi_2hp au0=tluafed,tnemtsujda ;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101;au8=001 21x 0e rocv ]4:6[soi_3hp ]0:2[soi_4hp w/ rh 00 eract'nod:]7[tib tesffoecnalabtnerruc3esahperocv:]4:6[soi_3hp au0=tluafed,tnemtsujda ;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101;au8=001 eract'nod:]0:3[tib 31x 0e rocv ]4:7[1pmocr ]0:3[2pmocr w/ rh 37 gnittesrotsiserpmocrerocv noitasnepmocnoitarepoesahp-elgnis:]4:7[1pmocr ,gnittesrotsiser ,k04=xam,k5.2=nim,)]4:7[tib+1(xk5.2=1pmocr k02=tluafed noitasnepmocnoitarepoesahp-itlum:]0:3[2pmocr ,gnittesrotsiser ,k04=xam,k5.2=nim,)]0:3[tib+1(xk5.2=2pmocr k01=tluafed functional description upi confidential UP9508 26 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 41x0 ,erocv tgccv ]4:7[pmocgs ]0:3[pmocg w/ rh 00 noitceleseulavmg ato tgccv:]7[pmocgs ]4:6[pmocgs,)v/au0202(eulavtluafedesuotecrof=0 ;)tluafed(derongieblliwgnittes ]4:6[pmocgsniteseulavehtesu=1 ,gnittesmg ecnatcudnocsnarttgccv:]4:6[pmocgs oitarehtsadenifed,rebmunesahpgnitarepollaotdeilppa )v/au0202=(tluafedot ;x13.1=010;x71.1=100;)tluafed(x1=000 ;x6.0=011;x18.0=101;x96.1=001;x54.1=110 x33.0=111 noitceleseulavmg ato erocv:]3[pmocg ]0:2[pmocg,)v/au0202(eulavtluafedesuotecrof=0 ;)tluafed(derongieblliwgnittes ]0:2[pmocgniteseulavehtesu=1 deilppa,gnittesmg ecnatcudnocsnarterocv:]0:2[pmocg otoitarehtsadenifed,rebmunesahpgnitarepollaot )v/au0202=(tluafed ;x13.1=010;x71.1=100;)tluafed(x1=000 ;x6.0=011;x18.0=101;x96.1=001;x54.1=110 x33.0=111 51x 0e roc v] 0:7[divhc lw / rh b a. )v001.1(hba=tluafed.retsigerdivhctalerocv 61x 0e roc v] 0:7[tuo io r- -. gnitropertuoilaererocv 71x 0e roc v] 0:7[tuo vo r- - .gnidaeregatlovtuptuoerocv tluserd/a morfebnac]0:7[tuovnieulavgnidaeregatlov retsigerdivsfoypocaebnacro,egatlovtuptuolautcafo atadehtsenimreted]6[2csim.tnetnoc)gnittes_div(h13x0 ]0:7[tuovfoecruos 81x 0e roc v] 0:5[dni_tcetor po rh 00 sinoitcetorphcihwgnitacidni,rotacidninoitcetorperoc v dereggirt eract'nod:]6:7[tib rotacidnipco:]5[dni_tcetorp evitca=1;evitcaton=0 rotacidnipco esahprep:]4[dni_tcetorp evitca=1;evitcaton=0 rotacidnipvo:]3[dni_tcetorp evitca=1;evitcaton=0 rotacidnipvu:]2[dni_tcetorp evitca=1;evitcaton=0 ]4[dni_tcetorpfirotacidnipco esahprep:]0:1[dni_tcetorp 1= ;00=4esahp;11=3esahp;01=2esahp;10=1esahp nehwylnodilavsi]0:1[dni_tcetorpfoeulavtroper 1=]4[dni_tcetorp upi confidential UP9508 27 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 91x 0e roc v] 4:7[pcolato tw / rh 08 gnittespcotnerructuptuolatoterocv:]4:7[pcolatot ,egatlovnip musiv5.1otoitarehtsadenifedsignittes %031=tluafed ;%08=1100;%07=0100;%06=1000;%05=0000 ;%021=1110;%011=0110;%001=1010;%09=0010 1101;%051=0101;%041=1001;)tluafed(%031=0001 ;%061= %002=1111;%091=0111;%081=1011;%071=0011 eract'nod:]0:3[tib a1x 0e rocv ]6:7[rvonomi ]4:5[co ]2:3[vu ]0:1[vo w/ rh 04 ,erocvrof)nomi(h51x0divsetirwrevo:]7[rvonomi elbasid=tluafed elbasid=0;elbane=1 rofoitar)nomi(h51x0divsetirwrevo:]6[rvonomi 2/1=tluafed,erocv 4/1=0;)tluafed(2/1=1 au001=tluafed,dlohserhtpco esahpreperocv:]4:5[co ;au021=10;)tluafed(au001=00 au061=11;au041=01 vm004=tluafed,gnittesdlohserhtpvuerocv:]2:3[vu ;vm005=10;)tluafed(vm004=00 vm007=11;vm006=01 vm004=tluafed,gnittesdlohserhtpvo erocv:]0:1[vo ;vm005=10;)tluafed(vm004=00 vm007=11;vm006=01 b1x 0d erah s] 2:7[yaled_pc ow / rh 86 gnittesemasehterahstgccvdnaerocvhtob su02=tluafed,emityaledpcolatot:]5:7[yaled_pco ;)tluafed(su02=110;su51=010;su01=100;su5=000 su04=111;su53=011;su03=101;su52=001 s u6=tluafed,emityaledpco esahprep:]2:4[yaled_pco ;su8=110;)tluafed(su6=010;su4=100;su2=000 su61=111;su41=011;su21=101;su01=001 eract'nod:]0:1[tib c1x0 ,erocv tgccv ]4:6[rs_rv ]0:2[rs_rvs w/ rh 00 eract'nod:]7[tib tluafed.noitcelesetarwelstsafdiv-derocv:]4:6[rs_rv .su/vm21= ; su/vm81=010;su/vm51=100;)tluafed(su/vm21=000 ;su/vm72=101;su/vm42=001;su/vm12=110 su/vm33=111;su/vm03=011 dnam mocdivtesswollofgnimitnoitressa#trela:eton eract'nod:]3[tib .noitcelesetarwelstsafdiv-dtgccv:]0:2[rs_rvs .su/vm21=tluafed ; su/vm81=010;su/vm51=100;)tluafed(su/vm21=000 ;su/vm72=101;su/vm42=001;su/vm12=110 su/vm33=111;su/vm03=011 dnam mocdivtesswollofgnimitnoitressa#trela:eton upi confidential UP9508 28 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed d1x 0e roc v] 0:7[1csi mw / rh f0 erocvrofsiretsigersiht =tesffo mumixam wolla(noitcnuftesffolluf:]7[1csim elbasid=tluafed,)v572.1+ )v536.0-/+nihtiwdetimilsitesffo,tluafed(elbasid=0 )v555.2otpudetimilsituovllarevotahteton(elbane=1 lortnocegatlovcadv:]6[1csim dnam mocdivs wollofcadvh13x0.ger divs=0 )tluafed( dnam mocdivserongicadvh13x0.ger divs=1 lortnocetatsrewop:]5[1csim dnam mocdivs wollofetatsr w ph23x0.ger divs=0 )tluafed( dnam mocdivserongietatsr w ph23x0.ger divs=1 lortnoctesffo:]4[1csim dnam mocdivs wolloftesffoh33x0.ger divs=0 )tluafed( dnam mocdivserongitesffoh33x0.ger divs=1 lortnocpcotuptuolatot:]3[1csim noitcnufpcotuptuolatotelbasid=0 )tluafed(noitcnufpcotuptuolatotelbane=1 lortnocpco esahp-rep:]2[1csim noitcnufpco esahp-repelbasid=0 )tluafed(noitcnufpco esahp-repelbane=1 lortnocpvo:]1[1csim noitcnufpvo elbasid=0 )tluafed(noitcnufpvo elbane=1 lortnocpvu:]0[1csim noitcnufpvuelbasid=0 )tluafed(noitcnufpvuelbane=1 upi confidential UP9508 29 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed e1x 0e roc v] 0:7[2csi mw / rh c0 erocvrofsiretsigersiht ycneuqerfgnihctiwsrofmurtcepsdaerps:]7[2csim )tluafed(murtcepsdaerpselbasid=0 murtcepsdaerpselbane=1 .gersubmsfoecruosatadehtfonoitceles:]6[2csim )]0:7[tuov(gnidaeregatlovtuptuoerocvh71x0 )gnittes_div(h13x0retsigerdivsfoedocdiv=0 )tluafed( tluserd/atuovlautca=1 lortnocelbanetesffoegatlovtuptuo:]5[2csim .gersubmsnignittestesffo(tesffoelbasid=0 )tluafed()h90x0~h70x0 tesffo elbane=1 lortnocelbanenoitcnufesahpotua:]4[2csim )tluafed(esahpotuaelbasid=0 fisp_divs wollofro,1=]5[d1x0fi0pciiwollof:eton( )0=]5[d1x0 esahpotuaelbane=1 esahp-elgnisninehwlortnocelbane mcd:]3[2csim noitarepo )mccnisyawla(mcdelbasid=0 ybdetcelesrehtrufsimsu/msp,mcdelbane=1 )tluafed(]1[2csim lortnocelbaneenildaol:]2[2csim )0=ll(enildaolelbasid=0 )tluafed(enildaolelbane=1 =]3[2csim nehwylnodilav,noitcelesmsp/msu:]1[2csim )mcdelbane(1 )tluafed(msp=0 msu=1 tonod.esopruptsetlanretnirofdevreser:]0[2csim tibsihtegnahc f1x 0d erah s] 5:7[d ww / rh 00 noitcnufgodhctaw:]7[d w )tluafed(elbasid=0;elbane=1 sutatsgodhctaw:]6[d w doirepgodhctawnihtiwderruccosnoitcasnartsubms=0 godhctawsdeecxenoitcasnartsubmsneewtebemit=1 doirep submsonfi,delbanesinoitcnufgodhctawehtnehw rosm008(doirepdetcelesanihtiwruccosnoitcasnart . eulavtluafedottesereblliwstnetnocretsigerlla,)sm006 1 .retsigersihtmorfdaersubmsybderaelcsitibsiht doirepgodhctaw:]5[d w sm0061=1;)tluafed(sm008=0 eract'nod:]0:4[tib upi confidential UP9508 30 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 22x0 ,erocv derahs ]6[netluafsys ]5[nepto ]0:4[tohrv_pmet w/ rh 50 erocvrofsiretsigersiht :]6[netluafsys .lortnocelbasid/elbanenoitcnuftluafsys elbane=1;)tluafed(elbasid=0 :]5[nepto e lbasid/elbanenoitcnuf)nwodtuhslamreht(ptorellortnoc .lortnoc elbane=1;)tluafed(elbasid=0 elbasid/elbanenoitcnuf#tohrv:]4[tohrv_pmet lortnoc elbasid=1;)tluafed(elbane=0 .bslybtfeltfihsh21x0.ger divs:]0:3[tohrv_pmet 19 morfsiegnargnitteserutarepmet o 121otc o ,c 3 o 601=tluafed,bsl/c o ,c ;bsl2tfihs=0100;bsl1tfihs=1000;tfihson=0000 ;bsl4tfihs=0010;bsl3tfihs=1100 ;bsl6tfihs=0110;)tluafed(bsl5tfihs=1010 ;bsl8tfihs=0001;bsl7tfihs=1110 bsl01tfihs=0101;bsl9tfihs=1001 32x 0e roc v] 0:7[b tw / rh 44 )0sp(noitarepoesahp-itlum nibterocv elbane=1;)tluafed(elbasid=0:]7[bt :]4:6[bt ;vm03=110;vm02=010;vm01=100;vm0=000 ;vm06=011;vm05=101;)tluafed(vm04=001 vm07=111 )3/2/1sp(noitarepoesahp-elgnisnibterocv elbane=1;)tluafed(elbasid=0:]3[bt :]0:2[bt ;vm03=110;vm02=010;vm01=100;vm0=000 ;vm06=011;vm05=101;)tluafed(vm04=001 vm07=111 42x 0e roc v] 0:7[gir tw / rh 00 )0sp(noitarepoesahp-itlum nitimilgirtv bterocv elbane=1;)tluafed(elbasid=0:]7[girt :]4:6[girt ;v53.1=010;v03.1=100;)tluafed(v52.1=000 ;v06.1=011;v05.1=101;v54.1=001;v04.1=110 v07.1=111 ) 3/2/1sp(noitarepoesahp-elgnisnitimilgirtv bterocv elbane=1;)tluafed(elbasid=0:]3[girt :]0:2[girt ;v53.1=010;v03.1=100;)tluafed(v52.1=000 ;v06.1=011;v05.1=101;v54.1=001;v04.1=110 v07.1=111 upi confidential UP9508 31 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 52x 0e rocv ]6:7[ffotucbt ]0:5[notbt w/ rh 00 lortnocycneuqerfffo-tucbterocv:]6:7[ffotucbt =11;zhk002=01;zhk001=10;)tluafed(zhk001=00 zhk003 esahp-itlum ninehwemitno bterocv:]3:5[notbt )0sp(noitarepo =110;sn004=010;sn003=100;)tluafed(sn002=000 =111;sn008=011;sn007=101;sn006=001;sn005 sn009 esahp-elgnisninehwemitno bterocv:]0:2[notbt )3/2/1sp(noitarepo =110;sn004=010;sn003=100;)tluafed(sn002=000 =111;sn008=011;sn007=101;sn006=001;sn005 sn009 bt.v21=nivnodesabsieulavemitno btevobaeht( )nivotlanoitroporpylesrevnisiemitno 62x 0e roc v] 0:7[rtuo iw / rh 00 gnim mirtgnitropertuoierocv mcdesahp-1rofsi]4:7[rtuoi evitagen=1,tesffoevitisop=0,tibngissi]7[rtuoi tesffo tnemtsujdafotnuomasi]4:6[rtuoi =1000 1+ =1110, 7+ )mumixam evitisop( =1001 7- =1111, 1- =0001, 8- )mumixam evitagen( mccesahp-1rofsi]0:3[rtuoi evitagen=1,tesffoevitisop=0,tibngissi]3[rtuoi tesffo tnemtsujdafotnuomasi]0:2[rtuoi =1000 1+ =1110, 7+ )mumixam evitisop( =1001 7- =1111, 1- =0001, 8- )mumixam evitagen( 72x 0e rocv ]4:7[bti ]0:3[ipd w/ rh c5 erocvrofsiretsigersiht tibgnitsetlanretni:]4:7[bti vm05=tluafed,]4:7[btixvm01 wolebsituovnehw divdgniruddexifemit-no:]0:3[ipd ]0:2[ipdybtesegatlov ,lortnocelbasid/elbanenoitcnufemit-nodexif:]3[ipd )tluafed(elbane=1;elbasid=0 gnittesdlohserhtegatlov:]0:2[ipd ;vm084=010;vm023=100;vm061=000 ;vm069=101;)tluafed(vm008=001;vm046=110 vm0821=111;vm0211=011 upi confidential UP9508 32 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 82x 0e roc v] 0:7[pma rw / rh 88 gnittesepolspmarlanretnierocv %001=tluafed,noitarepoesahp-itlumrofsi]4:7[pmar ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%011=0101;%501=1001;)tluafed(%001=0001 ;%521=1011;%021=0011;%511=1101 %531=1111;%031=0111 -elgnisninehwderongieblliwgnittes]4:7[pmartahteton noitarepoesahp %001=tluafed,noitarepoesahp-elgnisrofsi]0:3[pmar ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%011=0101;%501=1001;)tluafed(%001=0001 ;%521=1011;%021=0011;%511=1101 %531=1111;%031=0111 92x 0t gcc v] 0:7[0sfov sw / rh 0 0) pets/vm5(.0sclstgccvfotesffoegatlov a2x 0t gccv ]4:7[0fciis ]0:3[1fciis w/ rh 88 tluafed,0sclstgccvfoycneuqerfgnitarepo:]4:7[0fciis %001= tluafed,1sclstgccvfoycneuqerfgnitarepo:]0:3[1fciis .%001= ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%051=0101,%521=1001;)tluafed(%001=0001 ;%522=1011;%002=0011;%571=1101 %572=1111;%052=0111 b2x 0t gccv ]4:7[0llciis ]0:3[1llciis w/ rh 88 =tluafed,0sclstgccvfognittesenildaol:]4:7[0llciis %001 )pets/% 5.21,%5.781xam,%0nim,%001tluafed( =tluafed,1sclstgccvfognittesenildaol:]0:3[1llciis %001 )pets/% 5.21,%5.781xam,%0nim,%001tluafed( c2x 0t gccv ]7[ne_bcs ]4:6[niagi_1hps ]0:2[niagi_2hps w/ rh 44 ecnalabtnerructgccvfolortnocffo/no:]7[ne_bcs no =tluafed,noitcnuf )delbanesinoitcnufecnalabtnerruc(no =0 )delbasidsinoitcnufecnalabtnerruc(ffo =1 niagecnalabtnerruc1esahptgccv:]4:6[niagi_1hps %001=tluafed,tnemtsujda ;%5.78=110;%57=010;%5.26=100;%05=000 ;%521=011;%5.211=101;)tluafed(%001=001 %5.731=111 eract'nod:]3[tib niagecnalabtnerruc2esahptgccv:]0:2[niagi_2hps %001=tluafed,tnemtsujda ;%5.78=110;%57=010;%5.26=100;%05=000 ;%521=011;%5.211=101;)tluafed(%001=001 %5.731=111 upi confidential UP9508 33 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed d2x 0t gccv ]4:6[soi_1hps ]0:2[soi_2hps w/ rh 00 eract'nod:]7[tib tesffoecnalabtnerruc1esahptgccv:]4:6[soi_1hps au0=tluafed,tnemtsujda ;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101;au8=001 eract'nod:]3[tib tesffoecnalabtnerruc2esahptgccv:]0:2[soi_2hps .au0=tluafed,tnemtsujda ;au6=110;au4=010;au2=100;)tluafed(au0=000 au41=111;au21=011;au01=101;au8=001 e2x 0t gccv ]4:7[1pmocrs ]0:3[2pmocrs w/ rh 37 gnittesrotsiserpmocrtgccv noitasnepmocnoitarepoesahp-elgnis:]4:7[1pmocrs ,gnittesrotsiser =xam,k5.2=nim,)]4:7[tib+1(xk5.2=1pmocrs k02=tluafed,k04 noitasnepmocnoitarepoesahp-itlum:]0:3[2pmocrs ,gnittesrotsiser =xam,k5.2=nim,)]0:3[tib+1(xk5.2=2pmocrs k01=tluafed,k04 f2x 0t gcc v] 0:7[pmar sw / rh 88 gnittesepolspmarlanretnitgccv noitarepoesahp-itlumrofsi]4:7[pmars ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%011=0101;%501=1001;)tluafed(%001=0001 ;%521=1011;%021=0011;%511=1101 %531=1111;%031=0111 esahp-elgnisninehwderongieblliwgnittes]4:7[pmars noitarepo noitarepoesahp-elgnisrofsi]0:3[pmars ;%57=1100;%07=0100;%56=1000;%06=0000 ;%59=1110;%09=0110;%58=1010;%08=0010 ;%011=0101;%501=1001;)tluafed(%001=0001 ;%521=1011;%021=0011;%511=1101 %531=1111;%031=0111 03x 0t gcc v] 0:7[divhcl sw / rh b a. )v001.1(hba=tluafed.retsigerdivhctaltgccv 13x 0t gcc v] 0:7[tuoi so r- -. gnitropertuoilaertgccv 23x 0t gcc v] 0:7[tuov so r- - .gnidaeregatlovtuptuotgccv d/a morfebnac]0:7[tuovsnieulavgnidaeregatlov divsfoypocaebnacro,egatlovtuptuolautcafotluser ]6[2csims.tnetnoc)gnittes_div(h13x0retsiger .]0:7[tuovsfoecruosatadehtsenimreted upi confidential UP9508 34 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 33x 0t gcc v] 0:5[dni_cetorp so rh 00 sinoitcetorphcihwgnitacidni,rotacidninoitcetorptgcc v .dereggirt eract'nod:]6:7[tib rotacidnipco:]5[dni_cetorps evitca=1,evitcaton=0 rotacidnipco esahprep:]4[dni_cetorps evitca=1,evitcaton=0 rotacidnipvo:]3[dni_cetorps evitca=1,evitcaton=0 rotacidnipvu:]2[dni_cetorps firotacidnipco esahprep:]0:1[dni_cetorps 1=]4[dni_cetorps foeulavtroper;01=2esahp;10=1esahp .1=]4[dni_cetorpsnehwylnodilavsi]0:1[dni_cetorps 43x 0t gcc v] 4:7[pcolatot sw / rh 08 gnittespcotnerructuptuolatottgccv:]4:7[pcolatots , egatlovnipamusiv5.1otoitarehtsadenifedsignittes %031=tluafed ;%08=1100;%07=0100;%06=1000;%05=0000 ; %021=1110;%011=0110;%001=1010;%09=0010 ;%051=0101;%041=1001;)tluafed(%031=0001 ;%081=1011;%071=0011;%061=1101 %002=1111;%091=0111 eract'nod:]0:3[tib 53x 0t gccv ]6:7[rvonomis ]4:5[cos ]2:3[vus ]0:1[vos w/ rh 04 ,tgccvrof)nomi(h51x0divsetirwrevo:]7[rvonomis elbasid=tluafed )tluafed(elbasid=0;elbane=1 rofoitar)nomi(h51x0divsetirwrevo:]6[rvonomis 2/1=tluafed,tgccv 4/1=0;)tluafed(2/1=1 =tluafed,dlohserhtpco esahpreptgccv:]4:5[cos au001 ;au021=10;)tluafed(au001=00 au061=11;au041=01 vm004=tluafed,gnittesdlohserhtpvutgccv:]2:3[vus ;vm005=10;)tluafed(vm004=00 vm007=11;vm006=01 =tluafed,gnittesdlohserhtpvo tgccv:]0:1[vos vm004 ;vm005=10;)tluafed(vm004=00 vm007=11;vm006=01 upi confidential UP9508 35 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 63x 0t gcc v] 0:7[1csim sw / rh f0 tgccvrofsiretsigersiht =tesffo mumixam wolla(noitcnuftesffolluf:]7[1csims elbasid=tluafed,)v572.1+ )v536.0-/+nihtiwdetimilsitesffo,tluafed(elbasid=0 otpudetimilsituovllarevotahteton(elbane=1 )v555.2 lortnocegatlovcadv:]6[1csims dnam mocdivs wollofcadvh13x0.ger divs=0 )tluafed( dnam mocdivserongicadvh13x0.ger divs=1 lortnocetatsrewop:]5[1csims dnam mocdivs wollofetatsr w ph23x0.ger divs=0 )tluafed( dnam mocdivserongietatsr w ph23x0.ger divs=1 lortnoctesffo:]4[1csims dnam mocdivs wolloftesffoh33x0.ger divs=0 )tluafed( dnam mocdivserongitesffoh33x0.ger divs=1 lortnocpcotuptuolatot:]3[1csims noitcnufpcotuptuolatotelbasid=0 )tluafed(noitcnufpcotuptuolatotelbane=1 lortnocpco esahp-rep:]2[1csims noitcnufpco esahp-repelbasid=0 )tluafed(noitcnufpco esahp-repelbane=1 lortnocpvo:]1[1csims noitcnufpvo elbasid=0 )tluafed(noitcnufpvo elbane=1 lortnocpvu:]0[1csims noitcnufpvuelbasid=0 )tluafed(noitcnufpvuelbane=1 upi confidential UP9508 36 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 73x 0t gcc v] 0:7[2csim sw / rh c0 tgccvrofsiretsigersiht ycneuqerfgnihctiwsrofmurtcepsdaerps:]7[2csims )tluafed(murtcepsdaerpselbasid=0 murtcepsdaerpselbane=1 .gersubmsfoecruosatadehtfonoitceles:]6[2csims )]0:7[tuovs(gnidaeregatlovtuptuotgccvh23x0 )gnittes_div(h13x0retsigerdivsfoedocdiv=0 )tluafed( tluserd/atuovlautca=1 lortnocelbanetesffoegatlovtuptuo:]5[2csims ,h92x0.gersubmsnignittestesffo(tesffoelbasid=0 )tluafed()a0x0 tesffo elbane=1 lortnocelbanenoitcnufesahpotua:]4[2csims )tluafed(esahpotuaelbasid=0 fisp_divs wollofro,1=]5[63x0fi0pciis wollof:eton 0=]5[63x0 esahpotuaelbane=1 esahp-elgnisninehwlortnocelbane mcd:]3[2csims noitarepo )mccnisyawla(mcdelbasid=0 ybdetcelesrehtrufsimsu/msp,mcdelbane=1 )tluafed(]1[2csims lortnocelbaneenildaol:]2[2csims )0=ll(enildaolelbasid=0 )tluafed(enildaolelbane=1 nehwylnodilav,noitcelesmsp/msu:]1[2csims )mcdelbane(1=]3[2csims )tluafed(msp=0 msu=1 od.esopruptsetlanretnirofdevreser:]0[2csims .tibsihtegnahcton upi confidential UP9508 37 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed 83x 0t gcc v] 0:4[tohrv_pmet sw / rh 50 tgccvrofsiretsigersiht eract'nod:]5:7[tib elbasid/elbanenoitcnuf#tohrv:]4[tohrv_pmets lortnoc elbasid=1;)tluafed(elbane=0 . bslybtfeltfihsh21x0.ger divs:]0:3[tohrv_pmets 19 morfsiegnargnitteserutarepmet o 121otc o ,c 3 o 601=tluafed,bsl/c o c ;bsl2tfihs=0100;bsl1tfihs=1000;tfihson=0000 ;bsl4tfihs=0010;bsl3tfihs=1100 ;bsl6tfihs=0110;)tluafed(bsl5tfihs=1010 ;bsl8tfihs=0001;bsl7tfihs=1110 bsl01tfihs=0101;bsl9tfihs=1001 93x 0t gcc v] 0:7[bt sw / rh 44 )0sp(noitarepoesahp-itlum nibttgccv elbane=1;)tluafed(elbasid=0:]7[bts :]4:6[bts ;vm03=110;vm02=010;vm01=100;vm0=000 ;vm06=011;vm05=101;)tluafed(vm04=001 vm07=111 )3/2/1sp(noitarepoesahp-elgnisnibttgccv elbane=1;)tluafed(elbasid=0:]3[bts :]0:2[bts ;vm03=110;vm02=010;vm01=100;vm0=000 ;vm06=011;vm05=101;)tluafed(vm04=001 vm07=111 a3x 0t gcc v] 0:7[girt sw / rh 00 )0sp(noitarepoesahp-itlum nitimilgirtv bttgccv elbane=1;)tluafed(elbasid=0:]7[girts :]4:6[girts ;v53.1=010;v03.1=100;)tluafed(v52.1=000 ;v04.1=110 v07.1=111;v06.1=011;v05.1=101;v54.1=001 ) 3/2/1sp(noitarepoesahp-elgnisnitimilgirtv bttgccv elbane=1;)tluafed(elbasid=0:]3[girts :]0:2[girts ;v53.1=010;v03.1=100;)tluafed(v52.1=000 ;v06.1=011;v05.1=101;v54.1=001;v04.1=110 v07.1=111 upi confidential UP9508 38 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com table 8. smbus configuration register (cont.) functional description ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed b3x 0t gccv ]6:7[ffotucbts ]0:5[notbts w/ rh 00 lortnocycneuqerfffo-tucbttgccv:]6:7[ffotucbts ;zhk002=01;zhk001=10;)tluafed(zhk001=00 zhk003=11 esahp-itlum ninehwemitno bttgccv:]3:5[notbts )0sp(noitarepo ;sn004=010;sn003=100;)tluafed(sn002=000 ;sn008=011;sn007=101;sn006=001;sn005=110 sn009=111 esahp-elgnisninehwemitno bttgccv:]0:2[notbts )3/2/1sp(noitarepo ;sn004=010;sn003=100;)tluafed(sn002=000 ;sn008=011;sn007=101;sn006=001;sn005=110 sn009=111 bt.v21=nivnodesabsieulavemitno btevobaeht( )nivotlanoitroporpylesrevnisiemitno c3x 0t gcc v] 0:7[rtuoi sw / rh 00 gnim mirtgnitropertuoitgccv mcdesahp-1rofsi]4:7[rtuois evitagen=1,tesffoevitisop=0,tibngissi]7[rtuois tesffo tnemtsujdafotnuomasi]4:6[rtuois =1000 1+ =1110, 7+ )mumixam evitisop( =1001 7- =1111, 1- =0001, 8- )mumixam evitagen( mccesahp-1rofsi]0:3[rtuois evitagen=1,tesffoevitisop=0,tibngissi]3[rtuois tesffo tnemtsujdafotnuomasi]0:2[rtuois =1000 1+ =1110, 7+ )mumixam evitisop( =1001 7- =1111, 1- =0001, 8- )mumixam evitagen( d3x 0t gccv ]4:7[btis ]0:3[ipds w/ rh c5 tgccvrofsiretsigersiht tibgnitsetlanretni:]4:7[btis vm05=tluafed,]4:7[btisxvm01 wolebsituovnehw divdgniruddexifemit-no:]0:3[ipds ]0:2[ipdsybtesegatlov ,lortnocelbasid/elbanenoitcnufemit-nodexif:]3[ipds )tluafed(elbane=1;elbasid=0 gnittesdlohserhtegatlov:]0:2[ipds ;vm084=010;vm023=100;vm061=000 ;)tluafed(vm008=001;vm046=110 vm0821=111;vm0211=011;vm069=101 e3x 0e roc v] 0:7[toob vw / rh 00 gnittesegatlovtoobverocv ot)h10(v052.0 morfsiegnargnittes,tnetnoctib-8 .)hff(v025.1 erawdrahswollofegatlovtoobvehtsnaemti,h00=tluafed .gnittes ecivedsubmstluafedesufiylnodilavsinoitcnufsiht:eton neerofebretsigersihtotatadetirwdna,h88x0sserdda .hgihog upi confidential UP9508 39 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com functional description table 8. smbus configuration register (cont.) ger .rdda sucof liar emanretsige rs secc at luafe dn oitpircsed f3x 0t gcc v] 0:7[toobv sw / rh 00 gnittesegatlovtoobvtgccv ot)h10(v052.0 morfsiegnargnittes,tnetnoctib-8 .)hff(v025.1 swollofegatlovtoobvehtsnaemti,h00=tluafed .gnitteserawdrah submstluafedesufiylnodilavsinoitcnufsiht:eton retsigersihtotatadetirwdna,h88x0sserddaecived .hgihogneerofeb 04x 0e roc v] 0:7[m to rh 00 .gnidaereulavrotinomlamrehtsubmserocv rofnoisrevnocd/afoeulavehtserotsretsigersiht .nipesnest 051(h69x0sieulavdetropermumixam o .)c 14x 0t gcc v] 0:7[mt so rh 00 .gnidaereulavrotinomlamrehtsubmstgccv rofnoisrevnocd/afoeulavehtserotsretsigersiht .nipaesnest 051(h69x0sieulavdetropermumixam o .)c 84x 0d erah sd inoisre vo rh 10 2bx 0d erah sd ipih co rh a2 upi confidential UP9508 40 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com (note 1) supply input voltage vcc to gnd ---------------------------------------------------------------------------------------------- ---- -0.3v to +6v vinsen ----------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +30v other pins ------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v storage temperature ra nge ----------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------- --------------------------- 150 o c lead temperature (soldering, 10 sec) ----------------------------------------------------------------------------------------- ------------------- 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------------------------------ ----------------- 200v package thermal resistance (note 3) vqfn6x6 - 52l ja ---------------------------------------------------------------------------------------------------------------------- 35 o c/w vqfn6x6 - 52l jc ----------------------------------------------------------------------------------------------------------------------- 3 o c/w power dissipation, p d @ t a = 25 o c vqfn6x6 - 52l ------------------------------------------------------------------------------------------------------------------------------------ 2.86w (note 4) operating junction temperature range ------------------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature range ------------------------------------------------------------------------------------------- -40 o c to +85 o c supply input v oltage vcc ----------------------------------------------------------------------------------------------------- ---------- 4.5v to 5.5v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. upi confidential UP9508 41 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus ccv dlohserhtrop cc vr op ccv gnisircc v0 . 43 . 45 . 4v siseretsyh rop cc vs yh ropccv - -3 . 0- -v tnerrucylppu si ccv ,v0= divtgccvdnaerocv,v5=ne gnihctiwson m w p - -7- -a m tnerrucnwodtuh si ndhs_ccv v0=n e- -0 5- -a u 4spnitnerrucylppu si 4sp_ccv etats4sp,v5=n e- -0 5 1- -a u reifilpmarorre egatlovtesff ov )ae(so 1 -- -1v m ecnatcudnoc-snar tm g- -0 20 2- -v /au tcudorphtdiwdnabnia gg )ae(wb ngisedybdeetnarau g- -0 1- -z hm ycaruccaegatlov cad ycaruccaegatlov ca dv cad otegatnecrep,v25.1otv57.0= div div 5.0 -- -5 . 0% v547.0otv5.0= di v8 -- -8 v m v594.0otv52.0= di v0 1 -- -0 1v m etar wels tsafetar wel st saf_r st saf_divte s0 12 1- - /vm su wolsetar wel sw ols_rs =ha2x0retsigerdivs,wols_divtes 10 56 - - /vm su tupnine hgihtupn iv hi 8. 0- -- -v woltupn iv li - -- -3 . 0v tnerruc wol-llu pi lp_ne 12 3 a u esnes niv dlohserhtrop nesni vr op r_nesniv gnisirnesni v- -6- -v dlohserhtrop nesni vr op f_nesniv gnillafnesni v- -5 . 4- -v tnerructupn ii nesniv v21=nesniv,v5=n e- -0 3- -a u gnittesemit-no m w p emit-no m w pt no ,v2.1= div,v21=nesniv r tesnot k05= ? zhk002=wsf, - -0 0 5- -s n emit-ffo mumini mt nim_ffo noitarepoesahpelgni s- -0 0 3- -s n (vcc = 5v, t a = 25 o c, unless otherwise specified) upi confidential UP9508 42 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu gnim mustnerruclatotrofreifilpmaesenestnerruc egatlovtesff ov )ae(so 1 -- -1v m tnerrucsaibtupn ii ae v psc ngisedybdeetnaraug,v2.1 =0 1 -- -0 1a n tnerrucgnicruos mumixa mi crsxam 00 1- -- -a u tcudorphtdiwdnabnia gg )ae(wb ngisedybdeetnarau g- -0 1- -z hm ecnalabtnerrucesahprofreifilpmaesenestnerruc egatlovtesff ov )ae(so 1 -- -1v m tnerrucsaibtupn ii ae v xpsc ngisedybdeetnaraug,v2.1 =0 1 -- -0 1a n tnerrucgnicruos mumixa mi crsxam 00 1- -- -a u tcudorphtdiwdnabnia gg )ae(wb ngisedybdeetnarau g- -0 1- -z hm tuptuo m w p egatlov woltuptu ov )mwp(lo i knis am4 =- -- -2 . 0v egatlovhgihtuptu ov )mwp(ho i ecruos am4 =7 . 4- -- -v egakaeletatsecnadepmihgih i 0kael_mwp v mwp v0 =1 -- -0a u i 1kael_mwp v mwp v5 =0 - -1a u tnerrucecruo si crs_mwp doirepgnittesnoitcnufgnirud,v5=n e- -0 1- -a u gnittesretsiger xamccidivs ycarucca d/a nipaxami_2m w pdnaxami_3m w p retsigerdivsdaer,v15.1=egatlov h12x0 74 11 5 15 5 1c ed gnitropersysp divs ycarucca d/a ,v82.1=egatlovnipsysp hb1x0retsigerdivsdaer 42 18 2 12 3 1c ed #tohrv,#trela,oids,klcs )oids,klcs(egatlov woltupn iv divs_li - -- -5 4. 0v )oids,klcs(egatlovhgihtupn iv divs_hi 56. 0- -- -v ,oids(ecnatsisernwodllup )#tohrv,#trela r divs_no 4- -3 1 ? ,oids,klcs(tnerrucegakael )#tohrv,#trela i divs_l 1 -- -1a u #tluafsys,ydr_rv egatlov woltuptu ov lo i knis am4 =- -- -2 . 0v tnerrucegakaeltuptu oi l v5otpullu p- -- -1a u noitcetorprofgnirotinomtnerruc ycaruccarorrimtnerru ci mus iot nsc oita r5 90 0 15 0 1% upi confidential UP9508 43 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu gnitroperrofgnirotinomtnerruc ycaruccarorrimtnerru ci nom iot nsc oita r5 90 0 15 0 1% egnarecnatsiser nom ir nomi 0 1- -0 6k ? egatlovtesff ov sfo_nomi h00=tuodaerh51x0retsigerdiv s- -0 0 6- -v m egatlovtuptu ov nomi hff=tuodaerh51x0retsigerdiv s- -0 01 2- -v m poordrofgnirotinomtnerruc ycaruccarorrimtnerru ci pae iot nsc oita r5 90 0 15 0 1% 3gorp,2gorp,1gorp tnerrucecruo si crsgorp - -0 4- -a u tnerrucegakae li kael_gorp gnittesnoitcnufretfa,v0=xgorp doirep - -- -1a u gnirotinomlamreht tnerrucecruo si esnest r,v5=ne lrtcrd k01= ? 7 50 63 6a u dlohserhttressa#trel av 1esnest 301=tlusercdaerutarepmet o c- -2 8 1- -v m dlohserhttressa-ed#trel av 2esnest 001=tlusercdaerutarepmet o c- -3 9 1- -v m dlohserhttressa#tohr vv 3esnest 601=tlusercdaerutarepmet o c- -2 7 1- -v m dlohserhttressa-ed#tohr vv 4esnest 301=tlusercdaerutarepmet o c- -2 8 1- -v m lortnocelbanerevird tefsomlanretxe levelhgihegatlovtuptu ov no_lrtcrd r,v5=ne lrtcrd k01= ? - -4 . 2- -v levelwolegatlovtuptu ov l_lrtcrd r,v0=ne lrtcrd k01= ? - -0- -v noitcetorpegatlovrevo dlohserhtpv ov pvo v bf v- pae - -0 0 4- -v m emityaled pv ot yaled_pvo - -5- -s u noitcetorpegatlovrednu dlohserhtpv uv pvu v pae v- bf - -0 0 4- -v m yaled pv ut yaled_pvu - -5 . 7- -s u noitcetorptnerrucrevo divs(noitressa#trela dlohserht)trela xamcci v trela_musi egatlovxmusierusae m- -5 . 1- -v dlohserhtpcotnerruclato tv pco_musi esahplluf,egatlovxmusierusaem noitarepo - -5 9. 1- -v yaled pcotnerruclato tt yaled_1pco - -0 2- -s u dlohserhtpco esahp-re pi 2pco ierusaem xnsc tnerru c- -0 0 1- -a u yaled pco esahp-re pt yaled_2pco - -6- -s u noitcetorpnwodtuhslamreht dlohserhtnwodtuhslamreh tt pto ngisedybdeetnarau g- -0 6 1- - o c upi confidential UP9508 44 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. vqfn6x6 - 52l package 5.90 - 6.10 pin 1 mark bottom view - exposed pad 0.15 - 0.25 4.40 - 4.60 0.35 - 0.45 5.90 - 6.10 0.00 - 0.05 0.20 ref 0.80 -1.00 0.31 - 0.41 0.13 - 0.23 upi confidential UP9508 45 UP9508-ds-c3000, dec.. 2015 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2015, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064 upi confidential |
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