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greenpak 3 ? silego technology, inc. preliminary slg7nt4503 sequencer slg7nt4503_ds_r011 slg7nt4503_gp_r002 rev 0.11 revised august 26, 2014 general description features ? low power consumption ? pb - free / rohs compliant ? halogen - free ? s t qfn - 20 package output summary ? 2 outputs push pull 2x ? 7 outputs open drain nmos 1x pin configuration 1 2 3 4 5 6 7 11 8 9 10 20 19 18 s t q fn - 20 top view 12 13 14 15 16 17 vdd slg7nt4503 gnd sc_pwrgd_atx core_1v1_en/hps_1v1_en fpga_1v2_en fpga1v8/hps1v5_en fpga2v5/hps2v5_en fpga3v3/hps3v3_en hps_rst_n soft reset in core_1v1_pwrgd hps_1v1_pwrgd hps_por_n fpga1v2_pwrgd fpga1v8/hps1v5_pwrgd error all_pwrgd fpga_ps_reset fpga2v5/hps2v5_pwrgd fpga3v3/hps3v3_pwrgd sil ego slg7nt4503 is a low power and small form device. the soc is housed in a 2mm x 3mm stqfn package which is optimal for using with small devices.
preliminary page 2 2 sequencer slg7nt4503_ds_r011 slg7nt4503 block diagram
preliminary page 3 3 sequencer slg7nt4503_ds_r011 slg7nt4503 p in configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 sc_pwrgd_atx digital input digital input without schmitt trigger 3 core_1v1_en/hps_1v1_en digital output open drain nmos 1x 4 fpga_1v2_en digital output open drain nmos 1x 5 fpga1v8/hps1v5_en digital output open drain nmos 1x 6 fpga2v5/hps2v5_en digital output open drain nmos 1x 7 fpga3v3/hps3v3_en digital output open drain nmos 1x 8 hps_rst_n digital output open drain nm os 1x 9 soft reset in digital input digital input without schmitt trigger 10 core_1v1_pwrgd digital input digital input without schmitt trigger 11 gnd gnd ground 12 hps_1v1_pwrgd digital input digital input without schmitt trigger 13 hps_por_n digital output open drain nmos 1x 14 fpga1v2_pwrgd digital input digital input without schmitt trigger 15 fpga1v8/hps1v5_pwrgd digital input digital input without schmitt trigger 16 fpga2v5/hps2v5_pwrgd digital input digital input without schmitt trigger 17 f pga3v3/hps3v3_pwrgd digital input digital input without schmitt trigger 18 error digital output push pull 2x 19 all_pwrgd digital output push pull 2x 20 fpga_ps_reset digital input digital input without schmitt trigger ordering information part number package type slg7nt4503v v= s tqfn - 20 SLG7NT4503VTR vtr= s tqfn - 20 C tape and reel (3k units)
preliminary page 4 4 sequencer slg7nt4503_ds_r011 slg7nt4503 absolute maximum conditions parameter min. max. unit v high to gnd - 0.3 7 v voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperat ure range - 65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 13 00 -- v moisture sensitivity level 1 electrical characteristics (@ 25c, unless otherwise stated) symbol parame ter condition/note min. typ. max. unit v dd supply voltage 3 3.3 3.6 v t a operating temperature - 40 25 85 c i q quiescent current static inputs and outputs -- 1400 -- a v o maximal voltage applied to any pin in high - impedance state -- -- vdd v i o ma ximal average or dc current (note 1) per each chip side (pin2 - pin10, pin12 - pin20) -- -- 90 ma v ih high - level input voltage logic input, at vdd=3.3v 1.78 -- vdd v v il low - level input voltage logic input, at vdd=3.3v -- -- 1.21 v i ih high - level input cu rrent logic input pins; v in = vdd - 1.0 -- 1.0 a i il low - level input current logic input pins; v in = 0v - 1.0 -- 1.0 a v oh high - level output voltage push pull, i oh = 3ma, 2x driver, at vdd=3.3 v 2.87 3.21 -- v v ol low - level output voltage open drain, i o l = 3ma, 1x driver, at vdd=3.3 v -- 0.080 0.147 v push pull, i ol = 3ma, 2x driver, at vdd=3.3 v -- 0.060 0.108 i oh high - level output current push pull & pmos od, v oh = 2.4 v, 2x driver, at vdd=3.3 v 11.522 24.16 -- ma i ol low - level output current pus h pull, v ol =0.4v, 2x driver, at vdd=3.3 v 9.750 16.488 -- ma open drain, v ol =0.4v, 1x driver, at vdd=3.3 v 7.313 12.37 -- r pull_up internal pull up resistance pull up on pins 3, 4, 5, 6, 7 7 10 13 k ? pull up on pin 13 70 100 130 r pull_down inte rnal pull down resistance pull down on pins 10, 12, 14, 15, 16, 17, 20 700 1000 1300 k ?
preliminary page 5 5 sequencer slg7nt4503_ds_r011 slg7nt4503 t dly0 delay0 time at temperature 25c 4.86 5 5.16 s at temperature - 20c +45c (note 1) 4.59 5 5.85 t dly1 delay1 time at temperature 25c 194.68 200.02 205.73 ms at temperature - 20c +45c (note 1) 183.68 200.02 233.33 t dly2 delay2 time at temperature 25c 97.18 100.08 103.18 ms at temperature - 20c +45c (note 1) 91.69 100.08 117.02 t dly7 delay7 time at temperature 25c 975.6 1002.48 1031.19 ms at tem perature - 20c +45c (note 1) 920.5 1002.48 1169.55 t su start up time from vdd rising past 1.6v -- 1 -- ms 1. guaranteed by design .
preliminary page 6 6 sequencer slg7nt4503_ds_r011 slg7nt4503 functionality waveforms d0 C pin# 2 ( sc_pwrgd_atx ) d1 C pin# 10 ( core_1v1_pwrgd ) d2 C pin# 12 ( hps_1v1_pwrgd ) d3 C pi n# 14 ( fpga1v2_pwrgd ) d4 C pin# 15 ( fpga1v8/hps1v5_pwrgd ) d5 C pin# 16 ( fpga2v5/hps2v5_pwrgd ) d6 C pin# 17 ( fpga3v3/hps3v3_pwrgd ) d7 C pin# 20 ( fpga_ps_reset ) d8 C pin# 3 ( core_1v1_en/hps_1v1_en ) d9 C pin# 4 ( fpga_1v2_en ) d10 C pin# 5 ( fpga1v8/hps1v5_en ) d 11 C pin# 6 ( fpga2v5/hps2v5_en ) d12 C pin# 7 ( fpga3v3/hps3v3_en ) d13 C pin# 13 ( hps_por_n ) d14 C pin# 19 ( all_pwrgd ) d15 C pin# 18 ( error ) 1. sequencer operation
preliminary page 7 7 sequencer slg7nt4503_ds_r011 slg7nt4503 2. sequencer after latched reset state operation 3. sequencer after reset signal on pi n20 (fpga_ps_reset) operation
preliminary page 8 8 sequencer slg7nt4503_ds_r011 slg7nt4503 channel 1 ( yellow/top line) C pin# 9 ( soft reset in ) channel 2 ( light blue/2nd line) C pin# 8 ( hps_rst_n ) with external 5k ? pull up resistor 4. pin8 (hps_rst_n) operation
preliminary page 9 9 sequencer slg7nt4503_ds_r011 slg7nt4503 package top marking datasheet revision progra mming code number locked status part code revision date 0.11 002 u 08/26/2014 the ic security bit is locked/set for code security for production unless otherwise specified. revis ion number is not changed for bit locking .
preliminary page 10 10 sequencer slg7nt4503_ds_r011 slg7nt4503 package drawing and dimensio ns 20 lead s t q fn package jedec mo - 220, variation wece ic net weight: 0.015 g
preliminary page 11 11 sequencer slg7nt4503_ds_r011 slg7nt4503 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch s t q fn 20l 2 x3 mm 0.4p green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocke t pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w s t q fn 20l 2 x3 mm 0.4p green 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 refer to eia - 481 specifications recommended reflo w soldering profile please see ipc/jedec j - std - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). more information can be found at www.jedec.org .
preliminary page 12 12 sequencer slg7nt4503_ds_r011 slg7nt4503 datasheet revision history date ve rsion change 08 / 18 /201 4 0.10 new design for slg46722 08/26/2014 0.11 removed inverter from hps_por_n output
preliminary page 13 13 sequencer slg7nt4503_ds_r011 slg7nt4503 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit: http://g reenpak.silego.com/ http://greenpak2.silego.com/ http://greenpak3.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ products are also available for purchase directly from silego at the silego online store at http://www.silego.com/ silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support docu ments and the latest software releases are available at the silego website or can be requested direc tly at info@silego.com. for specific greenpak design or applications questions and support please send e - mail requests to greenpak@silego.com users of silego products can receive assistance through several channels: online training silego technology has live training assistance and sales support available at http://www.silego.com/ . please contact us to schedule a 1 on 1 training sessi on with one of our application engineers. contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for suppo rt. local sales offices a re also available to help customers. more inform ation regarding your local representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world - wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does not assume any liability arising out of such applications or uses of its products. silego technology reserves the right to improve product design, functions and reliability with out notice

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