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1 features description ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 dual channel 11 bit, 200 msps adc with snrboost programmable gain up to 6db for snr/sfdr trade-off maximum sample rate: 200 msps dc offset correction 11-bit resolution with no missing codes gain tuning capability in fine steps (0.001 90 dbc sfdr at fin = 10 mhz db) allows channel-to-channel gain matching 79.8 dbfs snr at 125 mhz if, 20 mhz bw supports input clock amplitude down to 400 using ti proprietary snrboost technology mv p-p differential total power 1.1 w at 200 msps internal and external reference support 90 db cross-talk 64-qfn package (9 mm 9 mm) double data rate (ddr) lvds and parallel cmos output options ads62c17 is a dual channel 11-bit, 200 msps a/d converter that combines high dynamic performance and low power consumption in a compact 64 qfn package. this makes it well-suited for multi-carrier, wide band-width communications applications. ads62c17 uses ti-proprietary snrboost technology that can be used to overcome snr limitation due to quantization noise for bandwidths less than nyquist (fs/2). it includes several useful and commonly used digital functions such as adc offset correction, gain (0 to 6 db in steps of 0.5 db) and gain tuning (in fine steps of 0.001 db). the gain option can be used to improve sfdr performance at lower full-scale input ranges. using the gain tuning capability, each channel ? s gain can be set independently to improve channel-to-channel gain matching. the device also includes a dc offset correction loop that can be used to cancel the adc offset. both ddr lvds (double data rate) and parallel cmos digital output interfaces are available. it includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. nevertheless, the device can also be driven with an external reference. the device is specified over the industrial temperature range ( ? 40 c to 85 c). 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2009, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. figure 1. ads62c17 block diagram package/ordering information transport package- package specified product package marking ordering number media, lead designator temperature range quantity ADS62C17IRGCR ads62c17 qfn-64 rgc ? 40 c to 85 c az62c17 tape and reel ads62c17irgct 2 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 control interface ina_p ina_m clkp clkm vcm sclk se n sd ata avd d a gnd drvd d drgnd 14 bit adc inb_p inb_m reset c trl1 ctr l2 ct rl3 clkoutp/m lvds interface ads62c17 da0p/m da2p/mda4p/m da6p/m da8p/m da10p/m db0p/mdb2p/m db4p/m db6p/m db8p/m db10p/m 14 bit adc digital processing block channel a snrboost digital processing block channel b 11 bit 11 bit sdout ddrserializer ddrserializer outputclock buffer snrboost sample & hold clockgen reference sample & hold
thermal characteristics (1) absolute maximum ratings (1) ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 over operating free-air temperature range (unless otherwise noted) parameter test conditions typ unit r q ja (2) soldered thermal pad, no airflow 22 soldered thermal pad, 200 lfm 15 c/w r q jt (3) bottom of package (thermal pad) 0.57 (1) with a jedec standard high k board and 5x5 via array. see exposed pad in the application information. (2) r q ja is the thermal resistance from the junction to ambient. (3) r q jt is the thermal resistance from the junction to the thermal pads. value unit supply voltage range avdd -0.3 to 3.9 v supply voltage range drvdd ? 0.3 to 2.2 voltage between agnd and drgnd ? 0.3 to 0.3 voltage between avdd to drvdd (when avdd leads drvdd) 0 to 3.3 v voltage between drvdd to avdd (when drvdd leads avdd) ? 1.5 to 1.8 voltage applied to external pin, vcm (in external refersnce mode) ? 0.3 to 2.0 ? 0.3v to minimum voltage applied to analog input pins ? inp_a, inm_a, inp_b, inm_b v (3.6, avdd + 0.3v) voltage applied to input pins ? clkp, clkm (2) , reset, sclk, sdata, sen, ctrl1, ? 0.3v to add + 0.3v ctrl2, ctrl3 t a operating free-air temperature range ? 40 to 85 c t j operating junction temperature range 125 c t stg storage temperature range ? 54 to 150 c esd, human body model 2 kv (1) stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) when avdd is turned off, it is recommended to switch off the input clock (or ensure the voltage on clkp, clkm is < |0.3v|. this prevents the esd protection diodes at the clock input pins from turning on. copyright ? 2009, texas instruments incorporated submit documentation feedback 3 product folder link(s): ads62c17
recommended operating conditions (1) ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com min typ max unit supplies avdd analog supply voltage 3.15 3.3 3.8 v drvdd digital supply voltage 1.7 1.8 1.9 v analog inputs differential input voltage range 2 v pp input common-mode voltage 1.5 0.1 v voltage applied on cm in external reference mode 1.5 0.05 v maximum analog input frequency with 2v pp input amplitude (1) 500 mhz maximum analog input frequency with 1v pp input amplitude (1) 800 mhz clock input input clock sample rate 1 200 msps input clock amplitude differential (v clkp ? v clkm ) sine wave, ac-coupled 0.2 3.0 v pp lvpecl, ac-coupled 1.6 v pp lvds, ac-coupled 0.7 v pp lvcmos, single-ended, ac-coupled 3.3 v input clock duty cycle 40% 50% 60% digital outputs c l maximum external load capacitance from each output pin to drgnd 5 pf r l differential external load resistance between the lvds output (lvds interface) 100 ? t a operating free-air temperature ? 40 85 c (1) see theory of operation in the application section. 4 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
electrical characteristics (1) ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical values are at 25 c, avdd = 3.3v, drvdd = 1.8v, sampling frequency = 200 msps, 50% clock duty cycle, ? 1dbfs differential analog input, internal reference mode, lvds and cmos interfaces unless otherwise noted. min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = 3.3v, drvdd = 1.8v parameter test conditions min typ max unit resolution 11 bits analog inputs differential input voltage range 2.0 v pp differential input resistance (at dc) see figure 44 > 1 m ? differential input capacitance see figure 45 3.5 pf analog input bandwidth 700 mhz analog input common mode current (per channel) 3.6 m a/msps vcm common mode voltage output 1.5 v vcm output current capability 4 ma power supply iavdd analog supply current 262 ma idrvdd output buffer supply current lvds interface with 100 ? external 120 ma termination idrvdd output buffer supply current cmos interface no external load 87 ma capacitance analog power 865 1025 mw digital power lvds interface 216 306 mw global power down 45 75 mw no missing codes assured dc accuracy dnl differential non-linearity fin = 170 mhz -0.6 0.2 0.6 lsb inl integral non-linearity fin = 170 mhz -2.5 0.75 2.5 lsb offset error -20 2 20 mv offset error temperature coefficient 0.02 mv/c offset error variation with supply 0.5 mv/v there are two sources of gain error ? internal reference inaccuracy and channel gain error gain error due to internal reference inaccuracy alone -1 0.2 1 % fs gain error of channel alone (2) -1 +0.2 1 % fs channel gain error temperature coefficient 0.002 %/ c difference in gain errors between two channels -2 2 within the same device gain matching (3) % fs difference in gain errors between two channels -4 4 across two devices (1) in cmos interface, the drvdd current scales with the sampling frequency and the load capacitance on output pins. (2) this is specified by design and characterization; it is not tested in production. (3) for two channels within the same device, only the channel gain error matters, as the reference is common for both channels. copyright ? 2009, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads62c17
electrical characteristics ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical values are at 25 c, avdd = 3.3v, drvdd = 1.8v, sampling frequency = 200 msps, 50% clock duty cycle, ? 1dbfs differential analog input, internal reference mode, snrboost disabled, lvds and cmos interfaces unless otherwise noted. min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = 3.3v, drvdd = 1.8v parameter test conditions min typ max unit snr fin = 20 mhz 67 signal to noise ratio fin = 70 mhz 66.8 dbfs lvds fin = 170 mhz 0 db gain 64.5 66.3 6 db gain 64.4 table 1. snr enhancement with snrboost enabled snrboost bath-tub centered at fsx0.25, ? 1 dbfs input applied at fin = 125mhz, sampling frequency = 200msps snr within specified bandwidth, dbfs bandwidth, mhz in default mode ( snrboost disabled) with snrboost enabled (1) min typ max min typ max 5 78.8 79.6 83 85.6 10 75.8 76.6 80 82.6 15 74 74.9 78.2 80.9 20 72.7 73.6 77 79.6 30 71 71.9 74.4 76.4 40 69.8 70.6 72.7 74.5 (1) using recommended snrboost coefficients. see note on snrboost in application section. 6 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
electrical characteristics ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical values are at 25 c, avdd = 3.3v, drvdd = 1.8v, sampling frequency = 200 msps, 50% clock duty cycle, ? 1dbfs differential analog input, internal reference mode, snrboost disabled, 0db gain, lvds and cmos interfaces unless otherwise noted. min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = 3.3v, drvdd = 1.8v parameter test conditions min typ max unit fin= 20 mhz 66.9 fin = 70 mhz 66.6 sinad dbfs signal to noise and distortion ratio 0 db gain 63.5 65.7 fin = 170 mhz 6 db gain 64.2 fin= 20 mhz 85 fin = 70 mhz 83 sfdr dbc spurious free dynamic range 0 db gain 73 78 fin = 170 mhz 6 db gain 81 fin= 20 mhz 83 fin = 70 mhz 81 thd dbc total harmonic distortion 0 db gain 71.5 75.5 fin = 170 mhz 6 db gain 79 fin= 20 mhz 94 fin = 70 mhz 90 hd2 dbc second harmonic distortion 0 db gain 73 83 fin = 170 mhz 6 db gain 92 fin= 20 mhz 85 fin = 70 mhz 83 hd3 dbc third harmonic distortion 0 db gain 73 78 fin = 170 mhz 6 db gain 81 fin= 20 mhz 94 worst spur fin = 70 mhz 92 dbc other than second, third harmonics fin = 170 mhz 80 90 imd f1 = 185 mhz, f2 = 190 mhz, each tone at ? 7 dbfs 87 dbfs 2-tone inter-modulation distortion recovery to within 1% (of final value) for 6-db overload with 1 clock input overload recovery sine wave input at fclk/4 cycles cross-talk up to 200 mhz cross-talk frequency 90 db psrr for 100 mv pp signal on avdd supply 25 db ac power supply rejection ratio copyright ? 2009, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads62c17
digital characteristics ? ads62c17 ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. avdd = 3.3v, drvdd = 1.8v parameter test conditions min typ max unit digital inputs ? ctrl1, ctrl2, ctrl3, reset, sclk, sdata, sen (1) high-level input voltage 1.3 all digital inputs support 1.8 v and 3.3 v cmos v logic levels. low-level input voltage 0.4 sdata, sclk (2) v high = 3.3 v 16 high-level input current m a sen (3) v high = 3.3 v 10 sdata, sclk v low = 0 v 0 low-level input current m a sen v low = 0 v ? 20 input capacitance 4 pf digital outputs ? cmos interface (da0-da10, db0-db10, clkout, sdout) ioh = 1ma drvdd ? drvdd high-level output voltage v 0.1 low-level output voltage iol = 1ma 0 0.1 v output capacitance (internal to device) 2 pf digital outputs ? lvds interface (da0p/m to da10p/m, db0p/m to db10p/m, clkoutp/m) vodh, high-level output differential voltage with external 100 ? termination +275 +350 +425 mv vodl, low-level output differential voltage with external 100 ? termination. ? 425 ? 350 ? 275 mv vocm, output common-mode voltage 1.0 1.15 1.40 v capacitance inside the device from each output 2 pf output capacitance to ground (1) sclk, sdata, sen function as digital input pins in serial configuration mode. (2) sdata, sclk have internal 200 k pull-down resistor (3) sen has internal 100 k ? pull-up resistor to avdd. figure 2. lvds output voltage levels 8 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 gnd gnd logic 0 v = -350 mv* odl logic 1 v = +350 mv* odh v ocm danp / dbnp danm / dbnm * with external 100 termination w
timing characteristics ? lvds and cmos modes (1) ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical values are at 25 c, avdd = 3.3v, drvdd = 1.8v, sampling frequency = 200 msps, sine wave input clock, c load = 5pf (2) , r load = 100 ? (3) , no internal termination, low speed mode disabled, unless otherwise noted. min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = 3.3v, drvdd = 1.7v to 1.9v. parameter test conditions min typ max unit t a aperture delay 0.7 1.2 1.7 ns aperture delay matching between two channels of the same device 50 ps t j aperture jitter 145 fs rms time to valid data after coming out of standby mode 1 3 m s wake-up time time to valid data after coming out of global powerdown 20 50 time to valid data after stopping and restarting the input clock 10 clock cycles adc latency (4) default, after reset 22 ddr lvds mode (5) t su data setup time (6) data valid (7) to zero-crossing of clkoutp 0.8 1.15 ns t h data hold time (7) zero-crossing of clkoutp to data becoming invalid (7) 0.8 1.15 ns t pdi clock propagation delay input clock falling edge cross-over to output clock rising edge t pdi = 0.69 ts + t delay cross-over 100 msps sampling frequency 200 msps t delay 4.2 5.7 7.2 ns ts = 1/sampling frequency difference in t delay between two devices operating at same t delay skew 500 ps temperature & svdd supply voltage. duty cycle of differential clock, (clkoutp-clkoutm) lvds bit clock duty cycle 52% 100 msps sampling frequency 200 msps rise time measured from ? 100 mv to +100 mv t rise , t fall data rise time, data fall time fall time measured from +100 mv to ? 100 mv 0.14 ns 1msps sampling frequency 200 msps rise time measured from ? 100 mv to +100 mv output clock rise time, t clkrise , fall time measured from +100 mv to ? 100 mv 0.14 ns t clkfall output clock fall time 1 msps sampling frequency 200 msps t oe output buffer enable to data delay time to valid data after output buffer becomes active 100 ns parallel cmos mode at fs=200 msps (8) t start input clock to data delay input clock falling edge cross-over to start of data valid (7) 2.5 ns t dv data valid time time interval of valid data (7) 1.7 2.7 ns t pdi clock propagation delay input clock falling edge cross-over to output clock rising edge t pdi = 0.28 ts + t delay cross-over 100 msps sampling frequency 150 msps t delay 5.5 7.5 8.5 ns ts = 1/sampling frequency duty cycle of output clock, clkout output clock duty cycle 43 100 msps sampling frequency 150 msps rise time measured from 20% to 80% of drvdd t rise , t fall data rise time, data fall time fall time measured from 80% to 20% of drvdd 1.2 ns 1 sampling frequency 200 msps rise time measured from 20% to 80% of drvdd output clock rise time, t clkrise , fall time measured from 80% to 20% of drvdd 0.8 ns t clkfall output clock fall time 1 sampling frequency 150 msps output buffer enable (oe) to data t oe time to valid data after output buffer becomes active 100 ns delay (1) timing parameters are ensured by design and characterization and not tested in production. (2) c load is the effective external single-ended load capacitance between each output pin and ground (3) r load is the differential load resistance between the lvds output pair. (4) at higher frequencies, t pdi is greater than one clock period and overall latency = adc latency + 1. (5) measurements are done with a transmission line of 100 ? characteristic impedance between the device and the load. setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) data valid refers to logic high of +100.0mv and logic low of -100.0mv. (7) data valid refers to logic high of 1.26v and logic low of 0.54v. (8) for fs > 150 msps, it is recommended to use external clock for data capture and not the device output clock signal (clkout). copyright ? 2009, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com table 2. lvds timings at lower sampling frequencies setup time, ns hold time, ns sampling frequency, msps min typ max min typ max 185 0.9 1.25 0.85 1.25 150 1.15 1.6 1.1 1.5 125 1.6 2 1.45 1.85 < 100 enable low speed mode 2 2 t pdi , ns 1 fs 100 enable low speed mode min typ max 12.6 table 3. cmos timings at lower sampling frequencies timings specified with respect to input clock sampling frequency, msps t start , ns data valid time, ns min typ max min typ max 190 1.9 2 3 170 0.9 2.7 3.7 150 6 3.6 4.6 timings specified with respect to clkout sampling frequency, msps setup time, ns hold time, ns min typ max min typ max 150 2.8 4.4 0.5 1.2 125 3.8 5.4 0.8 1.5 < 100 enable low speed mode 5 1.2 t pdi , ns 1 fs 100 enable low speed mode min typ max 9 10 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 3. latency diagram figure 4. lvds interface timing copyright ? 2009, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads62c17 clkoutm clkoutm clkoutp clkoutp output data pair output data pair t su t su dn* dn+1* t h t h t su t su t h t h danp/m dbnp/m danp/m dbnp/m t pdi t pdi clkp clkp clkm clkm output clock output clock input clock input clock *dn C bits d1,d3,d5... *dn+1 C bits d0,d2,d4... o e o e o e o e o e e o e o e o e o e o n n-1 n+1 22 clock cycles * input clock clkoutm clkoutp output data dxp, dxm ddr lvds n-22 n-21 n-20 n-19 n- 18 n-1 n n+1 n+2 22 clock cycles * clkout output data d0:d10 parallel cmos input signal sample n n+1 n+2 n+3 n+4 t pdi t a e C even bits d0, d2, d4... o C odd bits d1, d3, d5... t pdi clkm clkp n+2 n-22 n-21 n-20 n-19 n+22 n+23 n+24
device configuration parallel configuration only ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 5. cmos interface timing ads62c17 can be configured independently using either parallel interface control or serial interface programming. to put the device in parallel configuration mode, keep reset tied to high (avdd). now, pins sen, sclk, ctrl1, ctrl2 and ctrl3 can be used to directly control certain modes of the adc. the device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in table 3 to table 6 . there is no need to apply reset and sdata can be kept low. in this mode, sen and sclk function as parallel interface control pins. frequently used functions can be controlled in this mode ? power down modes, internal/external reference, selection between lvds/cmos interface and output data format. table 4 has a brief description of the modes controlled by the four parallel pins. table 4. parallel pin definition pin controls modes sclk analog control pins (controlled by analog internal or external reference voltage level, see figure 5 sen lvds/cmos interface and output data format ctrl1 digital control pints (controlled by digital control snrboost, standby and mux logic levels) ctrl2 mode. ctrl3 12 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 clkout clkout su dn* clkp clkp clkm clkm clkp clkp clkm clkm input clock output clock dan, dbn output data input clock dan, dbn output clock t pdi t su t h t start t dv dn* *dn - bits d0, d1, d2....of channel a and b
serial interface configuration only using both serial interface and parallel controlls details of parallel configuration only ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 to exercise this mode, first the serial registers have to be reset to their default values and reset pin has to be kept low. sen, sdata and sclk function as serial interface pins in this mode and can be used to access the internal registers of the adc. the registers can be reset either by applying a pulse on reset pin or by setting the < reset > bit high. the serial interface section describes the register programming and register reset in more detail. for increased flexibility, a combination of serial interface registers and parallel pin controls (ctrl1 to ctrl3) can also be used to configure the device. to allow this, keep reset low. the parallel interface control pins ctrl1 to ctrl3 are available. after power-up, the device will automatically get configured as per the voltage settings on these pins (table 6). sen, sdata, and sclk function as serial interface digital pins and are used to access the internal registers of adc. the registers must first be reset to their default values either by applying a pulse on reset pin or by setting bit < rst > = 1. after reset, the reset pin must be kept low. the serial interface section describes the register programming and register reset in more detail. the functions controlled by each parallel pin are described below. a simple way of configuring the parallel pins is shown in figure 6 . table 5. sclk control pin sclk description 0 internal reference +200mv/-0mv (3/8)avdd external reference 200mv (5/8)2avdd external reference 200mv avdd internal reference +0mv/-200mv table 6. sen control pin sen description 0 offset binary and ddr lvds output +200mv/-0mv (3/8)avdd 2 ? s complement format and ddr lvds output 200mv (5/8)2avdd 2 ? s complement format and parallel cmos output 200mv avdd offset binary and parallel cmos output +0mv/-200mv table 7. ctrl1, ctrl2 and ctrl3 pins ctrl1 ctrl2 ctrl3 description low low low normal operation low low high snrboost enabled for channel b (1) low high low snrboost enabled for channel a (1) low high high snrboost enabled for channel a and b (1) high low low global power down high low high channel b standby (1) to enable & disable snrboost mode using the ctrl pins, reset the register bits < snrboost enable - cha > = 0 & < snrboost enable - chb > = 0. copyright ? 2009, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads62c17
serial interface register initialization (when using serial interface only) ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com table 7. ctrl1, ctrl2 and ctrl3 pins (continued) ctrl1 ctrl2 ctrl3 description high high low channel a standby high high high mux mode of operation, channel a and b data is multiplexed and output on da10 to da0 pins. figure 6. simple scheme to configure parallel pins the adc has a set of internal registers, which can be accessed by the serial interface formed by pins sen (serial interface enable), sclk (serial interface clock) and sdata (serial interface data). serial shift of bits into the device is enabled when sen is low. serial data sdata is latched at every falling edge of sclk when sen is active (low). the serial data is loaded into the register at every 16 th sclk falling edge when sen is low. in case the word length exceeds a multiple of 16 bits, the excess bits are ignored. data can be loaded in multiple of 16-bit words within a single active sen pulse. the first 8 bits form the register address and the remaining 8 bits are the register data. the interface can work with sclk frequency from 20 mhz down to very low speeds (few hertz) and also with non-50% sclk duty cycle. after power-up, the internal registers must be initialized to their default values. this can be done in one of two ways: 1. either through hardware reset by applying a high-going pulse on reset pin (of width greater than 10 ns) as shown in figure 7 or 2. by applying software reset. using the serial interface, set the < reset > bit (d7 in register 0x00) to high. this initializes internal registers to their default values and then self-resets the < reset > bit to low. in this case the reset pin is kept low. figure 7. serial interface timing 14 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 (5/8)avdd (3/8)avdd gnd avdd (5/8)avdd (3/8)avdd avdd gnd to parallel pin a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 register address register data sdata sclk sen reset t sclk t dsu t dh t sloads t sloadh
serial interface timing characteristics serial register readout ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical values at 25 c, min and max values across the full temperature range t min = ? 40c to t max = 85 c, avdd = 3.3v, drvdd = 1.8v, unless otherwise noted. parameter min typ max unit f sclk sclk frequency (= 1/ t sclk ) > dc 20 mhz t sloads sen to sclk setup time 25 ns t sloadh sclk to sen hold time 25 ns t ds sdata setup time 25 ns t dh sdata hold time 25 ns the device includes an option where the contents of the internal registers can be read back. this may be useful as a diagnostic check to verify the serial interface communication between the external controller and the adc. a. first, set register bit < serial readout > = 1 to put the device in serial readout mode. this disables any further writes into the registers, except the register at address 0. note that the < serial readout > bit is also located in register 0. the device can exit readout mode by writing < serial readout > to 0. also, only contents of register at adress 0 cannot be read in the register readout mode. b. initiate a serial interface cycle specifying the address of the register (a7 ? a0) whose content has to be read. c. the device outputs the contents (d7 ? d0) of the selected register on the sdout pin. d. the external controller can latch the contents at the falling edge of sclk. e. to exit the serial readout mode, reset register bit < serial readout > = 0, which enables writes into all registers of the device. the serial register readout works with both cmos and lvds interfaces. when < serial readout > is disabled, sdout pin is forced low by the device (and not put in high-impedance). if serial readout is not used, sdout pin has to be floated. copyright ? 2009, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads62c17
reset timing (when using serial interface only) ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 8. serial readout typical values at 25 c, min and max values across the full temperature range t min = ? 40 c to t max = 85 c, unless otherwise noted. parameter conditions min typ max unit t 1 power-on delay delay from power-up of avdd and drvdd to reset pulse active 1 ns t 2 reset pulse width pulse width of active reset signal 10 ns 1 (1) m s t 3 register write delay delay from reset disable to sen active 100 ns (1) the reset pulse is needed only when using the serial interface configuration. if the pulse width is greater than 1usec, the device could enter the parallel configuration mode briefly and then return back to serial interface mode. 16 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 register address (a7:a0) = 0x00 register data (d7:d0) = 0x01 sdata sclk sen a) enable serial readout ( = 1) a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdata sclk sen sdout b) read contents of register 0x3f. this register has been initialized with 0x04 (device is put in global power down mode) register address (a7:a0) = 0x3f register data (d7:d0 ) = xx (dont care) sdout 1 0 0 0 0 0 0 pin sdout functions as serial readout ( = 1) 0 pin sdout is not in high-impedance state; it is forced low by the device ( = 0)
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 note: a high-going pulse on reset pin is required in serial interface mode in case of initialization through hardware reset. for parallel interface operation, reset has to be tied permanently high. figure 9. reset timing diagram copyright ? 2009, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads62c17
serial register map ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com table 8. summary of functions supported by serial interface (1) register register functions address a7 - a0 d7 d6 d5 d4 d3 d2 d1 d0 in hex < reset > < serial 00 0 0 0 0 0 0 software readout > reset < enable low 20 0 0 0 0 0 0 0 speed mode > < ref > < stand 3f 0 0 0 0 0 by > internal or external reference 40 0 0 0 0 < power down modes > < lvds cmos > 41 0 0 0 0 0 0 0 output interface 44 < clkout edge control > 0 0 < data format > < enable 50 0 independent 0 0 0 0 2s comp or offset channel control > binary 51 < custom pattern low > 0 0 0 52 0 0 < custom pattern high > < offset correction 53 0 enable ? common/ch 0 a > < gain programmability ? common/ch a > < offset correction time 55 0 to 6 db in 0.5 db steps constant ? common/ ch a > 56 < snrboost coeff 1 ? common/ ch a > < snrboost coeff 2 ? common/ ch a > < fine gain adjust ? common/ ch a > 57 0 +0.001 db to +0.134 db, in 128 steps < snrboost enable ? 59 0 0 0 0 0 0 0 common/ ch a > 62 0 0 0 0 0 < test patterns - common/ ch a > 63 0 0 < offset pedestal ? common/ ch a > < offset correction 66 0 0 0 0 0 0 0 enable ? ch b > < gain programmability ? ch b > < offset correction time 68 0 to 6 db in 0.5 db steps constant ? ch b > 69 < snrboost coeff 1 ? ch b > < snrboost coeff 2 ? ch b > < fine gain adjust ? ch b > 6a 0 +0.001 db to +0.134 db, in 128 steps < snrboost 6c 0 0 0 0 0 0 0 enable ? ch b > 75 0 0 0 0 0 < test patterns - ch b > 76 0 0 < offset pedestal ? ch b > (1) multiple functions in a register can be programmed in a single write operation. 18 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
description of serial registers ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 00 < reset > 0 0 0 0 0 0 < serial readout > software reset d7 < reset > 1 software reset applied ? resets all internal registers and self-clears to 0. d0 < serial readout > 0 serial readout disabled. sdout is forced high or low by the device (and not out in high impedance state). 1 serial readout enabled, pin sdout functions as serial data readout. this mode is available only with cmos output interface. with lvds interface, pin 56 becomes clkoutm. a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 20 0 0 0 0 0 < enable low 0 0 speed mode > d2 < enable low speed mode > 0 low speed mode disabled. use for sampling frequency > 100 msps. 1 enable low speed mode for sampling frequencies < = 100 msps. a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 3f 0 < ref > 0 0 0 < standby > 0 d6-d5 < ref > internal or external reference selection 01 internal reference enabled 11 external reference enabled d1 < standby > 0 normal operation 1 adc is powered down for both channels. internal references, output buffers are active. this results in quick wake-up time from standby. copyright ? 2009, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 40 0 0 0 0 power down modes d3-d0 < power down modes > 0000 pins ctrl1, ctrl2 & ctrl3 determine power down modes. 1000 normal operation 1001 output buffer disabled for channel b 1010 output buffer disabled for channel a 1011 output buffer disabled for channel a and b 1100 global power down 1101 channel b standby 1110 channel a standby 1111 multiplexed mode, mux ? (only with cmos interface) channel a and b data is multiplexed and output on da10 to da0 pins. a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 41 < lvds 0 0 0 0 0 0 0 cmos > d7 < lvds cmos > 0 parallel cmos interface 1 ddr lvds interface 20 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 44 < clkout edge control > 0 0 output clock edge control lvds interface d7-d5 < clkout posn > output clock rising edge position 000, 100 default output clock position (refer to timing specification table) 101 rising edge shifted by + (4/26)ts 110 rising edge aligned with data transition 111 rising edge shifted by ? (4/26)ts d4-d2 < clkout posn > output clock falling edge position 000, 100 default output clock position (refer to timing specification table) 101 falling edge shifted by + (4/26)ts 110 falling edge aligned with data transition 111 falling edge shifted by ? (4/26)ts cmos interface d7-d5 < clkout posn > output clock rising edge position 000, 100 default output clock position (refer to timing specification table) 101 rising edge shifted by + (4/26)ts 110 rising edge shifted by ? (6/26)ts 111 rising edge shifted by ? (4/26)ts d4-d2 < clkout posn > output clock falling edge position 000, 100 default output clock position (refer to timing specification table) 101 falling edge shifted by + (4/26)ts 110 falling edge shifted by ? (6/26)ts 111 falling edge shifted by ? (4/26)ts a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 50 0 < enable independent 0 0 0 < data format > 0 channel control > 2s complement or offset binary 0 d6 < enable independent channel control > 0 common control ? both channels use common control settings for test patterns, offset correction, gain, gain correction and snrboost functions. these settings can be specified in a single set of registers. 1 independent control ? both channels can be programmed with independent control settings for test patterns, offset correction and snrboost functions. separate registers are available for each channel. d2-d1 < data format > 10 2s complement 11 offset binary copyright ? 2009, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 51 < custom pattern low > 0 0 0 52 0 0 < custom pattern high > d7-d3 < custom low > 5 lower bits of custom pattern available at the output instead of adc data d5-d0 < custom high > 6 upper bits of custom pattern available at the output instead of adc data a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 53 0 < offset correction enable ? 0 0 0 0 0 0 common/ch a > offset correction enable d6 < offset correction enable ? common/ch a > offset correction enable control for both channels ( with common control) or for channel a only ( with independent control). 0 offset correction disabled 1 offset correction enabled see offset correction 22 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 55 < gain programmability ? common/ch a > < offset corr time constant ? common/ch a > offset correction time constant d7-d4 < gain programmability ? common/ch a > gain control for both channels (with common control) or for channel a only (with independent control). 0000 0 db gain, default after reset 0001 0.5 db gain 0010 1.0 db gain 0011 1.5 db gain 0100 2.0 db gain 0101 2.5 db gain 0110 3.0 db gain 0111 3.5 db gain 1000 4.0 db gain 1001 4.5 db gain 1010 5.0 db gain 1011 5.5 db gain 1100 6.0 db gain d3-d0 < offset corr time constant ? common/ch a > correction loop time constant in number of clock cycles. applies to both channels (with common control) or for channel a only (with independent control). 0000 256 k 0001 512 k 0010 1 m 0011 2 m 0100 4 m 0101 8 m 0110 16 m 0111 32 m 1000 64 m 1001 128 m 1010 256 m 1011 512 m a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 56 < snrboost coeff 1 ? common/ch a > < snrboost coeff 2 ? common/ch a > see snr enhancement using snrboost copyright ? 2009, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 57 0 < fine gain adjust ? common/ch a > +0.001 db to +0.134 db, in 128 steps using the fine gain adjust register bits, the channel gain can be trimmed in fine steps. the trim is only additive, has 128 steps & a range of 0.134db. the relation between the fine gain adjust bits & the trimmed channel gain is: channel gain = 20 log10[1 + (fine gain adjust/8192)] note that the total device gain = adc gain + channel gain. the adc gain is determined by register bits < gain programmability> a7 ? a0 in d7 d6 d5 d4 d3 d2 d1 d0 hex 59 0 0 0 0 0 0 0 < snrboost enable ? ch a > d0 < snrboost enable ? ch a > snrboost control for both channels ( with common control) or for channel a only ( with independent control). 0 snrboost disabled 1 snrboost enabled a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 62 0 0 0 0 0 < test patterns > d2-d0 < test patterns > test patterns to verify data capture. applies to both channels ( with common control) for channel a only ( with independent control) 000 normal operation 001 outputs all zeros 010 outputs all ones outputs toggle pattern 011 output data < d10:d0 > alternates between 01010101010 and 10101010101 every clock cycle. outputs digital ramp 100 output data increments by one lsb (12-bit) every 8th clock cycle from code 0 to code 2047. 101 outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern) 110 unused 111 unused 24 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 63 0 0 < offset pedestal ? common/ch a > d5-d0 < offset pedestal ? common/ch a > when the offset correction is enabled, the final converged value after the offset is corrected will be the adc mid-code value. a pedestal can be added to the final converged value by programming these bits. see " offset correction " in application section. applies to both channels ( with common control) or for channel a only ( with independent control). 011111 pedestal = 31 lsb 011110 pedestal = 30 lsb 011101 pedestal = 29 lsb .... 000000 pedestal = 0 lsb .... 111111 pedestal = ? 1 lsb 111110 pedestal = ? 2 lsb .... 100000 pedestal = ? 32lsb a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 66 0 < offset correction enable 0 0 0 0 0 0 ? ch b > offset correction enable d6 < offset correction enable ? ch b > offset correction enable control for channel b ( only with independent control). 0 offset correction disabled 1 offset correction enabled copyright ? 2009, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 68 < gain programmability ? ch b > < offset corr time constant ? ch b > offset correction time constant d7-d4 < gain ? ch b > gain programmability in 0.5 db steps applies to channel b ( only with independent control). 0000 0 db gain, default after reset 0001 0.5 db gain 0010 1.0 db gain 0011 1.5 db gain 0100 2.0 db gain 0101 2.5 db gain 0110 3.0 db gain 0111 3.5 db gain 1000 4.0 db gain 1001 4.5 db gain 1010 5.0 db gain 1011 5.5 db gain 1100 6.0 db gain d3-d0 < offset corr time constant ? ch b > time constant of correction loop in number of clock cycles. applies to channel b ( only with independent control) 0000 256 k 0001 512 k 0010 1 m 0011 2 m 0100 4 m 0101 8 m 0110 16 m 0111 32 m 1000 64 m 1001 128 m 1010 256 m 1011 512 m a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 69 < snrboost coeff 1 ? ch b > < snrboost coeff 2 ? ch b > see snr enhancement using snrboost 26 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 6a < gain correction ? ch b > +0.001 db to +0.134 db, in 128 steps using the fine gain adjust register bits, the channel gain can be trimmed in fine steps. the trim is only additive, has 128 steps & a range of 0.134db. the relation between the fine gain adjust bits & the trimmed channel gain is: channel gain = 20 log10[1 + (fine gain adjust/8192)] note that the total device gain = adc gain + channel gain. the adc gain is determined by register bits < gain programmability> a7 ? a0 in d7 d6 d5 d4 d3 d2 d1 d0 hex 6c 0 0 0 0 0 0 0 < snrboost enable ? ch b > d0 < snrboost enable ? ch b > snrboost control for channel b ( only with independent control). 0 snrboost disabled 1 snrboost enabled a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 75 0 0 0 < test patterns ? ch b > d2-d0 < test patterns > test patterns to verify data capture applies to both channels ( with common control) for channel a only ( with independent control) 000 normal operation 001 outputs all zeros 010 outputs all ones outputs toggle pattern 011 output data < d10:d0 > alternates between 01010101010 and 10101010101 every clock cycle. outputs digital ramp 100 output data increments by one lsb (12-bit) every 8th clock cycle from code 0 to code 2047. 101 outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern) 110 unused 111 unused copyright ? 2009, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com a7 ? a0 in hex d7 d6 d5 d4 d3 d2 d1 d0 76 0 0 < offset pedestal ? common/ch a > d5-d0 < offset pedestal ? ch b > when the offset correction is enabled, the final converged value after the offset is corrected will be the adc mid-code value. a pedestal can be added to the final converged value by programming these bits. see " offset correction " in application section. applies to both channels ( with common control) or for channel a only ( with independent control). 011111 pedestal = 31 lsb 011110 pedestal = 30 lsb 011101 pedestal = 29 lsb .... 000000 pedestal = 0 lsb .... 111111 pedestal = ? 1 lsb 111110 pedestal = ? 2 lsb .... 100000 pedestal = ? 32lsb 28 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
pin configuration (lvds interface) ? ads62c17 ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 10. pin configuration copyright ? 2009, texas instruments incorporated submit documentation feedback 29 product folder link(s): ads62c17 a g n d a g n d i n p _ b n c i n m_ a a g n d a g n d c l kp c l k m ctrl 3 avdd ctrl 1 ctrl 2 a g n d avdd i n m _ b a g n d i n p _ a a g n d a g n d 18 19 20 21 22 23 24 31 30 29 28 27 26 25 63 62 60 59 58 57 56 50 52 53 54 55 51 64 61 23 45 6 7 9 10 8 11 12 13 14 15 1 16 3635 34 48 47 46 45 4443 4241 40 39 3837 32 drvdd db4m db4p db 6 p db 6 m db8p db8m db10p db10m sdata sclk reset sen avdd drvdd da4p da 2 p da4m da0p da 2 m da 0 m drgnd drvdd da 6 p da 6 m c l k o u t p c l k o u t m db0 m db0 p s d o u t d r g n d da 1 0 m da 1 0 p da 8 m d a 8 p d r g n d d r v dd db 2 p db 2 m nc nc n c n c pad (connected to drgnd) vcm
pin assignments (lvds interface) ? ads62c17 ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com pin no. pin description of type name number pins avdd 16, 33, 34 3 i analog power supply agnd 17,18,21,24, 8 i analog ground 27,28,31,32 clkp, clkm 25, 26 2 i differential clock input inp_a, inm_a 29, 30 2 i differential analog input, channel a inp_b, inm_b 19, 20 2 i differential analog input, channel b vcm 23 1 io internal reference mode ? common-mode voltage output. external reference mode ? reference input. the voltage forced on this pin sets the internal references. reset 12 1 i serial interface reset input. when using the serial interface mode, the user must initialize internal registers through hardware reset by applying a high-going pulse on this pin or by using software reset option. refer to serial interface section. in parallel interface mode, the user has to tie reset pin permanently high. (sclk and sen are used as parallel control pins in this mode) the pin has an internal 100 k ? pull-down resistor. sclk 13 1 i this pin functions as serial interface clock input when reset is low. it controls selection of internal or external reference when reset is tied high. see table 5 for detailed information. the pin has an internal 100 k ? pull-down resistor. sdata 14 1 i serial interface data input. the pin has an internal 100 k ? pull-down resistor. the pin has no function in parallel interface mode and can be tired to ground. sen 15 1 i this pin functions as serial interface enable input when reset is low. it controls selection of data format and interface type when reset is tied high. see table 6 for detailed information. the pin has an internal 100 k ? pull-up resistor to avdd sdout 64 1 o this pin functions as serial interface register readout, when the < serial readout > bit is enabled. when < serial readout > = 0, this pin forces logic low & is not tri-stated. ctrl1 35 1 i digital control input pins. together, they control snrboost control and power down ctrl2 36 1 i modes. ctrl3 37 1 i clkoutp 57 1 o differential output clock, true clkoutm 56 1 o differential output clock, complement da0p, da0m 2 o differential output data pair, d0 and 0 multiplexed ? channel a da2p, da2m 2 o differential output data d1 and d2 multiplexed, true ? channel a da4p, da4m 2 o differential output data d3 and d4 multiplexed, true ? channel a da6p, da6m 2 o differential output data d5 and d6 multiplexed, true ? channel a da8p, da8m 2 o differential output data d7 and d8 multiplexed, true ? channel a da10p, da10m 2 o differential output data d9 and d10 multiplexed, true ? channel a refer to figure 10 db0p, db0m 2 o differential output data pair, d0 and 0 multiplexed ? channel b db2p, db2m 2 o differential output data d1 and d2 multiplexed, true ? channel b db4p, db4m 2 o differential output data d3 and d4 multiplexed, true ? channel b db6p, db6m 2 o differential output data d5 and d6 multiplexed, true ? channel b db8p, db8m 2 o differential output data d7 and d8 multiplexed, true ? channel b db10p, db10m 2 o differential output data d9 and d10 multiplexed, true ? channel b drvdd 1,38,48,58 4 i output buffer supply 30 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
pin configuration (cmos interface) ? ads62c17 ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 pin no. pin description of type name number pins drgnd 39,49,59,pad 4 i output buffer ground nc refer to do not connect figure 10 figure 11. pin configuration copyright ? 2009, texas instruments incorporated submit documentation feedback 31 product folder link(s): ads62c17 agnd agnd inp_b nc inm_a agnd agnd clkp clkm u nused drvdd ctrl 3 db0 sdout drgnd db 4 db 5 db 7 db 6 db 9 db 8 db10 da10 da8 da9 da3 da4 da1 da2 da0 avdd sdata sclk ctrl 1 ctrl 2 agnd avdd inm_b agnd inp_a avdd agnd agnd 18 19 20 21 22 23 24 31 30 29 28 27 26 25 63 62 60 59 58 57 56 50 52 53 54 55 51 64 61 23 4 5 6 7 9 10 8 11 12 13 14 15 1 16 3635 34 48 47 4645 44 43 42 41 40 3938 37 drgnd drvdd drgnd drvdd db3 db2 da7 da6 32 nc nc ncnc da5 nc db1 nc clkout pad (connected to drgnd) drvdd reset sen vcm
pin assignments (cmos interface) ? ads62c17 ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com pin no. pin description of type name number pins avdd 16, 33, 34 3 i analog power supply agnd 17,18,21,24, 8 i analog ground 27,28,31, 32 clkp, clkm 25, 26 2 i differential clock input inp_a, inm_a 29, 30 2 i differential analog input, channel a inp_b, inm_b 19, 20 2 i differential analog input, channel b vcm 23 1 io internal reference mode ? common-mode voltage output. external reference mode ? reference input. the voltage forced on this pin sets the internal references. reset 12 1 i serial interface reset input. when using the serial interface mode, the user must initialize internal registers through hardware reset by applying a high-going pulse on this pin or by using software reset option. refer to serial interface section. in parallel interface mode, the user has to tie reset pin permanently high. (sdata and sen are used as parallel control pins in this mode) the pin has an internal 100 k ? pull-down resistor. sclk 13 1 i this pin functions as serial interface clock input when reset is low. it controls selection of internal or external reference when reset is tied high. see table 5 for detailed information. the pin has an internal 100 k ? pull-down resistor. sdata 14 1 i serial interface data input. the pin has an internal 100 k ? pull-down resistor. the pin has no function in parallel interface mode and can be tired to ground. sen 15 1 i this pin functions as serial interface enable input when reset is low. it controls selection of data format and interface type when reset is tied high. see table 6 for detailed information. the pin has an internal 100 k ? pull-up resistor to avdd sdout 64 1 o this pin functions as serial interface register readout, when the < serial readout > bit is enabled. when < serial readout > = 0, this pin forces logic low & is not tri-stated. ctrl1 35 1 i digital control input pins. together, they control snrboost control & power down ctrl2 36 1 i modes. ctrl3 37 1 i clkout 57 1 o cmos output clock da0, da10 11 o channel a 11-bit adc output data bits, cmos levels refer to figure 11 db0-db10 11 o channel b 11-bit adc output data bits, cmos levels drvdd 1,38,48,58 4 i output buffer supply drgnd 39,49,59,pad 3 i output buffer ground nc refer to figure 11 do not connect 32 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
typical characteristics ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) fft for 20 mhz input signal figure 12. fft for 60 mhz input signal figure 13. fft for 170 mhz input signal figure 14. copyright ? 2009, texas instruments incorporated submit documentation feedback 33 product folder link(s): ads62c17 -140 -120 -100 -80 -60 -40 -20 0 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz amplitude - db ain = -1 dbfs,sfdr = 83.6 dbc, snr = 66.8 dbfs, sinad = 66.8 dbfs, thd = 83 dbc -140 -120 -100 -80 -60 -40 -20 0 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz amplitude - db ain = -1 dbfs,sfdr = 83.8 dbc, snr = 67 dbfs, sinad = 66.9 dbfs, thd = 83.3 dbc -140 -120 -100 -80 -60 -40 -20 0 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz amplitude - db ain = -1 dbfs,sfdr = 74.2 dbc, snr = 66.3 dbfs, sinad = 65.7 dbfs, thd = 73.5 dbc
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) fft for 270 mhz input signal figure 15. fft for 2-tone input signal (intermodulation distortion) figure 16. fft for 2-tone input signal (intermodulation distortion) figure 17. 34 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -7 dbfs each tone,fin1 = 185 mhz, fin2 = 190 mhz, amd3 = 87.5 dbfs, sfdr = 90 dbfs -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -35 dbfs each tone,fin1 = 185 mhz, fin2 = 190 mhz, imd3 = 107 dbfs, sfdr = 104 dbfs 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz -140 -120 -100 -80 -60 -40 -20 0 amplitude - db ain = -1 dbfs,sfdr = 71.7 dbc, snr = 65.7 dbfs, sinad = 64.8 dbfs, thd = 70.8 dbc
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) fft with snrboost enabled for 5mhz, 10mhz, and 15 mhz bandwidths, fin = 150 mhz, fcenter = fs/4 figure 18. fft with snrboost enabled for 20 mhz bandwidth, fin = 150 mhz, fcenter = fs/4 figure 19. fft with snrboost enabled for 30mhz, bandwidth, fin = 150 mhz, fcenter = fs/4 figure 20. copyright ? 2009, texas instruments incorporated submit documentation feedback 35 product folder link(s): ads62c17 -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -36 dbfs, snrboost coeff1 = 0xd, , sfdr = 52.7 dbc,thd = 53.1 dbc, snr over 30 m bw (35 m to 65 m) snrboost coeff2 = 0x3 = 78.4 dbfs -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -36 dbfs, snrboost coeff1 = 0x0, , sfdr = 51.8 dbc,thd = 51 dbc, snr over 5 m bw (47.5 m to 52.5 m) , snrboost coeff2 = 0x0 = 88.4 dbfs snr over 10 m bw (45 m to 55 m) = 84.5 dbfs,snr over 15 m bw (42.5 m to 57.5 m) = 82.5 dbfs -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -36 dbfs, snrboost coeff1 = 0xf, , sfdr = 52 dbc,thd = 52.8 dbc, snr over 20 m bw (40 m to 60 m) snrboost coeff2 = 0x1 = 80.9 dbfs
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) fft with snrboost enabled for 40mhz, bandwidth, fin = 150 mhz, fcenter = fs/4 figure 21. snr with snrboost enable and disabled sfdr across input frequency figure 22. figure 23. 36 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 78 80 82 84 86 88 90 snr (37.5 m to 42.5 m) snr (42.5 m to 47.5 m) snr (47.5 m to 52.5 m) snr (52.5 m to 57.5 m) snr (57.5 m to 62.5 m) snr - dbfs snrboost enabled snrboost disabled ain = -36 dbfs,fin = 150.2 mhz, , optimized for 20 mhz bandwidth, snr over 20 m bw (snrboost disabled) , snrboost coeff2 = 0x1 = 73.7 dbfs snr over 20 m bw ( ) = 80.9 dbfs snrboost enabled 66 70 74 78 82 86 90 0 100 200 300 400 500 input frequency - mhz sfdr - dbc -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 10 20 30 40 50 60 70 80 90 100 f - frequency - mhz ain = -36 dbfs, snrboost coeff1 = 0xd, , sfdr = 54.4 dbc,thd = 53.8 dbc, snr over 40 m bw (30 m to 70 m) snrboost coeff2 = 0x3 = 75.8 dbfs
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) snr across input frequency sfdr across gain figure 24. figure 25. performance across input amplitude sinad scross gain single tone figure 26. figure 27. copyright ? 2009, texas instruments incorporated submit documentation feedback 37 product folder link(s): ads62c17 63 64 65 66 67 68 0 100 200 300 400 500 input frequency - mhz snr - dbfs 40 50 60 70 80 90 100 -40 -35 -30 -25 -20 -15 -10 -5 0 65 65.5 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs sfdr - dbc input amplitude - dbfs snr - dbfs 68 72 76 80 84 88 92 0 100 200 300 400 500 input frequency - mhz gain = 0 db gain = 2 db gain = 5 db gain = 6 db gain = 3 db gain = 4 db sfdr - dbc gain = 1 db 62 63 64 65 66 67 68 0 50 100 150 200 250 300 350 400 450 input frequency - mhz gain = 0 db gain = 1 db gain = 2 db gain = 3 db gain = 4 db gain = 6 db 500 sinad - dbfs gain = 5 db
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) inter-modulation with 2-tone input performance across input across input amplitude common-mode voltage figure 28. figure 29. sfdr across temperature snr across temperature vs vs avdd supply avdd supply figure 30. figure 31. 38 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 65.5 66 66.5 67 67.5 -40 -25 25 55 85 avdd = 3 v avdd = 3.3 v avdd = 3.6 v snr - dbfs t - free-air temperature - c a input frequency = 60 mhz 82 83 84 85 86 87 88 89 90 -40 -25 25 55 85 avdd = 3 v avdd = 3.3 v avdd = 3.6 v input frequency = 60 mhz sfdr - dbc t - free-air temperature - c a 80 81 82 83 84 85 86 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 input common mode voltage - v 65 65.5 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs sfdr - dbc snr - dbfs input frequency = 60 82 86 90 94 98 102 106 110 -7 -12 -18 -24 -30 -36 -42 -48 input amplitude of each tone - dbfs sfdr - dbfs imd3, sfdr, dbfs imd3 - dbfs
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) performance across performance across drvdd supply voltage input clock amplitude figure 32. figure 33. performance performance across across input clock duty cycle external reference mode figure 34. figure 35. copyright ? 2009, texas instruments incorporated submit documentation feedback 39 product folder link(s): ads62c17 81 82 83 84 85 input clock amplitude, v differential pp 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs sfdr - dbc snr, dbfs 0.11 0.31 0.52 0.73 0.94 1.15 1.36 1.57 1.77 1.97 2.15 input frequency = 60 mhz 85 86 87 88 89 30 35 40 45 50 55 60 65 70 input clock duty cycle - % 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs input frequency = 20 mhz sfdr - dbc snr, dbfs 82 83 84 85 86 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 voltage forced on vcm pin - v 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs snr - dbfs sfdr - dbc 83 84 85 86 87 1.6 1.7 1.8 1.9 drvdd - supply voltage - v 66 66.5 67 67.5 68 sfdr - dbc snr - dbfs input frequency = 60 mhz, avdd = 3.3 v sfdr - dbc snr, dbfs
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) cmrr vs power dissipation across frequency sampling frequency figure 36. figure 37. drvdd current across sampling frequency figure 38. 40 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 0.4 20.4 60.4 80.4 100.4 120.4 140.4 0 25 50 75 100 125 150 175 200 sampling frequency - msps 40.4 dr vdd current - ma fin = 2.5 mhz cmos 15 pf load capacitance lvds cmos no load capacitance -70 -65 -60 -55 -50 -45 -40 -35 -30 20 40 60 80 100 130 170 230 270 common-mode frequency - mhz cmrr - db 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 0 25 50 75 100 125 150 175 200 sampling frequency - msps total power - w cmos(no load capacitance) lvds
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) sfdr contour 0 db gain up to 500 mhz figure 39. sfdr contour 6 db gain up to 800 mhz figure 40. copyright ? 2009, texas instruments incorporated submit documentation feedback 41 product folder link(s): ads62c17 200 180160 140 120 100 80 20 50 100 150 200 250 300 350 400 450 500 70 75 80 85 90 95 sampling frequency - msps 200180 160 140 120 100 80 sampling frequency - msps 65 60 100 200 300 400 500 600 700 800 70 75 80 85 90 20
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com typical characteristics (continued) all plots are at 25 c, avdd = 3.3 v, drvdd = 1.8 v, sampling frequency = 200 msps, sine wave input clock. 1.5 vpp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, snrboost disabled, internal reference mode, 0 db gain, lvds output interface (unless otherwise noted) snr contour 0 db gain up to 500 mhz figure 41. snr contour 6 db gain up to 800 mhz figure 42. 42 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 200180 160 140 120 100 80 20 50 100 150 200 250 300 350 400 450 500 63 64 65 66 67 sampling frequency - msps 63.5 64.5 65.5 66.5 200180 160 140 120 100 80 sampling frequency - msps 60 60.5 100 200 300 400 500 600 700 800 61 62 63 64 65 20 61.5 62.5 63.5 65.5 64.5
application information theory of operation analog input drive circuit requirements ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 ads62c17 is a low power 11-bit pipeline a/d converters with maximum sampling rate up to 200 msps. at every falling edge of the input clock, the analog input signal of each channel is sampled simultaneously. the sampled signal in each channel is converted by a pipeline of low resolution stages. in each stage, the sampled and held signal is converted by a high speed, low resolution flash sub-adc. the difference (residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. at every clock, each succeeding stage resolves the sampled input with greater accuracy. the digital outputs from all stages are combined in a digital correction logic block and processed digitally to create the final 11 bit code, after a data latency of 22 clock cycles. the digital output is available as either ddr lvds or parallel cmos and coded in either straight offset binary or binary 2s complement format. the dynamic offset of the first stage sub-adc limits the maximum analog input frequency to about 500mhz (with 2v pp amplitude) and about 800mhz (with 1v pp amplitude). the analog input consists of a switched-capacitor based differential sample and hold architecture. this differential topology results in very good ac performance even for high input frequencies at high sampling rates. the inp and inm pins have to be externally biased around a common-mode voltage of 1.5v, available on vcm pin. for a full-scale differential input, each input pin inp, inm has to swing symmetrically between vcm + 0.5v and vcm ? 0.5v, resulting in a 2vpp differential input swing. figure 43. analog input circuit for optimum performance, the analog inputs must be driven differentially. this improves the common-mode noise immunity and even order harmonic rejection. a 5 ? to 15 ? resistor in series with each input pin is recommended to damp out ringing caused by package parasitic. sfdr performance can be limited due to several reasons - the effect of sampling glitches (described below), non-linearity of the sampling circuit & non-linearity of the quantizer that follows the sampling circuit. depending on the input frequency, sample rate & input amplitude, one of these plays a dominant part in limiting performance. at very high input frequencies (> about 300 mhz), sfdr is determined largely by the device ? s sampling circuit non-linearity. at low input amplitudes, the quantizer non-linearity usually limits performance. copyright ? 2009, texas instruments incorporated submit documentation feedback 43 product folder link(s): ads62c17 inp inm 10 w rcr filter sampling capacitor sampling switch sampling switch ron 15 w ron 100 w 3 pf lpkg~ 2 nh sampling capacitor ron 10 w lpkg~ 2 nh c ~1 pf bond r200 w r200 w c ~1 pf bond 3 pf 100 w c20.5 pf c10.25 pf c20.5 pf 15 w c 2 pf samp c 2 pf samp 10 w
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com glitches are caused by the opening & closing of the sampling switches. the driving circuit should present a low source impedance to absorb these glitches. otherwise, this could limit performance, mainly at low input frequencies (up to about 200 mhz). it is also necessary to present low impedance ( < 50 ? ) for the common mode switching currents. this can be achieved by using two resistors from each input terminated to the common mode voltage (vcm). the device includes an internal r-c filter from each input to ground. the purpose of this filter is to absorb the sampling glitches inside the device itself. the cut-off frequency of the r-c filter involves a trade-off. a lower cut-off frequency (larger c) absorbs glitches better, but it reduces the input bandwidth. on the other hand, with a higher cut-off frequency (smaller c), bandwidth support is maximized. but now, the sampling glitches need to be supplied by the external drive circuit. this has limitations due to the presence of the package bond-wire inductance. in ads62c17, the r-c component values have been optimized while supporting high input bandwidth (up to 700 mhz). however, in applications with input frequencies up to 200-300mhz, the filtering of the glitches can be improved further using an external r-c-r filter (as shown in figure 46 and figure 47 ). in addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. while doing this, the adc input impedance must be considered. figure 44 and figure 45 show the impedance (zin = rin || cin) looking into the adc input pins. figure 44. adc analog input resistance (rin) across frequency 44 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 0.01 0.10 1 10 100 0 100 200 300 400 500 600 700 800 900 1000 f - frequency - mhz resistance - k w
driving circuit ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 45. adc analog input capacitance (cin) across frequency two example driving circuit configurations are shown in figure 46 and figure 47 ? one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. in figure 46 , an external r-c-r filter using 22pf has been used. together with the series inductor (39nh), this combination forms a filter and absorbs the sampling glitches. due to the large capacitor (22pf) in the r-c-r and the 15 ? resistors in series with each input pin, the drive circuit has low bandwidth and supports low input frequencies ( < 100mhz). to support high input frequencies (up to about 300mhz, see figure 47 ), the capacitance used in the r-c-r is reduced to 3.3pf and the series inductors are shorted out. together with the lower series resistors (5 ? ), this drive circuit provides high bandwidth and supports high input frequencies. transformers such as adt1-1wt or etc1-1-13 can be used up to 300mhz. without the external r-c-r filter, the drive circuit has very high bandwidth & can support very high input frequencies (> 300mhz). for example, a transmission line transformer such as adtl2-18 can be used (figure 48 ). note that both the drive circuits have been terminated by 50 ohms near the adc side. the termination is accomplished by a 25 ohms resistor from each input to the 1.5v common-mode (vcm) from the device. this allows the analog inputs to be biased around the required common-mode voltage. copyright ? 2009, texas instruments incorporated submit documentation feedback 45 product folder link(s): ads62c17 1 1.5 2 2.5 3 3.5 4 4.5 0 100 200 300 400 500 600 700 800 900 1000 f - frequency - mhz capacitance - pf
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 46. drive circuit with low bandwidth (for low input frequencies) the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. connecting two identical rf transformers back to back helps minimize this mismatch and good performance is obtained for high frequency input signals. an additional termination resistor pair may be required between the two transformers as shown in the figures. the center point of this termination is connected to ground to improve the balance between the p and m sides. the values of the terminations between the transformers and on the secondary side have to be chosen to get an effective 50 ? (in the case of 50 ? source impedance). figure 47. drive circuit with high bandwidth (for high input frequencies) figure 48. drive circuit with very high bandwidth (> 300 mhz) 46 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 inp inm vcm 1:1 1:1 3.3 pf 0.1 f m 0.1 f m 0.1 f m 0.1 f m 25 w 25 w 5 w 5 w 50 w 50 w inp inm vcm 1:1 15 w 0.1uf 1:1 22 pf 25 w 50 w 39 nh 39 nh 0.1 f m 0.1 f m 0.1 f m 50 w 25 w 15 w 50 w 50 w inp inm vcm 0.1 f 25 25 0.1 f 0.1 f t1 t2
input common-mode reference internal reference ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 all these examples show 1:1 transformers being used with a 50 ohms source. as explained in the "drive circuit requirements", this helps to present a low source impedance to absorb the sampling glitches. with a 1:4 transformer, the source impedance will be 200 ohms. the higher impedance can lead to degradation in performance, compared to the case with 1:1 transformers. for applications where only a band of frequencies are used, the drive circuit can be tuned to present a low impedance for the sampling glitches. figure 49 shows an example with 1:4 transformer, tuned for a band around 150mhz. figure 49. drive circuit with 1:4 transformer to ensure a low-noise common-mode reference, the vcm pin is filtered with a 0.1 m f low-inductance capacitor connected to ground. the vcm pin is designed to directly drive the adc inputs. the input stage of the adc sinks a common-mode current in the order of 3.6 m a / msps (about 720 m a at 200 msps). ads62c17 has built-in internal references refp and refm, requiring no external components. design schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors eliminates the need for external decoupling. the full-scale input range of the converter can be controlled in the external reference mode as explained below. the internal or external reference modes can be selected by programming the serial interface register bit < ref>. figure 50. reference section when the device is in internal reference mode, the refp and refm voltages are generated internally. common-mode voltage (1.5v nominal) is output on vcm pin, which can be used to externally bias the analog input pins copyright ? 2009, texas instruments incorporated submit documentation feedback 47 product folder link(s): ads62c17 inp inm vcm 1:4 5 0.1 f 5 100 100 25 25 15pf 72nh differential input signal _ + _ + internal reference intref extref refm refp vcm
external reference snr enhancement using snrboost ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com when the device is in external reference mode, the vcm acts as a reference input pin. the voltage forced on the vcm pin is buffered and gained by 1.33 internally, generating the refp and refm voltages. the differential input voltage corresponding to full-scale is given by the following: full-scale differential input pp = (voltage forced on vcm) 1.33 in this mode, the 1.5v common-mode voltage to bias the input pins has to be generated externally. snrboost technology makes it possible to overcome snr limitations due to quantization noise. with snrboost, enhanced snr can be obtained for any bandwidth (less than nyquist or fs/2, see table 1 ). the snr improvement is achieved without affecting the default harmonic performance. snrboost is disabled after reset; it can be enabled using register bit < snrboost enable> or using the control pins ctrl1, 2, 3. (while using the register bits to control snrboost, keep ctrl1, ctrl2, ctrl3 low. to use the ctrl pins as snrboost control, reset the < snrboost enable> register bits). when it is enabled, the noise floor in the spectrum acquires a typical bath-tub shape as shown in figure 51 . the bath-tub is centered around a specific frequency (called center frequency). the center frequency is located mid-way between two corner frequencies, which are specified by the snrboost coefficients (register bits < snrboost coeff1> and snrboost coeff2>). table 9 shows the relation between each coefficient and its corner frequency. by choosing appropriate coefficients, the bath-tub can be positioned over the frequency range 0 to fs/2 (table 10 shows some examples). by positioning the bath-tub within the desired signal band, snr improvement can be achieved (see table 1 ). note that as the bandwidth is increased, the amount of snr improvement reduces. figure 51. specturm with snrboost enabled table 9. setting the corner frequency snrboost coefficient value normalized corner frequency snrboost coefficient value normalized corner frequency (f/fs) (f/fs) 7 0.420 f 0.230 6 0.385 e 0.210 5 0.357 d 0.189 4 0.333 c 0.167 3 0.311 b 0.143 2 0.290 a 0.115 1 0.270 9 0.080 0 0.250 8 0.000 48 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 -140 -120 -100 -80 -60 -40 -20 0 amplitude - db 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 f - frequency - mhz center frequency= f s x 0.25 fs = 200mspsfin =150 mhz snrboost coeff1 = 0x0f, snrboost coeff2 = 0x01,
clock input ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 table 10. positioning the corner frequency (some examples) snrboost coefficient1, normalized corner snrboost coefficient1, normalized corner center frequency frequency1 frequency2 < snrboost coeff1 > < snrboost coeff2 > (f/fs) (f/fs) 0 0.250 0 0.250 fs 0.25 f 0.230 1 0.270 fs 0.25 6 0.385 2 0.290 fs 0.3375 d 0.189 b 0.143 fs 0.166 9 0.080 7 0.420 fs 0.25 figure 52. snrboost active delay snrboost does not introduce any group delay in the input signal path. the adc latency increases by four clock cycle (to 26 clock cycles). when it is enabled using the serial interface, the mode becomes fully active 10 input clock cycles after the 16 th sclk falling edge. when it is disabled, normal data (without snrboost) resumes after 6 clock cycle. ads62c17 clock inputs can be driven differentially (sine, lvpecl or lvds) or single-ended (lvcmos), with little or no difference in performance between them. the common-mode voltage of the clock inputs is set to vcm using internal 5-k ? resistors as shown in figure 53 . this allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for lvpecl, lvds clock sources (figure 54 and figure 55 ). copyright ? 2009, texas instruments incorporated submit documentation feedback 49 product folder link(s): ads62c17 a7 a6 a1 a0 d7 d6 d1 d0 register address = 0x59 register data = 0x01 sdata sclk sen clkm clkp n-26 output data clock cycle 1 clock cycle 9 clock cycle 10 n-25 serial register write to enable snrboost 10 clock cycles after the 16 th sclk falling edge, the device starts giving out valid snrboost data valid snrboost data starts n-1 n n+1 analog input signal
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 53. internal clock buffer for best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise. for high input frequency sampling, it is recommended to use a clock source with very low jitter. band-pass filtering of the clock source can help reduce the effect of jitter. there is no change in performance with a non-50% duty cycle clock input. figure 54. differential clock driving circuit single-ended cmos clock can be ac-coupled to the clkp input, with clkm tied to 1.5v common-mode voltage. as shown in figure 55 , clkm can be tied to vcm pin. 50 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 clkp vcm 2 pf lpkg ~ 2 nh lpkg ~2 nh clkm clock buffer ceq ceq ceq~ 1 to 3 pf, equivalent input capacitance of clock buffer c ~1 pf bond r~100 w 20 w 20 w c ~1 pf bond r~100 w 5 k w 5 k w clkp clkm 0.1 f m 0.1 f m differential sine-wave or pecl or lvds clock input
gain programmability offset correction ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 55. single-ended clock driving circuit ads62c17 includes gain settings that can be used to get improved sfdr performance (compared to 0db gain). the gain is programmable from 0db to 6db (in 0.5 db steps). for each gain setting, the analog input full-scale range scales proportionally, as shown in table 11 . the sfdr improvement is achieved at the expense of snr; for each 1db gain step, the snr degrades about 1db. the snr degradation is less at high input frequencies. as a result, the gain is very useful at high input frequencies as the sfdr improvement is significant with marginal degradation in snr. so, the gain can be used to trade-off between sfdr and snr. note that the default gain after reset is 0 db. table 11. full-scale range across gains gain, db full-scale, vpp 0 2v 1 1.78 2 1.59 3 1.42 4 1.26 5 1.12 6 1.00 ads62c17 has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mv. the correction can be enabled using the serial register bit < offset correction enable>. once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. the time constant of the correction loop is a function of the sampling clock frequency. the time constant can be controlled using register bits < offset corr time constant> as described in table 12 . after the offset is estimated, the correction can be frozen by setting < offset correction enable> = 0. once frozen, the last estimated value is used for offset correction every clock cycle. the correction does not affect the phase of the signal. note that offset correction is disabled by default after reset. figure 56 shows the time response of the offset correction algorithm, after it is enabled. copyright ? 2009, texas instruments incorporated submit documentation feedback 51 product folder link(s): ads62c17 clkp clkm vcm 0.1 f m 0.1 f m cmos clock input
power down ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com table 12. time constant of offset correction algorithm < offset corr time time constant (tcclk), time constant, sec constant > number of clock cycles (=tc clk x 1/fs) (1) d3-d0 0000 256 k 1.2 ms 0001 512 k 2.5 ms 0010 1 m 5 ms 0011 2 m 10 ms 0100 4 m 20 ms 0101 8 m 40 ms 0110 16 m 80 ms 0111 32 m 0.16 s 1000 64 m 0.32 s 1001 128 m 0.64 s 1010 256 m 1.28 s 1011 512 m 2.5 s 1100 reserved 1101 reserved 1110 reserved 1111 reserved (1) sampling frequency, fs = 200 msps figure 56. time response of offset correction ads62c17 has three power down modes ? power down global, individual channel standby and individual channel output buffer disable. these can be set using either the serial register bits or using the control pins ctrl1 to ctrl3. 52 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 1019 1020 1021 1022 1023 1024 1025 1026 -2 0 2 4 6 8 10 12 14 16 18 time - ms output codesm - lsb 1018 20 offset correctiondisabled offset correctionenabled output data withoffset corrected output data with4 lsb offset
power down global channel power down (individual or both channels) output buffer disable (individual or both channels) input clock stop power supply sequence digital output interface ddr lvds interface ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 table 13. power down controls power down modes configure using wake-up time serial interface parallel control pins normal operation < power down modes > =0000 low low low ? output buffer disabled for channel b < power down modes > =1001 the pins do not ? support output buffer output buffer disabled for channel a < power down modes > =1010 ? disable output buffer disabled for channel a and b < power down modes > =1011 fast (100 ns) global power down < power down modes > =1100 high low low slow (20 m s) channel b standby < power down modes > =1101 high low high fast (1 m s) channel a standby < power down modes > =1110 high high low fast (1 m s) multiplexed (mux) mode ? output data of channel a < power down modes > =1111 high high high ? and b is multiplexed & available on da10 to da0 pins. in this mode, the entire chip including both the a/d converters, internal reference and the output buffers are powered down resulting in reduced total power dissipation of about 45mw. the output buffers are in high impedance state. the wake-up time from the global power down to data becoming valid in normal mode is typically 20 m s. here, each channel ? s a/d converter can be powered down. the internal references are active, resulting in quick wake-up time of 1 m s. the total power dissipation in standby is about 450 mw. each channel ? s output buffer can be disabled and put in high impedance state ? wakeup time from this mode is fast, about 100 ns. in addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1msps. the power dissipation is about 275 mw. during power-up, the avdd and drvdd supplies can come up in any sequence. the two supplies are separated in the device. ads62c17 provides 11-bit data and an output clock synchronized with the data. two output interface options are available ? double data rate (ddr) lvds and parallel cmos. they can be selected using the serial interface register bit < lvds_cmos> or using dfs pin in parallel configuration mode. in this mode, the data bits and clock are output using lvds (low voltage differential signal) levels. two data bits are multiplexed and output on each lvds differential pair. copyright ? 2009, texas instruments incorporated submit documentation feedback 53 product folder link(s): ads62c17
ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 57. ddr lvds outputs even data bits d0, d2, d4 ? are output at the falling edge of clkoutp and the odd data bits d1, d3, d5 ? are output at the rising edge of clkoutp. both the rising and falling edges of clkoutp have to be used to capture all the data bits (figure 58 ). 54 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 clkoutpclkoutm db0_p db0_m db2_p db2_m db4_p db4_m db6_p db6_m db8_p db8_m db10_p db10_m output clockdata bit d0 data bits d1, d2 data bits d3, d4 data bits d5, d6 data bits d7, d8 data bits d9, d10 ads62c17 lvds buffers 11 bit adc data channel b
lvds buffer ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 58. ddr lvds interface the equivalent circuit of each lvds output buffer is shown in figure 59 . the buffer is designed to present an output impedance of 100 ? (rout). the differential outputs can be terminated at the receive end by a 100 ? termination. the buffer output impedance behaves like a source-side series termination. by absorbing reflections from the receiver end, it helps to improve signal integrity. note that this internal termination cannot be disabled and its value cannot be changed. copyright ? 2009, texas instruments incorporated submit documentation feedback 55 product folder link(s): ads62c17 sample n sample n clkoutm clkoutm clkoutp clkoutp da0, db0 da0, db0 sample n+1 sample n+1 da2, db2 da2, db2 da4,db4 da4,db4 da6,db6 da6,db6 da8,db8 da8,db8 da10,db10 da10,db10 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 0 0
parallel cmos interface ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com figure 59. lvds buffer equivalent circuit in the cmos mode, each data bit is output on separate pin as cmos voltage level, every clock cycle. the rising edge of the output clock clkout can be used to latch data in the receiver (for sampling frequencies up to 150 msps). up to 150msps, the setup and hold timings of the output data with respect to clkout are specified. it is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the receiver. also, match the output data and clock traces to minimize the skew between them. for sampling frequencies above 150 msps, it is recommended to use an external clock to capture data. the delay from input clock to output data and the data valid times are specified for the higher sampling frequencies. these timings can be used to delay the input clock appropriately and use it to capture the data. 56 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 when the high switches are closed , outp = 1.375 v, outm = 1.025 v when the low switches are closed , outp = 1.025 v, outm = 1.375 v switch impedance is nominally 50 w (+/- 10%) when the high (or low) switches are closed, rout = 100 w 1.2 v + 0.35 v - 0.35 v outp outm rout ads62c18 low high low high
cmos interface power dissipation ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 figure 60. parallel cmos outputs with cmos outputs, the drvdd current scales with the sampling frequency and the load capacitance on every output pin. the maximum drvdd current occurs when each output bit toggles between 0 and 1 every clock cycle. in actual applications, this condition is unlikely to occur. the actual drvdd current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. digital current due to cmos output switching = c l drvdd (n f avg ), where c l = load capacitance, n f avg = average number of output bits switching. figure 38 shows the current with various load capacitances across sampling frequencies at 2 mhz analog input frequency. copyright ? 2009, texas instruments incorporated submit documentation feedback 57 product folder link(s): ads62c17 da0 da1 da2 da8 pins da9 da10 clkout 11 bit adc data channel a sdout 11 bit adc data channel b db0 db1 db2 db8 db9 db10
output data format board design considerations migration from ads62c15 to ads62c17 ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com two output data formats are supported ? 2s complement and offset binary. they can be selected using the serial interface register bit < data format> or controlling the dfs pin in parallel configuration mode. in the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. for a positive overdrive, the output code is 0x7ff in offset binary output format, and 0x3ff in 2s complement output format. for a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2s complement output format. grounding a single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. see the evm user guide (slau237a) for details on layout and grounding. supply decoupling as ads62c17 already includes internal decoupling, minimal external decoupling can be used without loss in performance. note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. the decoupling capacitors should be placed very close to the converter supply pins. exposed pad in addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground internally. so, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. for detailed information, see application notes qfn layout guidelines (sloa122 ) and qfn/son. pcb attachment (slua271 ). while migrating from the c15 to c17, note the following differences between the two devices. ads62c15 ads62c17 pinout pin 22 is agnd pin 22 is nc pin 64 is drgnd pin 64 is sdout (serial readout pin) supply avdd is 3.3v no change drvdd is 1.8v to 3.3v (for cmos interface) and is drvdd is 1.8v (for both cmos and lvds 3.3v (for lvds interface) interfaces) serial interface protocol: 8 bit register address & 8 bit register data no change in protocol serial register map is completely different 58 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17
definition of specifications (3) (4) ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 analog bandwidth ? the analog input frequency at which the power of the fundamental is reduced by 3 db with respect to the low frequency value. aperture delay ? the delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. this delay will be different across channels. the maximum variation is specified as aperture delay variation (channel-channel). aperture uncertainty (jitter) ? the sample-to-sample variation in aperture delay. clock pulse width/duty cycle ? the duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. duty cycle is typically expressed as a percentage. a perfect differential sine-wave clock results in a 50% duty cycle. maximum conversion rate ? the maximum sampling rate at which certified operation is given. all parametric testing is performed at this sampling rate unless otherwise noted. minimum conversion rate ? the minimum sampling rate at which the adc functions. differential nonlinearity (dnl) ? an ideal adc exhibits code transitions at analog input values spaced exactly 1 lsb apart. the dnl is the deviation of any single step from this ideal value, measured in units of lsbs. integral nonlinearity (inl) ? the inl is the deviation of the adc's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. gain error ? gain error is the deviation of the adc's actual input full-scale range from its ideal value. the gain error is given as a percentage of the ideal input full-scale range. gain error has two components: error due to reference inaccuracy and error due to the channel. both these errors are specified independently as e gref and e gchan . to a first order approximation, the total gain error will be e total ~ e gref + e gchan . for example, if e total = 0.5%, the full-scale input varies from (1-0.5/100) x fs ideal to (1 + 0.5/100) x fs ideal . offset error ? the offset error is the difference, given in number of lsbs, between the adc's actual average idle channel output code and the ideal average idle channel output code. this quantity is often mapped into mv. temperature drift ? the temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree celsius of the parameter from t min to t max . it is calculated by dividing the maximum deviation of the parameter across the t min to t max range by the difference t max ? t min . signal-to-noise ratio ? snr is the ratio of the power of the fundamental (ps) to the noise floor power (pn), excluding the power at dc and the first nine harmonics. snr is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. signal-to-noise and distortion (sinad) ? sinad is the ratio of the power of the fundamental (p s ) to the power of all the other spectral components including noise (p n ) and distortion (p d ), but excluding dc. sinad is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. effective number of bits (enob) ? the enob is a measure of the converter performance as compared to the theoretical limit based on quantization noise. copyright ? 2009, texas instruments incorporated submit documentation feedback 59 product folder link(s): ads62c17 10 s n d p sinad = 10log p + p 10 s n p snr = 10log p
(5) (6) (7) (8) ads62c17 slas631a ? april 2009 ? revised july 2009 ............................................................................................................................................................. www.ti.com total harmonic distortion (thd) ? thd is the ratio of the power of the fundamental (p s ) to the power of the first nine harmonics (pd). thd is typically given in units of dbc (db to carrier). spurious-free dynamic range (sfdr) ? the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). sfdr is typically given in units of dbc (db to carrier). two-tone intermodulation distortion ? imd3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 ? f2 or 2f2 ? f1. imd3 is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. dc power supply rejection ratio (dc psrr) ? the dc pssr is the ratio of the change in offset error to a change in analog supply voltage. the dc psrr is typically given in units of mv/v. ac power supply rejection ratio (ac psrr) ? ac psrr is the measure of rejection of variations in the supply voltage by the adc. if v sup is the change in supply voltage and vout is the resultant change of the adc output code (referred to the input), then voltage overload recovery ? the number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. this is tested by separately applying a sine wave signal with 6db positive and negative overload. the deviation of the first few samples after the overload (from their expected values) is noted. common mode rejection ratio (cmrr) ? cmrr is the measure of rejection of variation in the analog input common-mode by the adc. if vcm_in is the change in the common-mode voltage of the input pins and v out is the resultant change of the adc output code (referred to the input), then cross-talk (only for multi-channel adc) ? this is a measure of the internal coupling of a signal from adjacent channel into the channel of interest. it is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). it is usually measured by applying a full-scale signal in the adjacent channel. cross-talk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. it is typically expressed in dbc. 60 submit documentation feedback copyright ? 2009, texas instruments incorporated product folder link(s): ads62c17 sinad 1.76 enob = 6.02 - (expressed in dbc) d v sup d v out 10 psrr = 20log 10 s n p thd = 10log p (expressed in dbc) d v cm d v out 10 cmrr = 20log
ads62c17 www.ti.com ............................................................................................................................................................. slas631a ? april 2009 ? revised july 2009 revision history changes from original (april 2009) to revision a .......................................................................................................... page added missing value ............................................................................................................................................................. 9 added paragraph - this disables any further writes into the registers, except the register at address 0. note that the < serial readout > bit is also located in register 0. the device can exit readout mode by writing < serial readout > to 0. also, only the ......................................................................................................................................... 15 changed to - to exit the serial readout mode, reset register bit < serial readout > =0, which enables writes into all registers of the device. .................................................................................................................................................... 15 changed normalized corner frequencies changed to fix error with respect to the mapping between the snrboost coefficient value and normalized corner frequency (f/fs). ................................................................................................... 48 changed values for normalized corner frequency1, 2, and center frequency .................................................................. 49 copyright ? 2009, texas instruments incorporated submit documentation feedback 61 product folder link(s): ads62c17
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads62c17irgc25 active vqfn rgc 64 25 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ADS62C17IRGCR active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr ads62c17irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-dec-2009 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS62C17IRGCR vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 ads62c17irgct vqfn rgc 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 package materials information www.ti.com 18-may-2009 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS62C17IRGCR vqfn rgc 64 2000 333.2 345.9 28.6 ads62c17irgct vqfn rgc 64 250 333.2 345.9 28.6 package materials information www.ti.com 18-may-2009 pack materials-page 2

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