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1 datasheet radiation hardened 5v 32-channel analog multiplexer isl71831seh the isl71831seh is a radiation tolerant, 32-channel multiplexer that is fabricated using intersil?s proprietary p6-soi process technology to provide excellent latch-up performance. it operates with a single supply range from 3v to 5.5v and has a 5-bit address line plus an enab le that can be driven with adjustable logic thresholds to conveniently select one of 32 available channels. an inactive channel is separated from the active channel by a high impedance, which inhibits any interaction between them. the isl71831seh?s low r ds(on) allows for improved signal integrity and reduced power losses. the isl71831seh is also designed for cold sparing, making it excellent for redundancy in high reliability applications. it is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without incurring extra power dissipati on. the isl71831seh also has analog overvoltage protection on the input that disables the switch during an overvoltage event to protect upstream and downstream devices. the isl71831seh is available in a 48 ld cqfp and operates across the extended temperature range of -55c to +125c. there is also a 16-channel version available offered in a 28 ld cdfp. refer to the ISL71830SEH datasheet for more information. for a list of differences, refer to table 1 on page 2 . related literature ? for a full list of related documents, visit our website - isl71831seh product page features ?dla smd# 5962-15248 ? fabricated using p6 soi process technology ? rail-to-rail operation ?no latch-up ?low r ds(on) . . . . . . . . . . . . . . . . . . . . . . . . . .<120 (maximum) ? single supply operation . . . . . . . . . . . . . . . . . . . . . . 3v to 5.5v - adjustable logic threshold control ? cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 7v ? analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4v to 7v ? switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120na ? transition times (t ahl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns ? internally grounded metal lid ? break-before-make switching ? esd protection 5kv (hbm) ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation tolerance - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . .75krad(si) - sel/seb let th (v + = 6.3v). . . . . . . . . . . . . 60mev?cm 2 /mg note: all lots are assurance te sted to 75krad (0.01rad(si)/s) wafer-by-wafer. applications ? telemetry signal processing ? harsh environments ? down-hole drilling figure 1. typical application figure 2. r ds(on) vs common-mode voltage (v + = 5v) in01 in02 in32 address 5 in03 . . . out adc isl71831seh en 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode voltage (v) r ds(on) () -55c +25c +125c november 18, 2016 fn8759.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl71831seh 2 fn8759.2 november 18, 2016 submit document feedback ordering information ordering number ( note 2 ) part number ( note 1 ) temp range (c) package (rohs compliant) pkg. dwg. # 5962l1524801vxc isl71831sehvf -55 to +125 48 ld cqfp r48.a n/a isl71831sehf/proto -55 to +125 48 ld cqfp r48.a 5962l1524801v9a isl71831sehvx -55 to +125 die n/a isl71831sehx/sample -55 to +125 die n/a isl71831sehev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the de fense logistics agency land and maritime (dla). the smd numbe rs listed must be used when ordering. table 1. key differences between family of parts part number number of chan nels output leakage package ISL71830SEH 16 60na 28 ld cdfp isl71831seh 32 120na 48 ld cqfp
isl71831seh 3 fn8759.2 november 18, 2016 submit document feedback pin configuration isl71831seh (48 ld cqfp) top view 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 15 16 17 18 19 20 21 22 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 in28 in27 in26 in25 in24 in23 in22 in21 in20 in19 in18 in17 in12 in11 in10 in9 in8 in5 in4 in3 in2 in1 in7 in6 in13 in14 in15 in16 nc nc nc in32 in31 in30 in29 out v+ vref a0 a1 a2 a3 a4 nc nc en gnd nc pin descriptions pin name esd circuit pin number description out 2 1 output for multiplexer. v + 1 19 positive power supply. inx 1 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46 inputs for multiplexer. ax 1 21, 22, 23, 24, 25 address lines for multiplexer. en 1 28 enable control for multiplexer (active low). vref 1 20 reference voltage used to set logic thresholds. gnd - 29 ground lid - - package lid is internally connected to gnd (pin 29). nc - 2, 26, 27, 30, 47, 48 not electrically connected. pin # circuit 2 vdd 9v clamp gnd 9v clamp gnd pin # 9v clamp circuit 1
isl71831seh 4 fn8759.2 november 18, 2016 submit document feedback absolute maximum ratings thermal information maximum supply voltage (v + to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v maximum supply voltage (v+ to gnd) ( note 5 ) . . . . . . . . . . . . . . . . . . .6.3v analog input voltage range (inx) . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 7v digital input voltage range (en , ax) . . . . . . . . . . . . . . . (gnd - 0.4v) to v ref vref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v esd tolerance human body model (tested per mil-std-883 tm 3015) . . . . . . . . . 5kv charged device model (tested per jesd22-c101d) . . . . . . . . . . . . 250v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 250v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld cqfp ( notes 3 , 4 ) . . . . . . . . . . . . . . . 59 5 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c recommended operating conditions ambient operating temperature range . . . . . . . . . . . . . .-55c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.5v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured with the component mounted on a high-effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for ? jc , the ?case temp? location is the center of the package underside. 5. tested in a heavy ion environment at let = 60mev ? cm 2 /mg at +125c. electrical specifications (v + = 5v) gnd = 0v, v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55 c to +125c.; over a total ionizing dose of 75krad(si) with e xposure at a low dose rate of <10mrad(si)/s. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit analog input signal range v in 0v + v channel on-resistance r ds(on) v + = 4.5v, v in = 0v to v + i out = 1ma -40 120 r ds(on) match between channels r ds(on) v + = 4.5v, v in = 0v, 2.25v, 4.5v i out = 1ma -- 5 on-resistance flatness r flat(on) v + = 4.5v, v in = 0v to v + -- 40 switch input off leakage i in(off) v + = 5.5v, v in = 5v, unused inputs and v out = 0.5v -30 - 30 na v + = 5.5v, v in = 0.5v, unused inputs and v out = 5v -30 - 30 na switch input off overvoltage leakage i in(off-ov) v + = 5.5v, v in = 7v, unused inputs and v out = 0v t a = +25c, -55c -30 - 30 na t a = +125c -30 - 120 na post radiation, +25c -30 - 30 na switch input off leakage with supply voltage grounded i in(power-off) v in = 7v, v out = 0v v + = v en = v ref = 0v t a = +25c, -55c -20 - 20 na t a = +125c -20 - 100 na post radiation, +25c -20 - 20 na switch input off leakage with supply voltage open i in(power-off) v in = 7v, v out = 0v v + = v en = v ref = open, t a = +25c, -55c -20 - 20 na t a = +125c -20 - 100 na post radiation, +25c -20 - 20 na switch on input leakage with overvoltage applied to the input i in(on-ov) v + = 5.5v, v in = 7v v out = open 2.75 - 5.50 a
isl71831seh 5 fn8759.2 november 18, 2016 submit document feedback switch output off leakage i out(off) v + = 5.5v, v out = 5v all inputs = 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 200 na post radiation, +25c -30 - 30 na v + = 5.5v, v out = 0.5v all inputs = 5v, t a = +25c, -55c -30 - 30 na t a = +125c -60 - 0 na post radiation, +25c -30 - 30 na switch output leakage with switch enabled i out(on) v + = 5.5v, v in = v out = 5v all unused inputs at 0.5v t a = +25c, -55c -30 - 30 na t a = +125c 0 - 200 na post radiation, +25c -30 - 30 na v + = 5.5v, v in = v out = 0.5v all unused inputs at 5v t a = +25c, -55c -30 - 30 na t a = +125c -60 - 0 na post radiation, +25c -30 - 30 na logic input voltage high/low v ih/l v + = 5.5v v ref = 3.3v 1.3 - 1.6 v input current with v ah, v enh i ah , i enh v + = 5.5v v en = v a = v ref -0.1 - 0.1 a input current with v al, v enl i al , i enl v + = 5.5v v en = v a = 0v -0.1 - 0.1 a quiescent supply current i supply v + = v ref = v en = 5.5v v a = 0v, t a = +25c, -55c --100na t a = +125c - - 500 na post radiation, +25c - - 300 na reference quiescent supply current i ref v + = v ref = v en = 5.5v v a = 0v -- 200 na dynamic addressing transition time t ahl v + = 4.5v; figure 3 10 - 70 ns break-before-make delay t bbm v + = 4.5v; figure 5 5 18 40 ns enable turn-on time t en(on) v + = 4.5v; figure 4 -- 40 ns enable turn-off time t en(off) v + = 4.5v; figure 4 -- 50 ns charge injection v cte c l = 100pf, v in = 0v, figure 6 - 1.4 5.0 pc off isolation v iso v en = v ref , r l = open, f = 1khz 60 -- db crosstalk v ct v en = 0v, f = 1khz, v p-p = 1v r l = open 73 -- db input capacitance c in(off) f = 1mhz - - 5 pf output capacitance c out(off) f = 1mhz - - 25 pf electrical specifications (v + = 5v) gnd = 0v, v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55 c to +125c.; over a total ionizing dose of 75krad(si) with e xposure at a low dose rate of <10mrad(si)/s. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl71831seh 6 fn8759.2 november 18, 2016 submit document feedback electrical specifications (v + = 3.3v) v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c , unless otherwise noted . boldface limits apply across the operating temperature range, -55 c to +125c.; over a total ionizing dose of 75krad(si) with e xposure at a low dose rate of <10mrad(si)/s. parameter description conditions min (note 6) typ max (note 6) unit v in analog input signal range 0 v + v r ds(on) channel on-resistance v + = 3v, v in = 0v to v + i out = 1ma 25 70 200 r ds(on) r ds(on) match between channels v + = 3v, v in = 0.5v, 2.5v i out = 1ma -- 5 r flat(on) on-resistance flatness v + = 3v, v in = 0v to v + -- 50 i in(off) switch input off leakage v + = 3.6v, v in = 3.1v, unused inputs and v out = 0.5v -30 - 30 na v + = 3.6v, v in = 0.5v, unused inputs and v out = 3.1v -30 - 30 na i in(off-ov) switch input off overvoltage leakage v + = 3.6v, v in = 7v, unused inputs and v out = 0v, t a = +25c, -55c -30 - 30 na t a = +125c -30 - 100 na post radiation, +25c -30 - 30 na i in(on-ov) switch on input leakage with overvoltage applied to the input v + = 3.6v, v in = 7v v out = open 1.8 - 3.6 a i out(off) switch output off leakage v + = 3.6v, v out = 3.1v, all inputs = 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 120 na post radiation, +25c -30 - 30 na v + = 3.6v, v out = 0.5v, all inputs = 3.1v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 30 na post radiation, +25c -30 - 30 na i out(on) switch output leakage with switch enabled v + = 3.6v, v in = v out = 3.1v all unused inputs at 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 120 na post radiation, +25c -30 - 30 na v + = 3.6v, v in = v out = 0.5v all unused inputs at 3.1v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 30 na post radiation, +25c -30 - 30 na i supply quiescent supply current v + = v ref = v en = 3.6v v a = 0v, t a = +25c, -55c --100na t a = +125c - - 300 na post radiation, +25c - - 300 na i ref reference quiescent supply current v + = v ref = v en = 3.6v, v a = 0v - - 200 na
isl71831seh 7 fn8759.2 november 18, 2016 submit document feedback dynamic t ahl addressing transition time v + = 3v; figure 3 10 - 100 ns t bbm break-before-make delay v + = 3v; figure 5 5 15 50 ns t en(on) enable turn-on time v + = 3v; figure 4 -- 60 ns t en(off) enable turn off time v + = 3v; figure 4 -- 80 ns note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications (v + = 3.3v) v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c , unless otherwise noted . boldface limits apply across the operating temperature range, -55 c to +125c.; over a total ionizing dose of 75krad(si) with e xposure at a low dose rate of <10mrad(si)/s. (continued) parameter description conditions min (note 6) typ max (note 6) unit
isl71831seh 8 fn8759.2 november 18, 2016 submit document feedback table 2. truth table a4 a3 a2 a1 a0 en ?on?-channel xxxxx1none 0000001 0000102 0001003 0001104 0010005 0010106 0011007 0011108 0100009 01001010 01010011 01011012 01100013 01101014 01110015 01111016 10000017 10001018 10010019 10011020 10100021 10101022 10110023 10111024 11000025 11001026 11010027 11011028 11100029 11101030 11110031 11111032 note: x = don?t care, ?1? = logic high, ?0? = logic low
isl71831seh 9 fn8759.2 november 18, 2016 submit document feedback timing diagrams figure 3. address time to output test circuit figure 4. address time to output diagram figure 5. time to enable/dis able output test circuit figure 6. time to enable /disable output diagram figure 7. break-before-make test circuit figure 8. break-before-make diagram figure 9. charge injection test circuit figure 10. charge injection diagram isl71831seh a3 a2 a1 a0 en in01 in02-in31 in32 out 50 0v 10k 50pf 0v, v + v + , 0v v out 0v v ref a4 t ahl 50% address output 0v v ref v + 0v 50% 11111 00000 90% t alh 90% isl71831seh 50 0v 1k 50pf v + v out a3 a2 a1 a0 en in01 in02-in32 out v ref a4 t enable t disable 50% enable output 0v v ref v + 0v 50% 10% 90% in01 in02-in31 in32 out 100 50pf v + v out isl71831seh a3 a2 a1 a0 en 50 0v 0v v ref a4 address 0v v ref 50% t bbm out 0v v + isl71831seh a3 a2 a1 a0 en in01 in02-in31 in32 out 50 0v 100pf 0v v out 0v v ref a4 vout q = 100pf * vout address 0v v ref out 0v
isl71831seh 10 fn8759.2 november 18, 2016 submit document feedback typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. figure 11. r ds(on) vs common-mode voltage (v + = 4.5v) figure 12. r ds(on) vs common-mode voltage (v + = 5v) figure 13. r ds(on) vs common-mode voltage (v + = 5.5v) figure 14. r ds(on) vs common-mode voltage (v + = 3v) figure 15. r ds(on) vs common-mode voltage (v + = 3.3v) figure 16. r ds(on) vs common-mode voltage (v + = 3.6v) 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 common-mode voltage (v) r ds(on) () +125c +25c -55c 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode voltage (v) r ds(on) () -55c +25c +125c 0 10 20 30 40 50 60 70 80 012345 +125c +25c -55c r ds(on) () common-mode voltage (v) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 r ds(on) () common-mode voltage (v) +25c +125c -55c 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 common-mode voltage (v) r ds(on) () -55c +25c +125c 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 +125c r ds(on) () +25c -55c common-mode voltage (v)
isl71831seh 11 fn8759.2 november 18, 2016 submit document feedback figure 17. address propagation delay (high to low) figure 18. address propagation delay (low to high) figure 19. address propagation delay figure 20. break-before-make delay figure 21. break-before-make delay figure 22. enable to output propagation delay typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0 10 20 30 40 50 60 70 80 3.0 3.5 4.0 4.5 5.0 5.5 address delay (ns) +125c -55c +25c supply voltage (v) 0 10 20 30 40 50 60 70 80 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) address delay (ns) -55c +125c +25c 200ns/div 1v/div 2v/div t adhl = 34.382ns t adlh = 44.087ns 0 5 10 15 20 25 30 35 40 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) t bbm delay (ns) +25c -55c +125c 200ns/div 1v/div 2v/div t bbm = 17.929ns 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 +25c -55c +125c supply voltage (v) t enable delay (ns)
isl71831seh 12 fn8759.2 november 18, 2016 submit document feedback figure 23. disable to output propagation delay figure 24. enable/disable propagation delay figure 25. off isolation (v + = 5v, +25c, r l = 511 ? ) figure 26. off isolation (v + = 5v, +25c, r l = open) figure 27. crosstalk (v + = 5v, +25c, r l = open) figure 28. charge injection typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 t disable delay (ns) supply voltage (v) +25c +125c -55c 200ns/div 1v/div 2v/div t enable = 22.670ns t disable = 41.720ns 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m 100m frequency (hz) off isolation (db) 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m 10m 100m frequency (hz) off isolation (db) 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m crosstalk (db) frequency (hz) 0 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 3.0 3.5 4.0 4.5 5.0 5.5 +125c +25c -55c supply voltage (v) charge injection (pc)
isl71831seh 13 fn8759.2 november 18, 2016 submit document feedback post low dose rate radiation characteristics (v + = 5v) unless otherwise specified, v + = 5v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed. figure 29. r ds(on) (v + = 4.5v), biased figure 30. r ds(on) (v + = 4.5v), grounded figure 31. r ds(on) minimum (v + = 4.5v) figure 32. r ds(on) maximum (v + = 4.5v) figure 33. r ds(on) flatness (v + = 4.5v) figure 34. r ds(on) match (v + = 4.5v, v in = 0.5v) 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () v in = 0.5v v in = 2.25v v in = 4v 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) v in = 4v v in = 2.25v v in = 0.5v r ds(on) () 0 20 40 60 80 100 120 0 1020304050607080 biased grounded r ds(on) () low dose rate radiation (krad(si)) 0 20 40 60 80 100 120 0 1020304050607080 biased grounded low dose rate radi ation (krad(si)) r ds(on) () 0 5 10 15 20 25 30 35 40 45 0 1020304050607080 r ds(on) () low dose rate radi ation (krad(si)) grounded biased 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () grounded biased
isl71831seh 14 fn8759.2 november 18, 2016 submit document feedback figure 35. r ds(on) match (v + = 4.5v, v in = 4v) figure 36. i s(off) (v + = 5.5v, v in = 5v) figure 37. i s(off) (v + = 5.5v, v in = 7v) figure 38. i s(on) (v + = 5.5v, v in = 5v) figure 39. i d(on) (v + = 5.5v, v in = 5v) figure 40. i d(off) (v + = 3.6v, v in = 3.1v) post low dose rate radiation characteristics (v + = 5v) unless otherwise specified, v + = 5v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 r ds(on) () low dose rate radiation (krad(si)) grounded biased biased -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 grounded biased low dose rate radiation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radi ation (krad(si)) grounded biased 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1020304050607080 biased grounded leakage (na) low dose rate radiation (krad(si)) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 grounded biased low dose rate radi ation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radiation (krad(si)) grounded biased
isl71831seh 15 fn8759.2 november 18, 2016 submit document feedback post low dose rate radiation characteristics (v + = 3.3v) unless otherwise specified, v + = 3.3v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiat ion exposure at a low dose ra te of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. figure 41. r ds(on) (v + = 3v), biased figure 42. r ds(on) (v + = 3v) - grounded figure 43. r ds(on) minimum (v + = 3v) figure 44. r ds(on) maximum (v + = 3v) figure 45. r ds(on) flatness (v + = 3v) figure 46. r ds(on) match (v + = 3v, v in = 0.5v) 0 20 40 60 80 100 120 0 1020304050607080 r ds(on) () low dose rate radi ation (krad(si)) v in = 0.5v v in = 1.5v v in = 2.5v 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () v in = 1.5v v in = 0.5v v in = 2.5v 0 20 40 60 80 100 120 0 1020304050607080 grounded biased r ds(on) () low dose rate radiation (krad(si)) 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () grounded biased 0 5 10 15 20 25 30 35 40 45 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () biased grounded 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 biased grounded low dose rate radiation (krad(si)) r ds(on) ()
isl71831seh 16 fn8759.2 november 18, 2016 submit document feedback figure 47. r ds(on) match (v + = 3v, v in = 2.5v) figure 48. i s(off) (v + = 3.6v, v in = 3.1v) figure 49. i s(off) (v + = 3.6v, v in = 7v) figure 50. i s(on) (v + = 3.6v, v in = 7v) figure 51. i d(on) (v + = 3.6v, v in = 3.1v) figure 52. i d(off) (v + = 3.6v, v in = 3.1v) post low dose rate radiation characteristics (v + = 3.3v) unless otherwise specified, v + = 3.3v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiat ion exposure at a low dose ra te of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () biased grounded -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 biased grounded leakage (na) low dose rate radiation (krad(si)) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 low dose rate radi ation (krad(si)) leakage (na) biased grounded 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1020304050607080 grounded biased low dose rate radiation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 low dose rate radiation (krad(si)) leakage (na) biased grounded -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radiation (krad(si)) biased grounded
isl71831seh 17 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8759.2 november 18, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback applications information power-up considerations the circuit is designed to be insensitive to any given power-up sequence between v+ and vref, however, it is recommended that all supplies power-up relatively close to each other. overvoltage protection the isl71831seh has overvoltage protection on both the input as well as the output. on the outp ut, the voltage is limited to a diode past the rails. each of the inputs has independent overvoltage protection that works regardless of the switch being selected. if a switch experiences an overvoltage condition, the switch is turned off. as soon as the voltage returns within the rails, the switch returns to normal operation. vref and logic functionality the vref pin sets the logic threshold for the isl71831seh. the range for vref is between 3v and 5.5v. the switching point is set to around 50% of the voltage presented to vref. this switching point allows for both 5v and 3.3v logic control. ISL71830SEH vs isl71831seh a 16-channel version of the isl71831seh is available in a 28 ld cdfp. in terms of performance specs, the parts are very similar in behavior. apart from the apparent increase in channel density, the isl71831seh does have slightly higher output leakage compared to the ISL71830SEH due to having more channels connected to the output. the supply current for the isl71831seh is also a bit higher comp ared to the ISL71830SEH.
isl71831seh 18 fn8759.2 november 18, 2016 submit document feedback die characteristics die dimensions 3102m x 2800m (122.1260 mils x 110.2362 mils) thickness: 483m 25m (19 mils 1 mil) interface materials glassivation type: 12k? silicon nitride on 3k? oxide top metallization type: 300? tin on 2.8m alcu in bondpads, tin has been removed. backside finish silicon process p6soi assembly related information substrate potential floating additional information worst case current density 1.6 x 10 5 a/cm 2 transistor count 7734 weight of packaged device 1.522 grams lid characteristics finish: gold potential: grounded, ti ed to package pin 29 metalization mask layout out in16 in15 in14 in13 in12 in11 in10 in09 in08 in07 in06 in05 in04 in03 in02 in01 v+ vref a0 a1 a2 a3 a4 en gnd in17 in18 in19 in20 in21 in22 in23 in24 in25 in26 in27 in28 in29 in30 in31 in32
isl71831seh 19 fn8759.2 november 18, 2016 submit document feedback table 3. isl71831seh die layout x-y coordinates pad number pad name packaging pin x (m) y (m) x (m) y (m) 1 in28 p42 110 110 2769.8 2467.8 2 in29 p43 110 110 2526.8 2467.8 3 in30 p44 110 110 2320.8 2467.8 4 in31 p45 110 110 2114.8 2467.8 5 in32 p46 110 110 1908.8 2467.8 9 out p1 110 110 1268.8 2467.8 10 in16 p3 110 110 1062.8 2467.8 11 in15 p4 110 110 856.8 2467.8 12 in14 p5 110 110 650.8 2467.8 13 in13 p6 110 110 444.8 2467.8 14 in12 p7 110 110 201.8 2467.8 15 in11 p8 110 110 201.8 2261.8 16 in10 p9 110 110 201.8 2055.8 17 in9 p10 110 110 201.8 1849.8 18 in8 p11 110 110 201.8 1643.8 19 in7 p12 110 110 201.8 1437.8 20 in6 p13 110 110 201.8 1231.8 21 in5 p14 110 110 201.8 1025.8 22 in4 p15 110 110 201.8 819.8 23 in3 p16 110 110 201.8 613.8 24 in2 p17 110 110 201.8 407.8 25 in1 p18 110 110 201.8 201.8 26 v + p19 110 110 427.8 201.8 27 vref p20 110 110 638.8 201.8 28 a0 p21 110 110 849.8 201.8 29 a1 p22 110 110 1055.8 201.8 30 a2 p23 110 110 1261.8 201.8 31 a3 p24 110 110 1467.8 201.8 32 a4 p25 110 110 1673.8 201.8 36 en p28 110 110 2313.8 201.8 37 gnd p29 110 110 2543.8 201.8 38 in17 p31 110 110 2769.8 201.8 39 in18 p32 110 110 2769.8 407.8 40 in19 p33 110 110 2769.8 613.8 41 in20 p34 110 110 2769.8 819.8 42 in21 p35 110 110 2769.8 1025.8 43 in22 p36 110 110 2769.8 1231.8 44 in23 p37 110 110 2769.8 1437.8 45 in24 p38 110 110 2769.8 1643.8 46 in25 p39 110 110 2769.8 1849.8 47 in26 p40 110 110 2769.8 2055.8 48 in27 p41 110 110 2769.8 2261.8 note: origin of coordinates is the center of the die.
isl71831seh 20 fn8759.2 november 18, 2016 submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change november 18, 2016 fn8759.2 on page 1 - updated related literature section on page 3 - added circuit 1 and circuit 2 diagrams and esd circuit column in the pin description table. december 10, 2015 fn8759.1 on page 1 changed in description, 2nd paragraph ?r on ?to ?r ds(on) ? changed in description and features supply voltage from ?3.3v to 5v? to ?3v to 5.5v?. updated features ?sel/seb let th ? by changing v + from 5v to 6.3v and value from 86.4 to 60mev?cm 2 /mg. removed high dose rate feature. updated low dose value from 100 to 75krad(si) on feature bullet and note. made correction to package in last paragraph of description from ?cqfp? to ?cdfp? made correction to smd from ?5962-1548? to ?5962-15248? on page 4 - in the abs max section, changed from ?maximum supply voltage (v+ to v-) (note 5) . . . . . 7v? to ?maximum supply voltage (v+ to gnd) (note 5) . . . . . 6.3v? updated note 5 by changing value from 86.3 to 60mev ? cm 2 /mg electrical spec changes - updated heading on ?electrical specifications (v + = 5v)? table. - changed parameter names from r on to r ds(on) . - changed r ds(on) typical from 60 to 40. - removed min ?15? from ? r ds(on) - added leakage to description of i in(off-0v) on page 5 - changed t bbm typical from ?15? to ?18? - changed v cte typical from ?2? to ?1.4? - for v iso , -updated test conditions from ?ven = 0v? to ?ven = vref? -moved typical values to min column. - for v ct , -updated test conditions from ?ven = vref? to ?ven = 0v? -moved typical values to min column. on page 6 - changed parameter names from r on to r ds(on) . - changed r ds(on) typical from 60 to 70. - added leakage to description of i in(off-0v) on page 7 - changed t bbm typical from ?15? to ?25? on page 8 - added table 2 on page 9 - updated figure 7 by changing 1k to 100 . on page 11 through page 16 - updated y-axis label on figures 20, 22 and 23 - updated y-axis label and title on figures 29 through 35 and figures 41 through 47 on page 18 - replaced metalization mask layout image. on page 19 - updated the pad name for pad 26 from ?vdd? to ?v+? september 24, 2015 fn8759.0 initial release
isl71831seh 21 fn8759.2 november 18, 2016 submit document feedback package outline drawing r48.a 48 ceramic quad flatpack package (cqfp) rev 3, 10/12 top view side view note: 1. all dimensions are in inches (millimeters). 0.015 (0.38) 1.118 (28.40) 0.015 (0.38) min 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) pin 1 index area 0.008 (0.20) 1.118 (28.40) 1.080 (27.43) 0.040 (1.02) bsc 0.572 (14.53) 0.555 (14.10) 0.287 (7.29) 0.253 (6.43) 0.016 (0.41) 0.009 (0.23) 0.099 (2.51) 0.076 (1.93) 0.007 (0.18) min #48 #1 for the most recent package outline drawing, see r48.a .

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