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up1651q 1 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com 2/1-phase pwm controller with svid for vr12.5 ?? ?? ? intel vr12.5 compliant ?? ?? ? output current and thermal reporting ?? ?? ? programmable iccmax,vboot ?? ?? ? rcot tm control topology ?? ?? ? easy setting ?? ?? ? smooth mode transition ?? ?? ? fast transient response ?? ?? ? selectable 2/1-phase operation ?? ?? ? differential remote voltage sensing ?? ?? ? 2 embedded 12v mosfet gate drivers with integrated bootstrap diode ?? ?? ? summed dcr current sensing for load line setting ?? ?? ? lower mosfet r ds(on) current sensing for current balance and channel ocp ?? ?? ? programmable auto phase reduction per load current ?? ?? ? ocp/ovp/uvp/otp ?? ?? ? adjustable soft-start ?? ?? ? support pre-biased start up ?? ?? ? rohs compliant and halogen free rebmunredr oe pytegakca pg nikram pot ikqq1561p ul 23-4x4nfq wq 1561pu general description applications features ?? ?? ? desktop pc core power supplies ordering information the up1651q is a vr12.5 compliant pwm controller that surpports 2/1-phase operation. this device integrates 2 mosfet gate drivers with embedded bootstrap diode to minimize external component count. to comply with vr12.5 specification, the up1651q accurately reports output current and vr temperature. the up1651q provides programmable 2/1 phase operation. up1651q integrates 2 bootstrapped drivers that support 12v + 12v driving capability. 2/1 phase operation is enabled by a logic level isenx output, achieving optimal balance between cost and flexibility. the up1651q supports automatic phase adding/dropping that is activated by psi command from svid or h/w psi setting. the up1651q operates in diode emulation mode at extreme light load condition, yielding maximum efficiency over entire load current range. other features include adjustable soft start, under/over voltage protection, over current protection and thermal shutdown. the up1651q is available in wqfn4x4-32l. pin configuration ph2 4 3 2 1 isen1 isum vrhot # eap ug2 csp 33 gnd 14 13 12 11 31 32 19 18 17 20 alert # enabl e boot2 csn 6 5 isen2 16 15 29 30 8 7 sdat vcc5 imon sclk dac/s s fbrtn fb lg2 24 23 vboot 22 21 prog boot1 ug1 ph1 25 26 27 28 lg1 vcc12 10 9 comp psrt vrok tm note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/ jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes.
up1651q 2 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com typical application circuit alert# vrhot# tm isen2 isen1 sclk vcc5 imon eap vboot sdat fb comp dac/ss fbrtn enable ps csp csn rt vrok vcc12 boot2 ph2 lg2 ug2 gnd ph1 ph2 v in v core boot1 ph1 lg1 ug1 prog isum 0.1 f 0.1 f 5v v cc_sens e v ss_sense
up1651q 3 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 11 nesi .1esahprofgnisnestnerruc edongnihctiws1esahpotnipsihtmorfrotsiseratcennoc .gnisnestnerrucrof 22 nesi .2esahprofgnisnestnerruc edongnihctiws2esahpotnipsihtmorfrotsiseratcennoc .gnisnestnerrucrof 3p sc v eroc .tupnievitisopesnestnerruclatot 4n sc v eroc .tupnievitagenesnestnerruclatot 5m usi v eroc .noitacidnitnerructuptuo d aollatototlanoitroporpsinip musifotnerructuptuo l anoitroporpsimusifoegatlovehtnehtdng dna musineewtebrotsiseratcennoc.tnerruc e ht.divsfo#trelaxamccireggirtlliwti,v2otlauqesimusin ehw.tnerrucdaollatotot .nipsihtotroticapacynaddadiova.noitcetorptnerrucrev orofdesuoslasiegatlovmusi 6n omi .niprotinomtnerructuptuo daollatotehtotlanoitroporpsinipnomifotnerructuptuoe ht r ofcdaybdedocedsiegatlovnomieht.dng otnipsihtmorfrotsiseratcennoc.tnerruc t nerrucfoemitesnopserehttsujdaotnipsihtotdeddaebyamr oticapaca.gnitropertnerruc .gnitroper 7n trbf v eroc .nruterkcabdeef v eroc g nisnesetomerrofecnereferreifilpmarorredna cad div .egatlovtuptuoehtfo 8b f v eroc .nipkcabdeef vehtfognisnesetomerroftupnignitrevnireifilpmarorre eroc t uptuo .egatlov 9p moc v eroc .tuptuo noitasnepmoc .tniopnoitasnepmocdnatuptuoreifilpmarorre 0 1p ae .reifilpmarorreehtfotupnignitrevni-non s tesss/cadehtdnapaeneewtebrotsisera .enildaoleht 1 1s s/cad v eroc .tuptuo cad e tarwelsehtmargorpotntrbfotnipsihtmorfroticapacatcen noc .noitisnartdivcimanyddnatratstfosgnirud 2 15 ccv .tupniylppus .tiucriclortnoccigolrofegatlovseilppusnipsiht 3 1k lcs .nipkcolc divs 4 1# trela .nip#trela divs 5 1t ads .ni patad divs 6 1k orv v eroc .noitacidnidoogrewop tr atstfosehtsetacidnitahttuptuoniard-neponasinipsiht .sneppahtluafondnaetelpmocsissecorp 7 1t r .gnittesemitno m w p .emitno m w pehttesotdng otnipsihtmorfrotsiseratcennoc 8 1s p .tupnignittesedom gnivasrewop dngot5ccv morfredividegatlovrotsiseratcennoc .leveldlohserhtnoitcuderesahpehttesot 9 1# tohrv .tuptuo #tohrv vehtnehw.tuptuoniard-neponasinipsiht mt e httahtlevelehtsehcaer ctntcennoc.#tohrvreggirtlliwti,)h46(xampmetsehcaere rutarepmetdedoced d/araenilnoncificepssesu q1561pu.erutarepmetrv gnisnesrofnipsihtotkrowten ehtdna,k01sirotsimrehtctn dednem mocereht.gnitroperlamrehtniretrevnoc k6sirotsisergnidividrewoldednem mocer ? . 0 2m t .gnirotinomlamreht vrofnipsihtotkrowtenctntcennoc eroc .gnirotinomlamreht
up1651q 4 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com functional pin description .o ne ma nn oitcnufnip 1 2g orp .nipgnim margorpnoitcnuf . xamccitnerrucdetroppusmumixam mroftalpehtstesnipsiht .eulavxamcciehttesotdng ot5ccv morfredividegatlovrotsiseratcennoc 2 2e lbane .elbane pihc v3.0nahtrewol.rellortnocehtselbane v7.0nahtrehgihnipsihtfoegatlov r evirdtefsomrehtehwtcetedotnipsihtesuotdednem mocersiti.rellortnocehtselbasid .ydaersiylppusrewop 3 2t oobv .nipgnim margorpnoitcnuf ) toobv(egatlovputratslaitinieht:sretemarapowtstesnip siht otdng ot5ccv morfredividegatlovrotsiseratcennoc.oitarnoitcetorpt nerrucrevoehtdna .sretemarapowtehttes 4 22 gl .2esahprofrevirdetagrewol .tefsomrewol2esahpfoetagehtotnipsihttcennoc 5 22 hp .2esahprofnipesahp t cennoc.2esahprofrevirdetagreppufohtapnruterehtsinip siht esahpehtforevirdetagreppuroftiucricpartstoobamrofot 2toobotnipsihtmorfroticapaca .2 6 22 gu .2esahprofrevirdetagreppu .tefsomreppu2esahpfoetagehtotnipsihttcennoc 7 22 toob .2esahproftoob r oftiucricpartstooba mrofot2hpotnipsihtmorfroticapacatcennoc .2esahpehtforevirdetagreppu 8 22 1ccv .tupniylppus .srevirdetagroftnerrucseilppusnipsiht 9 21 gl .1esahprofrevirdetagrewol .tefsomrewol1esahpfoetagehtotnipsihttcennoc 0 31 hp .1esahprofnipesahp t cennoc.1esahprofrevirdetagreppufohtapnruterehtsinip siht esahpehtforevirdetagreppuroftiucricpartstoobamrofot 1toobotnipsihtmorfroticapaca .1 1 31 gu .1esahprofrevirdetagreppu .tefsomreppu1esahpfoetagehtotnipsihttcennoc 2 31 toob .1esahproftoob r oftiucricpartstooba mrofot1hpotnipsihtmorfroticapacatcennoc .1esahpehtforevirdetagreppu dapdesopxe .dnuorg .dng otdetcennocdnabcpegralaotderedlosebtsum dapdesopxeeht
up1651q 5 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com functional block diagram vcc12 por gate control logic boot1 ug1 ph1 lg1 gate control logic boot2 ug2 ph2 lg2 svid soft start & power ok eap isum csn csp fb comp fbrtn enable ocp 2v x 1.33 s/h isen2 gnd uvp ovp 200mv eap + 300mv tm sclk vboot vrhot# alert# sdat dac/ss vrok vcc5 on time generation and current balance ramp generation prog psi ps s/h isen1 imon 30mv gm i sum i sum i sum rt
up1651q 6 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com functional description the up1651q is a vr12.5 compliant pwm controller that supports 2/1-phase operation. this device integrates 2 mosfet gate drivers with embedded bootstrap to minimize external component count. power ready detection figure 1 shows the power ready detection of the up1651q. the up1651q continuously monitors vcc5, enable and vcc12 voltages to ensure all power voltages are ready for normal operation of logic control circuit and companion gate drivers. the vcc5 por threshold level is vcc5 > 4.3v at the respective rising edge. when vcc5 por = low, the up1651q sets all gate drivers to turn off both high side and low side mosfets. 0.7v enable por 4.3v 5.1v vcc5 vcc12 figure1. circuit for power ready detection operation phase selection the up1651q controller supports 2/1-phase operation. the phase number of operation is set and latched by the status of isen2 pin at por rising edge. normally, the controller operates as a 2-phase pwm controller. pull isen2 to vcc5 for 1-phase operation. initial parameters setting the prog and vboot pins set the parameters required for vr12.5 as shown in figure 2. prog vboot a/d converter r 5 tm r2 r4 r 6 v cc5 v cc5 r1 v cc5 r3 figure 2. initial parameter setting the prog pin is used for iccmax setting. the iccmax is the maximum supported output current of the vr, this value is stored in svid register 0x21h. the adc scales one-fourth of vcc5 (0v to vcc5/4) into 256 levels for iccmax setting (svid register 0x21h). the ratio of prog pin voltage to vcc determines the svid register 0x21h value, which means (vcc5/1024) equals 1a. if the prog pin voltage is equal to or greater than (vcc5/4), the svid register 0x21h value will be ffh. when vcc5 = 5v, the lsb = 1.25v / 256 = 4.9mv, which means 4.9mv applied to prog pin equals to 1a setting. for example, if the maximum level of current is 50a, the prog pin voltage should be 4.9mv x 50 = 0.245v. note that the iccmax setting is dependent on vcc5 voltage (it tracks vcc5 voltage). therefore, make sure to use resistor voltage divider for iccmax setting as shown in table 1. table 1. iccmax setting v gorp ccvfo % =) a(xamcci %29. 30 4 %09. 40 5 %88. 50 6 %68. 60 7 %48. 70 8 %28. 80 9 %08. 90 01 %87.0 10 11
up1651q 7 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com the vboot pin is used for initial start up voltage vboot and ocp ratio setting. connect a resistor voltage divider from vcc5 to gnd to set the two parameters. the recommended resistance value is shown in table 2. table 2. boot voltage and ocp ratio setting k(3r ? )k (4r ? )) v(toobv ) %(oitar pco c n0 0 %331 00 20 15 6.1 02 10 17 .1 0 80 15 7.1 4 60 15 7.1 %051 8 90 27 .1 8 70 25 6.1 5 60 20 5 50 20 %171 7 40 25 6.1 0 40 27 .1 5 30 25 7.1 thermal monitor and reporting the tm pin is designed for system thermal monitoring by connecting a ntc thermistor resistive voltage divider from vcc5 to gnd. the ntc thermistor should be the upper resistor. the up1651q uses specific nonlinear a/d converter for thermal monitor function. the typical ratio of tm pin voltage to vcc5, the corresponding decoded temperature and thermal zone readout value are shown in table 3. note that this a/d conversion is dependent on vcc5 voltage (it tracks vcc5 voltage). therefore, make sure to use specific ntc thermistor in resistor voltage divider from vcc5 to gnd. it is recommended to use mitsubishi th11- 3h103h ntc as r5 and 6kohm as r6 for tempmax = 100 o c thermal zone reporting. pwm on time setting the up1651q adopts upi proprietary rcot tm (robust constant on-time) topology to have fast transient response and smooth mode transition. the pwm on time is set by an external resistor connected between rt pin and gnd. the pwm on time can be calculated as below. 11 1 r v vid t rt in on = functional description for example, if v in = 12v, vid = 1.7v, r rt = 30k ? , equation gives t on = 472ns. v dac generator the up1651q builds in precise bandgap reference circuit as shown in figure 3. the output voltage of bandgap reference is 3.04v with respective to fbrtn. the up1651q uses plural resistors to generate precise reference voltage ranging from 0.5v to 3.04v with 10mv increments. all the voltage connect to a multiplexer (mux). the multiplexer outputs the selected voltage, v dac , according to the svid inputs. please note that all the voltage values in figure 3 are referred to fbrtn. vbg mux fbrtn 3.04v rn 0.0v fbrtn r1 r2 3.04v svid interface v dac 0.5v ~ 3.04v step = 10mv figure 3. v dac generator circuit for v core . the v dac voltage is expressed as: offse t vid v dac + = where vid and offset can be programmed by svid. table 4 illustrates the vid voltages according to vid code. table 3. thermal monitor a/d conversion erutarepmet ( o )c h21x0ger erutarepmet( tuodaer)enoz egatlovmt )5ccvot%( mt )v(egatlov )v5=5ccv( eton 5 71 01 6.5 70 87.3 2 83 07 0.9 73 59.3 5 87 02 4.0 81 20.4 8 8f 07 6.1 83 80.4 1 9f 14 8.2 82 41.4 4 9f 34 9.3 87 91.4 7 9f 76 9.4 88 42.4 tressa divs l amreht trela 00 1f f2 9.5 86 92.4 tressa # tohrv
up1651q 8 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( divs xeh v cad )v( 00x 00 0. 05 2x 06 8. 0a 4x 03 2. 1f 6x 00 6. 14 9x 07 9. 18 bx 03 3. 2c dx 09 6.2 10x 00 5. 06 2x 07 8. 0b 4x 04 2. 10 7x 01 6. 15 9x 08 9. 19 bx 04 3. 2d dx 00 7.2 20x 01 5. 07 2x 08 8. 0c 4x 05 2. 11 7x 02 6. 16 9x 09 9. 1a bx 05 3. 2e dx 01 7.2 30x 02 5. 08 2x 09 8. 0d 4x 06 2. 12 7x 03 6. 17 9x 00 0. 2b bx 06 3. 2f dx 02 7.2 40x 03 5. 09 2x 00 9. 0e 4x 07 2. 13 7x 04 6. 18 9x 01 0. 2c bx 07 3. 20 ex 03 7.2 50x 04 5. 0a 2x 01 9. 0f 4x 08 2. 14 7x 05 6. 19 9x 02 0. 2d bx 08 3. 21 ex 04 7.2 60x 05 5. 0b 2x 02 9. 00 5x 09 2. 15 7x 06 6. 1a 9x 03 0. 2e bx 09 3. 22 ex 05 7.2 70x 06 5. 0c 2x 03 9. 01 5x 00 3. 16 7x 07 6. 1b 9x 04 0. 2f bx 00 4. 23 ex 06 7.2 80x 07 5. 0d 2x 04 9. 02 5x 01 3. 17 7x 08 6. 1c 9x 05 0. 20 cx 01 4. 24 ex 07 7.2 90x 08 5. 0e 2x 05 9. 03 5 x 02 3. 18 7x 09 6. 1d 9x 06 0. 21 cx 02 4. 25 ex 08 7.2 a0x 09 5. 0f 2x 06 9. 04 5x 03 3. 19 7x 00 7. 1e 9x 07 0. 22 cx 03 4. 26 ex 09 7.2 b0x 00 6. 00 3x 07 9. 05 5x 04 3. 1a 7x 01 7. 1f 9x 08 0. 23 cx 04 4. 27 ex 00 8.2 c0x 01 6. 01 3x 08 9. 06 5x 05 3. 1b 7x 02 7. 10 ax 09 0. 24 cx 05 4. 28 ex 01 8.2 d0x 02 6. 02 3x 09 9. 07 5x 06 3. 1c 7x 03 7. 11 ax 00 1. 25 cx 06 4. 29 ex 02 8.2 e0x 03 6. 03 3x 00 0. 18 5x 07 3. 1d 7x 04 7. 12 ax 01 1. 26 cx 07 4. 2a ex 03 8.2 f0x 04 6. 04 3x 01 0. 19 5x 08 3. 1e 7x 05 7. 13 ax 02 1. 27 cx 08 4. 2b ex 04 8.2 01x 05 6. 05 3x 02 0. 1a 5x 09 3. 1f 7x 06 7. 14 ax 03 1. 28 cx 09 4. 2c ex 05 8.2 11x 06 6. 06 3x 03 0. 1b 5x 00 4. 10 8x 07 7. 15 ax 04 1. 29 cx 00 5. 2d ex 06 8.2 21x 07 6. 07 3x 04 0. 1c 5x 01 4. 11 8x 08 7. 16 ax 05 1. 2a cx 01 5. 2e ex 07 8.2 31x 08 6. 08 3x 05 0. 1d 5x 02 4. 12 8x 09 7. 17 ax 06 1. 2b cx 02 5. 2f ex 08 8.2 41x 09 6. 09 3x 06 0. 1e 5x 03 4. 13 8x 00 8. 18 ax 07 1. 2c cx 03 5. 20 fx 09 8.2 51x 00 7. 0a 3x 07 0. 1f 5x 04 4. 14 8x 01 8. 19 ax 08 1. 2d cx 04 5. 21 fx 00 9.2 61x 01 7. 0b 3x 08 0. 10 6x 05 4. 15 8x 02 8. 1a ax 09 1. 2e cx 05 5. 22 fx 01 9.2 71x 02 7. 0c 3x 09 0. 11 6x 06 4. 16 8x 03 8. 1b ax 00 2. 2f cx 06 5. 23 fx 02 9.2 81x 03 7. 0d 3x 00 1. 12 6x 07 4. 17 8x 04 8. 1c ax 01 2. 20 dx 07 5. 24 fx 03 9.2 91x 04 7. 0e 3x 01 1. 13 6x 08 4. 18 8x 05 8. 1d ax 02 2. 21 dx 08 5. 25 fx 04 9.2 a1x 05 7. 0f 3x 02 1. 14 6x 09 4. 19 8x 06 8. 1e ax 03 2. 22 dx 09 5. 26 fx 05 9.2 b1x 06 7. 00 4x 03 1. 15 6x 00 5. 1a 8x 07 8. 1f ax 04 2. 23 dx 00 6. 27 fx 06 9.2 c1x 07 7. 01 4x 04 1. 16 6x 01 5. 1b 8x 08 8. 10 bx 05 2. 24 dx 01 6. 28 fx 07 9.2 d1x 08 7. 02 4x 05 1. 17 6x 02 5. 1c 8x 09 8. 11 bx 06 2. 25 dx 02 6. 29 fx 08 9.2 e1x 09 7. 03 4x 06 1. 18 6x 03 5. 1d 8 x 00 9. 12 bx 07 2. 26 dx 03 6. 2a fx 09 9.2 f1x 00 8. 04 4x 07 1. 19 6x 04 5. 1e 8x 01 9. 13 bx 08 2. 27 dx 04 6. 2b fx 00 0.3 02x 01 8. 05 4x 08 1. 1a 6x 05 5. 1f 8x 02 9. 14 bx 09 2. 28 dx 05 6 . 2c fx 01 0.3 12x 02 8. 06 4x 09 1. 1b 6x 06 5. 10 9x 03 9. 15 bx 00 3. 29 dx 06 6. 2d fx 02 0.3 22x 03 8. 07 4x 00 2. 1c 6x 07 5. 11 9x 04 9. 16 bx 01 3. 2a dx 07 6. 2e fx 03 0.3 32x 04 8. 08 4x 01 2. 1d 6x 08 5. 12 9x 05 9. 17 bx 02 3. 2b dx 08 6. 2f fx 04 0.3 42x 05 8. 09 4x 02 2. 1e 6x 09 5. 13 9x 06 9.1 functional description table 4. intel svid table
up1651q 9 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com state transition figure 4 illustrates the state diagram of the up1651q. the up1651q initiates it soft start cycle whenever por transits from low to high. vrok are set high when soft start cycle completes and no fault occurs. when any faults occurs, the up1651q will be shutdown and latched off. the latch state can only be reset by por. controller por calibrate and initialize soft start ramp i vrok = high vboot not 0v v dac = setvid + offset soft start ramp ii protection por = l to reset por = l to reset v dac = vboot vboot = 0v soft start ramp i vrok = high v dac = setvid + offset figure 4. state diagram. soft start the up1651q features programmable soft start functions for vr. the soft start function limits the output voltage slew rate during both soft start and vid on the fly (vid_otf) periods as shown in figure 5. the soft start buffer is a current limited buffer whose output current i ss is used to charge/discharge the soft start capacitor c ss when v dac transition during soft start and vid_otf. this limits the slew rate of v dac/ss . consequently eap and fb pin voltages will follow the slew rate of v dac/ss . v dac fbrtn c s s eap dac/ss ss buffer fb v comp r drp figure 5. circuit for soft start and dynamic vid. the dac/ss level can be dynamically programmed by svid interface. power sequencefigure 6 shows the typical start up power sequence of vr12.5 for non-zero vboot. after vcc12 por, enable is set high to initialize the power sequence. because platform pull-up bias rail vtt is still not available, all open drain outputs are floating. after a delay time t1 (< 5ms) upon enable goes high, the pwm start switching and v out ramps up to vboot. the v out ramping time t2 is determined by vboot and setvid_slow slew rate. after v out ramps to vboot, pwm controller asserts vrok and alert# immediately. the delay time t3 from alert# assertion to vrok assertion is less than 6us. platform vtt then ramps up, and svid bus is active and idle. pwm controller waits for svid command. cpu then initializes svid clock, and sends out initial svid command sequence, reading varies svid registers. after that, cpu sends out setvid command to program vr output voltage. pwm controller acknowledges the setvid command and ramps the output voltage to the targeted vid at commanded slew rate. enable t1 t2 t3 v out = v dac/ss vrok (open drain) svid packet alert# open drain svid bus open drain vboot vcc12 por vtt pullup bias rail figure 6. vr12.5 typical power sequence dynamic vid the up1651q can accept vid input changes during normal operation. this allows the output voltage v out to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (vid_otf). a vid_otf may occur under either light or heavy load conditions. this change can be positive or negative. during vid_otf, v dac is a staircase waveform. in the up1651q, c ss is also used to filter the v dac/ss . by properly selecting c ss , vid_otf performance can be improved. output voltage differential sensing the up1651q uses differential sensing by a high-gain low- offset error amplifier as shown in figure 7. the cpu voltage is sensed between the fb and fbrtn pins. a functional description
up1651q 10 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com resistor r fb connects fb pin and the positive remote sense pin of the cpu v ccp . fbrtn pin connects to the negative remote sense pin of cpu v ccn directly. the error amplifier compares the v fb with v eap (= v dac/ss - i sum x r drp ) to regulate the output voltage. fb r fb v ccp eap r drp dac/ss c fb r 1 c 1 v ccn fbrtn comp i sum positive remote sense pin of cpu nagative remote sense pin of cpu gm v dac c ss i sum figure 7. circuit for v core differential sensing. channel current sensing the up1651q extracts phase currents for current balance and per channel over current protection by parasitic on- resistance of the lower mosfets when turn on as shown in figure 8. the isen1/2 pins sense the corresponding phase current when the lower mosfets are turned on. i senx = ((i phx x r ds(on) ) + v dc ) / r senx where i senx is the sampled and held phase current signal, i phx is phase current, r ds(on) is the on-resistance of the lower mosfets, and v dc is an internal 30mv offset voltage for the current balance circuit. the current balance circuit increases the pwm on time width of the phase whose phase current is smaller than others and decrease the pwm on time width of the phase whose phase current is larger than others. ph1 current balance ph2 isen1 isen2 i sen1 r sen1 r sen2 i sen2 figure 8. phase current sensing and current balance. total load current sensing the up1651q provides low input offset current sense amplifier (csa) to monitor the total load current flowing through inductor as shown in figure 9. r sw2 r sw1 1ohm1ohm v core v core ph1 ph2 csp r sum csn i sum c sum figure 9. total load current sensing. output current of csa (i sum ) is used for active voltage positioning (avp), load current monitoring and over current protection. r sw and c sum must be selected according to the below equation: n c r r l k sum sw dc = where r dc is the dcr of the output inductor, n is the phase number of operation. k is used for load transient response fine tune. theoretically, k should be equal to 1 to sense the instantaneous total load curret. but in real application, k is usually set to between 1.2 and 1.8 to obtain better load transient response. the relationship between sensed current i sum and total output current i out is shown as follows. n r r i i sum dc out sum = for a given vr maximum output current i max , r sum can be determined using above equation. droop (load line) setting the i sum is mirrored to eap pin as shown in figure 7. the voltage drop across r drp and makes v eap as: n r r r i v r i v v csn drp dc out ss / dac drp sum ss / dac eap = = in steady state, output voltage is equal to v eap . thus, the output voltage decreasing linearly with obtained i out . the loadline is defined as: n r r r i v l oadline sum drp dc out out = ? ? = functional description
up1651q 11 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com output current monitoringthe summed current i sum is mirrored to flow out of imon pin for output current reporting. connect a resistor r imon from the imon pin to gnd to obtain v imon voltage. the v imon voltage is proportional to the output current. the internal adc converts v imon to a digital content for current reporting. the adc outputs ffh when v imon is equal to or greater than 2v. a capacitor can be added to the imon pin to adjust the response time of current reporting. the resistor r imon can be determined as follows. n r r i r v2 sum dc max imon = output over current protection the summed current i sum is separately mirrored to the isum pin for svid iccmax alert and over current protection (ocp). connect a resistor r isum from the isum pin to gnd to get v isum voltage. the voltage v isum is proportional to the output current. for 2-phase configuration, when v isum reaches 2v, svid iccmax alert is triggered. when v isum is greater than 2v times the ocp ratio defined in table 2, ocp is triggered. when ocp is triggered, vrok will go low immediately, and the controller will turn off all mosfets and set the pwm output to high impedance state. the ocp has a 20us time delay to prevent false-tripping. the iccmax alert and ocp threshold is dependent on the configuration and operating phase number as shown in table 2. when the controller is in single-phase operation during svid setps command or psi setting, the iccmax alert and ocp threshold will be half of the original value of 2-phase operation. the change in iccmax alert and ocp threshold is to reflect the actual operating condition so as to provide proper protection. the ocp is latch-off type and can be reset only by por toggling. avoid adding capacitance to the isum pin. any capacitance added to the isum pin will affect the svid iccmax alert threshold and the ocp level. power saving mode and automatic phase reduction the ps pin is used for auto phase function setting by connecting a resistor voltage divider from vcc5 to gnd. the auto phase has one level, v ps , which can be calculated as below: () 2r 1r 2r 5 vcc v ps + = according v isum and v ps information, the up1651q operation phase number is as shown in table 5. when v ps = 0.3v and v isum = 0.25v, the up1651q turns off phase 2 and operates in 1-phase. the automatic phase reduction reduces the switching and conduction losses at light load condition and enables high efficiency over a wide range of output current. there is no time delay in operation phase number increase. when operation phase number drops, there is a delay of 300us, and a hysteresis of 50mv. refer to table 5, when up1651q operates in normal mode, the up1651q follows svid setps command to determine the power state as shown in table 6. when up1651q is configured to operate in forced 2-phase operation mode, it will ignore the svid setps command and keep 2-phase operation. when up1651q is configured to operate in auto psi mode, it will ignore the svid setps command and changes the operating phase number by v ps threshold setting. table 5. operation phase and auto psi mode edo ml evels pr ebmunesahpnoitarepo edomlamro nv sp v0= ,dnammocspteswollof 6elbatninwohssa llufdecrof noitarepoesahp sitluafed(edom sdneped,esahp-2 )noitarugifnocno v sp v5= noitarepoesahplluf ,esahp-2sitluafed( )noitarugifnocnosdneped edomispotua v sp v< musi noitarepoesahplluf ,esahp-2sitluafed( )noitarugifnocnosdneped v sp v> musi noitarepoesahp1 power state and operation mode definition the up1651q has different definition in power state and operation mode per enable voltage level. enable > 4v and enable < 4v has individual definition. the power state and operation mode definition is as shown in table 6. table 6. enable and power state definition enable > 4v noitarugifno ce sahp- 2e sahp-1 sptes divs etatsrewop 0s pm cchp- 2m cchp-1 1s pm cchp- 1m cchp-1 2s pm edhp- 1m edhp-1 3s pm edhp- 1m edhp-1 functional description
up1651q 12 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com enable < 4v noitarugifno ce sahp- 2e sahp-1 sptesdivs etatsrewop 0s pm cchp- 2m cchp-1 1s pm edhp- 1m edhp-1 2s pm edhp- 1m edhp-1 3s pm edhp- 1m edhp-1 control loop the up1651q adopts the upi proprietary rcot tm control technology. the rcot uses the constant on-time modulator. the output voltage is sensed to compare with the internal high accurate dac. the dac is commanded by cpu through the svid interface. the amplified error signal, v comp , is compared to the internal ramp to initiate a pwm on time. the rcot features easy design, fast transient response and smooth mode transition and is especially suitable for powering the microprocessor. over voltage protection (ovp) the over voltage protection monitors the output voltage via the fb pin. once v fb exceeds v eap + 300mv, ovp is triggered and latched. the up1651q will try to turn on lower mosfets and turn off upper mosfets to protect cpu. a 20us delay is used in ovp detection circuit to prevent false trigger. only re-start up can release ovp latch. under voltage protection (uvp) the under voltage protection monitors the output voltage via the fb pin. after the up1651q starting up and v out ramping up to v boot , the up1651q initiates uvp function. once v fb is lower than 200mv, uvp is triggered and latched. the up1651q will try to turn off both upper and lower mosfets. a 5us time delay is used in uvp detection circuit to prevent false trigger. only re-start up can release uvp latch. serialvid (svid) serialvid is a three wire (sclk,sdat,alert#) serial synchronous interface and used to transfer power management information between a micoprocessor and a vrm,the link is between one microprocessor and multiple vr controller on the same bus. the supported data register is shown in table 7. functional description
up1651q 13 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com xedn ie manretsige rs secc at luafe dn oitpircsed h0 0d i_redne vo rh 6 2d irednev h1 0d i_tcudor po rh 8 1d itcudorp h2 0n oisiver_tcudor po rh 5 0n oisivertcudorp h5 0n oisrev_locotor po rh 4 0n oisrevlocotorp divs h6 0y tilibapac_r vo rh 18 seitilibapacrv divsehtseifitnedi,retsigerdeppamtib .detroppuserayrtemeletlanoitpoehtfohcihwdna h0 11 _sutat sm w p-w,m- rh 0 0. rvfosutatsehtgniniatnocretsigeratad h1 12 _sutat sm w p-w,m- rh 0 0. noissimsnartfosutatsehtgniniatnocretsigeratad h2 1e noz_erutarepme tm w p-w,m- rh 00 neebevahtahtenozerutarepmetgniwohsretsigeratad .deretne h5 1t nerruc_tuptu om w p-w,m- r- - neebevahtahttnerructuptuoehtgniwohsretsigeratad .deretne hc 1d aertsal_2_sutat sm w p-w,m- rh 0 0. 2_sutatsehtfoypocasniatnocretsigersiht h1 2x am_cc im roftalp o r- - ehttnerructuptuo mumixam ehtgniniatnocretsigeratad .stroppusmroftalp h2 2x am_pme tm roftalp o rh 46 ehterutarepmetmumixam ehtgniniatnocretsigeratad nietamrofyranib.stroppusmroftalp o 001=h46.e.i,c o .c h4 2t saf_r so r ha0 ehtetarwelstsaffoytilibapacehtgniniatnocretsigerata d =ha0.e.i,su/vm nitamrofyranib.niatsusnacmroftalp .su/vm01 h5 2w ols_r so r h20 etarwelswolsfoytilibapacehtgniniatnocretsigeratad =h20.e.i,su/vm nitamrofyranib.niatsusnacmroftalpeht .su/vm5.2 h6 2t oob vm roftalp o r- -v gniniatnocretsigeratad toob .spetsdivniegatlov h0 3x am_tuo vr etsam w rh ff ehtstesdnaretsamybdem margorpsiretsigersiht .div mumixam h1 3g nittes_di vr etsam w rh 0 0. divdem margorpyltnerrucgniniatnocretsigeratad h2 3e tats_rewo pr etsam w rh 00 rewopdem margorpyltnerrucehtgniniatnocretsigeratad .etats h3 3t esff or etsam w rh 0 0. spetsdivnitesffotes h4 3g ifnoc_rv_itlu mr etsam w rh 00 srvelpitlum serugifnochcihwretsigerataddeppamtib .subemasehtnoroivaheb h5 3r etnio pr etsam w r- - ehtfoegarotsyraropmetrofretsigerdaphctarcs .retsigerretnioprdagertes functional description table 7. svid data and configuration registers
up1651q 14 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com (note 1) supply input voltage, vcc5 ------------------------------------------------------------------------------------------------ - 0.3v to +6v supply input voltage, vcc12 ----------------------------------------------------------------------------------------------- - 0.3v to +15v bootx to phx ------------------------------------------------------------------------------------------------------------------ -0.3v to +15v phx to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0.7v to 15v < 200ns --------------------------------------------------------------------------------------------------------------------- - 8v to 30v bootx to gnd dc ------------------------------------------------------------------------------------------------------------ -0.3v to vcc12 + 15v < 200ns ------------------------------------------------------------------------------------------------------------------- -0. 3v to 42v ugx to phx dc---------------------------------------------------------------------------------------------------- -0.3v to (bootx - phx + 0.3v) <200ns --------------------------------------------------------------------------------------------- -5v to (bootx - phx + 0.3 v) lgx to gnd dc ------------------------------------------------------------------------------------------------------ -0.3v to + (vcc12 + 0.3v) <200ns ------------------------------------------------------------------------------------------------------- -5v to vcc12 + 0.3v other pins -------------------------------------------------------------------------------------------------------------------- ------ -0.3v to +6v storage temperature ra nge ----------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------------------- 150 o c lead temperature (soldering, 10 sec) ----------------------------------------------------------------------------------------- ------- 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ---------------------------------------------------------------------------------------------------------------- 200v package thermal resistance (note 3) wqfn4x4 - 32l ja -------------------------------------------------------------------------------------------------------- 40 o c/w wqfn4x4 - 32l jc ---------------------------------------------------------------------------------------------------------- 4 o c/w power dissipation, p d @ t a = 25 o c wqfn4x4 - 32l -------------------------------------------------------------------------------------------------------------------- 2.5w (note 4) operating junction temperature ra nge ------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature ra nge --------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, vcc5 --------------------------------------------------------------------------------------------------- 4.5v to 5.5v supply input voltage, vcc12 --------------------------------------------------------------------------- 10.8v to 13.2v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
up1651q 15 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus dlohserhtrop5ccv 1. 43 . 45 . 4v siseretsyh rop5cc v. gnillaf5cc v- -3 . 0- -v tnerrucylppus5cc vi 5ccv v0=n e- -3- -a m dlohserhtrop21ccv 9. 41 . 53 . 5v siseretsyh rop21cc v. gnillaf21cc v- -1- -v tnerrucylppus21cc vi 21ccv v0=n e- -3 . 0- -a m reifilpmarorre egatlovtesff ov )ae(so 1 -- -1v m ecnatcudnoc-snar tm g- -0 05 1- -v /au tcudorphtdiwdnabnia gw bg ae ngisedybdeetnarau g- -0 1- -z hm )knis&ecruos(tnerruc mumixa mi pmoc 00 2- -- -a u ycaruccaegatlov cad ycaruccatuptuo ca dv ss/cad v40.3otv5. 15 .0 -- -5 . 0% v94.1otv 18 -- -8 v m v99.0otv5. 00 1 -- -0 1v m tratstfos tnerrucegrahcsid/egrahc ss/ca di ss tsaf_divte s0 8 10 0 20 4 2a u wols_divte s5 40 50 6a u tupnielbane woltupn iv li - -- -3 . 0v hgihtupn iv hi 7. 0- -- -v elbanefotnerrucegakae li elbane v0=elban e- -01a u v1=elban e1 -0- -a u gnittesemitno m w p emitn ot no v ni ,v7.1= div,v21= r tr mhok03= - -2 7 4- -s n emitffo mumini mt nim_ffo noitarepoesahpelgni s- -0 0 2- -s n poordrofreifilpmaesnestnerruc egatlovtesff ov )asc(so 1 -- -1v m tnerrucsaibtupn in gisedybdeetnarau g0 1 -- -0 1a n tcudorphtdiwdnabnia gg )asc(wb ngisedybdeetnarau g- -0 1- -z hm tnerrucgnicruos mumixa mi xamnsc 00 1- -- -a u ycaruccarorrimtnerru ci poord iot nsc oita r4 90 0 16 0 1% electrical characteristics (vcc5 = 5v, vcc12 = 12v, t a = 25 o c, unless otherwise specified)
up1651q 16 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu ecnalabtnerrucrofreifilpmaesnestnerruc egatlovtesff os ov )sccv( 2 20 30 4v m lennahcneewtebhctamsimtesffo 2 -02 +v m tcudorphtdiwdnabnia gg )sccv(wb ngisedybdeetnarau g- -0 1- -z hm noitcetedtnerruc orez dlohserht dc zv dcz egatlov1hperusae m1 -01v m #tohrv,#trela,tads ecnatsisernwodllu pr divs_no 4- -3 1 ? tnerrucegakael i divs_l 001 -- -0 0 1a u egatlov woltupn iv divs_li - -- -5 4. 0v egatlovhgihtupn iv divs_hi 56. 0- -- -v )korv(tuptuo niard nepo egatlov woltuptu ov lo i knis am4 =- -- -2 . 0v egakaelhgihtuptu ov korv v5 =- -- -1a u )musi,nomi(gnirotinomtnerruc tnerrucgnicruos mumixam 00 1- -- -a u ycaruccarorrimtnerruc musi,nom ii nomi i, musi iot nsc oita r4 90 0 16 0 1% ycarucca gnitropertnerruclatigid ecnarelotnoisrevnoc d/a v nomi )hff(v2ot)h00(v0= h51x0.gerdaer 2 -02 +c ed srevirdetag ecruosetagrepp ur crs_gu i gu am08- =- -24 ? knisetagrepp ur kns_gu i gu am08 =- -24 ? ecruosetagrewo lr crs_gl i gl am08- =- -24 ? knisetagrewo lr kns_gl i gl am08 =- -8 . 06 .1 ? emitdae dt td - -0 3- -s n )gorp(gnittestnerruc mumixam rv d/ an oisrevno cy carucc av gorp 5ccvfo4/1otv0 =2 -02 +c ed
up1651q 17 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu noitcetorp dlohserhtpv ov pvo v bf v- pae - -0 0 3- -v m yaled pv ot pvo - -0 2- -s u dlohserhtpv uv pvu pvuetulosb a- -0 0 2- -v m yaled pv ut pvu - -5- -s u dlohserhttrela xamcci v _musi xamcci erusaem,noitarepoesahp-2 egatlovmusi - -2- -v dlohserhtpcotnerruclato tv pco_musi ,%331otoitarpcotes egatlovmusierusaem - -6 6. 2- -v emityaled pcotnerruclato tt 1pco - -0 2- -s u dlohserhtpcotnerruclennah ci xnsc - -0 6- -a u emityaled pcotnerruclennah ct 2pco - -5- -s u dlohserhtnwodtuhslamreh tt pto - -0 6 1- - o c
up1651q 18 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com typical operation characteristics this page is intentionally left blank and will be updated later.
up1651q 19 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com application information this page is intentionally left blank and will be updated later.
up1651q 20 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wqfn4x4 - 32l 3.90 - 4.10 pin 1 mark bottom view - exposed pad 0.15 - 0.25 3.90 - 4.10 0.0 - 0.05 0.70 - 0.80 0.20 ref 2.30 - 2.80 2.30 - 2.80 0.30 - 0.50
up1651q 21 up1651q-ds-f00a0, apr. 2018 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2013, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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