1/9 USBUFXXW6 ? emi filter and line termination for usb upstream ports march 2002 - ed: 3a a.s.d. ? sot323-6l functional diagram tm: asd and transil are a trademarks of stmicroelectronics. emi filter and line termination for usb upstream ports on: - usb hubs - pc peripherals applications n monolithic device with recommended line termi- nation for usb upstream ports n integrated rt series termination and ct bypass- ing capacitors. n integrated esd protection n small package size features the usb specification requires upstream ports to be terminated with pull-up resistors from the d+ and d- lines to vbus. on the implementation of usb systems, the radiated and conducted emi should be kept within the required levels as stated by the fcc regulations. in addition to the requirements of termination and emc compatibility, the computing devices are required to be tested for esd susceptibility. the USBUFXXW6 provides the recommended line termination while implementing a low pass filter to limit emi levels and providing esd protection which exceeds iec61000-4-2 level 4 standard. the device is packaged in a sot323-6l which is the smallest available lead frame package (50% smaller than the standard sot23). description n emi / rfi noise suppression n required line termination for usb upstream ports n esd protection exceeding iec61000-4-2 level 4 n high flexibility in the design of high density boards n tailored to meet usb 1.1 standard benefits 3.3 v rp ct rt ct rt d1 grd d2 d4 d3 3.3 v rt rp ct code 01 33 w 1.5k w 47pf code 02 22 w 1.5k w 47pf tolerance 10% 10% 20%
USBUFXXW6 2/9 iec61000-4-2, level 4 15 kv (air discharge) 8 kv (contact discharge) mil std 883e, method 3015-7 class 3 c = 100 pf r = 1500 w 3 positive strikes and 3 negative strikes ( f=1hz) complies with the following esd standards: symbol parameter value unit v pp esd discharge iec 61000-4-2, air discharge esd discharge iec 61000-4-2, contact discharge esd discharge - mil std 883e - method 3015-7 16 9 25 kv kv kv t j maximum junction temperature 150 c t stg storage temperature range - 55 to +150 c t l lead solder temperature (10 second duration) 260 c t op operating temperature range 0to70 c p r power rating per resistor 100 mw absolute ratings (t amb = 25c) technical information host or hub port twisted pair shielded zo = 90ohms 5m max hub 0 or full-speed function untwisted unshielded 3m max full speed connection low speed connection 3.3v 3.3v d+ d- d+ d- d+ d- d+ d- 1.5k 1.5k hub 0 or low-speed function low-speed usb transceiver full-speed or low-speed usb transceiver 15k rt rt ct ct host or hub port full-speed or low-speed usb transceiver 15k rt rt ct ct rt rt ct ct full-speed usb transceiver rt rt ct ct 15k 15k fig. a1: usb standard requirements
USBUFXXW6 3/9 fig. a2: implementation of st' solutions for usb ports application example d+ d- cable host/hub usb por transceivert d- d+ d+ d- upstream port downstream port usbdf01w5 d+ d- rt d+ in gnd d- in d+ out d- out rt rd rd ct ct gnd 3.3 v rp ct rt ct rt d1 gnd d2 d4 d3 3.3v peripheral transceiver usbuf01w6 full speed connection d+ d- cable host/hub usb por transceivert d- d+ d+ d- upstream port downstream port usbdf01w5 d+ d- rt d+ in gnd d- in d+ out d- out rt rd rd ct ct gnd 3.3 v rp ct rt ct rt d1 gnd d2 d4 d3 3.3v peripheral transceiver usbuf01w6 low speed connection
USBUFXXW6 4/9 current fcc regulations requires that class b computing devices meet specified maximum levels for both radiated and conducted emi. - radiated emi covers the frequency range from 30mhz to 1ghz. - conducted emi covers the 450khz to 30mhz range. for the types of devices utilizing the usb, the most difficult test to pass is usually the radiated emi test. for this reason the USBUFXXW6 device is aiming to minimize radiated emi. the differential signal (d+ and d-) of the usb does not contribute significantly to radiated or conducted emi because the magnetic field of both conductors cancels each other. the inside of the pc environment is very noisy and designers must minimize noise coupling from the different sources. d+ and d- must not be routed near high speed lines (clocks spikes). induced common mode noise can be minimized by running pairs of usb signals parallel to each other and running grounded guard trace on each side of the signal pair from the usb controller to the usbuf device. if possible, locate the usbuf device physically near the usb connectors. distance between the usb con- troller and the usb connector must be minimized. the 47pf (ct) capacitors are used to bypass high frequency energy to ground and for edge control, and are placed between the driver chip and the series termination resistors (rt). both ct and rt should be placed as close to the driver chip as is practicable. the USBUFXXW6 ensures a filtering protection against electromagnetic and radiofrequency interferences thanks to its low-pass filter structure. this filter is characterized by the following parameters : - cut-off frequency - insertion loss - high frequency rejection. emi filtering 1 10 100 1,000 -30 -20 -10 0 frequency (mhz) s21 (db) fig. a3: USBUFXXW6 typical attenuation curve. test board 50 w vg 50 w uux fig. a4: measurement configuration in addition to the requirements of termination and emc compatibility, computing devices are required to be tested for esd susceptibility. this test is described in the iec 61000-4-2 and is already in place in europe. this test requires that a device tolerates esd events and remains operational without user intervention. the USBUFXXW6 is particularly optimized to perform esd protection. esd protection is based on the use of device which clamps at : vv ri cl br d pp =+ . this protection function is splitted in 2 stages. as shown in figure a5, the esd strikes are clamped by the first stage s1 and then its remaining overvoltage is applied to the second stage through the resistor rt. such a configuration makes the output voltage very low at the output. esd protection
USBUFXXW6 5/9 esd surge vinput voutput rload rg rt s1 rd v br v br v pp device to be protected usbuf01w6 rd s2 fig. a5: USBUFXXW6 esd clamping behavior test board esd surge 16kv air discharge vin vout uux fig. a6: measurement board to have a good approximation of the remaining voltages at both vin and vout stages, we give the typical dynamical resistance value rd. by taking into account these following hypothesis : rt>rd, rg>rd and rload>rd, it gives these formulas: vinput rv rv r gbr dg g = + .. voutput r v r vinput r tbr d t = + .. the results of the calculation done for vg=8kv, rg=330 w (iec61000-4-2 standard), v br =7v (typ.) and rd = 1 w (typ.) give: vinput = 31.2 v voutput = 7.95 v this confirms the very low remaining voltage across the device to be protected. it is also important to note that in this approximation the parasitic inductance effect was not taken into account. this could be few tenths of volts during few ns at the vinput side. this parasitic effect is not present at the voutput side due the low current involved after the resistance rt. the measurements done hereafter show very clearly (fig. a7) the high efficiency of the esd protection : - no influence of the parasitic inductances on voutput stage - voutput clamping voltage very close to v br (breakdown voltage) in the positive way and -v f (forward voltage) in the negative way
USBUFXXW6 6/9 fig. a7: remaining voltage at both stages s1 (vinput) and s2 (voutput) during esd surge. vin vout a. positive surge b.negative surge vin vout please note that the USBUFXXW6 is not only acting for positive esd surges but also for negative ones. for these kinds of disturbances it clamps close to ground voltage as shown in fig. a7b. the early ageing and destruction of ics is often due to latch-up phenomenon which is mainly induced by dv/dt. thanks to its structure, the USBUFXXW6 provides a high immunity to latch-up phenomenon by smoothing very fast edges. latch-up phenomena crosstalk behavior line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers ab 1g1 12g2 v+ v ab 2g2 21g1 v+ v fig. a8: crosstalk phenomenon the crosstalk phenomenon is due to the coupling between 2 lines. the coupling factor ( b 12 or b 21 ) in- creases when the gap across lines decreases, particularly in silicon dice. in the example above the ex- pected signal on load r l2 is a 2 v g2 , in fact the real voltage at this point has got an extra value b 21 v g1 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency ana- log signals in the disturbing line. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k w ).
USBUFXXW6 7/9 vg 50 w 50 w test board uux fig. a9: analog crosstalk measurements 1 10 100 1,000 -100 -80 -60 -40 -20 0 frequency (mhz) analog crosstalk (db) fig. a10: typical analog crosstalk results figure a9 gives the measurement circuit for the analog crosstalk application. in figure a10, the curve shows the effect of the d+ cell on the d- cell. in usual frequency range of analog signals (up to 100mhz) the effect on disturbed line is less than -37db. d+ d- v g1 v g1 +5v +5v 74hc04 +5v square pulse generator 74hc04 b 21 3.3 v rp ct rt ct rt d1 gnd d2 d4 d3 3.3 v fig. a11: digital crosstalk measurements configuration v g1 b 21 g1 v fig. a12: digital crosstalk results figure a11 shows the measurement circuit used to quantify the crosstalk effect in a classical digital appli- cation. figure a12 shows, with a signal from 0 to 5v and rise time of few ns, the impact on the disturbed line is less than 250mv peak to peak. no data distur- bance was noted on the other line.the measure- ments performed with falling edges gives an impact within the same range.
USBUFXXW6 8/9 figure a13 shows the circuit used to perform measurements of the transition times. in figure a14, we see the results of such measurements: trise = 3.8ns driver alone trise = 7.8ns with protection device the adding of the protection device causes the rise time increase of roughly 4ns. note : rise time has been measured between 10% and 90% of the signal (resp. 90% and 10%) d+ d- +5v +5v +5v 74hc04 +5v square pulse generator 74hc04 usbuf -xxw6 v d+ fig. a13: typical rise and fall times: measure- ments configuration without with fig. a14: typical rise times with and without pro- tection device this low pass filter has been designed in order to meet the usb 1.1 standard requirements that implies the signal edges are maintained within the 4ns-20ns stipulated usb specification limits. to verify this point, we have measured the rise time of vd+ voltage (please refer to fig. a13) with and without the USBUFXXW6 device. transition times
USBUFXXW6 9/9 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore spain - sweden - switzerland - united kingdom - united states. http://www.st.com package mechanical data. sot323-6l a2 a a1 e b h d e e q c ref. dimensions millimeters inches min. max. min. max. a 0.8 1.1 0.031 0.043 a1 0 0.1 0 0.004 a2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 d 1.8 2.2 0.071 0.086 e 1.15 1.35 0.045 0.053 e 0.65 typ. 0.025 typ. h 1.8 2.4 0.071 0.094 q 0.1 0.4 0.004 0.016 0.3mm 1mm 1mm 0.35mm 2.9mm recommended footprint (mm) lead plating tin-lead lead plating thickness 5 m m min 25 m m max lead material sn / pb (70% to 90%sn) lead coplanarity 10 m m max body material molded epoxy flammability ul94v-0 mechanical specifications ordering code marking package weight base qty delivery mode usbuf01w6 uu1 sot323-6l 5.4 mg 3000 tape & reel usbuf02w6 uu2 sot323-6l 5.4 mg 3000 tape & reel marking
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