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| 1. general description the TEA19161T is a fully digital controller for high-efficiency resonant power supplies. together with the tea19162t pfc controller and the tea1995t dual sr controller, a complete resonant power supply can be built which is easy to design and has a very low component count. this power supply meets the efficiency regulations of energy star, the department of energy (doe), the eco-design directive of the european union, the european code of conduct, and other guidelin es. so, any auxiliary low-power supply can be omitted. in contrast to traditional resonant topologies, the TEA19161T (llc) shows a high efficiency at low loads due to the newly intr oduced low-power mode. this mode operates in the power region between continuous switching (also called high-power mode) and burst mode. because the TEA19161T is regulated via the primary capacitor voltage, it has accurate information about the power delivered to the output. the measured output power defines the mode of operation (burst mode, low-power mode or high-power mode). a configuration pin can easily set the tr ansition levels of the operating modes. the TEA19161T contains a low-voltage die with a fully digital controller for output power control, start-up, init ializations, and protections. thes e protections include overcurrent protection (ocp), overvoltage protecti on (ovp), open-loop protection (olp), and capacitive mode regulation (cmr). it also contains a high-voltage silicon-on-insulator (soi) controller for high-voltage start-up, integr ated drivers, level shifter, protections, and circuitry assuring zero-voltage switching. the TEA19161T is designed to cooperate with the tea19162t power factor control (pfc) controller. for communications about start-up and protections, the TEA19161T contains a digital control interface. the digital control enables a fast latch reset mechanism. it maximizes the overall system ef ficiency at low output power levels by setting the tea19162t to operate in burst mode. the TEA19161T/tea19162t/tea1995t combi nation gives an easy to design, highly efficient and reliable power supply, providin g 90 w to 500 w, with a minimum of external components. the system provides a very low no-load input power (< 75 mw; total system including the TEA19161T/tea19162t/tea1995t combination) and high efficiency from minimum to maximum load. so, any additional low-power supply can be omitted, ensuring a significant system cost saving and highly simplified power supply design. TEA19161T digital controller for high-efficiency resonant power supply rev. 1 ? 10 march 2016 product data sheet
TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 2 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 2. features and benefits 2.1 distinctive features ? complete functionality as a combination with tea19162t ? integrated high-voltage start-up ? integrated high-voltage level shifter (ls) ? extremely fast start-up (< 500 ms at v mains =100v(ac)) ? continuously v supic regulation via the suphv pin during start-up and protection, allowing minimum supic capacitor values ? operating frequencies are outside the audible area at all operating modes ? integrated soft start ? power good function ? maximum 500 khz half-bri dge switching frequency 2.2 green features ? extremely high efficiency from low load to high load ? compliant with energy using product directive (eup) lot 6 ? excellent no-load input power (< 75 mw for TEA19161T/tea19162t/tea1995t combination) ? regulated low optocurrent, enabling low no-load power consumption ? very low supply current during non-switching state in burst mode ? transition between different operation modes (high-power/low-power/burst mode) occur at integrated, externally adjustable power levels ? adaptive non-overlap time 2.3 protection features ? supply undervoltage protection (uvp) ? overpower prot ection (opp) ? integrated adjustable overpower time-out ? adjustable latch or restart function for overpower protection ? on-chip overtemperature protection (otp) ? capacitive mode regulation (cmr) ? accurate overvoltage protection (ovp) ? maximum on-time protection for low- side and high-side driver output ? overcurrent protection (ocp) ? disable input 3. applications ? desktop and all-in-one pcs ? lcd television ? notebook adapter ? printers TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 3 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 4. ordering information table 1. ordering information type number package name description version TEA19161T so16 plastic small outline package; 16 leads; body width 3.9 mm; body thickness 1.47 mm sot109-3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 4 of 46 nxp semiconductors TEA19161T digital controller for high-efficiency resonant power supply 5. block diagram fig 1. block diagram & 2 1 7 5 2 / / 2 * , & 6 2 ) 7 6 7 $ 5 7 3 2 : ( 5 & 2 1 7 5 2 / 6 : , 7 & + , 1 * 6 7 $ 7 ( 0 $ & + , 1 ( 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 7 ( $ $ ' $ ' 9 % 8 5 6 7 & < & / ( 6 9 $ / / ( < 3 ( $ . ' ( 7 ( & 7 3 2 7 3 / 6 d d d 9 6 1 6 ) % 6 ( 7 7 , 1 * 6 & 2 1 7 5 2 / 3 ) & & 2 1 7 5 2 / ) ( ( ' % $ & . & 2 1 7 5 2 / 2 3 ( 5 $ 7 , 2 1 0 2 ' ( 3 ) & e x u v w v h w w l q j 6 1 6 6 ( 7 6 1 6 % 2 2 6 7 , , , , 3 ) & s u r w h f w l r q v w d u w x s 6 1 6 2 8 7 & 2 1 7 5 2 / ' 5 , 9 ( 5 6 6 : , 7 & + , 1 * & 2 1 7 5 2 / v h w w l q j , v x s l f b f k d u j h 6 8 3 + 9 6 8 3 , & 6 8 3 5 ( * 8 9 3 6 8 3 , & 8 9 3 6 8 3 5 ( * , e l d v 6 1 6 & $ 3 l q w h u q d o v x s s o l h v 9 6 8 3 3 / < 6 1 6 2 8 7 * $ 7 ( / 6 * d w h + 6 * d w h / 6 6 1 6 & $ 3 6 1 6 & 8 5 2 & 3 + % 9 * $ 7 ( + 6 * d w h + 6 6 8 3 5 ( * * d w h / 6 6 8 3 + 6 3 o r z s z u v u t o r z s r z h u p r g h 9 e x u v w r q 9 9 n n 9 9 7 & 0 5 9 v h w w l q j TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 5 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 6. pinning information 6.1 pinning 6.2 pin description fig 2. TEA19161T pin configuration (sot109-3) , & 6 8 3 , & 6 1 6 % 2 2 6 7 6 1 6 ) % 6 1 6 & $ 3 6 1 6 2 8 7 6 1 6 & 8 5 * 1 ' 6 1 6 6 ( 7 6 8 3 5 ( * q f * $ 7 ( / 6 + % q f 6 8 3 + 6 6 8 3 + 9 * $ 7 ( + 6 d d d table 2. pin description symbol pin description supic 1 input supply voltage and output of internal hv start-up source; externally connected to an auxiliary winding of the llc via a diode or to an external dc supply snsfb 2 output voltage regulation feedback sense in put; externally connected to an optocoupler snsout 3 sense input for setting the burst frequency and monitoring the llc output voltage; externally via a resistive divider and a diode connected to the auxiliary winding gnd 4 ground supreg 5 regulated supreg ic supply; internal regulator output; input for drivers; externally connected to supreg buffer capacitor gatels 6 llc low-side mosfet gate driver output n.c. 7 not connected suphv 8 internal hv start-up source high-voltage supp ly input; externally connected to (pfc) boost voltage gatehs 9 llc high-side mosfet gate driver output suphs 10 high-side driver supply input; exte rnally connected to bootstrap capacitor (c suphs ) hb 11 low-level reference for high-side driver and input fo r half-bridge slope detection; externally connected to half-bridge node hb between the llc mosfets n.c. 12 not connected snsset 13 settings for transition levels high/low pow er mode and low-power/burst mode, overpower level, overpower time-out, and restart or la tched. output of the power good signal. snscur 14 llc current sense input; externally connected to the resonant current sense resistor snscap 15 llc capacitor voltage sense input; externally connected to divider across llc capacitor snsboost 16 sense input for boost voltage; output for pfc burst control; externally connected to resistive divided boost voltage TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 6 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7. functional description 7.1 supply voltages the TEA19161T includes: ? a high-voltage supply pin for start-up (suphv) ? a general supply to be connected to an external auxiliary winding (supic pin) ? an accurate regulated voltage (supreg pin) ? a floating supply for the high-side driver (suphs pin) 7.1.1 start-up and supply voltage initially, the capacitors on the supic and su preg pins are charged via the suphv pin. the suphv pin is connected to the output vo ltage of a pfc via an external resistor. internally, a high-voltage series switch is located between the suphv and supic pins. from the supic pin, the supreg pin is supplied using a linear regulator (see figure 3 ). initially, when the voltage on the su pic pin is below the reset level v rstsupic) (3.5 v), the supic charge current is internally limited to i lim(suphv) (0.75 ma). in this way, the dissipation is limited when supic is shorte d to ground. when the voltage on the supic pin exceeds v rst(supic) , the internal switch is closed. to limit the ic power dissipation, an external resistor (r suphv ) is required to reduce the voltage drop between the suphv and supic pins when charging the supic capacitor. r suphv must be dimensioned such that the maximum current is limited to below limiting value i suphv (20 ma) and it can handle the required power dissipation. the maximum power dissipation of the external resistor can be reduced by using several resistors in series. fig 3. TEA19161T hv start-up d d d , & 6 8 3 , & 9 e r r v w 6 8 3 + 9 v x s l f b f k d u j h 9 l q w u h j g 6 8 3 5 ( * 5 6 8 3 + 9 f x u u h q w o l p l w h u & 6 8 3 , & & 6 8 3 5 ( * 9 u v w 6 8 3 , & 6 8 3 5 ( * TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 7 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when the supic reaches the v start(supic) level (19.1 v), it is continuously regulated to this start level with a hysteresis (v start(hys)supic ; ? 0.7 v). it activates the switch between the suphv and supic pins when the supic voltage drops to below v start(supic) +v start(hys)supic . it deactivates the switch when it exceeds v start(supic) . when start-up is complete and the llc controller is operating, the llc transformer auxiliary winding supplies the supic pin. in this operational state, the hv start-up source is disabled (see figure 4 ). when the system enters the pr otection mode, the supic pin is also regulated to the start level. during the non-switchin g period of the burst mode, th e system also activates the switch between the suphv and supic pins when the supic voltage drops below v low(supic) . it regulates the voltage with a hysteresis of v low(hys)supic . in this way, the system avoids that the supic undervoltage protection (v uvp(supic) ) is triggered because of a long non-switching period in burst mode. fig 4. start-up sequence and normal operation d d d q r v x s s o \ u h d g r x w v h w w l q j v r i i 3 ) & v w d u w x s / / & v w d u w x s r s h u d w l q j , 6 1 6 ) % ! , u h j 6 1 6 ) % 9 v w d u w 6 1 6 % 2 2 6 7 9 v w d u w 6 8 3 , & v x s l f b f k d u j h o 6 8 3 , & 9 6 8 3 , & o o l p 6 8 3 + 9 p $ s x o o g r z q b v q v e r r v w 6 1 6 % 2 2 6 7 p r g h r i r s h u d w l r q 9 r x w 9 v w d u w k \ v 6 8 3 , & 9 u v w 6 8 3 , & r i i r q r q TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 8 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.1.2 regulated supply (supreg pin) the voltage range on the supic pin exceeds that of the maximum external mosfets gate-source voltage. so, the TEA19161T inco rporates an integrated series stabilizer. the series stabilizer creates an accurate regulated voltage (v intregd(supreg) =11v) at the buffer capacitor c supreg . the stabilized voltage is used to: ? supply the internal low-side llc driver ? supply the internal high-side driver using external components ? as a reference voltage for optional external circuits to ensure that the external mosfets receive sufficient gate drive, the voltage on the supreg pin must reach v uvp(supreg) before the system starts switching. if the supreg voltage drops to below this undervoltage protection level, the system restarts. 7.1.3 high-side driver floating supply (suphs pin) external bootstrap buffer capacitor c suphs supplies the high-side driver. the bootstrap capacitor is connected between the high-sid e driver supply, the suphs pin, and the half-bridge node, hb. c suphs is charged from the supreg pin using an external diode d suphs (see figure 27 ). careful selection of the appropriate diode minimizes the voltage drop between the supreg and suphs pins, especially wh en large mosfets and high switching frequencies are used. a large voltage drop across the diode reduces the gate drive of the high-side mosfet. TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 9 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.2 system start-up figure 5 shows the flow diagram corresponding with figure 4 . when the supic or supreg pins drop to be low their stop levels, the TEA19161T enters the no supply state. it recharges the supic an d supreg pins to their start levels via the suphv pin. when the start levels are reached, measuring the external resistances on the snsset, snsout, and gatels pins initializes the settings. during the no supply and readout settings states, the snsboost pin is pulled low, disabling the tea19162t pfc. when the settings have been defined, the snsboost pin is released and the pfc starts up. when the snsboost reaches the minimum level v start(snsboost) , the llc starts switching. when a small optocurrent is detected (i snsfb TEA19161T llc controller flow diagram d d d 1 2 6 8 3 3 / < 9 6 8 3 , & 9 x y s 6 8 3 , & r u 9 6 8 3 5 ( * 9 x y s 6 8 3 5 ( * d o o v h w w l q j v g h i l q h g 9 6 1 6 % 2 2 6 7 ! 9 v w d u w 6 1 6 % 2 2 6 7 3 ) & g l v d e o h g y l d 6 1 6 % 2 2 6 7 5 ( $ ' 2 8 7 6 ( 7 7 , 1 * 6 3 ) & 6 7 $ 5 7 8 3 / / & 6 7 $ 5 7 8 3 2 3 ( 5 $ 7 , 1 * 6 8 3 , & u h j x o d w h g y l d 6 8 3 + 9 9 6 8 3 , & ! 9 v w d u w 6 8 3 , & d q g 9 6 8 3 5 ( * ! 9 x y s 6 8 3 5 ( * , 6 1 6 ) % ! , u h j 6 1 6 ) % TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 10 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.3 llc system regulation a typical resonant controller regulates th e output power by adapting the operating frequency. if the power drops and so the voltage of the llc converter exceeds the targeted regulation level (12 v or 19.5 v typical), the optocurrent increases and the voltage at the snsfb decreases (see figure 6 ). the resonant controller then increases the frequency according to its internal frequency control cu rve. because of the higher frequency, the power to the output is reduced and the outp ut voltage drops. if the output voltage becomes too low, the controller lowers the system frequency, increasing the output power. in this way, the system regulates the output power to the required level. as a small change in frequency gives a significant change in output power, frequency control has a high gain of the control loop. to increase the efficiency at low loads, most converters switch to burst mode as soon as the output power is below a minimum level. the burst mode level is most ly derived from the voltage on the snsfb pin. for a frequency controlled resonant converter, it implies that the burst mode is entered at a certain frequency instead of at a certain load. a small variation of the resonant components then results in a significant variat ion in power level at which the burst mode is activated. in the TEA19161T, the control mechanism is different. the advantage is a constant gain of the control loop and a burst mode which is derived from the output power. the TEA19161T does not regulate the output power by adjusting the frequency but by the voltage across the primary capacitor. fig 6. resonant frequency controller d d d ) 5 ( 4 8 ( 1 & < & 2 1 7 5 2 / i u h t x h q f \ i p d [ i p l q 9 6 1 6 ) % / 6 w u d i r p r g h o * $ 7 ( + 6 9 e r r v w * $ 7 ( / 6 9 6 1 6 ) % 6 8 3 5 ( * 6 1 6 % 8 5 6 7 / v & u / p ' 9 r x w ' TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 11 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply the input power (related to the output power) of a resonant converter can be calculated with equation 1 : (1) equation 1 shows that the input power has a linear relationship with the capacitor voltage difference ? v cr . figure 7 shows an alternative explanation of the linear relationship between the input power and the energy stored in the resonant capacitor. when the high-side switch is on, a primary current is flowing through the transformer and resonant capacitor c r as indicated by the red line. half the energy the input delivers is transferred to the output. the other half charges resonant capacitor c r . the voltage across the resonant capacitor increases. when the high-side switch is off and the low-si de switch is on, the energy which is stored in resonant capacitor c r is transferred to the output and its voltage decreases. in this way, the linear relationship between the increase of the resonant capacitor voltage and the output power can be seen. although the TEA19161T uses the primary capacitor voltage as a regulation parameter, all application values, like the resonant inductances, resonant capacitor, and primary mosfets remain unchanged compared to a frequency controlled llc converter. a secondary tl431 circuitry in combination with an optocoupler connected to the primary snsfb pin continuously regulates the output voltage. fig 7. linear relationship between in put power and energy stored in c r p in v boost i boost ? v boost ? v cr c r f sw ??? == d d d 9 r x w 9 e r r v w / p & u / v + % * $ 7 ( + 6 * $ 7 ( / 6 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 12 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.3.1 output power regulation loop figure 8 shows the output power regulation loop of v cap control as used by the TEA19161T. figure 9 shows a corresponding timing diagram. when the divided resonant capacitor voltage (v snscap ) exceeds the capacitor voltage high level (v hs(snscap) ), the high-side mosfet is switched off (see figure 9 (t1). after a short delay, the low-side mosfet is switched on. because of the resonant current, the resonant capacitor voltage initially in creases further but eventually drops. fig 8. regulation loop v cap control fig 9. timing diagram of the regulation loop d d d / 6 t t q 9 k v 6 1 6 & $ 3 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 ' ' 9 o v 6 1 6 & $ 3 , 6 1 6 ) % v u , & 9 f d s & 2 1 7 5 2 / e x u v w * $ 7 ( + 6 9 e r r v w w u d i r p r g h o 9 r x w * $ 7 ( / 6 & u / v / p 6 1 6 & $ 3 6 1 6 ) % 9 , e x u v w , 6 1 6 ) % 9 6 1 6 & $ 3 d d d , o r d g , 6 1 6 ) % , u h j 6 1 6 ) % ? $ * $ 7 ( / 6 * $ 7 ( + 6 w w 9 o v 6 1 6 & $ 3 9 6 1 6 & $ 3 9 k v 6 1 6 & $ 3 w TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 13 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when the divided capacitor voltage (v snscap ) drops to below the capacitor voltage low level (v ls(snscap) ), the low-side mosfet is switched off (see figure 9 (t2)). after a short delay, the high-side mosfet is switched on. figure 9 shows that the switching frequency is a result of this switching behavior. in a frequency controlled system, the frequency is a control parameter and the output power is a result. the TEA19161T regulates the power and the frequency is a result. the difference between the high and low capacitor voltage level is a measure of the delivered output power. the value of the primary optocurrent, defined by the secondary tl431 circuitry, determines the difference between the high and low capacitor voltages. figure 9 also shows the behavior at a transient. if the output load increases, the current pulled out of the snsfb pin decreases. the result is that the TEA19161T increases the high-level capacitor voltage and lowers the low-level capacitor vo ltage. according to equation 1 , the output power increases and eventua lly the output voltage increases to its regulation level. to minimize no-load input powe r of the system, the primary current into the optocoupler is continuously regulated to 85 ? a (see section 7.5 ). 7.3.2 output voltage start-up the system controls the output power by regulating the primary v cr (see section 7.3 ). when the system is in regula tion and the output voltage is stabilized, a small change in ? v cr corresponds to a small change in the output current (see equation 2 ). (2) however, before start-up, when the output voltage is around zero, a small capacitor voltage increase ( ? v cr ) corresponds to a substantial output current increase. so, at start-up, the divided ? v cr voltage ( ? v snscap ) is slowly increased from a minimum value to the regulation level. as a resu lt, the system starts up at a higher frequency. the gatels resistor sets the starting value of the ? v snscap . p out v out i out v boost i boost ?? ?? v cr c r f sw v boost ??? == i out c r f sw ? v boost ? ? v cr v out ------------ - ? ? TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 14 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.4 modes of operation figure 10 shows the control curve between the ou tput power and the voltage difference between the high and low capacitor voltage levels. when the output power (p out ) is at its maximum, the low capacitor voltage level (v ls(snscap) ) is at its minimum and the high capacitor voltage (v hs(snscap) ) is at its maximum level. according to equation 1 , the maximum ? vsnscap (v hs(snscap) ? v ls(snscap) ), which is the divided ? v cr voltage, corresponds to the maximum output power. when the output load decreases, the ? v snscap voltage decreases. as a result, the output power decreases and the output voltage is regulated. this mode is called high-power mode. when the output power drops to below the transition level (p t(lp) ), the system enters the low-power mode. external components can set the applied p t(lp) level (see section 7.7.3 ). fig 10. TEA19161T control curve d d d 9 6 1 6 & $ 3 3 r x w w o s 9 6 1 6 & $ 3 & 2 1 7 5 2 / o r z s r z h u s h u l r g k l j k s r z h u p r g h o r z s r z h u p r g h e x u v w p r g h i u 3 w o s 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 9 6 1 6 & $ 3 3 r x w p d [ 3 r x w p d [ i o s p l q TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 15 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply to compensate for the hold period, ? v snscap is initially increa sed at entering the low-power mode (see section 7.4.2 ). in low-power mode, the output power is initially regulated by adapting ? v snscap , until it reaches a minimum. then, the output power is regulated by lowering the duty cycle of the low-power mode with a fixed ? v snscap until the period time of a low-power cycle reaches a maximum (1 / f lp(min) ). the system enters the burst mode (see section 7.4.3 ). TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 16 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.4.1 high-power mode in high-power mode, the system operates as described in section 7.3.1 . figure 11 shows a flow diagram of the high-power mode. fig 11. high-power mode flow diagram d d d * $ 7 ( / 6 r q * $ 7 ( + 6 r i i * $ 7 ( / 6 r i i * $ 7 ( + 6 r i i w ! w r q p l q w ! w q r p l q w ! w q r p d [ o s u l p ? ( q g r i + % v o r s h o s u l p o r f s 9 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 9 6 1 6 & $ 3 ! 9 k v 6 1 6 & $ 3 w ! w r q p d [ o s u l p ! o u h j f d s p * $ 7 ( / 6 r i i * $ 7 ( + 6 r q w ! w r q p l q o s u l p ! o r f s w ! w r q p d [ o s u l p o u h j f d s p v h w w l q j v h [ l w f r q g l w l r q h [ s o d q d w l r q i o r z g l d j u d p v h w w l q j v d f w l r q v w d n h q z k h q w k h v \ v w h p l v l q w k l v v w d w h h [ l w f r q g l w l r q h [ l w f r q g l w l r q k d v w r e h i x o i l o o h g d q g r q h r i w k h h [ l w f r q g l w l r q v [ h [ l w f r q g l w l r q e h [ l w f r q g l w l r q d h [ l w f r q g l w l r q g h [ l w f r q g l w l r q f * $ 7 ( / 6 r i i * $ 7 ( + 6 r i i w ! w q r p l q w ! w q r p d [ o s u l p ? ( q g r i + % v o r s h 6 \ v w h p r i i TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 17 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when the system is off, gatels is on and gatehs is off. the external bootstrap buffer capacitor (c suphs ) is charged via the supreg pin and an external diode. the system remains in this state for at least the minimum on-time (t on(min) ) of gatels. before entering the next state, one of the follo wing conditions must be fulfilled: ? the v snscap voltage drops to below the minimum v snscap voltage (v ls(snscap) ) ? the measured current exceeds the ocp level (see section 7.6.6 ) ? the system is close to capacitive mode (see section 7.6.5 ) ? the maximum on-time (t on(max) ), a protection that maximizes the time the high-side or low-side mosfet is kept on, is exceeded. in the next state, to avoid false detection of the hb peak voltage, the system waits until the minimum non-overlap time (t no(min) ) is exceeded. when it is exceeded, the system starts to detect the end (= peak voltage) of the hb node. when it detects the peak of the hb node and the measured resonant current is neg ative (or zero), it en ters the next state. if the system does not detect a peak at the hb node, it also enters the next state when the maximum non-overlap time (t no(max) ) is exceeded under the condition of a negative (or zero) resonant current. finally, the third and fourth states (see figure 11 ) describe the gatehs and gatehs to gatels transition criteria which are the inverse of the first two states. 7.4.2 low-power mode at low loads, the operating frequency of a resonant converter increases. as a result, the magnetization and switching loss es increase. for this reason, the efficiency of a resonant converter drops at low loads. a newly introduced low-power mode ensures high efficiency at lower loads as well. when the output power drops to below the p t(lp) level, the system enters the low-power mode (see figure 10 and figure 12 ). it continues switching fo r 3 half-cycles (low-side, high-side, low-side) with a fixed duty cycle of 67 %. to ensure a constant output power level, it increases the energy per cycle (v hs(snscap) ? v ls(snscap) ) at the same time. so 1/3 of the time the converter is in a "hold" period. the result is a 33 % magnetization and switching losses reduction. TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 18 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply as the system continuously tracks the primary capacitor voltage, it knows exactly when to enter the "hold" period. it can also continue again at exactly the correct voltage and current levels of the resonant converter. in this way, a "hold" period can be introduced which reduces the magnetizat ion and switching losses withou t any additional losses. the currents i d1 and i d2 (see figure 12 ) are the secondary currents through diodes d1 and d2 (see figure 27 ). when in the low-power mode the output power is further reduced, the amount of energy per cycle (= ? v snscap ) is reduced and the duty cycle remains the same (see figure 13 ). fig 12. timing diagram transition high-power mode to low-power mode d d d o r z s r z h u p r g h k l j k s r z h u p r g h , o r d g 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 , ' , ' 9 6 1 6 & $ 3 k d o i f \ f o h v k r o g s h u l r g 9 6 1 6 & $ 3 w o s TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 19 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when, in low-power mode, the minimum energy per cycle is reached, the duty cycle regulates the output power (see figure 14 ). increasing the ?hold? period lowers the duty cycle. to avoid audible noise, the system reduces the duty cycle until the frequency reaches f lp(min) (23 khz). if the output power is lowered further, the system en ters the burst mode. fig 13. low-power mode, lowering the energy per cycle ( ? v snscap ) fig 14. low-power mode, lowering the duty cycle d d d , o r d g 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 , ' , ' 9 6 1 6 & $ 3 d d d , o r d g 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 , ' , ' 9 6 1 6 & $ 3 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 20 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.4.3 burst mode in burst mode, the system alternates betw een operating in low-power mode and an extended hold state (see figure 15 ). because of this additional extended hold period, the magnetization and switching losses are further re duced. so, the efficien cy of the system is increased. figure 15 shows that all operating frequencies are outside the audible area. the minimum low-power frequency is 23 khz. within a low-po wer period, the system is switching at the resonant frequency of the converter, whic h is typically between 50 khz and 200 khz. the burst frequency (1 / t burst ) is continuously regulated to a predefined value, which can be set externally to 200 hz, 400 hz, 800 hz or 1600 hz. i sec is the secondary current flowing through either diode d1 or d2 (see figure 27 ). when the primary optocurrent (i snsfb ) drops to below 106 ? a, a new burst-on period is started. the end of the burst-on period dep ends on the calculated number of low-power cycles. the number of low-power cycles within a burst-on is continuously adjusted so that the burst period is at least the period defined by the setting (see figure 16 ). the system continuously measures the burst peri od from the start of the previous burst-on period to a new burst-on period. at t1, the measured burst period (t burst ) equals the required t burst . so, the next number of low-power cy cles equals the number of previous low-power cycles. at a consta nt output power, the system expects that when the next burst-on period has the same number of lo w-power cycles as the previous burst-on period, the burst period (t burst ) remains constant. fig 15. burst mode fig 16. burst mode: regulating the number of low-power cycles d d d , 6 1 6 ) % ? $ , v h f o r z s r z h u o r z s r z h u k r o g k r o g k r o g w o s e x u v w r q 7 e x u v w d d d e x u v w r q , 6 1 6 ) % ? $ , v h f 7 e x u v w 7 e x u v w 7 e x u v w 7 e x u v w w w w w , o r d g TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 21 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply at a positive transient (t2), a new low-power cycle is started immediately to minimize the drop in output voltage. the measured time period, at time t2, is below the targeted burst period. the system increases the number of bu rst cycles. at t3, it measures the burst period again. in this example, the burst peri od is still below the targeted burst period. so, the system increases the number of low-powe r cycles again and again until the measured burst period equals the target burst period, which occurs at t4. 7.5 optobias regulation in a typical application, the output voltage is sensed using a tl431 and connected to the snsfb pin of the TEA19161T via an optocoupler (see figure 27 ). because of the behavior of the tl431, the current through the optocoupler is at the maximum level when the output power is at the minimum level. it is therefore one of the most critical parameters to achieve the required no-load input powe r. to achieve maximum efficiency at low load/no-load, the TEA19161T continuously regulates the optocu rrent to a low level that is independent of the output load. a very low optocurrent reduces the transient response of the system, because of the parasitic capacitance at the optocoupler collector. so, the TEA19161T applies a fixed voltage at the snsfb pin. it measures the current through the optocoupler which defines the required output power. via an additional inte rnal circuitry, which adds an offset to the required output power, the optocurrent is continuously (slowly) regulated to the i reg(snsfb) level (= 85 ? a). this level is independent of the output power. at a positive load transient, the optocurrent initially decreases (see figure 9 ; i snsfb ). the TEA19161T immediately increases the ? v snscap which again increases the output power. figure 17 shows that when the optocurrent decreases, the internal voltage across the 12 k ? resistor drops to below the targeted level of 1020 mv (= 85 ? a ? 12 k ? ). the TEA19161T then slowly increases an additional offset at the power level ( ? p). it continues to increase the additional offset until the optocurrent reaches the target of 85 ? a. at a negative transient, the additional offset to th e power level is decreased. as a result, the output voltage increases which again increases the optocurrent. in this way, the optocurrent is continuously regulated to the i reg(snsfb) level (see figure 9 ). fig 17. optobias regulation d d d $ ' 3 9 6 1 6 & $ 3 ) ( ( ' % $ & . & 2 1 7 5 2 / 9 9 7 6 1 6 ) % n 9 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 22 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply the behavior of the internal circuitry connec ted to the snsfb pin is the same as the behavior of the traditional circuitry. the fixe d voltage at the snsfb pin and the continuous regulation of the optocurrent level does not influence the regulation level. the advantage, however, is a reduction in no-load input power and an optimization of the transient response. when the system operates in low-power mode at the minimum energy per cycle and at minimum duty cycle, it can no longer reduce the optocurrent level to the i reg(snsfb) target ( ? 85 ? a). if the output power decreases further and the optocurrent increases to above the level of i start(burst) ( ? 106 ? a), the burst mode is triggered. when the output power drops to below this level again, a new burst cycle is started (see figure 15 and figure 16 ). 7.6 protections ta b l e 3 gives an overview of the available protections. [1] can be longer due to the sharing of the internal adc converter. [2] latched implies that the system only restarts after a mains disconnection. [3] can be set by external components. when the system is in a latched or safe restart protection, the supic voltage is regulated to its start level via the suphv pin. 7.6.1 undervoltage protection supic/supreg when the voltage on the supic pin or the supreg pin is below its undervoltage level v uvp(supic) /v uvp(supreg) , the llc converter stops switch ing. the capacitors at the supic and supreg pins are rec harged via the suphv pin (see figure 5 ). the snsboost pin is pulled low, disabling the pfc. when the supply voltages exceed their start levels, the system restarts. table 3. protections protection description action pfc uvp supic/supreg undervoltage protection supic/supreg pins llc = off; recharge via suphv; restart when v supic >v start(supic) and v supreg >v start(supreg) off uvp suphs undervoltage protection suphs pin gatehs = off uvp snsboost undervoltage protection boost llc = off; restart when v snsboost >v start(snsboost) ovp output overvoltage protection output latched after 5 consecutive cycles [1] [2] off cmr capacitive mode regulation system ensures that mode of operation is inductive ocp overcurrent protection swit ch off cycle-by-cycle; after 5 consecutive cycles, it follows the opp setting. [2] off otp overtemperature protection latched [2] off opp overpower protection latched [2] /safe restart [3] off TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 23 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.6.2 undervoltage protection suphs to ensure a minimum drive voltage at the high-s ide driver output (gatehs), this driver is kept off when its voltage is below the minimum level (v suphs TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 24 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.6.6 overcurrent protection the system measures the primary current cont inuously via a sense resistor connected to the snscur pin. if the measured volt age exceeds the overcurrent level (v ocp ), the corresponding switch (gatels/gatehs) is turned off, but the system continuous switching. in this way, the pr imary current is limited to the oc p level. if the ocp level is exceeded for 5 consecutive cycles (gatels and/or gatehs), the system stops switching and enters the latched ocp protec tion mode. the pfc is disabled via the snsboost pin. 7.6.7 overtemperature protection when the internal junction temperature exceeds the t otp level, the overtemperature protection is triggered. otp is a latched protection which also disables the pfc. fig 18. near capacitive mode switching d d d , s u l p 9 6 1 6 & $ 3 9 u h j f d s p 9 u h j f d s p + % * $ 7 ( / 6 * $ 7 ( + 6 9 k v 6 1 6 & $ 3 w w w w 9 o v 6 1 6 & $ 3 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 25 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.6.8 overpower protection the external capacitive/resistive divider connected to the snscap pin must be chosen such that: ? the voltage difference between v hs(snscap) and v ls(snscap) equals ? v opp(snscap) ? the voltage difference between v hs(snscap) and v ls(snscap) occurs at 125 % of the maximum output power or at 175 %, depending on the settings when the ? v snscap (v hs(snscap) ? v ls(snscap) ) exceeds the ? v opp(snscap) voltage difference, an internal counter is st arted. when this counter exceeds t d(opp) (50 ms/200 ms), the system enters a latched/safe restart protection as defined by the external settings. the voltage difference between v hs(snscap) and v ls(snscap) is also limited to ? v th(max)snscap , which then corresponds to an output power of 150 % or 200 %, depending on the settings (see figure 19 ). if the output of the llc converter requires additional power, the output voltage drops as the power delivered by the llc converter is limited to 150 % or 200 %. an additional option is to disable the overpower counter, using the external settings. in this way, the overpower rating can be used as an extension of the typical power level. fig 19. TEA19161T overpower d d d 3 r x w 3 w o s 9 6 1 6 & $ 3 9 6 1 6 & $ 3 & 2 1 7 5 2 / 9 k v 6 1 6 & $ 3 9 o v 6 1 6 & $ 3 o r z s r z h u p r g h v w d u w l q j l q w h u q d o f r x q w h u p v e x u v w p r g h 9 r s s 6 1 6 & $ 3 9 w k p d [ 6 1 6 & $ 3 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 26 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.7 external settings before the system starts switchi ng, it reads the external sett ings. using specific resistor values at the gatels, snsset, and snsout pins, several internal settings can be defined. 7.7.1 burst period figure 20 shows how the internal regulated burst frequency can be set using the external resistor connected to the snsout pin. the absolute value of the resistor conn ected between the snsout pin and ground (r snsout1 ) defines the burst frequency. an accurate resistor of 1 % according to ta b l e 4 is required. the ovp level can be set using resistor r snsout2 . a low burst frequency is best for minimum audible noise. however, a high burst frequency minimizes the output voltage ripple. 7.7.2 general settings variables on the opp function can be set using resistor r snsset1 connected to the snsset pin (see figure 21 ). fig 20. external setting of the burst frequency table 4. external setting of the burst frequency r snsout1 burst frequency 22 k ? 200 hz 15 k ? 400 hz 10 k ? 800 hz 6.8 k ? 1600 hz d d d 5 6 1 6 2 8 7 6 1 6 2 8 7 5 6 1 6 2 8 7 fig 21. external setting of the snsset pin d d d 6 1 6 6 ( 7 5 6 1 6 6 ( 7 5 6 1 6 6 ( 7 & 6 1 6 6 ( 7 , & TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 27 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when the measured value of r snsset1 <10k ? , the system assumes a shorted pin to ground and the start-up is inhibited. at a value of 46.4 k ? , the system can of continuously delivering the maximum power of 200 %. the output power level at which the overpower timer is started can be set to 125 % or 175 %. two corresponding timer values can be selected, 50 ms or 200 ms. finally, the value of r snsset1 (see ta b l e 5 ) can set the behavior of the overpower function (either a 1 s restart or latched). during this protecti on period, the supic is regulated at its v start(supic) level. 7.7.3 low-power mode/burst mode transition levels to ensure the best efficiency, the system mu st enter the low-power mode and the burst mode at high power levels. however, to ensur e the best output ripple, these modes must be entered at low-power levels. to choose the optimum level for a specific application, the power transition levels at which the system enters the low-power mode and the burst mode can be set externally. resistor r snsset2 defines the power levels at which the system enters the low-power mode and the burst mode. ta b l e 6 gives an overview. table 5. general settings r snsset1 (k ? ) power capability level (%) opp timer level (%) end of power good timer (ms) opp timer (ms) protection < 10 no start-up 46.4 200 infinite 53.6 200 175 190 200 1 s restart 61.9 200 175 45 50 1 s restart 71.5 150 125 190 200 1 s restart 82.5 150 125 45 50 1 s restart 95.3 200 175 190 200 latched 110 200 175 45 50 latched 127 150 125 190 200 latched 147 150 125 45 50 latched TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 28 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply [1] the values in this table are including the additional shift due to the internal (t pd(snscap) ) delay and a typical external delay of 150 ns and 300 ns, respectively. when an external r + c network compensates these delays, the levels in ta b l e 6 can be lowered. the power level at which the system enters the burst mode also depends on the defined burst period. in this way, the optimum between efficiency and output voltage ripple can be chosen. 7.8 power good function the TEA19161T provides a power good function via the snsset pin. at initialization, the TEA19161T measures the resi stors connected to the sn sset pin to set internal variables. after that, the pin is used for the power good function. after the system has read the external settings (see figure 5 ), the snsset output is active high, enabling an external mosfet. a secondary power good signal can be pulled low using an external optocoupler. when the system enters the operating state (see figure 5 ), the snsset output is pulled low and the external power good signal beco mes active high. any required delay can be achieved via an external r/c network. table 6. external setting of the high-power /low-power and low-po wer/burst transition levels r snsset2 (k ? ) high-power => low-power (%) [1] burst mode [1] 200 hz (%) 400 hz (%) 800 hz (%) 1600 hz (%) 125 9 9 9 9 6.8 25 12 12 12 12 15 37.5 9 9 9 10 27 37.5 12 12 12 13 47 50 9 10 11 12 82 50 12 13 15 17 180 62.5 9 10 12 14 open 62.5 12 15 17.5 20 a. primary side b. secondary side fig 22. power good function d d d 6 1 6 6 ( 7 6 8 3 5 ( * , & d d d 9 r x w ' ' s r z h u j r r g TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 29 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply at low power good, the snsset out put becomes acti ve high when: ? the voltage on the snsboost pin drops to below v det(snsboost ) (1.95 v) ? the opp counter is at a value indicated in ta b l e 5 . in this way, the secondary power good signal is pulled low at 5 ms or 10 ms before the output is disabled. when the system enters protection mode (ovp, ocp, uvp or otp), it pulls low the snsset pin and stops switching immediately. 7.9 pfc/llc comm unication protocol the TEA19161T is designed to cooperate with the tea19162t (pfc) in one system. the TEA19161T and tea19162t can be seen as a combination, split up into two packages. all required functionality between the two co ntrollers is arranged via the combined supic and snsboost pins. 7.9.1 start-up to ensure that at start-up the TEA19161T and tea19162t are enabled at the same time, the TEA19161T (llc) pulls down the snsboost pin to below the snsboost short protection level of the pfc. the te a19161t disables the tea19162t (pfc) (see figure 23 ) until the system enters the pfc start-up phase (see figure 5 and figure 23 ). the supic start levels and stop levels of the tea19162t (pfc) are below the supic start levels and stop levels of the TEA19161T (llc). when the supic exceeds the start level of the TEA19161T, both controllers are enabled. in this way, both controllers are enabled/disabl ed at the same supic start and stop levels. TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 30 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply when the llc reaches a minimum supply voltage level (v rst(supic) ; t1), the llc pulls down the snsboost pin to disable the pfc. at t2, the supic reaches the start level of t he pfc converter. however, as the llc pulls low the snsboost voltage to < t he pfc short prot ection level, the pfc is still off. when at t3 the supic reaches the start level of th e llc, after the llc has read out the external settings, the snsboost voltage is released. it increases because of the connected resistive divider which is connected to the pfc boost voltage. to ensure that the snsboost voltage is a representative of the v boost voltage before the system actually starts to switch, an additional delay (until t4) is built into the pfc controller before it starts. when at t5 the snsboost voltage reaches the start level of the llc, the llc converter starts to switch. at t6, the supic is supplied via the primary auxiliary winding. fig 23. start-up of the pfc and llc d d d 6 8 3 , & 9 e r r v w 6 1 6 % 2 2 6 7 3 ) & r i i z d l w 8 9 / 2 r q 8 9 / 2 r q 6 8 3 , & u h j x o d w l r q 3 ) & / / & 9 r x w 9 v w d u w 6 8 3 , & 9 9 x y s 6 8 3 , & 9 9 u h j 6 1 6 % 2 2 6 7 9 9 v k r u w 6 1 6 % 2 2 6 7 9 w g v w d u w w w w w w w / / & 9 v w d u w 6 8 3 , & 9 9 v w d u w k \ v 6 8 3 , & 9 9 x y s 6 8 3 , & 9 9 u v w 6 8 3 , & 9 9 v w d u w 6 1 6 % 2 2 6 7 9 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 31 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 7.9.2 protection when a protection is triggered in either the pfc or llc, it may also disable the other converter. for example, if an ovp is detected at the llc, both converters are latched. also, at initial start-up, the pfc disables th e llc converter until the mains voltage detects the brownin level. the pfc can disable the llc converter by pulling down the snsboost pin to below the v uvp(snsboost) level of the llc converter. the llc can disable the pfc converter by pulling down the snsboost pin to below the shor t protection level of the pfc converter snsboost pin. ta b l e 3 in section 7.6 gives an overview of protections in the llc converter. it shows which protections also disable the pfc. fig 24. system protection d d d w g v w d u w / / & 6 8 3 , & p d l q v 6 1 6 % 2 2 6 7 3 ) & / / & 3 ) & 9 v w d u w 6 8 3 , & 9 9 x y s 6 8 3 , & 9 9 v w d u w 6 8 3 , & 9 9 v w d u w k \ v 6 8 3 , & 9 9 x y s 6 8 3 , & 9 9 u v w 6 8 3 , & 9 w w w w e u r z q r x w 8 9 3 r q 8 9 3 r q 6 8 3 , & u h j x o d w l r q 9 r x w e u r z q l q z d l w 6 1 6 2 8 7 r i i 2 9 3 9 u h j 6 1 6 % 2 2 6 7 9 9 v k r u w 6 1 6 % 2 2 6 7 9 w w w w w ! f \ f o h v 9 v w d u w 6 1 6 % 2 2 6 7 9 9 r y s 6 1 6 2 8 7 9 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 32 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply the start-up period up to t3 is identical in figure 23 and figure 24 . at t3, the llc converter releases the pull-down of the snsboost pin. however, as the mains voltage is below the brownin level, the pfc converter pulls low the snsboost pin. when the mains voltage exceeds the brownin level (t4), the snsboost pin is released and increases because of the resistive divider connected between the pfc boost voltage and the snsboost pin. to allow some external capacitance on the snsboost pin, the pfc converter waits until the sn sboost voltage is stabilized. at t5, the pfc converter starts to switch. at t6 , the llc converter also starts to switch, as the snsboost voltage reaches the v start(snsboost) of the llc converter. at t7, the primary auxiliary winding ta kes over the supply of the supic pin. at t8, the llc detects an ovp at the snsout pin. after at least 5 consecutive ovp cycles (t9), the llc stops switching and pulls down the snsboost pin. as a result, the pfc also stops switching. when either the pfc or llc is in protec tion, the supic pin is regulated to the v start(supic) via the suphv pin as soon as it drops below the v start(supic) level. 7.9.3 fast latch reset the supic pin is regulated to the v start(supic) level when a (latched) protection is triggered. so, it can re main in this protection mode unt il the capacitor at the pfc output, which the suphv is connected to, is discharged. hence, it may remain in protection mode for a long time after the mains is disconnected. when protection modes are tested at mass-pro duction, a long reset time is not acceptable in most cases. so, a fast latc h reset function is built into the pfc and the llc. when the mains is initially disconnected and then reconnected, all protections the pfc or the llc initiated are released again. TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 33 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply before t1, the llc is in a (latched) protecti on and pulls down the snsboost pin, which also disables the pfc. when the mains voltage drops to below the brownout level for a minimum period of t d(mains)bo , the pfc enters the brownout protection mode. when the mains voltage increases again to > the brownin level (t2) in the brownout protection mode, the pfc pulls up the snsboost voltage until it reaches the v uvp(snsboost ) level of the llc converter. the llc converter then releases all protecti on modes and waits until the snsboost pin exceeds its start level (v start(snsboost) ). after a waiting time, the pfc converter starts (t3), followed by a start-up of the llc converter (t4). 7.9.4 pfc burst mode when the llc operates in burst mode and the duty cycle of the burst is below 50 % for at least 8 consecutive burst periods, the TEA19161T (llc) sets the tea19162t (pfc) in burst mode as well. the corresponding output power level is then 50 % of the power level at which the llc enters the burst mode (see ta b l e 6 ). when the output power exceeds 75 % of the po wer level at which the llc enters the burst mode (see table 6 ), the pfc burst is disabled again. when the pfc burst is enabled, an additiona l current out of the snsboost pin stops the pfc from switching via a soft stop, so the audible noise is minimized (see figure 26 ). fig 25. fast latch reset d d d w g v w d u w / / & 9 v w d u w 6 8 3 , & 9 9 v w d u w k \ v 6 8 3 , & 9 6 8 3 , & 9 6 1 6 % 2 2 6 7 3 ) & r i i z d l w s u r w h f w l r q r q 8 9 3 6 1 6 % 2 2 6 7 3 ) & / / & 9 r x w w w w p d l q v e u r z q r x w r q e u r z q l q e u r z q r x w w 9 v w d u w 6 1 6 % 2 2 6 7 9 9 x y s 6 1 6 % 2 2 6 7 9 w g p d l q v e r 9 u h j 6 1 6 % 2 2 6 7 9 9 s x u v w 6 1 6 % 2 2 6 7 9 9 v f s v w r s 9 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 34 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply at t1, the current out of the llc snsboost pin (i off(burst) ) is activated and the voltage on the snsboost pin increases. when an external 100 k ? resistor (r snsboost ) is used between the snsboost pin and gnd pin (see figure 27 ), the snsboost voltage increase is approximately 640 mv (= i off(burst) *r snsboost ). because of this increase, the snsboost voltage is between the v det(l)snsboost and v det(h)snsboost levels of the pfc (t2), so the soft stop of the pfc converter is started. at the end of the soft stop, the pfc enters the energy safe state and stops switching (t3). because of the continuous operation of the llc converter, even when th e pfc is stopped, the pfc output capacitor is discharged. when the pfc boost capacitor is discharged so much that the voltage on the snsboost pin has dropped 75 mv ( ? v off(burst) ; t4), the internal current source in the llc converter is switched off. because of the negative voltag e drop at the snsboost pin, the pfc starts switching again. when v snsboost exceeds the llc v on(burst)max level (2.37 v) again, the internal current source is reactivated and the pfc stops switching again (t1). a. block diagram b. timing diagram fig 26. pfc burst mode d d d * 0 $ 0 3 / , ) , ( 5 v r i w v w r s 3 ) & / / & 6 1 6 % 2 2 6 7 3 ) & e x u v w p r g h 9 6 1 6 % 2 2 6 7 ! 9 n ? v ' ( / $ < 9 9 9 9 2 9 3 3 ) & & 2 0 3 , r i i e x u v w ? $ , r q v w r s v r i w ? $ 9 r i i e x u v w t 5 ( 6 ( 7 0 $ ; 9 $ / 8 ( v u 9 r i i e x u v w p 9 9 r q e x u v w p d [ 9 , r i i e x u v w d d d 2 ) ) 2 ) ) 2 1 2 1 9 g h w + 6 1 6 % 2 2 6 7 9 3 ) & / / & 9 g h w / 6 1 6 % 2 2 6 7 9 9 r y s v w r s 9 9 u h j 6 1 6 % 2 2 6 7 9 9 f o d p s 3 ) & & 2 0 3 9 9 w r q ] h u r 3 ) & & 2 0 3 9 9 6 1 6 % 2 2 6 7 w w w w 9 * $ 7 ( 3 ) & w w TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 35 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 8. limiting values table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit voltages v suphv voltage on pin suphv maximum during mains surge; not repetitive ? 0.4 +700 v v suphs voltage on pin suphs v hb v hb +14 v v hb voltage on pin hb maximum during mains surge; not repetitive ? 3 +700 v t<1 ? s ? 14 - v v supic voltage on pin supic ? 0.4 +36 v v supreg voltage on pin supreg ? 0.4 +12 v v gatehs voltage on pin gatehs v hb ? 0.4 v suphs +0.4 v v gatels voltage on pin gatels ? 0.4 v supreg +0.4 v v snsfb voltage on pin snsfb ? 0.4 +12 v v snsout voltage on pin snsout ? 0.4 +12 v v snsset voltage on pin snsset ? 0.4 +12 v v snscur voltage on pin snscur ? 0.4 +12 v v snscap voltage on pin snscap ? 0.4 +12 v v snsboost voltage on pin snsboost ? 0.4 +12 v currents i suphv current on pin suphv - 20 ma general p tot total power dissipation t amb <75 ?c- 0 . 7 w t stg storage temperature ? 55 +150 ?c t j junction temperature ? 40 +150 ?c latch-up i lu latch-up current all pins; according to jedec: standard 78d ? 100 +100 ma esd v esd electrostatic discharge voltage human body model pins suphv, suphs, gatehs, and hb ? 1000 +1000 v other pins ? 2000 +2000 v charged device model; all pins ? 500 +500 v TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 36 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 9. thermal characteristics 10. characteristics table 8. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air; jedec test board 107 k/w r th(j-c) thermal resistance from junction to case in free air, jedec test board 60 k/w table 9. characteristics t amb =25 ? c; v supic = 19.5 v; all voltages are measured with respect to gnd; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit suphv pin i lim(suphv) current limit on pin suphv v supic TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 38 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply pfc burst mode controller ? en(burst) burst mode enable duty cycle enable of pfc burst mode; duty cycle of llc burst mode -50-% n cy(en)burst burst mode enable number of cycles enable of pfc burst mode; cycles of llc burst mode -8- ? dis(burst) burst mode disable duty cycle disable of pfc burst mode; duty cycle of llc burst mode -75-% v pu(snsboost) pull-up voltage on pin snsboost to enter pfc burst mode off-state - 2.95 - v i off(burst) burst mode off-state current duri ng pfc burst mode off-state ? 7.1 ? 6.4 ? 5.7 ? a ? v off(burst) burst mode off-state voltage difference during pfc burst mode off-state; between peak voltage and end of off-state - ? 75 - mv v on(burst)max maximum burst mode on-state voltage during pfc burst mode on-state 2.29 2.37 2.45 v t to(det)on(burst) burst mode on-state detection time-out time during pfc burst mode on-state 3.7 4.0 4.3 ms pfc protection controller r pd(snsboost) pull-down resistance on pin snsboost at protection activation - 550 - ? i pd(snsboost) pull-down current on pin snsboost during active protection 94 110 127 ? a i prot(snsboost) protection current on pin snsboost -60-na snsout pin v ovp(snsout) overvoltage protection voltage on pin snsout 3.36 3.50 3.64 v i prot(snsout) protection current on pin snsout for open pin - ? 60 - na snsfb pin v bias(snsfb) bias voltage on pin snsfb i snsfb = ? 85 ? a2.22.52.8v optobias regulator i reg(snsfb) regulation current on pin snsfb i start(burst) = 106 ? a; tracks with i start(burst) - ? 85 - ? a i reg(max)snsfb maximum regulation current on pin snsfb i start(burst) = 106 ? a; tracks with i start(burst) - ? 310 - ? a i reg(min)snsfb minimum regulation current on pin snsfb i start(burst) = 106 ? a; tracks with i start(burst) - ? 63 - ? a burst mode regulator i start(burst) burst mode start current llc burst mode ? 123 ? 106 ? 89 ? a i stop(burst) burst mode stop current llc burst mode - ? 200 - ? a table 9. characteristics ?continued t amb =25 ? c; v supic = 19.5 v; all voltages are measured with respect to gnd; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 39 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply gatels and gatehs pins i source(gatehs) source current on pin gatehs v gatehs ? v hb =4v - ? 340 - ma i source(gatels) source current on pin gatels v gatels ? v gnd =4v - ? 340 - ma i sink(gatehs) sink current on pin gatehs v gatehs ? v hb = 2 v - 580 - ma v gatehs ? v hb =11v - 2 - a i sink(gatels) sink current on pin gatels v gatels ? v gnd = 2 v - 580 - ma v gatels ? v gnd =11 v - 2 - a v rst(suphs) reset voltage on pin suphs 6.4 7 7.6 v v rst(hys)suphs hysteresis of reset voltage on pin suphs >v rst(suphs) -0.6-v t on(min) minimum on-time - 0.83 - ? s t on(max) maximum on-time 14.8 17.4 20.0 ? s t sweep sweep time frequency; at start-up 1 12 14 ms low-power mode regulator f lp(min) minimum low-power mode frequency 20 23 26 khz burst mode regulator f burst(max) maximum burst mode frequency r snsout1 =22k ? 170 200 230 hz r snsout1 =15k ? 340 400 460 hz r snsout1 =10k ? 680 800 920 hz r snsout1 =6.8k ? 1360 1600 1840 hz power good characteristics (pin snsset) v oh(snsset) high-level output voltage on pin snsset i snsset = ? 100 ? a; power good = low -4-v i oh(snsset) high-level output current on pin snsset v snsset =3v; power good = low ? 11 ? 8 ? 5ma i ol(snsset) low-level output current on pin snsset v snsset =0.5v; power good = high 81114ma t d(h)snsset high-level delay time on pin snsset see ta b l e 5 for related r snsset1 35 45 55 ms see ta b l e 5 for related r snsset1 150 190 230 ms settings sensor (snsout, snsset, and gatels pins) i o(snsout) output current on pin snsout during r snsout1 measurement - ? 171 - ? a i o(snsset) output current on pin snsset during r snsset measurement - ? 26.8 - ? a ? v o(gatels-supreg) output voltage difference between pin gatels and pin supreg during r gatels measurement - 1.25 - v table 9. characteristics ?continued t amb =25 ? c; v supic = 19.5 v; all voltages are measured with respect to gnd; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 40 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply hb pin (dv/dt) tno(min) minimum non-overlap time rate of change of voltage -- 120v/ ? s t no(min) minimum non-overlap time - 200 - ns t no(max) maximum non-overlap time - 1.1 - ? s overtemperature protection t otp overtemperature protection trip 130 140 150 ?c table 9. characteristics ?continued t amb =25 ? c; v supic = 19.5 v; all voltages are measured with respect to gnd; currents are positive when flowing into the ic; unless otherwise specified. symbol parameter conditions min typ max unit TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 41 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 11. application information fig 27. TEA19161T application diagram d d d * $ 7 ( + 6 6 8 3 + 6 6 8 3 5 ( * 6 8 3 + 9 6 1 6 % 2 2 6 7 6 8 3 5 ( * 9 e r r v w & 6 8 3 + 6 & 6 8 3 5 ( * 5 6 8 3 + 9 * $ 7 ( / 6 + % 6 1 6 & $ 3 7 ( $ 6 1 6 & 8 5 6 8 3 , & 6 1 6 2 8 7 6 1 6 6 ( 7 6 1 6 ) % * 1 ' / v & u & 6 8 3 , & / p ' 6 6 9 r x w ' s r z h u j r r g ' 6 8 3 + 6 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 42 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 12. package outline fig 28. package outline sot109-3 (so16) ; z 0 $ $ $ e s ' + ( / s g h w d l o ; ( = h f / y 0 $ $ $ \ s l q l q g h [ 8 1 , 7 $ p d [ $ $ $ e s f ' ( h + ( / / s = \ z y 5 ( ) ( 5 ( 1 & ( 6 2 8 7 / , 1 ( 9 ( 5 6 , 2 1 ( 8 5 2 3 ( $ 1 3 5 2 - ( & 7 , 2 1 , 6 6 8 ( ' $ 7 ( , ( & - ( ' ( & - ( , 7 $ p p l q f k h v r r ' , 0 ( 1 6 , 2 1 6 l q f k g l p h q v l r q v d u h g h u l y h g i u r p w k h r u l j l q d o p p g l p h q v l r q v 1 r w h 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p l q f k p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 6 2 7 0 6 $ & p p v f d o h 6 2 s o d v w l f v p d o o r x w o l q h s d f n d j h o h d g v e r g \ z l g w k p p e r g \ w k l f n q h v v p p 6 2 7 TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 43 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 13. revision history table 10. revision history document id release date data sheet status change notice supersedes TEA19161T v.1 20160310 product data sheet - - TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 44 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 14.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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TEA19161T all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2016. all rights r eserved. product data sheet rev. 1 ? 10 march 2016 45 of 46 nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. greenchip ? is a trademark of nxp b.v. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors TEA19161T digital controller for high-ef ficiency resonant power supply ? nxp semiconductors n.v. 2016. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 march 2016 document identifier: TEA19161T please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 distinctive features . . . . . . . . . . . . . . . . . . . . . . 2 2.2 green features . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 protection features . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 start-up and supply voltage . . . . . . . . . . . . . . . 6 7.1.2 regulated supply (supreg pin) . . . . . . . . . . . 8 7.1.3 high-side driver floating supply (suphs pin) . . 8 7.2 system start-up. . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3 llc system regulation . . . . . . . . . . . . . . . . . . 10 7.3.1 output power regulation loop . . . . . . . . . . . . . 12 7.3.2 output voltage start-up . . . . . . . . . . . . . . . . . . 13 7.4 modes of operation . . . . . . . . . . . . . . . . . . . . . 14 7.4.1 high-power mode . . . . . . . . . . . . . . . . . . . . . . 16 7.4.2 low-power mode . . . . . . . . . . . . . . . . . . . . . . 17 7.4.3 burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 optobias regulation . . . . . . . . . . . . . . . . . . . . 21 7.6 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6.1 undervoltage protection supic/supreg . . . 22 7.6.2 undervoltage protection suphs . . . . . . . . . . 23 7.6.3 undervoltage protection boost . . . . . . . . . . . . 23 7.6.4 overvoltage protection . . . . . . . . . . . . . . . . . . 23 7.6.5 capacitive mode regulation (cmr) . . . . . . . . 23 7.6.6 overcurrent protection . . . . . . . . . . . . . . . . . . 24 7.6.7 overtemperat ure protection . . . . . . . . . . . . . . 24 7.6.8 overpower protection . . . . . . . . . . . . . . . . . . . 25 7.7 external settings . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.1 burst period . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.2 general settings . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.3 low-power mode/burst mode transition levels 27 7.8 power good function . . . . . . . . . . . . . . . . . . . . 28 7.9 pfc/llc communication protocol . . . . . . . . . 29 7.9.1 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9.2 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9.3 fast latch reset . . . . . . . . . . . . . . . . . . . . . . . . 32 7.9.4 pfc burst mode . . . . . . . . . . . . . . . . . . . . . . . 33 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 35 9 thermal characteristics . . . . . . . . . . . . . . . . . 36 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36 11 application information . . . . . . . . . . . . . . . . . 41 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 42 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 14 legal information . . . . . . . . . . . . . . . . . . . . . . 44 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15 contact information . . . . . . . . . . . . . . . . . . . . 45 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 |
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