fn8222 rev 3.00 page 1 of 10 july 20, 2009 fn8222 rev 3.00 july 20, 2009 x9c102, x9c103, x9c104, x9c503 digitally controlled potentiometer (xdcp?) datasheet the x9c102, x9c103, x9c104 , x9c503 are intersils digitally controlled (xdcp) po tentiometers. the device consists of a resistor array, wi per switches, a control section , and non-volatile memory. the wiper position is controlled by a three-wire interface. the potentiometer is impleme nted by a resistor array composed of 99 resistive ele ments and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is co ntrolled by the cs , u/d , and inc inputs. the position of the wiper can be stored in non-volatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer or as a two-terminal va riable resistor in a wide variety of applications ranging from cont rol to signal processing to parameter adjustment. pinout x9c102, x9c103, x9c104, x9c503 (8 ld soic, 8 ld pdip) top view features ? solid-state potentiometer ? three-wire serial interface ? 100 wiper tap points - wiper position stored in n on-volatile memory and recalled on power-up ? 99 resistive elements - temperature compensated - end-to-end resistance, 20% - terminal voltages, 5v ? low power cmos -v cc = 5v - active current, 3ma max. - standby current, 750a max. ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ? x9c102 = 1k ? ? x9c103 = 10k ? ? x9c503 = 50k ? ? x9c104 = 100k ? ? packages - 8 ld soic - 8 ld pdip ? pb-free available (rohs compliant) block diagram v cc cs v l /r l v w /r w inc u/d v h /r h v ss 1 2 3 4 8 7 6 5 7-bit up/down counter 7-bit non-volatile memory store and recall control circuitry one of hundred decoder resistor array r l /v l r w /v w r h/ v h u/d inc cs transfer v cc one- gates 99 98 97 96 2 1 0 gnd up/down (inc ) increment device (u/d ) (cs ) v cc (supply voltage) v ss (ground) control and memory general v h /r h r w /v w v l /r l select detailed
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 2 of 10 july 20, 2009 ordering information part number part marking r total (k ? ) temp range (c) package package dwg. # x9c102p x9c102p 1 0 to +70 8 ld pdip mdp0031 x9c102pz (notes 1, 2) x9c102p z 0 to +70 8 ld pdip (pb-free) mdp003 1 x9c102pi x9c102p i -40 to +85 8 ld pdip mdp0031 x9c102piz (notes 1, 2) x9c102p zi -40 to +85 8 ld pdip (pb-free) md p0031 x9c102s* , ** x9c102s 0 to +70 8 ld soic mdp0027 x9c102sz* (note 1) x9c102s z 0 to +70 8 ld soic (pb-free) mdp0027 x9c102si* , ** x9c102s i -40 to +85 8 ld soic mdp0027 x9c102siz* , ** (note 1) x9c102s zi -40 to +85 8 ld soic (pb-free) mdp0027 x9c103p x9c103p 10 0 to +70 8 ld pdip mdp0031 x9c103pz (notes 1, 2) x9c103p z 0 to +70 8 ld pdip (pb-free) mdp003 1 x9c103pi x9c103p i -40 to +85 8 ld pdip mdp0031 x9c103piz (note 1) x9c103p zi -40 to +85 8 ld pdip (pb-free) mdp003 1 x9c103s* , ** x9c103s 0 to +70 8 ld soic mdp0027 x9c103sz* , ** (note 1) x9c103s z 0 to +70 8 ld soic (pb-free) mdp0027 X9C103SI* , ** x9c103s i -40 to +85 8 ld soic mdp0027 X9C103SIz* , ** (note 1) x9c103s zi -40 to +85 8 ld soic (pb-free) mdp0027 x9c503p x9c503p 50 0 to +70 8 ld pdip mdp0031 x9c503pz (notes 1, 2) x9c503p z 0 to +70 8 ld pdip (pb-free) mdp003 1 x9c503pi x9c503p i -40 to +85 8 ld pdip mdp0031 x9c503piz (notes 1, 2) x9c503p zi -40 to +85 8 ld pdip (pb-free) md p0031 x9c503s* x9c503s 0 to +70 8 ld soic mdp0027 x9c503sz* (note 1) x9c503s z 0 to +70 8 ld soic (pb-free) mdp0027 x9c503si* , ** x9c503s i -40 to +85 8 ld soic mdp0027 x9c503siz* , ** (note 1) x9c503s zi -40 to +85 8 ld soic (pb-free) mdp0027 x9c104p x9c104p 100 0 to +70 8 ld pdip mdp0031 x9c104pi x9c104p i -40 to +85 8 ld pdip mdp0031 x9c104piz (notes 1, 2) x9c104p zi -40 to +85 8 ld pdip (pb-free) md p0031 x9c104s* , ** x9c104s 0 to +70 8 ld soic mdp0027 x9c104sz* , ** (note 1) x9c104s z 0 to +70 8 ld soic (pb-free) mdp0027 x9c104si* , ** x9c104s i -40 to +85 8 ld soic mdp0027 x9c104siz* , ** (note 1) x9c104s zi -40 to +85 8 ld soic (pb-free) mdp0027 *add t1 suffix for tape and reel. please refer to tb347 for d etails on reel s pecifications. **add t2 suffix for tape and r eel. please refer to tb347 for details on reel specifications. notes: 1. these intersil pb-free plasti c packaged products employ speci al pb-free material sets, molding compounds/die attach material s, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil p b-free products are msl classified at pb -free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 2. pb-free pdips can be used for through-hole wave solder proces sing only. they are not intended for use in reflow solder proce ssing applications.
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 3 of 10 july 20, 2009 pin descriptions pin number pin name description 1inc increment the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the dire ction indicated by the logic l evel on the u/d input. 2u/d up/down the u/d input controls the direction of the wiper movement and whether the counter is incremented or decremented. 3v h /r h v h /r h the high (v h /r h ) terminals of the x9c102, x9c103, x9c104, x9c503 are equivalen t to the fixed terminals of a mechanical potentiometer. the minimum voltage is -5v and the maximum is +5v. the terminology of v h /r h and v l /r l references the relative positi on of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. 4v ss v ss 5v w /r w v w /r w v w /r w is the wiper terminal and is equi valent to the movable termina l of a mechanical potentiometer. the position of the wiper within the array is determined by the con trol inputs. the wiper terminal ser ies resistance is typically 40 ? . 6r l /v l r l /v l the low (v l /r l ) terminals of the x9c102, x9c103, x9c104, x9c503 are equivalen t to the fixed terminals of a mechanical potentiometer. the minimum voltage is -5v and the ma ximum is +5v. the terminology of v h /r h and v l /r l references the relative positi on of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. 7cs cs the device is selected when the cs input is low. the current counter value is stored in non-volat ile memory when cs is returned high while the inc input is also high. after the st ore operation is complete the x9c102, x9c103, x9c104, x9c503 device will be placed in the low power standby m ode until the device is s elected once again. 8v cc v cc
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 4 of 10 july 20, 2009 absolute maximum ratings thermal information voltage on cs , inc , u/d and v cc with respect to v ss . -1v to +7v voltage on v h /r h and v l /r l referenced to v ss . . . . . . . -8v to +8v ? v = |v h /r h - v l /r l | x9c102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4v x9c103, x9c104, and x9c503 . . . . . . . . . . . . . . . . . . . . . . . .10v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8ma power rating x9c102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mw x9c103 x0c104, and x9c503 . . . . . . . . . . . . . . . . . . . . . .10mw temperature under bias . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through-hole wave solder processing only. they are not intended for use in reflow solder processing applications. recommended operating conditions commercial temperature range. . . . . . . . . . . . . . . . . 0 c to +70c industrial temperature range . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range (v cc ) . . . . . . . . . . . . . . . . . . . . . . . 5v 10% caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications over recommended operating condi tions unless otherwise stated. symbol parameter test conditions limits unit min typ (note 6) max potentiometer characteristics r total end-to-end resistance variation -20 +20 % v vh/rh v h terminal voltage -5 +5 v v vl/rl v l terminal voltage -5 +5 v i w wiper current -4.4 4.4 ma r w wiper resistance wiper current = 1ma 40 100 ? resistor noise (note 7) ref 1khz -120 dbv charge pump noise (note 7) @ 850khz 20 mv rms resolution 1% absolute linearity (note 3) v w(n)(actual) - v w(n)(expected) -1 +1 mi (note 5) relative linearity (note 4) v w(n + 1)(actual) - [v w(n) + mi ] -0.2 +0.2 mi (note 5) r total temperature coefficient x9c103, x9c503, x9c104 300 (note 7) ppm/ c r total temperature coefficient x9c102 600 (note 7) ppm/c ratiometric temperature coefficient 20 ppm/c c h /c l /c w (note 7) potentiometer capacitances see circuit #3 spice macro model on page 5. 10/10/25 pf dc operating characteristics i cc v cc active current cs = v il , u/d = v il or v ih and inc = 0.4v to 2.4v at max t cyc 13ma i sb standby supply current cs = v cc - 0.3v, u/d and inc =v ss or v cc -0.3v 200 750 a i li cs , inc , u/d input leakage current v in = v ss to v cc 10 a v ih cs , inc , u/d input high voltage 2 v v il cs , inc , u/d input low voltage 0.8 v c in cs , inc , u/d input capacitance (note 7) v cc = 5v, v in = v ss , t a = +25c, f = 1mhz 10 pf
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 5 of 10 july 20, 2009 power-up and down requirements at all times, voltages on the p otentiometer pins must be less than v cc . the recall of the wiper position from non-volatile memory is not in effect until the v cc supply reaches its final value. the v cc ramp rate specification is always in effect. ac operation characteristics t cl cs to inc setup 100 ns t ld inc high to u/d change 100 ns t di u/d to inc setup 2.9 s t ll inc low period 1 s t lh inc high period 1 s t lc inc inactive to cs inactive 1 s t cph cs deselect time (store) 20 ms t cph cs deselect time (no store) 100 ns t iw (5) inc to v w/rw change 100 s t cyc inc cycle time 2 s t cyc inc input rise and fall time 500 s t r , t f power-up to wiper stable (note 7) 500 s t pu v cc power-up rate (note 7) 0.2 50 v/ms notes: 3. absolute linearity is utilized to determine actual wiper volt age vs expected voltage = [v w(n)(actual) - v w(n)(expected ) ] = 1 mi maximum. 4. relative linearity is a measure of the error in step size bet ween taps = v w(n + 1) - [v w(n) + mi ] = +0.2 mi. 5. 1 mi = minimum increment = r tot /99. 6. typical values are for t a = +25c and nominal supply voltage. 7. this parameter is not 100% tested. electrical specifications over recommended operating condi tions unless otherwise stated. (continued) symbol parameter test conditions limits unit min typ (note 6) max test circuit #1 7 ( 6 7 3 2 , 1 7 9 z 5 : 9 5 5 + 9 / 5 / 9 6 test circuit #2 ) 2 5 & ( 9 / 5 / 9 : 5 z 9 + 5 + 7 ( 6 7 3 2 , 1 7 & 8 5 5 ( 1 7 circuit #3 spice macro model & : 5 7 2 7 $ / 5 / 5 + & / 5 : s ) & / s ) s ) endurance and data retention parameter min unit medium endurance 100,000 data changes per bit per register data retention 100 years ac conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 6 of 10 july 20, 2009 ac timing diagram pin descriptions r h /v h and r l /v l the high (v h /r h ) and low (v l /r l ) terminals of the islx9c102, x9c103, x9c104, x9c503 are equivalent to the fixed terminals of a mechanical potentiometer. the minimum voltage is -5v and the maximum is +5v. the terminology of v h /r h and v l /r l references the relative position of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w /v w v w /r w is the wiper termi nal, and is equivalent to the movable terminal of a mechanical potenti ometer. the position of the wiper within the array is dete rmined by the control inputs. the wiper terminal series resistance is typically 40 ? . up/down (u/d ) the u/d input controls the direct ion of the wiper movement and whether the counter is in cremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indicated by the logic leve l on the u/d input. chip select (cs ) the device is sele cted when the cs input is low. the current counter value is stored in non-volatile memory when cs is returned high while the inc input is also high. after the store operation is complete the is lx9c102, x9c103, x9c104, x9c503 device will be placed in the low power standby mode until the device is selected once again. principles of operation there are three sections o f the x9c102, x9c103, isl9c104 and isl9c503: the input control, counter and decode section; the non-volatile memory; and the resistor array. the input cont rol section operates just like an up/down counter. the output of th is counter is decoded to turn on a single electronic switch connecting a point on the resist or array to the wiper output. under the proper conditions, the contents of the counter can be stored in non-volatile memory and retained for future use. the resistor array is comprised of 9 9 individual resistors connecte d in series. at either end of the array and between each resistor is an electronic switch that transf ers the potential at that point to the wiper. the wiper, when at either fixe d terminal, act s like its mechanical equivalent and does not move bey ond the last position. that is, the counte r does not wrap around when clocked to either extreme. the electronic switches on the device operate in a make-before-break mode when the wiper changes tap positions. if the wiper is moved several positions, multiple ta ps are connected to the wiper for t iw (inc to v w /r w change). the r total value for the device can te mporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-dow n, the last wiper position stored will be maintained in t he non-volatile memory. when power is restored, the contents of the memory are recalled and the wiper is reset to the value last stored. the internal charge pump allo ws a wide range of voltages (from -5v to 5v) applied to xdcp terminals yet given a convenience of single power su pply. the typical charge pump noise of 20mv at 850 khz should be taken in consideration when designing an application circuit. cs inc u/d v w t ci t il t ih t cyc t id t di t iw mi t ic t cph t f t r 10% 90% 90% (note) note: mi refers to the minimum increme ntal change in the v w output due to a change in the wiper position.
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 7 of 10 july 20, 2009 instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low, the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a 7-bit counter. the output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. the value of the counter is st ored in non-volatile memory whenever cs transitions high while the inc input is also high. the system may select the x9cxxx, move the wiper and deselect the device without having to store the latest wiper position in non-volatile memory. after the wiper movement is performed as previously describ ed and once the new position is reached, the syst em must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or un til a power-down/up cycle recalled the previously stored data. this procedure allows the system to always powe r-up to a pre- set value stored in non-volat ile memory; th en during system operation, minor adjustments could be made. the adjustments might be based on user prefere nce, i.e.: system parameter changes due to temper ature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. symbol table performance characteristics contact the factory for more information. applications information electronic digitally controlled (xcdp) potentiometers provide three powerful applic ation advantages: 1. the variability and reliability of a solid-state potentiomete r. 2. the flexibility of comput er-based digital controls. 3. the retentivity of non-volatile memory used for the storage of multiple potentiome ter settings or data. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position h x x standby current l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 8 of 10 july 20, 2009 basic configurations of electronic potentiometers basic circuits v r v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current v h /r h v l /r l v w /r w cascading techniques buffered reference voltage C + +5v r 1 +v -5v v w v ref v out op-07 v w /r w v w /r w +v +v +v x (a) (b) v out = v w /r w noninverting amplifier v o = (1+r 2 /r 1 )v s voltage regulator r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 offset voltage adjustment + C v s v o r 2 r 1 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 comparator with hysteresis v ul = {r 1 /(r 1 + r 2 )} v o (max) v ll = {r 1 /(r 1 + r 2 )} v o (min) + C v s v o r 2 r 1 lm308a +5v -5v + C v s v o r 2 r 1 } } lt311a (for additional circuits see an1145)
x9c102, x9c103, x9c104, x9c503 fn8222 rev 3.00 page 9 of 10 july 20, 2009 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail x c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150) so16 (0.300) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ? 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ? 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ? 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ? 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ? 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ? 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ? 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ? 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
fn8222 rev 3.00 page 10 of 10 july 20, 2009 x9c102, x9c103, x9c104, x9c503 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2009. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions o f 0.010 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions e and ea are measu red with the leads constrained p erpendicular to the seating plane. 4. dimension eb is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
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