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scls128d ? december 1982 ? revised august 2003 1 post office box 655303 ? dallas, texas 75265 wide operating voltage range of 2 v to 6 v high-current outputs drive up to 15 lsttl loads low power consumption, 80- a max i cc typical t pd = 9 ns 6-ma output drive at 5 v low input current of 1 a max 3-state outputs drive bus lines or buffer memory address registers 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1oe 1a1 2y4 1a2 2y3 1a3 2y2 1a4 2y1 gnd v cc 2oe 1y1 2a4 1y2 2a3 1y3 2a2 1y4 2a1 sn54hc240 ...j or w p ackage sn74hc240 . . . db, dw, n, ns, or pw package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 1y1 2a4 1y2 2a3 1y3 1a2 2y3 1a3 2y2 1a4 sn54hc24 0...fk p ackage (top view) 2y4 1a1 1oe 1y4 2a2 2oe 2y1 gnd 2a1 v cc description/ordering information these octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the ?hc240 devices are organized as two 4-bit buffers/drivers with separate output-enable (oe ) inputs. when oe is low, the device passes inverted data from the a inputs to the y outputs. when oe is high, the outputs are in the high-impedance state. ordering information t a package ? orderable part number top-side marking pdip ? n tube of 20 sn74hc240n sn74hc240n soic ? dw tube of 25 sn74hc240dw hc240 soic ? dw reel of 2000 sn74hc240dwr hc240 ?40 c to 85 c sop ? ns reel of 2000 sn74hc240nsr hc240 ?40 c to 85 c ssop ? db reel of 2000 sn74hc240dbr hc240 tube of 70 sn74hc240pw tssop ? pw reel of 2000 sn74hc240pwr hc240 tssop ? pw reel of 250 sn74hc240pwt hc240 cdip ? j tube of 20 snj54hc240j snj54hc240j ?55 c to 125 c cfp ? w tube of 85 snj54hc240w snj54hc240w ?55 c to 125 c lccc ? fk tube of 55 snj54hc240fk snj54hc240fk ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications o f texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 2003, texas instruments incorporated
scls128d ? december 1982 ? revised august 2003 2 post office box 655303 ? dallas, texas 75265 function table (each buffer/driver) inputs output oe a output y l h l l lh h x z logic diagram (positive logic) 1 2 4 6 8 19 11 13 15 17 3 5 7 9 12 14 16 18 1a1 1a2 1a3 1a4 1y1 2a1 2a2 2a3 2a4 2y1 1y2 1y3 1y4 2y2 2y3 2y4 1oe 2oe absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 35 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 70 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): db package 70 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dw package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n package 69 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ns package 60 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pw package 83 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
scls128d ? december 1982 ? revised august 2003 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) sn54hc240 sn74hc240 unit min nom max min nom max unit v cc supply voltage 2 5 6 2 5 6 v v cc = 2 v 1.5 1.5 v ih high-level input voltage v cc = 4.5 v 3.15 3.15 v v ih high-level input voltage v cc = 6 v 4.2 4.2 v v cc = 2 v 0.5 0.5 v il low-level input voltage v cc = 4.5 v 1.35 1.35 v v il low-level input voltage v cc = 6 v 1.8 1.8 v v i input voltage 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc v v cc = 2 v 1000 1000 ? t/ ? v input transition rise/fall time v cc = 4.5 v 500 500 ns ? t/ ? v input transition rise/fall time v cc = 6 v 400 400 ns t a operating free-air temperature ?55 125 ?40 85 c note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c sn54hc240 sn74hc240 unit parameter test conditions v cc min typ max min max min max unit 2 v 1.9 1.998 1.9 1.9 i oh = ?20 a 4.5 v 4.4 4.499 4.4 4.4 v oh v i = v ih or v il i oh = ?20 a 6 v 5.9 5.999 5.9 5.9 v v oh v i = v ih or v il i oh = ?6 ma 4.5 v 3.98 4.3 3.7 3.84 v i oh = ?7.8 ma 6 v 5.48 5.8 5.2 5.34 2 v 0.002 0.1 0.1 0.1 i ol = 20 a 4.5 v 0.001 0.1 0.1 0.1 v ol v i = v ih or v il i ol = 20 a 6 v 0.001 0.1 0.1 0.1 v v ol v i = v ih or v il i ol = 6 ma 4.5 v 0.17 0.26 0.4 0.33 v i ol = 7.8 ma 6 v 0.15 0.26 0.4 0.33 i i v i = v cc or 0 6 v 0.1 100 1000 1000 na i oz v o = v cc or 0 6 v 0.01 0.5 10 5 a i cc v i = v cc or 0, i o = 0 6 v 8 160 80 a c i 2 v to 6 v 3 10 10 10 pf
scls128d ? december 1982 ? revised august 2003 4 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from to v cc t a = 25 c sn54hc240 sn74hc240 unit parameter from (input) to (output) v cc min typ max min max min max unit 2 v 50 100 150 125 t pd a y 4.5 v 10 20 30 25 ns t pd a y 6 v 9 17 25 21 ns 2 v 75 150 225 190 t en oe y 4.5 v 15 30 45 38 ns t en oe y 6 v 13 26 38 32 ns 2 v 44 150 225 190 t dis oe y 4.5 v 22 30 45 38 ns t dis oe y 6 v 21 26 38 32 ns 2 v 28 60 90 75 t t y 4.5 v 8 12 18 15 ns t t y 6 v 6 10 15 13 ns switching characteristics over recommended operating free-air temperature range, c l = 150 pf (unless otherwise noted) (see figure 1) parameter from to v cc t a = 25 c sn54hc240 sn74hc240 unit parameter from (input) to (output) v cc min typ max min max min max unit 2 v 75 150 225 190 t pd a y 4.5 v 15 30 45 38 ns t pd a y 6 v 13 26 38 32 ns 2 v 100 200 300 250 t en oe y 4.5 v 20 40 60 50 ns t en oe y 6 v 17 34 51 43 ns 2 v 45 210 315 265 t t y 4.5 v 17 42 63 53 ns t t y 6 v 13 36 53 45 ns operating characteristics, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance per buffer/driver no load 35 pf
scls128d ? december 1982 ? revised august 2003 5 post office box 655303 ? dallas, texas 75265 parameter measurement information voltage waveform input rise and fall times 50% 50% 10% 10% 90% 90% v cc 0 v t r t f input voltage waveforms propagation delay and output transition times 50% 50% 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% t plh t phl 50% 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output 50% 10% 90% v cc v cc v ol 0 v output control (low-level enabling) output waveform 1 (see note b) 50% t pzl t plz voltage waveforms enable and disable times for 3-state outputs v oh 0 v 50% 50% t pzh t phz output waveform 2 (see note b) v cc test point from output under test c l (see note a) r l v cc s1 s2 load circuit parameter c l t pzh t pd or t t t dis t en t pzl t phz t plz 1 k ? 1 k ? 50 pf or 150 pf 50 pf open closed r l s1 closed open s2 open closed closed open 50 pf or 150 pf open open ?? notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by generators having the followi ng characteristics: prr 1 mhz, z o = 50 ? , t r = 6 ns, t f = 6 ns. d. the outputs are measured one at a time with one input transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t plh and t phl are the same as t pd . figure 1. load circuit and voltage waveforms
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 84074012A active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 84074012A snj54hc 240fk 8407401ra active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 8407401ra snj54hc240j 8407401sa active cfp w 20 1 tbd a42 n / a for pkg type -55 to 125 8407401sa snj54hc240w jm38510/65703b2a active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 jm38510/ 65703b2a jm38510/65703bra active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 65703bra m38510/65703b2a active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 jm38510/ 65703b2a m38510/65703bra active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 jm38510/ 65703bra sn54hc240j active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 sn54hc240j sn74hc240dbr active ssop db 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dwe4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dwg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dwre4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240dwrg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240n active pdip n 20 20 pb-free (rohs) cu nipdau n / a for pkg type -40 to 85 sn74hc240n sn74hc240n3 obsolete pdip n 20 tbd call ti call ti -40 to 85
package option addendum www.ti.com 10-jun-2014 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn74hc240ne4 active pdip n 20 20 pb-free (rohs) cu nipdau n / a for pkg type -40 to 85 sn74hc240n sn74hc240nsr active so ns 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240nsre4 active so ns 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pwre4 active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pwrg4 active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pwt active tssop pw 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 sn74hc240pwtg4 active tssop pw 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 hc240 snj54hc240fk active lccc fk 20 1 tbd post-plate n / a for pkg type -55 to 125 84074012A snj54hc 240fk snj54hc240j active cdip j 20 1 tbd a42 n / a for pkg type -55 to 125 8407401ra snj54hc240j snj54hc240w active cfp w 20 1 tbd a42 n / a for pkg type -55 to 125 8407401sa snj54hc240w (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes.
package option addendum www.ti.com 10-jun-2014 addendum-page 3 pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of sn54hc240, sn74hc240 : ? catalog: sn74hc240 ? military: sn54hc240 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74hc240dbr ssop db 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 q1 sn74hc240dwr soic dw 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 q1 sn74hc240nsr so ns 20 2000 330.0 24.4 9.0 13.0 2.4 12.0 24.0 q1 sn74hc240pwr tssop pw 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 sn74hc240pwt tssop pw 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 package materials information www.ti.com 17-aug-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74hc240dbr ssop db 20 2000 367.0 367.0 38.0 sn74hc240dwr soic dw 20 2000 367.0 367.0 45.0 sn74hc240nsr so ns 20 2000 367.0 367.0 45.0 sn74hc240pwr tssop pw 20 2000 367.0 367.0 38.0 sn74hc240pwt tssop pw 20 250 367.0 367.0 38.0 package materials information www.ti.com 17-aug-2016 pack materials-page 2

www.ti.com package outline c typ 10.63 9.97 2.65 max 18x 1.27 20x 0.51 0.31 2x 11.43 typ 0.33 0.10 0 - 8 0.3 0.1 0.25 gage plane 1.27 0.40 a note 3 13.0 12.6 b 7.6 7.4 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.43 mm per side. 5. reference jedec registration ms-013. 1 20 0.25 c a b 11 10 pin 1 id area note 4 seating plane 0.1 c see detail a detail a typical scale 1.200
www.ti.com example board layout (9.3) 0.07 max all around 0.07 min all around 20x (2) 20x (0.6) 18x (1.27) (r ) typ 0.05 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic symm symm land pattern example scale:6x 1 10 11 20 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details solder mask opening metal under solder mask solder mask defined
www.ti.com example stencil design (9.3) 18x (1.27) 20x (0.6) 20x (2) 4220724/a 05/2016 soic - 2.65 mm max height dw0020a soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 10 11 20 solder paste example based on 0.125 mm thick stencil scale:6x

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150

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