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MP9943 high efficiency 3a peak, 36v, synchronous step down converter with power good MP9943 rev.1.1 www.monolithicpower.com 1 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the MP9943 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power mosfets. it offers a very compact solution to achieve a 3a peak output current with excellent load and line regulation over a wide input supply range. the MP9943 has synchronous mode operation for higher efficiency over the output current load range. current-mode operation provides fast transient response and eases loop stabilization. full protection features include over-current protection and thermal shutdown. the MP9943 requires a minimal number of readily-available standard external components, and is available in a space-saving qfn-8 (3mmx3mm) package. features ? wide 4v to 36v continuous operating input range ? 85m ? /55m ? low r ds(on) internal power mosfets ? high-efficiency synchron ous mo de operation ? 410khz switching frequency ? synchronizes from 200khz to 2.2mhz external clock ? high duty cycle for automotive cold-crank ? internal power-save mode ? internal soft-start ? power good indicator ? over current protection and hiccup ? thermal shutdown ? output adjustable from 0.8v ? available in an qfn-8 (3mmx3mm) package applications ? general consumer ? multi-function printers (mfp) ? distributed power systems a ll mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithi c power systems, inc. typical application
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 2 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking MP9943gq qfn-8 (3mm 3mm) see below * for tape & reel, add suffix ?z (e.g. MP9943gq?z); top marking amg: product code of MP9943gq; y: year code; lll: lot number; package reference 1 2 3 45 6 7 8 top view fb vcc en/sync bst pg sw in gnd qfn-8 (3mm 3mm)
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 3 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. absolute maxi mum ratings (1) v in .................................................. -0.3v to 40v v sw .................................................. -0.3v to 41v v bs ......................................................... v sw +6v all other pins ................................ -0.3v to 6v (2) continuous power dissipation (t a = +25c) (3) qfn-8 (3mmx3mm) ................................. 2.27w junction temperature ............................... 150c lead temperature .................................... 260c storage temperature ................. -65c to 150c recommended operating conditions (4) continuous supply voltage v in ........... 4v to 36v output voltage v out .................. 0.8v to d max v in operating junction temp (t j ). . -40c to +125c thermal resistance (5) ja jc qfn-8 (3mmx3mm) ............... 55 ...... 13 ... c/w notes: 1) absolute maximum ratings are rated under room temperature unless otherwise noted. exceeding these ratings may damage the device. 2) about the details of en/sync pin?s abs max rating, please refer to page 12, enable/sync control section. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operation condition. 5) measured on jesd51-7, 4-layer pcb.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 4 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics v in = 12v, t j = +25c, unless otherwise noted. parameter symbol condition min typ max units supply current (shutdown) i shdn v en = 0v 8 a supply current (quiescent) i q v en = 2v, v fb = 1v 0.5 0.7 ma hs switch-on resistance r on_hs v bst-sw =5v 85 105 m ? ls switch-on resistance r on_ls v cc =5v 55 75 m ? switch leakage i lkg _ sw v en = 0v, v sw =12v 1 a current limit i limit under 40% duty cycle 3.2 4.4 5.5 a oscillator frequency f sw v fb =750mv 320 410 500 khz fold-back frequency f fb v fb <400mv 70 100 130 khz maximum duty cycle d max v fb =750mv, 410khz 92 95 % minimum on time ( 6 ) t on _ min 70 ns sync frequency range f sync 0.2 2.4 mhz feedback voltage v fb 778 792 806 mv feedback current i fb v fb =820mv 10 100 na en rising threshold v en _ rising 1.15 1.4 1.65 v en falling threshold v en _ falling 1.05 1.25 1.45 v en threshold hysteresis v en_hys 150 mv en input current i en v en =2v 4 6 a v en =0 0 0.2 a vin under-voltage lockout threshold-rising inuv rising 3.3 3.5 3.7 v vin under-voltage lockout threshold-falling inuv falling 3.1 3.3 3.5 v vin under-voltage lockout threshold-hysteresis inuv hys 200 mv vcc regulator v cc i cc =0ma 4.6 4.9 5.2 v vcc load regulation i cc =5ma 1.5 4 % soft-start period t ss v out from 10% to 90% 0.45 1. 5 2.55 ms thermal shutdown ( 6 ) t sd 150 170 c thermal hysteresis ( 6 ) t sd _ hys 30 c pg rising threshold pg vth _ rising as percentage of v fb 86 90 94 % pg falling threshold pg vth falling as percentage of v fb 80 84 88 %
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 5 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t j = +25c, unless otherwise noted. parameter symbol condition min typ max units pg threshold hysteresis pg vth_hys as percentage of v fb 6 % pg rising delay pg td _ rising 40 90 160 s pg falling delay pg td _ falling 30 55 95 s pg sink current capability v pg sink 4ma 0.1 0.3 v pg leakage current i lkg_pg 10 100 na notes: 6) derived from bench characteri zation. not tested in production.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 6 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 3.3v, l = 10h, r bst =20 ? , t a = +25c, unless otherwise noted.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 7 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 3.3v, l = 10h, r bst =20 ? , t a = +25c, unless otherwise noted.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 8 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 3.3v, l = 10h, r bst =20 ? , t a = +25c, unless otherwise noted.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 9 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 3.3v, l = 10h, r bst =20 ? , t a = +25c, unless otherwise noted.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 10 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions package pin # name description 1 fb feedback. connect to the tap of an external resistor divider fr om the output to gnd, to set the output voltage. the frequency fold-back co mparator lowers the oscillator frequency when the fb voltage is below 660mv to prevent current limit runaway during a short-circuit fault condition. 2 vcc bias supply. decouple with 0.1 f-to-0.22 f capacitor. select a capacitor that does not exceed 0.22 f 3 en/sync enable/synchronize. en/sync high to enable t he MP9943. apply an external clock to the en/sync pin to change the switching frequency. 4 bst bootstrap. requires a capacitor connected bet ween sw and bst pins to form a floating supply across the high-side switch driver. a 20 ? resistor placed between sw and bst cap is strongly recommended to reduce sw spike voltage. 5 gnd system ground. this pin is the reference ground of the regulated output voltage, and pcb layout requires special care. for best results, connect to gnd with copper traces and vias. 6 sw switch output. connect with a wide pcb trace. 7 in supply voltage input. the MP9943 operates from a 4v to 36v input rail. requires c1 to decouple the input rail. connect using a wide pcb trace. 8 pg power good. the output of this pin is an open drain and goes high if the output voltage exceeds 90% of the nominal voltage.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 11 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. functional block diagram figure 1: functional block diagram
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 12 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. operation the MP9943 is a high-frequency, synchronous, rectified, step-down, switch-mode converter with built-in power mosfets. it offers a very compact solution to achieve 3a peak output current with excellent load and line regulation over a wide input supply range. when MP9943 operates in a fixed-frequency, peak-current?control mode to regulate the output voltage. an internal clock initiates a pwm cycle. the integrated high-side power mosfet turns on and remains on until its current reaches the value set by the comp voltage. when the power switch is off, it remains off until the next clock cycle starts. if the current in the power mosfet does not reach the current value set by comp within 95% of one pwm period, the power mosfet will be forced to turn off. internal regulator the 5v internal regulator power most of the internal circuitries. this regulator is supplied by the v in input and operates in the full v in range: when v in exceeds 5.0v, the output of the regulator is in full regulation; when v in falls below 5.0v, the output of the regulator decreases following the vin. a 0.1uf decoupling ceramic capacitor is needed at the pin. error amplifier the error amplifier compares the fb pin voltage against the internal 0.8v reference (ref) and outputs a comp voltage?this comp voltage controls the power mosfet current. the optimized internal compensation network minimizes the external component count and simplifies the control loop design. power save mode for light load condition the MP9943 has aam (advanced asynchronous modulation) power-save mode for light load. the aam threshold is fixed internally. under the heavy load condition, the v comp is higher than v aam . when the clock goes high, the high-side power mosfet turns on and remains on until v ilsense reaches the value set by the comp voltage. the internal clock resets every time when v comp is higher than v aam . under the light load condition, the value of v comp is low. when v comp is less than v aam and v fb is less than v ref , v comp ramps up until it exceeds v aam . during this time, the internal clock is blocked, thus the MP9943 skips some pulses for pfm (pulse frequency modulation) mode and achieves the light load power save. figure 2: simplified aam control logic enable/sync control en/sync is a digital control pin that turns the regulator on and off: drive en/sync high to turn on the regulator, drive it low to turn it off. an internal 500k ? resistor from en/sync to gnd allows en/sync to be floated to shut down the chip. the en/sync pin is clamped internally using a 6.5v series zener diode, as shown in figure 3. connect the en/sync input pin through a pullup resistor to any voltage connected to the v in pin? the pullup resistor limits the en/sync input current to less than 150a. for example, with 12v connected to v in , r pullup (12v ? 6.5v) 150a = 36.7k ? . connecting the en/sync pin directly to a voltage source without any pullup resistor requires limiting voltage amplitude to 6v to prevent damage to the zener diode. figure 3: 6.5v-type zener diode connect an external clock with a range of 200khz to 2.2mhz 2ms after output voltage is set to synchronize the internal clock rising edge to the external clock rising edge. the pulse width of external clock signal should be less than 2 s.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 13 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. under-voltage lockout under-voltage lockout (uvlo) protects the chip from operating at an insufficient supply voltage. the MP9943 uvlo comparator monitors the output voltage of the internal regulator, vcc. the uvlo rising threshold is about 3.5v while its falling threshold is 3.3v. internal soft-start the soft-start prevents the converter output voltage from overshooting during startup. when the chip starts, the internal circuitry generates a soft-start voltage (ss) that ramps up from 0v to 1.2v. when ss is lower than ref, ss overrides ref so the error amplifier uses ss as the reference. when ss exceeds ref, the error amplifier uses ref as the reference. the ss time is internally set to 1.5ms. over-current protection and hiccup the MP9943 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. if the output voltage starts to drop until fb is below the under- voltage (uv) threshold?typically 84% below the reference?the MP9943 enters hiccup mode to periodically restart the part. this protection mode is especially useful when the output is dead- shorted to ground. the average short-circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. the MP9943 exits the hiccup mode once the over-current condition is removed. thermal shutdown thermal shutdown prevents the chip from operating at exceedingly high temperatures. when the silicon die temperature exceeds 170c, it shuts down the whole chip. when the temperature drops below its lower threshold (typically 140c) the chip is enabled again. floating driver and bootstrap charging an external bootstrap capacitor power the floating-power-mosfet driver. a dedicated internal regulator (see figure 4) charges and regulates the bootstrap capacitor voltage to ~5v. when the voltage between the bst and sw nodes drops below regulation, a pmos pass transistor connected from v in to bst turns on. the charging current path is from v in , bst and then to sw. the external circuit should provide enough voltage headroom to facilitate charging. as long as v in is significantly higher than sw, the bootstrap capacitor remains charged. when the hs-fet is on, v in v sw , so the bootstrap capacitor can?t be charged. when the ls-fet is on, v in ? v sw reaches its maximum for fast charging. when there is no inductor current, v sw =v out , so the difference between v in and v out can charge the bootstrap capacitor. the floating driver has its own uvlo protection, with a rising threshold of 2.2v and hysteresis of 150mv. a 20 ? resistor placed between sw and bst cap is strongly recommended to reduce sw spike voltage. figure 4: internal bootstrap charging circuit startup and shutdown if both v in and v en/sync exceed their appropriate thresholds, the chip starts: the reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. the regulator provides stable supply for the remaining circuitries. three events can shut down the chip: v en/sync low, v in low, and thermal shutdown. in the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. the comp voltage and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command. power good the MP9943 has power good (pg) output. the pg pin is the open drain of a mosfet. it should be connected to vcc or some other voltage source through a resistor (e.g. 100k ? ). in the presence of an input voltage, the mosfet turns on so that the pg pin is pulled to low before ss
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 14 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. is ready. after v fb reaches 90%ref, the pg pin is pulled high after a delay, typically 90 s. when v fb drops to 84%ref, the pg pin is pulled low. also, pg is pulled low if thermal shutdown or en/sync is pulled low.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 15 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. application information setting the output voltage the external resistor divider sets the output voltage (see typical application on page 1). choose r7 around 41.2k ? . r8 is then given by: 1 0.792v v r7 r8 out ? ? the t-type network?as shown in figure ?is highly recommended when v out is low. r7 r8 rt figure 5: t-type network rt+r7 is used to set the loop bandwidth. basically, higher rt+r7, lower bandwidth. to ensure the loop stability, it is strongly recommended to limit the bandwidth lower than 40khz based on the 410khz default fsw. table 1 lists the recommended t-type resistors value for common output voltages. table 1: resistor selection for common output voltages (7) v out (v) r7 (k ? ) r8 (k ? ) rt (k ? ) 3.3 41.2 (1%) 13 (1%) 51 (1%) 5 41.2 (1%) 7.68 (1%) 51 (1%) notes: 7) the recommended parameters is basing on 410khz switching frequency, different input vo ltage, output i nductor value and output capacitor value may affect the select of r7, r8 and rt. for other components? parameters, please refer to typical application circuits on page 19. selecting the inductor use a 1h-to-10h inductor with a dc current rating of at least 25% percent higher than the maximum load current for most applications. for highest efficiency, an inductor with small dc resistance is recommended. for most designs, the inductance value can be derived from the following equation. out in out 1 in l osc v(vv) l vif ?? ? ?? ? where ? i l is the inductor ripple current. choose the inductor ripple current to be approximately 30% of the maximum load current. the maximum inductor peak current is: 2 i i i l load ) max ( l ? ? ? use a larger inductor for improved efficiency under light-load conditions?below 100ma. vin uvlo setting MP9943 has internal fix under voltage lock out (uvlo) threshold: rising threshold is 3.5v while falling threshold is about 3.3v. for the application needs higher uvlo point, external resistor divider between en/sync and in as shown in figure 6 can be used to get higher equivalent uvlo threshold. vin en/sync in r en_up 500 k r en_down figure 6: adjustable uvlo using en/sync divider the uvlo threshold can be computed from below two equations: en_rising en_down en_up rising v 500k//r r (1 inuv ? ? ? ) en_falling en_down en_up falling v 500k//r r (1 inuv ? ? ? ) where v en_rising =1.4v, v en_falling =1.25v. when choose r en_up , make sure it is big enough to limit the current flows into en/sync pin lower than 150ua.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 16 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. selecting the input capacitor the input current to the step-down converter is discontinuous, therefore requires a capacitor is to supply the ac current to the step-down converter while maintaining the dc input voltage. use low esr capacitors for the best performance. use ceramic capacitors with x5r or x7r dielectrics for best results because of their low esr and small temperature coefficients. for most application, a 22f ceramic capacitor is sufficient to maintain the dc input voltage. and it is strongly recommended to use another lower value capacitor (e.g. 1f) with small package size (0603) to absorb high frequency switching noise. make sure place the small size capacitor as close to in and gnd pins as possible (see pcb layout section). since c1 absorbs the input switching current, it requires an adequate ripple current rating. the rms current in the input capacitor can be estimated by: ? ? ? ? ? ? ? ? ? ? ? ? in out in out load 1 c v v 1 v v i i the worse case condition occurs at v in = 2v out , where: 2 i i load 1 c ? for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitor can be electrolytic, tantalum or ceramic. when using electrolytic or tantalum capacitors, add a small, high quality ceramic capacitor (e.g. 1 f) placed as close to the ic as possible. when using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. the input voltage ripple caused by capacitance can be estimated by: load out out in in sin iv v v1 fc1v v ?? ?? ? ?? ?? ? ?? selecting the output capacitor the output capacitor (c2) maintains the dc output voltage. use ceramic, tantalum, or low- esr electrolytic capacitors. for best results, use low esr capacitors to keep the output voltage ripple low. the output voltage ripple can be estimated by: out out out esr s1 in s vv 1 v1r fl v 8fc2 ?? ?? ?? ?? ? ? ?? ?? ??? ?? ?? where l 1 is the inductor value and r esr is the equivalent series resistance (esr) value of the output capacitor. for ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and the capacitance causes the majority of the output voltage ripple. for simplification, the output voltage ripple can be estimated by: out out out 2 in s1 vv ? v1 v 8f l c2 ?? ??? ?? ??? ?? for tantalum or electrolytic capacitors, the esr dominates the impedance at the switching frequency. for simplification, the output ripple can be approximated to: out out out esr in s1 vv ? v1r fl v ?? ???? ?? ? ?? the characteristics of the output capacitor also affect the stability of the regulation system. the MP9943 can be optimized for a wide range of capacitance and esr values. the characteristics of the output capacitor also affect the stability of the regulation system. the MP9943 can be optimized for a wide range of capacitance and esr values. bst resistor and external bst diode a 20 ? resistor in series with bst capacitor is recommended to reduce the sw spike voltage. higher resistance is better for sw spike reduction, but will compromise the efficiency on the other hand. bst voltage may become insufficient at some particular specs. in this case an external bootstrap diode can enhance the efficiency of the regulator and avoid bst voltage insufficient at light load pfm operation. the bst voltage insufficient is more likely to happen at given either of following conditions:
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 17 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ? v in is below 5v ? v out is 5v or 3.3v; and d uty cycle is high: d= in out v v >65% in these cases, if bst voltage insufficient happens, the output ripple voltage may become extremely large at light load condition, add an external bst diode from the vcc pin or v out to bst pin, as shown in figure 7. figure 7: optional external bootstrap diode to enhance efficiency the recommended external bst diode is 1n4148, and the bst capacitor value is 0.1f to 1 f. pcb layout (8) pcb layout, especially the input capacitor and vcc capacitor placement, is very important to achieve stable operation. for the best results, follow these guidelines: 1) place the ceramics input capacitor as close to in and gnd pins as possible, especially the small package size (0603) input bypass capacitor. keep the connection of input capacitor and in pin as short and wide as possible. 2) place the vcc capacitor to vcc pin and gnd pin as close as possible. make the trace length of vcc pin-vcc capacitor anode-vcc capacitor cathode-chip gnd pin as short as possible. 3) use large ground plane directly connect to gnd pin. add vias near the gnd pin if bottom layer is ground plane. 4) route sw, bst away from sensitive analog areas such as fb. 5) place the t-type feedback resistor close to chip to ensure the trace which connects to fb pin as the short as possible. notes: 8) the recommended layout is based on the figure 9 typical application circuit on page 19. top layer bottom layer figure 8: recommended pcb layout
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 18 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. design example below is a design example following the application guidelines for the specifications: table 2: design example v in 12v v out 5v i out 3a peak the detailed application schematic is shown in figure 9. the typical performance and circuit waveforms have been shown in the typical performance characteristics section. for more device applications, please refer to the related evaluation board datasheets.
MP9943 ? 36v, 3a peak synchron ous step-down converter MP9943 rev.1.1 www.monolithicpower.com 19 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits figure 9: 12v in , 5v/3a peak output figure 10: 12v in , 3.3v/3a peak output
MP9943 ? 36v, 3a peak synchron ous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP9943 rev.1.0 www.monolithicpower.com 20 7/4/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-8 (3mm x 3mm)

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