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1 for more information www.linear.com/ltc2373-16 typical a pplica t ion fea t ures descrip t ion 16-bit, 1msps, 8-channel sar adc with 96db snr a pplica t ions the lt c ? 2373-16 is a low noise, high speed, 8- channel 16-bit successive approximation register ( sar) adc. oper - ating from a single 5 v supply, the ltc2373-16 has a highly configurable, low crosstalk 8- channel input multiplexer, supporting fully differential, pseudo-differential unipolar and pseudo-differential bipolar analog input ranges. the ltc2373-16 achieves 1 lsb inl ( maximum) in all input ranges, no missing codes at 16- bits and 96 db ( fully dif - ferential)/ 93.4db (pseudo-differential) snr (typical). the ltc2 373-16 has an onboard low drift (20 ppm/ c max ) 2.048v temperature-compensated reference and a single- shot capable reference buffer. the ltc2373-16 also has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3.3 v and 5 v logic through which a sequencer with a depth of 16 may be programmed. an internal os - cillator sets the conversion time, easing external timing considerations. the ltc2373-16 dissipates only 40mw and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also provided to reduce the power consumption of the ltc2373-16 to 300 w for further power savings during inactive periods. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765, 7961132, 8319673. n 1msps throughput rate n 16-bit resolution with no missing codes n 8-channel multiplexer with selectable input range n fully differential (4.096v) n pseudo-differential unipolar (0v to 4.096v) n pseudo-differential bipolar (2.048v) n inl: 1lsb (maximum) n snr: 96db (fully differential)/93.4db (pseudo- differential) (t ypical) at f in = 1khz n thd: C110db (typical) at f in = 1khz n programmable sequencer n selectable digital gain compression n single 5v supply with 1.8v to 5v i/o voltages n spi-compatible serial i/o n onboard 2.048v reference and reference buffer n no pipeline delay, no cycle latency n power dissipation 40mw (typical) n guaranteed operation to 125c n 32-lead 5mm 5mm qfn package n programmable logic controllers n industrial process control n high speed data acquisition n portable or compact instrumentation n ate integral nonlinearity vs output code sample clock 237316 ta01a 10f 0.1f 5v muxout ? muxout + adcin + adcin ? 1.8v to 5v 47f 1200pf 10 10 1200pf refbuf gnd reset rdl sdo sck sdi busy cnv ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com ltc2373-16 mux v dd 2.2f 0.1f refin v ddlbyp ov dd 16-bit sampling adc + ? ? + 4.096v 0v 0v 4.096v 0v 2.048v 4.096v 0v 4.096v 0v ltc 2373-16 237316fa 65536 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 ?0.0 0.2 0.4 0.6 fully differential 0.8 1.0 inl error (lsb) 237316 ta01b bipolar unipolar output code 0 16384 32768 49152
2 for more information www.linear.com/ltc2373-16 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (notes 1, 2) 32 33 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1ch2 ch3 muxout + adcin + adcin ? muxout ? ch4 ch5 reset gnd sdo sck sdi busy rdl gnd ch1 ch0 com v dd v ddlbyp gnd gnd ov dd ch6 ch7 gnd refbuf refin gnd gnd cnv t jmax = 125c, ja = 44c/w exposed pad is gnd (pin 33) must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2373cuh-16#pbf ltc2373cuh-16#trpbf 237316 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc2373iuh-16#pbf ltc2373iuh-16#trpbf 237316 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc2373huh-16#pbf ltc2373huh-16#trpbf 237316 32-lead (5mm 5mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. supply voltage (v dd ) ................................................. 6v su pply voltage ( ov dd ) ............................................... 6v ana log input voltage ( note 3) ch 0 to ch 7, com ........ ( gn d C 0.3 v) to (v dd + 0.3 v) re fbuf ....................... ( gn d C 0.3 v) to (v dd + 0.3 v) refin ...................................................................... 2. 8 v digital input voltage ( note 3) ........................... ( gn d C0.3 v) to ( ov dd + 0.3 v) digital output voltage ( note 3) ........................... ( gn d C0.3 v) to ( ov dd + 0.3 v) power dissipation .............................................. 50 0 mw operating temperature range ltc 2 373 c ................................................ 0 c to 70 c ltc 2 373 i ............................................. C 40 c to 85 c ltc 2 373 h .......................................... C4 0 c to 125 c storage temperature r ange .................. C 65 c to 150 c http://www .linear.com/product/ltc2373-16#orderinfo ltc 2373-16 237316fa
3 for more information www.linear.com/ltc2373-16 e lec t rical c harac t eris t ics c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in + absolute input range (ch0 to ch7) (note 5) l C0.1 v refbuf + 0.1 v v in C absolute input range (ch0 to ch7, com) fully differential (note 5) pseudo-differential unipolar (note 5) pseudo-differential bipolar (note 5) l l l C0.1 C0.1 v refbuf /2 C 0.1 0 v refbuf /2 v refbuf + 0.1 0.1 v refbuf /2 + 0.1 v v v v in + C v in C input differential voltage range fully differential pseudo-differential unipolar pseudo-differential bipolar l l l Cv refbuf 0 Cv refbuf /2 v refbuf v refbuf v refbuf /2 v v v v cm common mode input range pseudo-differential bipolar and fully differential (note 6) l Cv refbuf /2 C 0.1 v refbuf /2 v refbuf /2 + 0.1 v i in analog input leakage current l C1 1 a c in analog input capacitance sample mode hold mode 75 5 pf pf cmrr input common mode rejection ratio fully differential, f in = 500khz pseudo-differential unipolar , f in = 500 khz pseudo-differential bipolar, f in = 500khz 67 66 66 db db db symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise fully differential pseudo-differential unipolar pseudo-differential bipolar 0.3 0.6 0.6 lsb rms lsb rms lsb rms inl integral linearity error fully differential (note 7) pseudo-differential unipolar (note 7) pseudo-differential bipolar (note 7) l l l C1 C1 C1 0.1 0.1 0.1 1 1 1 lsb lsb lsb dnl differential linearity error fully differential (note 6) pseudo-differential unipolar (note 6) pseudo-differential bipolar (note 6) l l l C0.5 C0.5 C0.5 0.1 0.1 0.1 0.5 0.5 0.5 lsb lsb lsb zse zero -scale error fully differential (note 8) pseudo-differential unipolar (note 8) pseudo-differential bipolar (note 8) l l l C6 C6 C8 0.5 0.5 0.5 6 6 8 lsb lsb lsb zero -scale error drift fully differential pseudo-differential unipolar pseudo-differential bipolar 1 2 2 mlsb /c mlsb/c mlsb/c zero-scale error match fully differential pseudo-differential unipolar pseudo-differential bipolar l l l C6 C7 C8 0.5 1 1 6 7 8 lsb lsb lsb fse full -scale error fully differential refbuf = 4.096v (refbuf overdriven) (notes 8, 9) refin = 2.048v (refin overdriven) (note 8) pseudo-differential unipolar refbuf = 4.096v (refbuf overdriven) (notes 8, 9) refin = 2.048v (refin overdriven) (note 8) pseudo-differential bipolar refbuf = 4.096v (refbuf overdriven) (notes 8, 9) refin = 2.048v (refin overdriven) (note 8) l l l l l l C15 C25 C20 C45 C15 C30 2 3 1 4 2 3 15 25 20 45 15 30 lsb lsb lsb lsb lsb lsb ltc 2373-16 237316fa
4 for more information www.linear.com/ltc2373-16 dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 10) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio fully differential f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential unipolar f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven) l l l 93 90.5 90.5 96 93.4 93.4 db db db fully differential f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential unipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential bipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) 97 94.5 94.5 db db db fully differential f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 95 91.5 db db snr signal-to-noise ratio fully differential f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential unipolar f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven) l l l 93 90.5 90.5 96 93.4 93.4 db db db fully differential f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential unipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential bipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) 97 94.5 94.5 db db db fully differential f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 95 91.5 db db c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units full-scale error drift fully differential refbuf = 4.096v (refbuf overdriven) (note 9) pseudo-differential unipolar refbuf = 4.096v (refbuf overdriven) (note 9) pseudo-differential bipolar refbuf = 4.096v (refbuf overdriven) (note 9) 0.2 0.2 0.2 ppm/c ppm/c ppm/c full -scale error match fully differential refbuf = 4.096v (refbuf overdriven) (note 9) pseudo-differential unipolar refbuf = 4.096v (refbuf overdriven) (note 9) pseudo-differential bipolar refbuf = 4.096v (refbuf overdriven) (note 9) l l l C6 C7 C8 0.5 1 1 6 7 8 lsb lsb lsb ltc 2373-16 237316fa
5 for more information www.linear.com/ltc2373-16 symbol parameter conditions min typ max units thd total harmonic distortion fully differential f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential unipolar f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven) l l l C114 C110 C110 C101 C100 C100 db db db fully differential f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential unipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential bipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) C111 C110 C110 db db db fully differential f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 C113 C110 db db sfdr spurious free dynamic range fully differential f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential unipolar f in = 1khz, refin = 2.048v (refin overdriven) pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven) l l l 101 100 100 114 110 110 db db db fully differential f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential unipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) pseudo-differential bipolar f in = 1khz, refbuf = 5v (refbuf overdriven) (note 9) 112 112 112 db db db fully differential f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 pseudo-differential bipolar f in = 1khz, refin = 2.048v (refin overdriven), sel = 1 112.5 113.5 db db channel -to-channel crosstalk f in = 100khz, signal applied to an off channel C107 db C3db input linear bandwidth 22 mhz aperture delay 500 ps aperture jitter 4 ps rms transient response full-scale step 460 ns dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 10) i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v refin internal reference output voltage 2.043 2.048 2.053 v v refin temperature coefficient (note 11) l 4 20 ppm/c refin output impedance 15 k v refin line regulation v dd = 4.75v to 5.25v 0.06 mv/v refin input voltage range (refin overdriven) (note 5) 1.25 2.4 v ltc 2373-16 237316fa
6 for more information www.linear.com/ltc2373-16 a d c ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1 msps t conv conversion time l 460 527 ns t acq acquisition time t acq = t cyc C t conv C t busylh (note 6) l 460 ns t cyc time between conversions l 1 s t cnvh cnv high time l 20 ns t cnvl minimum low time for cnv (note 13) l 20 ns t busylh cnv to busy delay c l = 20pf l 13 ns t reseth reset pulse width l 200 ns t quiet sck, sdi and rdl quiet time from cnv (note 6) l 20 ns p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v ov dd supply voltage l 1.71 5.25 v i vdd i ovdd i nap i sleep supply current supply current nap mode current sleep mode current 1 msps sample rate 1msps sample rate (c l = 20pf) conversion done (i vdd + i ovdd ) sleep mode (i vdd + i ovdd ) l l l l 8 0.7 1.25 60 11 1.5 120 ma ma ma a p d power dissipation nap mode sleep mode 1 msps sample rate conversion done (i vdd + i ovdd ) sleep mode (i vdd + i ovdd ) 40 6.25 300 55 7.5 600 mw mw w digi t al i npu t s an d digi t al o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma r e f erence b u ff er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v refbuf reference buffer output voltage v refin = 2.048v l 4.088 4.096 4.104 v refbuf input voltage range (refbuf overdriven) (notes 5, 9) l 2.5 5 v refbuf output impedance v refin = 0v (buffer disabled) 13 k i refbuf refbuf load current v refbuf = 5v (refbuf overdriven) (notes 9, 12) v refbuf = 5v, nap mode (refbuf overdriven) (note 9) l 1 0.38 1.2 ma ma ltc 2373-16 237316fa
7 for more information www.linear.com/ltc2373-16 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd or ov dd without latchup. note 4: v dd = 5v, ov dd = 2.5v, f smpl = 1mhz, refin = 2.048v unless otherwise noted. note 5: recommended operating conditions. note 6: guaranteed by design, not subject to test. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: fully differential zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 0111 1111 1111 1111 and 1000 0000 0000 0000 in straight binary format and 0000 0000 0000 0000 and 1111 1111 1111 1111 in twos complement format. unipolar zero-scale error is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. bipolar zero-scale error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. fully differential full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from the ideal and includes the effect of offset error. bipolar full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. note 9: when refbuf is overdriven, the internal reference buffer must be turned off by setting refin = 0v. note 10: all specifications in db are referred to a full-scale v refbuf (fully differential), 0v to v refbuf (pseudo-differential unipolar), or v refbuf /2 (pseudo-differential bipolar) input. note 11: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 12: f smpl = 1mhz, i refbuf varies proportionally with sample rate. note 13: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 14: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising edge capture. figure 1. voltage levels for timing specifications the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) e lec t rical c harac t eris t ics 0.8 ? ov dd 0.2 ? ov dd 50% 50% 237316 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay t sck sck period (notes 13, 14) l 10 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 13) l 4 ns t hsdisck sdi hold time from sck (note 13) l 1 ns t dsdo sdo data valid delay from sck c l = 20pf, ov dd = 5.25v c l = 20pf, ov dd = 2.5v c l = 20pf, ov dd = 1.71v l l l 7.5 8 9.5 ns ns ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 6) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 6) l 5 ns t en bus enable time after rdl (note 13) l 16 ns t dis bus relinquish time after rdl (note 13) l 13 ns t wake refbuf wake-up time c refbuf = 47f, c refin = 0.1f 200 ms t cnvmrst cnv to mux starts resetting delay l 38 ns t mrst1 mux reset time during conversion l 36 ns t vldmrst 8th sck to mux starts resetting delay after programming 1st valid configuration word l 40 ns t mrst2 mux reset time during acquisition after programming 1st valid configuration word l 42 ns ltc 2373-16 237316fa
8 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics snr, sinad vs input level, f in = 1khz differential nonlinearity vs output code dc histogram (near full-scale) 32k point fft f smpl = 1msps, f in = 1khz 32k point fft f smpl = 1msps, f in = 1khz, refbuf = 5v snr, sinad vs refbuf, f in = 1khz thd, harmonics vs refbuf, f in = 1khz integral nonlinearity vs output code dc histogram (zero-scale) t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, fully differential range, v cm = 2.048v, f smpl = 1msps, unless otherwise noted. ltc 2373-16 237316fa ?0.6 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?0.4 amplitude (dbfs) 237316 g06 snr sinad refbuf voltage (v) 2.5 3 3.5 4 4.5 ?0.2 5 94.0 94.5 95.0 95.5 96.0 96.5 97.0 snr, sinad (dbfs) 237316 g07 ?0.0 snr sinad input level (db) ?40 ?30 ?20 ?10 0 94.0 94.5 0.2 95.0 95.5 96.0 96.5 97.0 snr, sinad (dbfs) 237316 g09 thd 3rd 2nd 0.4 refbuf voltage (v) 2.5 3 3.5 4 4.5 5 ?135 ?130 ?125 0.6 ?120 ?115 ?110 ?105 thd, harmonics (dbfs) 237316 g08 0.8 1.0 inl error (lsb) output code 237316 g01 output code ?32768 ?16384 0 16384 32768 ?0.5 ?0.4 ?0.3 ?32768 ?0.2 ?0.1 ?0.0 0.1 0.2 0.3 0.4 0.5 dnl error (lsb) 237316 g02 ?16384 = 0.21 code ?1 0 1 0 50000 100000 150000 200000 0 250000 counts 237316 g03 = 0.25 code 32744 32745 32746 0 50000 16384 100000 150000 200000 250000 counts 237216 g04 snr = 96.1db thd = ?114.3db sinad = 96.0db sfdr = 117.4db 32768 frequency (khz) 0 100 200 300 400 500 ?180 ?160 ?140 ?1.0 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 237316 g05 snr = 96.7db ?0.8 thd = ?110.8db sinad = 96.6db sfdr = 111.7db frequency (khz) 0 100 200 300 400 500
9 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics snr, sinad vs temperature, f in = 1khz psrr vs frequency thd, harmonics vs temperature, f in = 1khz inl vs temperature full-scale error vs temperature refbuf = 4.096v zero-scale error vs temperature snr, sinad vs input frequency thd, harmonics vs input frequency cmrr vs input frequency t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, fully differential range, v cm = 2.048v, f smpl = 1msps, unless otherwise noted. frequency (khz) 0 cmrr (db) 60 50 75 100 200 500 237316 g12 70 65 55 300 400 80 frequency (khz) 1 psrr (db) 75 65 60 55 50 45 90 10 1k 237316 g13 85 80 70 100 95 ltc 2373-16 237316fa 35 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 thd, harmonics (dbfs) 237316 g11 50 snr sinad temperature (c) ?40 ?25 ?10 5 20 35 50 65 65 80 95 110 125 94.5 95.0 95.5 96.0 96.5 80 97.0 snr, sinad (dbfs) 237316 g14 thd 2nd 3rd temperature (c) ?40 ?25 ?10 95 5 20 35 50 65 80 95 110 125 ?130 110 ?125 ?120 ?115 ?110 ?105 thd, harmonics (dbfs) 237316 g15 125 ?1.0 ?0.5 0 max inl 0.5 1.0 inl error (lsb) 237316 g16 +fs ?fs temperature (c) ?40 ?25 ?10 min inl 5 20 35 50 65 80 95 110 125 0 temperature (c) 0.5 1.0 1.5 2.0 full-scale error (lsb) 237316 g17 temperature (c) ?40 ?25 ?10 ?40 5 20 35 50 65 80 95 110 125 0 ?25 0.5 1.0 1.5 2.0 zero?scale error (lsb) 237316 g18 snr sinad frequency (khz) 0 ?10 25 50 75 100 125 150 175 200 70 75 5 80 85 90 95 100 snr, sinad (dbfs) 237316 g10 thd 2nd 3rd 20 frequency (khz) 0 25 50 75 100 125 150 175 200
10 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics differential nonlinearity vs output code dc histogram (near full-scale) 32k point fft f smpl = 1msps, f in = 1khz 32k point fft f smpl = 1msps, f in = 1khz, refbuf = 5v snr, sinad vs refbuf, f in = 1khz thd, harmonics vs refbuf, f in = 1khz integral nonlinearity vs output code dc histogram (zero-scale) t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, pseudo-differential unipolar range, f smpl = 1msps, unless otherwise noted. snr, sinad vs input level, f in = 1khz ltc 2373-16 237316fa ?0.6 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?0.4 ?40 ?20 0 amplitude (dbfs) 237316 g24 snr sinad refbuf voltage (v) 2.5 3 ?0.2 3.5 4 4.5 5 90 91 92 93 94 95 ?0.0 snr, sinad (dbfs) 237316 g25 thd 3rd 2nd refbuf voltage (v) 2.5 3 3.5 4 0.2 4.5 5 ?130 ?125 ?120 ?115 ?110 ?105 thd, harmonics (dbfs) 237316 g26 0.4 snr sinad input level (db) ?40 ?30 ?20 ?10 0 90 91 0.6 92 93 94 95 snr, sinad (dbfs) 237316 g27 0.8 1.0 inl error (lsb) output code 237316 g19 output code 0 16384 32768 49152 65536 ?0.5 ?0.4 ?0.3 0 ?0.2 ?0.1 ?0.0 0.1 0.2 0.3 0.4 0.5 dnl error (lsb) 237316 g20 16384 = 0.46 code 6 7 8 9 10 0 50000 100000 32768 150000 200000 250000 counts 237316 g21 = 0.51 code 65512 65513 65514 49152 65515 65516 0 50000 100000 150000 200000 counts 237316 g22 snr = 93.6db 65536 thd = ?110.0db sinad = 93.5db sfdr = 114.7db frequency (khz) 0 100 200 300 400 500 ?1.0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?0.8 amplitude (dbfs) 237316 g23 snr = 94.4db thd = ?110.0db sinad = 94.3db sfdr = 112.8db frequency (khz) 0 100 200
11 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics snr, sinad vs temperature, f in = 1khz psrr vs frequency thd, harmonics vs temperature, f in = 1khz inl vs temperature full-scale error vs temperature refbuf = 4.096v zero-scale error vs temperature snr, sinad vs input frequency thd, harmonics vs input frequency cmrr vs input frequency t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, pseudo-differential unipolar range, f smpl = 1msps, unless otherwise noted. frequency (khz) 0 cmrr (db) 60 50 75 100 200 500 237316 g30 70 65 55 300 400 80 frequency (khz) 1 psrr (db) 75 65 60 55 50 45 90 10 1k 237316 g31 85 80 70 100 95 ltc 2373-16 237316fa 35 70 75 80 85 90 95 snr, sinad (dbfs) 237316 g28 thd 2nd 50 3rd frequency (khz) 0 25 50 75 100 125 150 175 65 200 ?120 ?110 ?100 ?90 ?80 ?70 ?60 thd, harmonics (dbfs) 237316 g29 80 thd 2nd 3rd temperature (c) ?40 ?25 ?10 5 20 35 95 50 65 80 95 110 125 ?130 ?125 ?120 ?115 110 ?110 ?105 thd, harmonics (dbfs) 237316 g33 125 92.0 92.5 93.0 snr 93.5 94.0 94.5 snr, sinad (dbfs) 237316 g32 max inl min inl temperature (c) ?40 ?25 sinad ?10 5 20 35 50 65 80 95 110 125 temperature (c) ?1.0 ?0.5 0 0.5 1.0 inl error (lsb) 237316 g34 temperature (c) ?40 ?25 ?40 ?10 5 20 35 50 65 80 95 110 125 ?25 1.0 1.5 2.0 2.5 3.0 full?scale error (lsb) 237316 g35 temperature (c) ?40 ?25 ?10 ?10 5 20 35 50 65 80 95 110 125 5 0 0.5 1.0 1.5 2.0 zero?scale error (lsb) 237316 g36 snr sinad frequency (khz) 20 0 25 50 75 100 125 150 175 200 65
12 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, pseudo-differential bipolar range, f smpl = 1msps, unless otherwise noted. snr, sinad vs input level, f in = 1khz differential nonlinearity vs output code dc histogram (near full-scale) 32k point fft f smpl = 1msps, f in = 1khz 32k point fft f smpl = 1msps, f in = 1khz, refbuf = 5v snr, sinad vs refbuf, f in = 1khz thd, harmonics vs refbuf, f in = 1khz integral nonlinearity vs output code dc histogram (zero-scale) ltc 2373-16 237316fa ?0.6 200 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?0.4 ?60 ?40 ?20 0 amplitude (dbfs) 237316 g42 snr sinad input level (db) ?40 ?0.2 ?30 ?20 ?10 0 90 91 92 93 94 95 ?0.0 snr, sinad (dbfs) 237316 g45 snr sinad refbuf voltage (v) 2.5 3 3.5 4 4.5 0.2 5 90 91 92 93 94 95 snr, sinad (dbfs) 237316 g43 thd 0.4 3rd 2nd refbuf voltage (v) 2.5 3 3.5 4 4.5 5 ?130 0.6 ?125 ?120 ?115 ?110 ?105 thd, harmonics (dbfs) 237316 g44 0.8 1.0 inl error (lsb) output code 237316 g37 output code 0 16384 32768 49152 65536 ?0.5 ?0.4 ?0.3 0 ?0.2 ?0.1 ?0.0 0.1 0.2 0.3 0.4 0.5 dnl error (lsb) 237316 g38 16384 = 0.47 code ?2 ?1 0 1 2 0 50000 100000 32768 150000 200000 250000 counts 237316 g39 = 0.48 code 32743 32744 32745 49152 32746 32747 0 50000 100000 150000 200000 250000 counts 237316 g40 65536 snr = 93.5db thd = ?110.3db sinad = 93.4db sfdr = 112.8db frequency (khz) 0 100 200 300 400 ?1.0 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 ?0.8 0 amplitude (dbfs) 237316 g41 snr = 94.2db thd = ?109.5db sinad = 94.1db sfdr = 112.0db frequency (khz) 0 100
13 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, pseudo-differential bipolar range, f smpl = 1msps, unless otherwise noted. snr, sinad vs temperature, f in = 1khz psrr vs frequency thd, harmonics vs temperature, f in = 1khz inl vs temperature full-scale error vs temperature refbuf = 4.096v zero-scale error vs temperature snr, sinad vs input frequency thd, harmonics vs input frequency cmrr vs input frequency frequency (khz) 0 cmrr (db) 65 50 60 55 75 100 200 500 400 237316 g48 70 300 80 frequency (khz) 1 psrr (db) 75 65 60 55 50 45 90 10 1k 237316 g49 85 80 70 100 95 ltc 2373-16 237316fa 125 95 110 125 0 0.5 1.0 1.5 2.0 zero-scale error (lsb) 237316 g54 150 thd 2nd 3rd frequency (khz) 0 25 50 75 100 125 175 150 175 200 ?120 ?110 ?100 ?90 ?80 ?70 ?60 200 thd, harmonics (dbfs) 237316 g47 thd 2nd 3rd temperature (c) ?40 ?25 ?10 5 65 20 35 50 65 80 95 110 125 ?130 ?125 70 ?120 ?115 ?110 ?105 thd, harmonics (dbfs) 237316 g51 75 80 85 90 snr 95 snr, sinad (dbfs) 237316 g46 snr sinad temperature (c) ?40 ?25 ?10 5 sinad 20 35 50 65 80 95 110 125 92.0 92.5 frequency (khz) 93.0 93.5 94.0 94.5 snr, sinad (dbfs) 237316 g50 max inl min inl temperature (c) ?40 0 ?25 ?10 5 20 35 50 65 80 95 110 25 125 ?1.0 ?0.5 0 0.5 1.0 inl error (lsb) 237316 g52 +fs ?fs 50 temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 75 95 110 125 0 0.5 1.0 1.5 2.0 full?scale error (lsb) 237316 g53 100 temperature (c) ?40 ?25 ?10 5 20 35 50 65 80
14 for more information www.linear.com/ltc2373-16 typical p er f or m ance c harac t eris t ics t a = 25c, v dd = 5v, ov dd = 2.5v, refin = 2.048v, f smpl = 1msps, unless otherwise noted. internal reference output vs temperature internal reference output temperature coefficient distribution supply current vs sampling rate crosstalk fft (ac crosstalk- channel adjacent to muxout) crosstalk fft (ac crosstalk- channel not adjacent to muxout) supply current vs temperature sleep current vs temperature input leakage current vs temperature (muxout shorted to adcin) temperature (c) ?40 supply current (ma) 2 0 6 8 ?25 ?10 20 35 5 50 125 80 95 110 237316 g55 4 65 10 i vdd i ovdd temperature (c) ?40 supply current (a) 20 0 60 80 ?25 ?10 20 35 5 50 125 80 95 110 237316 g56 40 65 100 temperature (c) ?40 leakage current (na) ?100 ?200 60 100 ?25 ?10 20 35 5 50 125 80 95 110 237316 g57 65 200 on channel, v(chx,com) = 5v off channel, v(chx,com) = 5v on channel, v(chx,com) = 0v off channel, v(chx,com) = 0v temperature (c) ?40 internal reference output (v) 2.046 2.045 2.047 2.044 2.048 2.049 2.050 2.051 ?25 ?10 20 35 5 50 125 80 95 110 237316 g58 65 2.052 drift (ppm/c) 0 number of parts 30 25 20 15 10 5 40 35 237316 g59 ?8 ?6 ?4 ?2 0 2 4 6 8 1210 ?12 ?10 sampling frequency (khz) 0 supply current (ma) 2 0 6 8 100 200 300 400 500 1000 700 800 900 237316 g60 4 600 10 i vdd i ovdd ltc 2373-16 237316fa 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 sfdr = 107.3db 0 amplitude (dbfs) 327316 g61 sfdr = 127db f in = 100khz frequency (khz) 0 100 f in = 100khz 200 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 frequency (khz) ?60 ?40 ?20 0 amplitude (dbfs) 237316 g62 0 100 200 300 400
15 for more information www.linear.com/ltc2373-16 p in func t ions ch0 to ch 7 (pins 1, 2, 7, 8, 9, 10, 31 and 32): analog inputs. ch0 to ch7 can be configured as single-ended inputs relative to com, or as pairs of differential input channels. see the analog input multiplexer section. unused analog inputs should be tied to a dc voltage within the analog input voltage range of (gnd C 0.3 v) to (v dd + 0.3v) as specified in absolute maximum ratings. muxout + , muxout C (pin 3, pin 6): analog output pins of mux. adcin + , adcin C (pin 4, pin 5): analog input pins of adc core. gnd (pins 11, 14, 15, 17, 23, 26, 27 and exposed pad pin 33): ground. refbuf (pin 12): reference buffer output. an onboard buffer nominally outputs 4.096 v to this pin. this pin is referred to gnd and should be decoupled closely to the pin with a 47 f ceramic capacitor. the internal buffer driving this pin may be disabled by grounding its input at refin. once the buffer is disabled, an external refer - ence may overdrive this pin in the range of 2.5 v to 5v. a resistive load greater than 500 k can be placed on the reference buffer output. refin (pin 13): reference output/reference buffer in- put. an onboard bandgap reference nominally outputs 2.048v at this pin. bypass this pin with a 0.1 f ceramic capacitor to gnd to limit the reference output noise. if more accuracy is desired, this pin may be overdriven by an external reference in the range of 1.25v to 2.4v. cnv (pin 16): convert input. a rising edge on this input powers up the part and initiates a new conversion. logic levels are determined by ov dd . rdl (pin 18): read low input. when rdl is low, the serial data i/o bus is enabled. when rdl is high, the serial data i/o bus becomes hi-z. rdl also gates the external shift clock. logic levels are determined by ov dd . busy (pin 19): busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. logic levels are determined by ov dd . sdi (pin 20): serial data input. data provided on this pin in synchrony with sck can be used to program the mux channel configuration, converter input range and digital gain compression setting via the sequencer. input data on sdi is latched on rising edges of sck when the serial data i/o bus is enabled. logic levels are determined by ov dd . sck (pin 21): serial data clock input. when the serial data i/o bus is enabled, the conversion result followed by configuration information is shifted out at sdo on the rising edges of this clock msb first. serial input data is latched on the rising edges of this clock at sdi. logic levels are determined by ov dd . sdo (pin 22): serial data output. the conversion result followed by configuration information is output on this pin on each rising edge of sck msb first when the serial data i/o bus is enabled. the output data format is de- termined by the converter operating mode. logic levels are determined by ov dd . reset ( pin 24): reset input. when this pin is brought high, the ltc2373-16 is reset. if this occurs during a conver - sion, the conversion is halted and the data bus becomes hi-z. logic levels are determined by ov dd . ov dd (pin 25): i/o interface digital power. the range of ov dd is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. v ddlbyp (pin 28): 2.5 v supply bypass pin. the voltage on this pin is generated via an onboard regulator off of v dd . this pin must be bypassed with a 2.2 f ceramic capacitor to gnd. applying an external voltage to this pin can cause damage to the ic or improper operation. v dd (pin 29): 5 v power supply. the range of v dd is 4.75v to 5.25 v . bypass v dd to gnd with a 10 f ceramic capacitor . com (pin 30): common input. this is the reference point for all single-ended inputs. it must be free of noise and connected to gnd for unipolar conversions and refbuf/2 for bipolar conversions. if unused, this input should be tied to a dc voltage within the analog input voltage range of (gnd C 0.3 v) to (v dd + 0.3 v) as specified in absolute maximum ratings. ltc 2373-16 237316fa
16 for more information www.linear.com/ltc2373-16 func t ional b lock diagra m v dd = 5v ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com ov dd = 1.8v to 5v v ddlbyp = 2.5v rdl 15k 8-channel multiplexer gnd refin = 1.25v to 2.4v refbuf = 2.5v to 5v adcin ? muxout ? adcin + muxout + 2x reference buffer sdo sck sdi cnv busy reset 2.048v reference control logic ldo sequencer ltc2373-16 16-bit sampling adc spi port + ? 237316 bd01 ltc 2373-16 237316fa
17 for more information www.linear.com/ltc2373-16 ti m ing diagra m typical conversion and serial interface timing nap convert d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo sck cnv reset = 0 n n + 1 busy rdl sos a3 a2 a1 a0 c7 hi-z hi-z data from conversion n configuration word from conversion n c6 c5 c4 c3 c2 c1 c0 sdi 237316 td01 configuration word for conversion n + 1 r1 r0 sel ltc 2373-16 237316fa
18 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion overview the ltc2373-16 is a low noise, high speed, highly con- figurable 8-channel 16-bit successive approximation register ( sar) adc. the ltc2373-16 features a low crosstalk 8- channel input multiplexer ( mux) and a high performance 16- bit accurate adc core that can be con- figured to accept fully- differential, pseudo - differential unipolar and pseudo-differential bipolar input signals. the input range of the adc core can be set independently of the mux input channel configuration. the outputs of the mux and inputs of the adc core are pinned out, allowing flexibility in how the mux is connected to the adc core. the mux may be wired directly to the adc core or signal conditioning circuitry may be inserted between the mux and adc core, depending on the application. the ltc2373 - 16 also has a selectable digital gain compression (dgc) feature. the ltc2373-16 has a programmable sequencer that can be programmed with configuration words ranging from a depth of one up to a maximum depth of 16 configuration words. the ltc2373-16 has an onboard low drift reference and a single-shot capable reference buffer. the ltc2373-16 also has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3.3v and 5 v logic . the ltc2373- 16 automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. a sleep mode is also provided for further power savings during inactive periods. converter operation the ltc2373-16 operates in two phases. during the ac - quisition phase when muxout + / C is wired to adcin + / C , the charge redistribution capacitor d/a converter (cdac) is connected through the mux to the selected mux analog input pins. a rising edge on the cnv pin initiates a conversion. during the conversion phase, the 16-bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. v refbuf /2, v refbuf /4 v refbuf /65536) using a differ- ential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16- bit digital output code for serial transfer. figure 2. ltc 2373 -16 two s complement transfer function . straight binary transfer function can be obtained by inverting the most significant bit ( msb ) of each output code transfer function the ltc2373-16 digitizes the full-scale voltage of 2 refbuf in fully differential mode and refbuf in pseudo- differential mode into 2 16 levels. with refbuf = 4.096v, the resulting lsb sizes in fully differential and pseudo- differential modes are 125 v and 62.5 v, respectively. the binary format of the conversion result depends on the converter input range as described in table?6. the ideal twos complement transfer function is shown in figure 2, while the ideal straight binary transfer function is shown in figure 3. the ideal straight binary transfer function can be obtained from the twos complement transfer function by inverting the most significant bit ( msb) of each output code. figure 3. ltc 2373 -16 straight binary transfer function . input voltage (v) 0v output code (two?s complement) ?1 lsb 237316 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/65536 input voltage (v) output code (straight binary) 237316 f03 111...111 111...110 100...001 100...000 000...000 000...001 011...110 unipolar zero 011...111 fsr ? 1lsb 0v fsr = +fs 1lsb = fsr/65536 ltc 2373-16 237316fa
19 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion figure 4. equivalent circuit for the differential analog inputs of the ltc 2373 -16 analog inputs the ltc2373-16 can be configured to accept one of three voltage ranges: fully differential (4.096 v), pseudo- differential unipolar (0 v to 4.096v ), and pseudo- differential bipolar (2.048v ). in all three ranges, the adc samples and digitizes the voltage difference between the two adc core analog input pins ( adcin + ? adcin ? ), and any unwanted signal that is common to both inputs is reduced by the common mode rejection ratio ( cmrr) of the adc. the mux outputs the voltages of the selected mux analog input channels to muxout + / C , according to the mux configu- ration. muxout + / C may be wired directly to adcin + / C or connected through a buffer. refer to the configuring the ltc2373-16 section for details on how to select the analog input range and mux channel configuration. independent of the selected range or channel configuration, the mux analog inputs can be modeled by the equivalent circuit shown in figure 4. chx and chy are distinct input pins selected from the ch0 to ch7 mux analog inputs, depending on the mux configuration. each pin has esd protection diodes. the adc core analog inputs, adcin + / C , each see a sampling network consisting of approximately 50pf (c in ) from the sampling cdac in series with 40 (r on ) from the on-resistance of the sampling switch. the mux is modeled by a 40 resistor representing the mux switch on-resistance (r sw ) and a capacitance to ground, c par , at the output summing node of the mux. c par is a lumped capacitance on the order of 20 pf formed primarily by pin parasitics and diode junctions. parasitic capacitances from the pcb will also contribute to c par . this capacitance is discharged through a switch to ground every conversion cycle or when a first new configuration is programmed to minimize crosstalk due to charge sharing between channels. during acquisition, each active mux analog input sees a cascade of two first order lowpass filters formed by r sw , c par and the adc sampling network when muxout + / C is wired directly to adcin + / C . if a buffer is inserted between muxout + / C and adcin + / C , then each active mux analog input only sees a first order lowpass filter formed by r sw and c par that is loaded with the input impedance of the buffer. both c in and c par draw current spikes while being charged during acquisition. if muxout + / C is wired directly to adcin + / C , the current spikes from the charging of both capacitors are drawn from the active mux analog inputs. a buffer inserted between muxout + / C and adcin + / C will absorb the current spike from c in , leaving the current spike from c par to be drawn from the active mux analog inputs. during conversion and sleep, the mux analog inputs and adc core analog inputs draw only a small leakage current. 237316 f04 v dd r on 40 c in 50pf adcin + or v dd r on 40 c in 50pf bias voltage adcin ? muxout + muxout ? mux adc core or v dd r sw 40 c par 20pf ch x v dd v dd r sw 40 ch y , com c par 20pf v dd ltc 2373-16 237316fa
20 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion fully differential input range the fully differential input range provides the widest input signal swing, configuring the adc to digitize the differential analog input voltage to the adc core (adcin + ? adcin ? ) provided through the selected mux analog inputs over a span of v refbuf . in this range, the adcin + and adcin ? pins should be driven 180 degrees out-of-phase with respect to each other, centered around a common mode voltage (adcin + + adcin ? )/2 that is restricted to (v refbuf /2 0.1 v). both the adcin + and adcin ? pins are allowed to swing from (gnd ? 0.1 v) to (v refbuf + 0.1v). unwanted signals common to both inputs are reduced by the cmrr of the adc. the output data format may be selected as straight binary or twos complement. pseudo-differential unipolar input range in the pseudo-differential unipolar input range, the adc digitizes the differential analog input voltage to the adc core (adcin + ? adcin ? ) provided through the selected mux analog inputs over a span of (0 v to v refbuf ). in this range, a single-ended unipolar input signal, driven on the adcin + pin, is measured with respect to the signal ground reference level, driven on the adcin ? pin. the adcin + pin is allowed to swing from (gnd ? 0.1 v) to (v refbuf + 0.1v), while the adcin ? pin is restricted to (gnd 0.1v). unwanted signals common to both inputs are reduced by the cmrr of the adc. the output data format is straight binary. pseudo-differential bipolar input range in the pseudo-differential bipolar input range, the adc digitizes the differential analog input voltage to the adc core (adcin + ? adcin ? ) provided through the selected mux analog inputs over a span of (v refbuf /2). in this range, a single-ended bipolar input signal, driven on the adcin + pin, is measured with respect to the signal mid- scale reference level, driven on the adcin ? pin. the adcin + pin is allowed to swing from (gnd ? 0.1 v) to (v refbuf + 0.1 v), while the adcin ? pin is restricted to (v refbuf /2 0.1 v). unwanted signals common to both inputs are reduced by the cmrr of the adc. the output data format is twos complement. input drive circuits whether muxout + / ? is wired directly to adcin + / ? or through a buffer with high input impedance, the mux analog inputs of the ltc2373-16 are high impedance. in either case, a low impedance source can directly drive the mux analog inputs without gain error. a high impedance source should be buffered in both cases to minimize set- tling time during acquisition and to optimize adc linearity. for best performance, a buffer amplifier should be used to drive the mux analog inputs of the ltc2373-16 with muxout + / ? wired directly to adcin + / ? . the amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spikes drawn by the mux analog inputs when entering acquisition. noise and distortion the noise and distortion of the buffer amplifiers and signal sources must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the inputs of the buffers driving the mux analog inputs with an appropriate filter to minimize noise. the simple 1- pole rc lowpass filter ( lpf1) shown in figure 5 is sufficient for many applications. buffer amplifiers with low noise density must be selected to minimize snr degradation. coupling filter networks (lpf2) should be placed between the buffer outputs and mux analog inputs to both minimize the noise contribu- tion of the buffers and reduce disturbances reflected into the buffer from mux analog input sampling transients. if a buffer amplifier is used between muxout + / ? and adcin + / ? , a coupling filter network ( lpf3) should be placed between the buffer output and adc core analog inputs to both minimize the noise contribution of the buf- fer and reduce disturbances reflected into the buffer from the adc core analog input sampling transients. long rc time constants at the mux or adc core analog inputs will slow down the settling of those inputs. therefore, lpf2 and lpf3 typically require wider bandwidths than lpf1. ltc 2373-16 237316fa
21 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion figure 5. input signal chain the mux and adc core analog inputs may be modeled as a switched capacitor load on the drive circuit. a drive circuit may rely partially on attenuating switched- capacitor current spikes with small filter capacitors c filt placed directly at the adc inputs and partially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance. amplifiers optimized for dc performance may not have sufficient bandwidth to fully recover at the adcs maximum conversion rate, which can produce nonlinearity and other errors. coupling filter circuits may be classified in three broad categories: fully settled: this case is characterized by filter time constants and an overall settling time that are consider- ably shorter than the sample period. when acquisition begins, the coupling filter is disturbed. for a typical first order rc filter, the disturbance will look like an initial step with an exponential decay. the amplifier will have its own response to the disturbance, which may include ringing. if the input settles completely ( to within the accuracy of the ltc2373-16), the disturbance will not contribute any error . table 1 lists typical recommended values for the r and c of each lpf mentioned. table 1. recommended r and c values for each lowpass filter rx() cx(pf) bandwidth lpf1 50 100000 31.8khz lpf2 10 1200 13mhz lpf3 25 2700 2.4mhz high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input currents one of the biggest challenges in coupling an amplifier to the ltc2373-16 is in dealing with current spikes drawn by the mux and adc core analog inputs at the start of each acquisition phase. lpf2 and lpf3 are examples of coupling filters that are used to both filter noise and re- duce sampling transients due to the current spikes. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer muxout + / ? bandlimiting signal source noise bandlimiting buffer noise and reducing sampling transients bandlimiting buffer noise and reducing sampling transients adcin + / ? lpf2 lpf2 lpf2 lpf2 1/2 lpf2 ltc2373-16 16-bit adc core + ? 237316 f05 signal sources lpf1 lpf1 lpf1 lpf1 1/2 lpf1 lpf3 r x r x c x c x lpfx ltc 2373-16 237316fa
22 for more information www.linear.com/ltc2373-16 figure 6. equivalent circuit for the mux analog inputs of the ltc 2373 -16 at 1 msps figure 7. rc equivalent circuit for two mux analog input channels a pplica t ions i n f or m a t ion partially settled: in this case, the beginning of acquisition causes a disturbance of the coupling filter, which then begins to settle out towards the nominal input voltage. however, acquisition ends ( and the conversion begins) before the input settles to its final value. this generally produces a gain error, but as long as the settling is linear, no distortion is produced. the coupling filters response is affected by the amplifiers output impedance and other parameters. a linear settling response to fast switched- capacitor current spikes can not always be assumed for precision, low bandwidth amplifiers. the coupling filter serves to attenuate the current spikes high frequency energy before it reaches the amplifier. fully averaged: consider the case where muxout + / C is directly wired to adcin + / C . if the coupling filters capaci- tors (c filt ) at the mux analog inputs are much larger than the sum of the adcs sample capacitors (50 pf) and the mux s output summing node capacitances (20 pf), then the sampling glitch is greatly attenuated. the driving amplifier effectively only sees the average sampling current, which is quite small. at 1 msps, the equivalent input resistance is approximately 14k ( as shown in figure 6), a benign resis - tive load for most precision amplifiers. however, resistive voltage division will occur between the coupling filters dc resistance and muxs equivalent (switched-capacitor) input resistance, thus producing a gain error. the first form of crosstalk is often referred to as static crosstalk. in static crosstalk, a signal applied to an off channel, v interferer , couples capacitively into the input signal path, thus corrupting the input signal of the on channel, v signal . figure 7 shows an rc model of two mux input channels and the associated parasitic capacitances. capacitive coupling from an off channel into the input signal path can occur through c sw of an off switch to the muxout + / C output pins or through c pin to an adja- cent input pin or the muxout + / C output pins. coupling through c pin to the muxout + / C pins is the dominant coupling mechanism that limits the crosstalk to C107db with a 100 khz input signal applied to an off ch3 or ch4. these pins sit adjacent to the muxout + and muxout C pins, respectively. the second form of crosstalk is referred to as adjacent channel crosstalk, which has to do with memory from the input of one channel affecting the sampled value of another channel. in this case, c par at the output summing nodes of the mux, muxout + / C , can act as memory storage elements if not dealt with properly. the potential cross- talk mechanism here is through charge sharing. c par is charged approximately to the voltage of each channel that is sampled. if that charge is not cleared when switching from one channel to the next, then charge sharing between the charge on the filter capacitor (c filt ) of one channel will occur with the charge from another channel stored on c par . the unwanted charge from c par can take a long time to settle out depending on the input filter bandwidth. c par is discharged through a low impedance switch to ground every conversion cycle or when a first new configuration is programmed to mitigate this effect. crosstalk crosstalk is a typical concern in systems that employ multiplexers. the ltc2373-16 features a low crosstalk 8-channel mux. there are two forms of crosstalk in the ltc2373-16 that potentially allow the signal from one channel to corrupt the signal from another channel being sampled. 237316 f07 c filt c filt c par ch2/ch5 ch3/ch4 muxout + / ? c pin c pin r sw v signal v interferer r sw c sw off channel on channel c sw r eq r eq bias voltage ltc2373-16 237316 f06 c filt >> c tot c tot = c in + c par = 70pf c filt >> c tot ch y , com ch x r eq = 1 f smpl ? c tot ltc 2373-16 237316fa
23 for more information www.linear.com/ltc2373-16 figure 8a. lt 6237 buffering a fully differential or pseudo - differential signal source a pplica t ions i n f or m a t ion driving the mux analog inputs the ltc2373-16 can be programmed to accept fully differential or pseudo-differential input signals. in most applications, it is recommended that the ltc2373-16 be driven using the lt6237 adc driver configured as two unity-gain buffers regardless of the input range, as shown in figure 8 a. the lt6237 combines fast settling and good dc linearity with a 1.1nv/hz input-referred noise den- sity, enabling it to achieve the full adc data sheet snr and thd specifications for all input ranges, as shown in the fft plots in figures 8b, 8c and 8d. the rc filter time constant is chosen to allow for sufficient transient settling of the ltc2373-16 mux analog inputs during acquisition. with a maximum supply current of 7.8 ma, the lt6237 is a perfect complement to the low power ltc2373-16. figure 8b. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 8a; driven with fully differential inputs figure 8c. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 8a; driven with unipolar inputs figure 8d. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 8a; driven with bipolar inputs ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer mux channels ch0 and ch1 selected muxout + / ? shorted to adcin + / ? ltc2373-16 16-bit adc core + ? 237316 f08a 1200pf lt6237 4.096v 0v 4.096v 0v 10 ? + 10 1200pf ? + 4.096v 0v 0v 4.096v 0v 2.048v 2 1 7 5 3 6 v + 8 v ? 4 ltc 2373-16 237316fa 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 snr = 96db ?40 ?20 0 amplitude (dbfs) 237316 f08b snr = 93.2db thd = ?109.1db sinad = 93.1db sfdr = 111.1db frequency (khz) thd = ?113.5db 0 100 200 300 400 500 ?180 ?160 ?140 ?120 sinad = 95.9db ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 237316 f08c snr = 93db thd = ?109.1db sfdr = 114.1db sinad = 92.9db sfdr = 110.3db frequency (khz) 0 100 200 300 400 500 ?180 frequency (khz) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 237316 f08d 100 200
24 for more information www.linear.com/ltc2373-16 maximizing snr with a single-ended to differential conversion a single-ended input signal may be converted to a fully differential signal prior to driving the mux analog inputs of the ltc2373-16 to take advantage of the higher snr of the ltc2373-16 in the fully differential input range. the LT6350 adc driver shown in figure 9 a can be used to convert a 0 v to 4.096 v input signal to a fully differential 4.096v output signal. the rc time constant is larger in this case to limit the high frequency noise contribution of the LT6350. this topology provides a 3 db increase in snr over single-ended operation and achieves the full data sheet snr performance of the fully differential input range of 96 db as shown in the fft plot in figure 9 b. the maximum supply current of 10.4 ma makes the LT6350 a good companion to the low power ltc2373-16. figure 9a. lt 6350 converting a 0v to 4.096 v single - ended signal to a 4.096 v fully differential signal a pplica t ions i n f or m a t ion figure 9b. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 9a maximizing snr for eight single-ended inputs using a shared amplifier between muxout + / C and adcin + / C while converting a single-ended signal to a fully differ- ential signal offers the benefit of higher snr, two input channels are required per single-ended input, leading to a reduced number of single-ended input signals that can be interfaced to the ltc2373-16. performing the sin- gle-ended to differential conversion using the lt6237 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer mux channels ch0 and ch1 selected muxout + / ? shorted to adcin + / ? ltc2373-16 16-bit adc core + ? 237316 f09a 3300pf LT6350 v cm = 2.048v 4.096v 0v out2 10 ? + 10 3300pf ? + 4.096v 0v out1 4.096v 0v 5 4 2 v + 3 v ? 6 + ? r int r int 1 8 3300pf ltc 2373-16 237316fa 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 snr = 96db ?40 ?20 0 amplitude (dbfs) 237316 g09b thd = ?108.7db sinad = 95.8db sfdr = 111.3db frequency (khz) 0 100 200
25 for more information www.linear.com/ltc2373-16 between muxout +/C and adcin +/C as shown in figure 10 a provides the snr benefits of the fully differential range without sacrificing additional mux inputs to do so. using the mux configurations where ch0 to ch7 is output to muxout + and com to muxout C enables eight single- ended inputs to be converted with the fully differential input range. the com mux input channel is used in the feedback connection of the buffer amplifier connected in a follower configuration to improve the distortion performance of the circuit. thd degradation would oth- erwise occur due to the non-linear voltage drop across the mux switch from the input current of the buffer and the non-linear on-resistance of the mux switch. the 1k resistor between com and muxout C maintains negative feedback around the buffer when the mux turns off, so that the buffer output does not rail. eight single-ended inputs achieve an snr of 96 db with this circuit as shown in figure 10 b, which is a 3 db improvement in snr over single-ended operation. a pplica t ions i n f or m a t ion figure 10 a. lt 6236 buffering a single - ended 0v to 4.096 v input signal and the lt 6237 configured to perform a single - ended to d ifferential conversion to the 4.096 v fully differential input range figure 10 b. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 10 a ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer mux channels ch0 and com selected muxout ? adcin ? muxout + adcin + ltc2373-16 16-bit adc core + ? 237316 f10a 1200pf v cm = 2.048v lt6237 10 ? + ? + ? + 100pf 100pf 4.096v 0v lt6236 6 2 5 1 v + v ? v + 8 v ? 4 1k 6 7 5 499 499 2 3 1 + ? 24.9 2700pf 2700pf 24.9 3 4 ltc 2373-16 237316fa 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 snr = 96db ?40 ?20 0 amplitude (dbfs) 237316 f10b thd = ?105.2db sinad = 95.6db sfdr = 105.9db frequency (khz) 0 100 200
26 for more information www.linear.com/ltc2373-16 using digital gain compression for single supply operation the ltc2373-16 offers a digital gain compression (dgc) feature which defines the full-scale input swing to be be- tween 10% and 90% of the v refbuf analog input range. this feature allows the adc driver to be powered off of a single positive supply since each input swings between 0.41v and 3.69 v with v refbuf = 4.096 v as in figure 11a. needing only a positive supply and ground to power the adc driver results in additional power savings for the entire system versus conventional systems that have a negative supply for the adc driver. with dgc enabled, the ltc2373-16 can be driven by the low power ltc6362 differential driver which is powered from a single 5 v supply. figure 11 b shows how to configure the ltc6362 to accept a 3.28 v true bipolar single-ended input signal and level shift the signal to the reduced input range of the ltc2373-16 when digital gain compression is enabled. using the lt6236 to buffer the resistor divider that creates v cm , the entire signal chain solution can be powered from a single 5 v supply, minimizing power consumption and reducing complexity. the reduced input signal swing of this single 5 v supply solution limits the achievable snr to 94 db, as shown in the fft of figure 11 c. to enable dgc, set sel=1 in the configuration word. a pplica t ions i n f or m a t ion figure 11 b. ltc 6362 configured to accept a 3.28 v input signal while running from a single 5v supply when digital gain compression is enabled in the ltc 2373 -16 figure 11 a. input swing of the ltc 2373 -16 with digital gain compression enabled and v refbuf = 4.096 v v refbuf = 4. 096v 3. 69v 0.41v 0v 237316 f11a ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer mux channels ch0 and ch1 selected v dd muxout + / ? shorted to adcin + / ? ltc2373-16 16-bit adc core + ? 237316 f11b refbuf 1500pf v source r source = 50 35.7 1k 1k 5v 35.7 1500pf 3.69v 0.41v 4.096v 3.69v 0.41v digital gain compression enabled by setting sel = 1 in the configuration word 3.28v 0v ?3.28v 4 5 v + v ? 3 6 0.22f 0.22f ? + 6 5 2 1 3 ? + ltc6362 8 1 2 850 150 1k 1k v cm 100 850 10f lt6236 4 47f 0.1f 0.1f 10f ltc 2373-16 237316fa
27 for more information www.linear.com/ltc2373-16 figure 11 c. 32k point fft f smpl = 1 msps , f in = 1 khz for circuit shown in figure 11 b adc reference there are three ways of providing the adc reference. the first is to use both the internal reference and reference buffer. the second is to externally overdrive the internal reference and use the internal reference buffer. the third is to disable the internal reference buffer and overdrive the refbuf pin from an external source. the following tables give examples of these cases and the resulting fully differential, unipolar and bipolar input ranges. table 2. internal reference with internal buffer refin refbuf fully differential input range unipolar input range bipolar input range 2.048v 4.096v 4.096v 0v to 4.096v 2.048v table 3. external reference with internal buffer refin (overdrive) refbuf fully differential input range unipolar input range bipolar input range 1.25 (min) 2.5v 2.5v 0v to 2.5v 1.25v 2.048v 4.096v 4.096v 0v to 4.096v 2.048v 2.4v (max) 4.8v 4.8v 0v to 4.8v 2.4v table 4. external reference unbuffered refin refbuf fully differential input range unipolar input range bipolar input range 0v 2.5v (min) 2.5v 0v to 2.5v 1.25v 0v 5v (max) 5v 0v to 5v 2.5v a pplica t ions i n f or m a t ion figure 12 a. ltc 2373 -16 internal reference circuit internal reference with internal buffer the ltc2373-16 has an on-chip, low noise, low drift (20ppm/c), temperature compensated bandgap refer- ence that is factory trimmed to 2.048 v. it is internally connected to a reference buffer as shown in figure 12 a and is available at refin (pin 13). refin should be bypassed to gnd with a 0.1 f ceramic capacitor to minimize noise. the reference buffer gains the refin voltage by two to 4.096v at refbuf (pin 12). bypass refbuf to gnd with at least 47 f ceramic capacitor (x7r, 10v, 1210 size) to compensate the reference buffer and minimize noise. figure 12 b. using the ltc 6655 -2.048 as an external reference external reference with internal buffer if more accuracy and/or lower drift is desired, refin can be easily overdriven by an external reference since a 15k resistor is in series with the reference as shown in figure 12 b. refin can be overdriven in the range from 1.25v to 2.4 v. the resulting voltage at refbuf will be 2 refin. linear technology offers a portfolio of high performance references designed to meet the needs of 237316 f12a 47f 6.5k 15k ltc2373-16 reference buffer refbuf refin gnd bandgap reference 6.5k 0.1f 237316 f12b 47f 6.5k 15k ltc2373-16 reference buffer refbuf refin gnd bandgap reference 6.5k 2.7f ltc6655-2.048 ltc 2373-16 237316fa 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 snr = 94db ?40 ?20 0 amplitude (dbfs) 237316 f11c thd = ?107.3db sinad = 93.8db sfdr = 109.5db frequency (khz) 0 100 200
28 for more information www.linear.com/ltc2373-16 237316 f12c 47f 6.5k 15k ltc2373-16 reference buffer refbuf refin gnd bandgap reference 6.5k ltc6655-5 figure 12 c. overdriving refbuf using the ltc 6655 -5 many applications. with its small size, low power, and high accuracy, the ltc6655-2.048 is well suited for use with the ltc2373-16 when overdriving the internal reference. the ltc6655-2.048 offers 0.025% ( max) initial accuracy and 2ppm/c ( max) temperature coefficient for high pre- cision applications. the ltc6655-2.048 is fully specified over the h-grade temperature range and complements the extended temperature range of the ltc2373-16 up to 125 c . bypassing the ltc6655-2.048 with a 2.7 f to 100 f ceramic capacitor close to the refin pin is recommended. external reference unbuffered the internal reference buffer can also be overdriven from 2.5v to 5 v with an external reference at refbuf as shown in figure 12c. to do so, refin must be grounded to disable the reference buffer. a 13 k resistor loads the refbuf pin when the reference buffer is disabled. to maximize the input signal swing and corresponding snr, the ltc6655-5 is recommended when overdriving refbuf. the ltc6655-5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-2.048. by using a 5v reference, an snr of 97 db can be achieved. bypassing the ltc6655-5 with a 47 f ceramic capacitor ( x5r, 0805 size ) close to the refbuf pin is recommended. a pplica t ions i n f or m a t ion figure 13. cnv waveform showing burst sampling external reference must provide all of this charge with a dc current equivalent to i refbuf = q conv /t cyc . thus, the dc current draw of refbuf depends on the sampling rate and output code. in applications where a burst of samples is taken after idling for long periods, as shown in figure 13, i refbuf quickly goes from approximately 380 a to a maxi- mum of 1.2 ma for refbuf = 5 v at 1 msps. this step in dc current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at refbuf will affect the accuracy of the output code. if an external reference is used to overdrive refbuf, the fast settling ltc6655-5 reference is recommended. internal reference buffer transient response for optimum transient performance, the internal reference buffer should be used. the internal reference buffer uses a proprietary design that results in an output voltage change at refbuf of less than 1 lsb when responding to a sudden burst of conversions. this makes the internal reference buffer of the ltc2373-16 truly single-shot capable since the first sample taken after idling will yield the same re- sult as a sample taken after the transient response of the internal reference buffer has settled. figures 14a, 14b, and 14 c show the transient responses of the ltc2373- 16 with the internal reference buffer and with the internal reference buffer overdriven by the ltc6655-5, both with a bypass capacitance of 47 f in fully differential, pseudo- differential unipolar, and pseudo-differential bipolar input ranges, respectively. dynamic performance fast fourier transform ( fft ) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and ana - lyzing the digital output using an fft algorithm, the adc s spectral content can be examined for frequencies outside the fundamental. the ltc2373-16 provides guaranteed tested limits for both ac distortion and noise measurements. cnv idle period idle period 237316 f13 the refbuf pin of the ltc2373-16 draws a charge ( q conv ) from the external bypass capacitor during each conversion cycle. if the internal reference buffer is overdriven, the ltc 2373-16 237316fa
29 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion figure 15. 32 k point fft f smpl = 1 msps , f in = 1 khz figure 14 a. transient response of the ltc 2373 -16 in the fully differential input range figure 14 c. transient response of the ltc 2373 -16 in the pseudo - differential bipolar input range figure 14 b. transient response of the ltc 2373 -16 in the pseudo - differential unipolar input range signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 15 shows that the ltc2373-16 achieves a typical sinad of 96db ( fully differential) at a 1mhz sampling rate with a 1khz input. signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 15 shows that the ltc2373-16 achieves a typical snr of 96db (fully differential) at a 1mhz sampling rate with a 1khz input. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd=20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v 1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics. figure 15 shows that the ltc2373-16 achieves a typical thd of C114db (fully differential) at a 1mhz sampling rate with a 1khz input. ltc 2373-16 237316fa 500 600 700 800 900 1000 ?1.0 ?0.5 0 0.5 internal reference buffer 1.0 1.5 2.0 deviation from final value (lsbs) 237316 f14a internal reference buffer external source on refbuf time (s) 0 100 external source on refbuf 200 300 400 500 600 700 800 900 1000 ?1.0 time (s) ?0.5 0 0.5 1.0 1.5 2.0 deviation from final value (lsbs) 237316 f14b internal reference buffer external source on refbuf 0 time (s) 0 100 200 300 400 500 600 700 800 100 900 1000 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 deviation from final value (lsbs) 200 237316 f14c snr = 96.1db thd = ?114.3db sinad = 96.0db sfdr = 117.4db frequency (khz) 0 100 200 300 300 400 500 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 400 ?20 0 amplitude (dbfs) 237316 f15
30 for more information www.linear.com/ltc2373-16 power considerations the ltc2373-16 provides two power supply pins: the 5 v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2373-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5 v and 3.3v systems. power supply sequencing the ltc2373-16 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2373-16 has a power-on-reset ( por) circuit that will reset the ltc2373-16 at initial power-up or whenever the power supply voltage drops below 2 v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 100 ms after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2373-16 conversion is controlled by cnv. a ris - ing edge on cnv will start a conversion and power up the l tc2373-16. once a conversion has been initiated, it cannot be restarted until the conversion is complete. for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the ltc2373-16 powers down and begins acquiring the input signal. it is not necessary to clock out all of the data and configuration bits before starting a new conversion. internal conversion clock the ltc2373-16 has an internal clock that is trimmed to achieve a maximum conversion time of 527 ns. with a mini - mum acquisition time of 460 ns, throughput performance of 1 msps is guaranteed without any external adjustments. auto nap mode the ltc2373-16 automatically enters nap mode after a conversion has been completed and completely powers up once a new conversion is initiated on the rising edge of cnv. during nap mode, only the adc core powers down and all other circuits remain active. during nap, data from the last conversion can be clocked out. the auto nap mode feature will reduce the power dissipation of the ltc2373-16 as the sampling frequency is reduced. since full power is consumed only during a conversion, the adc core of the ltc2373-16 remains powered down for a larger fraction of the conversion cycle (t cyc ) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in figure 16. a pplica t ions i n f or m a t ion figure 16. power supply current of the ltc 2373 -16 vs sampling rate sampling frequency (khz) supply current (ma) 10 237316 f16 0 2 4 6 8 0 100 200 300 400 500 600 700 800 900 1000 i vdd i ovdd sleep mode the auto nap mode feature provides limited power savings since only the adc core powers down. to obtain greater power savings, the ltc2373-16 provides a sleep mode. during sleep mode, the entire part is powered down except for a small standby current resulting in a power dissipation of 300w. to enter sleep mode, toggle cnv twice with no intervening rising edge on sck. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising ltc 2373-16 237316fa
31 for more information www.linear.com/ltc2373-16 edge on sck will wake the part up. upon emerging from sleep mode, wait t wake ms before initiating a conversion to allow the reference and reference buffer to wake-up and charge the bypass capacitors at refin and refbuf. (refer to the timing diagrams section for more detailed timing information about sleep mode.) digital interface the ltc2373-16 has a serial digital interface. the flexible ov dd supply allows the ltc2373-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3v systems. the serial data i/o bus is enabled when rdl is low. serial output data is clocked out on the sdo pin and serial input configuration data is clocked in at the sdi pin when an external clock is applied to the sck pin if the serial data i/o bus is enabled. serial output data transitions on rising edges of sck and serial input data is latched on rising edges of sck. d15 remains valid till the first rising edge of sck. after the 16 bits of the conversion result are shifted out, a start-of-sequence ( sos) bit followed by the 7- bit control word corresponding to the conversion result is shifted out. sdo will remain low after 24 sck rising edges have been issued. clocking out the data and configuration informa - tion after the conversion will yield the best performance. t able 5 lists the minimum shift clock frequency needed to achieve 1 msps throughput when shifting out a different number of bits. table 5. minimum shift clock frequency vs number of bits for 1 msps number of bits f sck (mhz) conversion result 16 37 conversion result + sos bit 17 39 conversion result + sos bit + configuration data 24 55 the configuration of the ltc2373-16 is programmed via a sequencer through the serial interface. the following sections describe the various ways the ltc2373-16 can be programmed, the operation of the sequencer and general use of the ltc2373-16. configuring the ltc2373-16 the various modes of operation of the ltc2373-16 are programmed by seven bits of an 8-bit control word, c [7:0]. the control word is shifted in at sdi on the rising edges of sck, msb first. the control word is defined as follows: c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] x a[3] a[2] a[1] a[0] r[1] r[0] sel the msb of the control word, c[7], is used during the programming of the sequencer and does not control the operating mode or configuration of the mux or adc (see programming the sequencer section). referring to table 6, bits a[3:0] ( c[6:3]) control the analog input mux channel configuration. bits r [1:0] ( c[2:1]) control the input range configuration of the adc and the sel (c[0]) bit enables/disables the digital gain compression feature (see using digital gain compression for single supply operation section). table 6. description of decoded configuration bits bits name behavior [a3:a0] mux channel configuration bits see table 7 [r 1: r 0] input range selection bits 00 C pseudo-differential unipolar input ( straight binar y output data format) 01 C pseudo-differential bipolar input ( tw o s-complement output data format) 10 C fully differential input ( straight binar y output data format) 11 C fully differential input ( tw o s-complement output data format) sel digital gain compression bit 0 C digital gain compression disabled 1 C digital gain compression enabled note : digital gain compression feature always disabled for the pseudo- differential unipolar input range. analog input multiplexer the analog input mux is programmed by the a[3:0] (c[6:3]) bits of the input control word. table 7 lists the mux configurations for all combinations of the configu- ration bits. the selected positive (+) channel is output to muxout + and the selected negative (?) channel is output to muxout ? . figure 17 shows an example of the mux configuration being updated on successive conver- sions. note how the voltages of the selected positive (+) a pplica t ions i n f or m a t ion ltc 2373-16 237316fa
32 for more information www.linear.com/ltc2373-16 figure 17. changing the configuration of the ltc 2373 -16 on successive conversions muxout ? muxout + v(ch1) adcin ? adcin + 16-bit adc core r[1:0] = 10 fully differential straight binary v(ch0) conversion #1 (+) (?) a[3:0] = 0000 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com mux muxout ? muxout + conversion #2 (+) (?) a[3:0] = 1010 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com mux 237316 f17 v(com) adcin ? adcin + 16-bit adc core r[1:0] = 00 pseudo-differential unipolar v(ch2) and negative (?) channels are output at muxout + and muxout ? , respectively. table 7. channel configuration mux configuration bits multiplexer configuration a[3] a[2] a[1] a[0] ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch 7 com 0 0 0 0 + C 0 0 0 1 + C 0 0 1 0 + C 0 0 1 1 + C 0 1 0 0 C + 0 1 0 1 C + 0 1 1 0 C + 0 1 1 1 C + 1 0 0 0 + C 1 0 0 1 + C 1 0 1 0 + C 1 0 1 1 + C 1 1 0 0 + C 1 1 0 1 + C 1 1 1 0 + C 1 1 1 1 + C sequencer the ltc2373-16 features a sequencer that can store up to 16 7- bit control words in internal memory. the 7-bit control word is defined in the configuring the ltc2373-16 section. the sequencer repeatedly cycles through the control words stored in sequencer memory on succes- sive conversions if no new valid control words are input to the part in a given transaction. the sequencer memory is shown in figure 18a. an internal memory pointer determines which of the up to 16 programmed control words is currently controlling the converter. the pointer is reset to point to the first pro- grammed c ontrol w ord each time the sequencer memory is programmed. upon reaching the final programmed control word stored in memory, the pointer is automatically reset to the first memory location and the sequence is restarted. at power - up or after r esetting the ltc2373-16, the internal sequencer memory programming defaults to a depth of 1 with control word c 0[6:0] = 0000000 (ch0 + / ch1 C , unipolar input range, digital gain compression disabled). figure 18b shows the sequencer memory programmed with 8 configurations along with the memory pointer location for conversions run after programming. start of sequence the start of sequence ( sos) bit is output to sdo on the 17th sck cycle during all spi transactions and indicates whether the configuration for the conversion just per- formed corresponds to the control word stored in the first memory location of the sequencer memory. when sos = 1, the current configuration corresponds to the first memory location of the sequencer. the sos bit can be used to align the conversion data with the corresponding control word when truncated spi transactions are used to maximize throughput. only one extra bit needs to be shifted out to maintain alignment of the configuration with the conversion data. this results in needing 17 sck cycles instead of 24, which allows a higher throughput to be achieved while being able to keep the configuration information properly aligned with the conversion data. a pplica t ions i n f or m a t ion ltc 2373-16 237316fa
33 for more information www.linear.com/ltc2373-16 programming the sequencer transaction window a transaction window opens at power-up, after resetting the ltc2373-16, and every conversion cycle at the falling edge of busy, allowing the sequencer to be programmed. once the transaction window opens, the state machine controlling the programming of the sequencer memory is in a reset state, waiting for control words to be shifted in at sdi. the transaction window closes at the start of the next conversion when busy transitions from low to high, as shown in figure 19. serial input data at sdi is ignored by the sequencer state machine when busy is high. input control word the input control word is used to determine whether or not the sequencer is being programmed. in many cases the user will simply need to configure the converter once for their specific application after power-up or resetting the part, and then drive the sdi pin to gnd. this will force the control word bits to all zeros and the converter will automatically sequence through the configurations stored in sequencer memory. the following sections provide further details on programming the sequencer. the sequencer memory may be programmed by inputting one or more valid control words at sdi. each control word is an 8-bit word as described in the configuring the ltc2373- 16 section. a valid input control word is one where c [7] = 1 and the remaining lower seven bits, c[6:0], have been shifted in before the transaction window closes as shown in figure 20 a. when the 1 st control word is successfully en- tered on the 8 th rising edge of sck, the sequencer memory is cleared, the new configuration, c[6:0], is written into the first memory location and is applied to the converter. at this point, a new acquisition window begins since the a pplica t ions i n f or m a t ion figure 19. sequencer programming transaction window cnv busy transaction window 237316 f19 sequencer memory 7-bits wide 16 control words c0[6:0] c1[6:0] c2[6:0] c3[6:0] c4[6:0] c5[6:0] c6[6:0] c7[6:0] c8[6:0] c9[6:0] c10[6:0] c11[6:0] c12[6:0] c13[6:0] c14[6:0] c15[6:0] 237316 f18a figure 18 a. internal sequencer memory figure 18 b. sequencer programmed with eight control words and the memory pointer location for conversions run after programming 237316 f18b sequencer programmed with eight control words memory pointer location .... c0[6:0] c1[6:0] c2[6:0] c3[6:0] c4[6:0] c5[6:0] c6[6:0] c7[6:0] x x x x x x x x 1st conversion 2nd conversion 3rd conversion 4th conversion 5th conversion 6th conversion 7th conversion 8th conversion 9th conversion 10th conversion 11th conversion 12th conversion 13th conversion 14th conversion 15th conversion 16th conversion ltc 2373-16 237316fa
34 for more information www.linear.com/ltc2373-16 a pplica t ions i n f or m a t ion new configuration may result in a different channel being acquired. additional valid input control words are written into subsequent memory locations. the sequencer only stores valid input control words and discards control words that are partially written or have c [7] = 0. if c[7] = 0 at any point during sequencer programming, the ltc2373-16 closes the input transaction window until the completion of the next conversion as shown in figure 20 b. figure 21 shows a truncated programming transaction where the first partial input control word is discarded and the second complete input control word is successfully programmed. the transaction window also closes after 16 successive valid input control words have been written, since the sequencer memory has been filled. figure 20 a. valid control word successfully programmed , c[7] = 1 cnv busy rdl 1 2 3 4 sck 5 6 7 8 c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] sdi don?t care start of new transaction window hi-z 1st valid control word entered sequencer memory cleared and updated new configuration applied new acquisition period begins sdo 237316 f20a d15 d14 d13 d12 d11 d10 d9 d8 d7 figure 20 b. invalid control word entered , c[7] = 0 cnv busy rdl 1 2 3 4 sck 5 6 7 8 c[7] sdi don?t care don?t care start of new transaction window hi-z transaction window closed sdo 237316 f20b d15 d14 d13 d12 d11 d10 d9 d8 d7 ltc 2373-16 237316fa
35 for more information www.linear.com/ltc2373-16 figure 21. truncated programming transaction followed by the successful programming of one configuration a pplica t ions i n f or m a t ion cnv busy rdl 1 2 3 4 sck 5 6 1 2 c[7] a[3] c[7] a[3] a[2] a[1] a[0] a[2] a[1] a[0] r[1] r[1] r[0] sel sdi don?t care don?t care start of new transaction window start of new transaction window transaction window closed partial control word discarded partial control word discarded valid control word accepted hi-z hi-z hi-z 1st valid control word entered sequencer memory cleared and updated new configuration applied new acquisition period begins sdo 237316 f21 d15 d14 d13 d12 d11 d10 d15 d14 d13 d12 d11 d10 d9 d8 3 4 5 6 7 8 ltc 2373-16 237316fa
36 for more information www.linear.com/ltc2373-16 figure 23. sequencer memory before , during and after programming figure 22. sequencer programmed with two control words a pplica t ions i n f or m a t ion sequencer memory after programming 1st control word sequencer memory after programming 2nd control word memory pointer location .... c0[6:0] = 0111100 x x x x x x x x x x x x x x x 1st conversion 2nd conversion 3rd conversion 4th conversion 237316 f23 c0[6:0] = 0111100 c1[6:0] = 1011000 x x x x x x x x x x x x x x sequencer memory from previous programming c0[6:0] c1[6:0] c2[6:0] c3[6:0] c4[6:0] c5[6:0] c6[6:0] c7[6:0] c8[6:0] c9[6:0] c10[6:0] c11[6:0] c12[6:0] c13[6:0] c14[6:0] c15[6:0] cnv busy rdl 1 2 3 4 sck 5 6 7 8 c[7] c[7] a[3] c[7] a[3] a[2] a[1] r[1]a[0] a[2] a[1] a[0] r[1] r[0] sel r[0] sel sdi don?t care don?t care start of new transaction window transaction window closed control word #1 control word #2 hi-z 1st valid control word entered sequencer memory cleared and updated new configuration applied new acquisition period begins 2nd valid control word entered sequencer memory updated sdo 237316 f22 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 9 10 11 12 13 14 15 16 17 hi-z d1 d0 sos a3 programming the sequencer with tw o configurations figure 22 illustrates the sequencer memory being pro- grammed while reading out a conversion result. c[7] of the first two input control words is 1, so these control words are valid and are written to sequencer memory in succession. c[7] of the third control word is 0, so the input transaction is terminated at this point. since there were only two valid control words entered, the sequencer memory is programmed with a depth of two. figure 23 shows the state of the sequencer memory before, dur- ing and after the programming process. the first stored configuration will instruct the converter to sample a fully differential signal on the ch7 + /ch6 C pair with digital gain compression disabled, and the second stored configura- tion will instruct the converter to sample a unipolar signal on the ch3/com pair with digital gain compression dis- abled. the converter will then alternate between the two programmed configurations on successive conversions. note that configurations stored in sequencer memory are retained until the power is cycled, the part is reset, or a new series of configuration programming words are input. ltc 2373-16 237316fa
37 for more information www.linear.com/ltc2373-16 figure 24. mux reset timing ti m ing diagra m s mux reset timing the parasitic capacitances ( c par ) on the output summing nodes of the mux, muxout + / C , are discharged to ground every conversion cycle and when a first new valid con- figuration word is programmed into the sequencer. this is done to avoid crosstalk between input channels due to charge sharing from c par . the bottom most waveform in figure 24 represents the voltages of the mux output nodes. the mux is being reset when v(muxout + / C ) sits at 0v. the mux turns off and begins resetting t cnvmrst ns after a conversion is initiated by the rising edge of cnv. after t mrst1 ns, the mux turns on to the next channel programmed in the sequencer. the mux also turns off and resets after t vldmrst ns when a first new valid configuration word is programmed into the sequencer on the 8 th rising edge of sck. this is because the mux may need to switch channels based on the newly input configuration, so memory of the previous channel needs to be cleared. a new acquisition period begins when the mux is reconnected after t mrst2 ns. cnv busy v(muxout + / ? ) 0v t mrst1 t cnvmrst 1 2 3 4 sck 5 6 7 8 sdo 237316 f24 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 9 10 11 12 13 14 15 16 d1 d0 sos sdi c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] t vldmrst t mrst2 t acq ltc 2373-16 237316fa
38 for more information www.linear.com/ltc2373-16 ti m ing diagra m s figure 25. using a single ltc 2373 -16 without programming the sequencer convert digital host irq data in sdi clk cnv busy sdo sdi sck rdl reset ltc2373-16 cnv rdl = 0 reset = 0 nap and acquire convert convert nap and acquire busy t cnvh t conv t busylh 1 2 3 15 sck 16 17 18 19 sdo 237316 f25 d15 d14 d13 d0 sos t dsdo t hsdo t sck a[3] a[2] a[1] a[0] r[1] r[0] sel 20 21 22 23 24 sdi t quiet t cnvl t cyc t acq t acq = t cyc ? t conv ? t busylh t dsdobusyl t sckh t sckl single device, sequencer not programmed rdl enables or disables the serial data i/o bus. if rdl is high, the serial data i/o bus is disabled and the serial shift clock sck is ignored. if rdl is low, sdo is driven and serial input data may be shifted in at sdi. figure 25 shows a single ltc2373-16 operated with rdl and reset tied to ground. with rdl grounded, the serial data i/o bus is enabled and the msb(d15) of the new conversion data is available t dsdobusyl after the falling edge of busy. the start-of-sequence ( sos) bit followed by the current configuration is shifted out after the conversion data. bringing sdi low during data readback as shown closes the sequencer programming window at the first rising edge of sck after the falling edge of busy since c [7] = 0. as a result, the sequencer is not programmed. ltc 2373-16 237316fa
39 for more information www.linear.com/ltc2373-16 ti m ing diagra m s single device, sequencer programmed figure 26 shows the timing for a single device being operated with rdl and reset tied to ground. with rdl grounded, the serial data i/o bus is enabled and the msb(d15) of the new conversion data is available t dsdobusyl after the falling edge of busy. the start-of- sequence ( sos) bit followed by the configuration used for the conversion just performed is shifted out after the new conversion data. when sdi is high at the first rising edge of sck after the falling edge of busy as shown, the sequencer pro- gramming window stays open, allowing the sequencer to be programmed. with the sequencer programming window figure 26. using a single ltc 2373 -16 programming the sequencer open, a valid input configuration is detected on the 8th rising edge of sck. at this point, the mux turns off and resets and sequencer memory is reset and updated with the new configuration. the new channel configuration is applied when the mux turns on, marking the beginning of a new acquisition period. on the fly device programming the sequencer may be programmed with one control word as shown in figure 26 every conversion cycle to achieve complete flexibility in the multiplexer configura- tion, input range and digital gain compression setting on each conversion. cnv rdl = 0 reset = 0 nap busy t cnvh t conv convert nap t busylh 1 2 3 4 sck 5 6 7 8 sdo 237316 f26 d15 d14 d13 d11d12 d10 d9 d8 d7 r[1] r[0] sel 9 21 22 23 24 t quiet t sck t cnvl t vldmrst + t mrst2 + t acq convert t dsdobusyl t hsdisck t ssdisck t sckl t sckh t dsdo t hsdo sdi c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] ltc 2373-16 237316fa
40 for more information www.linear.com/ltc2373-16 ti m ing diagra m s multiple devices figure 27 shows the multiple ltc2373-16 devices operat- ing and sharing cnv, sdi, sck and sdo. by sharing cnv, sdi, sck and sdo, the number of signals required to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl input of each adc must be used to allow figure 2 7. multiple devices sharing cnv , sck and sdo cnv reset = 0 nap rdl a rdl b busy t cnvh t conv convert nap t busylh 1 2 3 sck 14 15 16 sdo 237316 f27 17 18 19 t cnvl convert t hsdisck t ssdisck t dsdo t dis hi-z t hsdo t sck sdi don?t care c a [7] c a [6] c a [5] 30 31 32 t quiet t sckl t sckh t en hi-z d15 a d14 a d13 a d1 a d0 a d15 b d14 b d13 b hi-z d1 b d0 b c b [7] c b [5] c b [6] convert digital host irq sdi data in clk rdl b rdl a cnv busy sdi sdo sck rdl reset ltc2373-16 a cnv busy sdi sdo sck rdl reset ltc2373-16 b only one ltc2373-16 to drive sdo at a time in order to avoid bus conflicts. rdl must also be used to selectively program each adc through the shared sdi input line. the rdl inputs idle high and are individually brought low to read data out of and selectively program each device between conversions. when rdl is brought low, the msb(d15) of the selected device is output onto sdo. ltc 2373-16 237316fa
41 for more information www.linear.com/ltc2373-16 sleep mode the ltc2373-16 automatically naps and starts acquiring the input once a conversion has completed. only the adc core powers down in nap mode. as a result, the auto nap feature provides limited power savings. to obtain greater power savings, the ltc2373-16 provides a sleep mode. during sleep mode, the entire part is powered down except for a small standby current resulting in a 300 w power dissipation. to enter sleep mode, toggle cnv twice with no intervening rising edge on sck as shown in figure 28. the part will enter sleep mode on the falling edge of busy from the last conversion initiated. once in sleep mode, a rising edge on sck will wake the part up. upon emerging from sleep mode, wait t wake ms before initiating a conversion to allow the reference and reference buffer to wake-up and charge the bypass capacitors at refin and refbuf. the serial data i/o bus is enabled or disabled by rdl during sleep mode. sleep mode does not affect the state of the sequencer memory or memory pointer. ti m ing diagra m s figure 28. sleep mode timing diagram cnv rdl = don?t care sdi = don?t care busy sck t cnvh t conv convert nap sleep t busylh convert convert nap t conv 237316 f28 cnv rdl = don?t care sdi = don?t care busy sck t cnvh t conv convert sleep t busylh convert nap t wake t wake ltc 2373-16 237316fa
42 for more information www.linear.com/ltc2373-16 reset timing when the reset pin is high, the ltc2373-16 is reset and the serial i/o data bus is put into a high impedance mode, as shown in figure 29. the serial data output register and sequencer memory are also cleared and set to their default states. if this occurs during a conversion, the conversion ti m ing diagra m s b oar d l ayou t figure 29. reset pin timing is immediately halted. during reset, requests for new conversions are ignored. once reset returns low, the ltc2373-16 is ready to start a new conversion after the acquisition time has been met. to obtain the best performance from the ltc2373-16 a printed circuit board is recommended. layout for the printed circuit board ( pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc2071, the evaluation kit for the ltc2373-16. 237316 f29 reset cnv sdo t reseth t acq hi-z ltc 2373-16 237316fa
43 for more information www.linear.com/ltc2373-16 figure 30. top silkscreen b oar d l ayou t ltc 2373-16 237316fa
44 for more information www.linear.com/ltc2373-16 b oar d l ayou t figure 31. layer 1 component side ltc 2373-16 237316fa
45 for more information www.linear.com/ltc2373-16 b oar d l ayou t figure 32. layer 2 ground plane ltc 2373-16 237316fa
46 for more information www.linear.com/ltc2373-16 figure 33. layer 3 power plane b oar d l ayou t ltc 2373-16 237316fa
47 for more information www.linear.com/ltc2373-16 figure 34. layer 4 bottom layer b oar d l ayou t ltc 2373-16 237316fa
48 for more information www.linear.com/ltc2373-16 s che m a t ics 100mhz max clk 3.3vpp ext 2.5v 2.048v gnd bufout refbuf refbuf bufout vccio vccio vccio vccio vccio v+ v+ v- v+ v- vccio vdd vccio cm csb sck sdo clkin busy sdi wrin cnv ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 vcm c26 opt c26 opt u2 nc7sz04p5x u2 nc7sz04p5x 4 5 3 2 j1 bnc j1 bnc c4 0.1uf c4 0.1uf c37 opt c37 opt r12 1k r12 1k r129 opt r129 opt r22 221 r22 221 r15 0 r15 0 c24 opt c24 opt c104 opt c104 opt c9 opt c9 opt r18 opt r18 opt r11 1k r11 1k r16 opt r16 opt + - en u8 lt6236cs6 + - en u8 lt6236cs6 3 4 1 6 5 2 c32 0.1uf c32 0.1uf u5 nc7sz04p5x u5 nc7sz04p5x 4 5 3 2 r130 opt r130 opt c34 1uf c34 1uf c3 0.1uf c3 0.1uf c31 1200pf c31 1200pf r24 0 r24 0 r13 opt r13 opt c29 opt c29 opt jp9 gnd cm com jp9 gnd cm com 1 3 2 c22 3300pf c22 3300pf c6 0.1uf c6 0.1uf c13 47uf 10v 1210 x7r c13 47uf 10v 1210 x7r u4 nl17sz74 u4 nl17sz74 cp 1 clr 6 pr 7 d 2 q 3 q 5 vcc 8 gnd 4 + - u7a opt + - u7a opt 3 2 1 8 4 sdi sdi c7 10uf 0805 25v c7 10uf 0805 25v r4 1k r4 1k c2 0.1uf c2 0.1uf r1 1k r1 1k r17 opt r17 opt c21 3300pf c21 3300pf jp2 hd2x4-100 jp2 hd2x4-100 1 3 5 6 4 2 7 8 c27 opt c27 opt cnv cnv r8 0 r8 0 8 ch- mux u1 ltc237x * 8 ch- mux u1 ltc237x * mu xo ut- 6 ch4 7 ch5 8 ch3 2 mu xo ut+ 3 adc in+ 4 adc in- 5 sck 21 sdo 22 gnd 23 reset 24 ov dd 25 ognd 26 gnd 27 vdd lbyp 28 ch2 1 ch6 9 ch7 10 gnd 11 ref buf 12 refin 13 gnd 14 sdi 20 busy 19 rdl 18 gnd 17 cnv 16 gnd 15 ch1 32 ch0 31 com 30 vdd 29 gnd 33 c23 3300pf c23 3300pf busy busy r128 0 r128 0 r10 33 r10 33 + - u7b opt + - u7b opt 5 6 7 8 4 c8 1200pf c8 1200pf c25 1500pf c25 1500pf c10 10uf 25v 0805 c10 10uf 25v 0805 r7 opt r7 opt c5 0.1uf c5 0.1uf wrin wrin c11 0.1uf c11 0.1uf c18 0.1uf c18 0.1uf r3 49.9 1206 r3 49.9 1206 u9 ltc6655bhms8-4.096 u9 ltc6655bhms8-4.096 shdn 1 vin 2 gnd 3 gnd 4 gnd 5 vout_s 6 vout_f 7 gnd 8 c19 4.7uf c19 4.7uf r20 787 r20 787 c35 10uf 25v 0805 c35 10uf 25v 0805 c1 0.1uf c1 0.1uf c17 opt c17 opt e1 refbuf e1 refbuf r21 10 r21 10 c15 opt c15 opt e2 ext_cm e2 ext_cm r6 33 r6 33 c14 1200pf c14 1200pf c12 0.1uf c12 0.1uf sck sck r9 33 r9 33 c16 opt c16 opt c30 1uf c30 1uf c33 2.2uf c33 2.2uf r19 opt r19 opt c36 0.1uf c36 0.1uf c103 opt c103 opt r131 opt r131 opt c20 opt c20 opt r14 opt r14 opt c28 1500pf c28 1500pf jp1 ext int ref jp1 ext int ref 1 3 2 u3 nc7sz04p5x u3 nc7sz04p5x 4 5 3 2 sdo sdo r23 1k r23 1k oe a b gnd vcc u6 nc7sz66p5x oe a b gnd vcc u6 nc7sz66p5x 1 3 5 2 4 r5 33 r5 33 r2 33 r2 33 ltc 2373-16 237316fa
49 for more information www.linear.com/ltc2373-16 s che m a t ics ain1- 0v - 4.096v ain1+ 0v - 4.096v coupling coupling ain2 +/- 8.192v ain3 0v - 4.096v coupling ain4- +/- 4.096v ain4+ +/- 4.096v v+ v- cm2 cm2 v+ v- vdd cm cm2 cm opamp+ opamp- cm2 cm ch0 ch1 ch5 ch4 ch6 ch7 vcm ch2 ch3 c108 0.01uf c108 0.01uf c90 15pf c90 15pf + - u24a lt6237cms8 + - u24a lt6237cms8 3 2 1 8 4 r117 150 r117 150 r106 opt r106 opt c82 0.1uf c82 0.1uf r121 0 r121 0 c88 0.1uf c88 0.1uf + - u25a lt1469cs8 + - u25a lt1469cs8 3 2 1 8 4 c99 10uf 6.3v c99 10uf 6.3v c100 0.22uf c0g 1812 c100 0.22uf c0g 1812 c74 10uf 6.3v c74 10uf 6.3v c75 0.1uf c75 0.1uf r97 opt r97 opt r113 0 r113 0 r109 0 r109 0 + - vocm v+ v- s hdn + - u28 ltc6362cms8 + - vocm v+ v- s hdn + - u28 ltc6362cms8 8 1 4 2 5 3 6 7 r135 20 c105 0.01uf c0g c105 0.01uf c0g j4 bnc j4 bnc j7 bnc j7 bnc c77 10uf 6.3v c77 10uf 6.3v c92 opt 1206 c92 opt 1206 r105 10 r105 10 r98 0 r98 0 c96 opt c96 opt c79 opt 1206 c79 opt 1206 + - u25b lt1469cs8 + - u25b lt1469cs8 5 6 7 8 4 r91 opt r91 opt c101 10uf 6.3v c101 10uf 6.3v j2 bnc j2 bnc jp8 ac dc -in1 jp8 ac dc -in1 1 3 2 r124 opt r124 opt c72 1uf c72 1uf r123 1k r123 1k r92 opt r92 opt c86 opt c86 opt cm cm c83 15pf c83 15pf c80 15pf c80 15pf c102 0.01uf c0g c102 0.01uf c0g r102 499 r102 499 r103 10 r103 10 c93 10uf 25v 0805 c93 10uf 25v 0805 r134 20 r115 1k r115 1k c76 10uf 6.3v c76 10uf 6.3v r107 24.9 r107 24.9 r90 0 r90 0 c87 10uf 6.3v c87 10uf 6.3v r132 20 r114 0 r114 0 r1 r2 r3 r4 ep u26 lt5400acms8e-4 r1 r2 r3 r4 ep u26 lt5400acms8e-4 5 8 1 2 3 4 7 6 9 r95 24.9 r95 24.9 jp6 ac dc +in1 jp6 ac dc +in1 1 3 2 r120 4.99k r120 4.99k r108 opt r108 opt r118 35.7 r118 35.7 c84 opt c84 opt c78 10uf 6.3v c78 10uf 6.3v r96 10 r96 10 j6 bnc j6 bnc + - u24b lt6237cms8 + - u24b lt6237cms8 5 6 7 8 4 r93 opt r93 opt c97 0.22uf c0g 1812 c97 0.22uf c0g 1812 j5 bnc j5 bnc r125 20k r125 20k c107 0.01uf c107 0.01uf r119 35.7 r119 35.7 c89 10uf 6.3v c89 10uf 6.3v r122 100 r122 100 c85 1uf c85 1uf r110 opt r110 opt c106 0.01uf c0g c106 0.01uf c0g r111 1k r111 1k r137 opt r137 opt jp7 ac dc in3 jp7 ac dc in3 1 3 2 r112 0 r112 0 r100 opt r100 opt c94 0.1uf c94 0.1uf r133 20 c81 opt 1206 c81 opt 1206 c73 0.1uf c73 0.1uf c98 10uf 25v 0805 c98 10uf 25v 0805 c91 10uf 6.3v c91 10uf 6.3v r104 24.9 r104 24.9 r94 0 r94 0 r126 10k r126 10k r99 10 r99 10 + - + - u27 LT6350cms8 + - + - u27 LT6350cms8 out2 5 +in1 8 -in1 1 +in2 2 v+ 3 out1 4 shdn 7 v- 6 r116 20k r116 20k e13 cm2 e13 cm2 r127 1k r127 1k r101 24.9 r101 24.9 j3 bnc j3 bnc c95 4.7uf 10v c95 4.7uf 10v ltc 2373-16 237316fa
50 for more information www.linear.com/ltc2373-16 p ackage descrip t ion please refer to http://www .linear.com/product/ltc2373-16#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) ltc 2373-16 237316fa
51 for more information www.linear.com/ltc2373-16 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 3/17 corrected table numbering 27 ltc 2373-16 237316fa
52 for more information www.linear.com/ltc2373-16 ? linear technology corporation 2015 lt 0317 rev a ? printed in usa www.linear.com/ltc2373-16 r ela t e d p ar t s typical a pplica t ion part number description comments adcs ltc2378-20/ltc2377-20 ltc2376-20 20- bit, 1msps/500ksps/250ksps, 0.5ppm inl serial, low power adc 2.5v supply, 5v fully differential input, 104db snr, msop-16 and 4mm 3mm dfn-16 packages ltc2379-18/ltc2378-18 ltc2377-18/ltc2376-18 18- bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16 ltc2377-16/ltc2376-16 16- bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2369-18/ltc2368-18 ltc2367-18/ltc2364-18 18- bit, 1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 96.5db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2370-16/ltc2368-16 ltc2367-16/ltc2364-16 16- bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 0v to 5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2756 18-bit, serial i out softspan? dac 1lsb inl/dnl, software-selectable ranges, ssop-28 package ltc2641 16-bit/14-bit/12-bit single serial v out dac 1lsb inl/dnl, msop-8 package, 0v to 5v output ltc2630 12-bit/10-bit/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references ltc6655 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v/2.048v/1.2v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt6237/lt6236 dual/single rail-to-rail output adc driver 215mhz gbw, 1.1nv/ hz, 3.5ma supply current LT6350 low noise single-ended-to-differential adc driver rail-to-rail inputs and outputs, 240ns, 0.01% settling time ltc6362 low power, fully differential input/output amplifier/driver single 2.8v to 5.25v supply, 1ma supply current, msop-8 and 3mm 3mm dfn-8 packages ltc 6362 configured to accept a 10 v input signal using a single 5v supply with digital gain compression enabled on the ltc 2373 -16 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 8-channel multiplexer mux channels ch0 and ch1 selected muxout + / ? shorted to adcin + / ? digital gain compression enabled by setting sel = 1 in the configuration word ltc2373-16 16-bit adc core + ? 237316 ta02 1500pf 3.69v 3.69v 0.41v 0.41v 10f ltc6362 35.7 47f v dd refbuf 35.7 1500pf 0.22f 0.22f ? + 5 4 1 8 6 333 333 850 850 3 2 1k ? + lt6236 ltc6362 1k v cm 150 100 r source = 50 10v 0v ?10v v source 10f 10f v + v ? 6 3 4 25 1 5v 4.096v ltc 2373-16 237316fa

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