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? 2016 microchip technology inc. advance information ds60001432a-page 1 IS2063 features ? qualified for bluetooth v4.2 specifications ? supports hfp 1.6, hsp 1.2, a2dp 1.3, spp 1.2 and avrcp 1.6 ? supports bluetooth 4.2 dual-mode (br/edr/ble) (fw dependent): - generic access service - device information service - proprietary services for data communication - apple notification center service (ancs) ? supports high resolution up to 24-bit, 96 khz audio data format ?i 2 s digital audio, microphone, analog audio and aux-in ? supports one microphone input ? uart, gpios and leds ? supports firmware field upgrade ? battery charging baseband features ? 16 mhz main clock input ? built-in flash memory for programing ? connects simultaneously two hosts (smartphone and tablet) with hfp/a2dp profiles ? adaptive frequency hopping (afh) audio codec ? sub-band coding (sbc) and optional advanced audio coding (aac) decoding ? 20-bit dac with 98 db snr ? 16-bit adc with 92 db snr ? supports up to 24-bit, 96 khz i 2 s digital audio rf features ? class 2 output power (+2 dbm typical) ? receive sensitivity: -90 dbm (2 mbps edr) ? combined tx/rx rf terminal simplifies external matching and reduces external antenna switches ? tx/rx rf switch for class 2 or class 3 applica- tions ? integrated synthesizer requires no external volt- age-controlled oscillator (vco), varactor diode, resonator and loop filter ? crystal oscillator with built-in digital trimming com- pensates for temperature or process variations dsp audio processing ? 32-bit dsp core ? supports 64 kbps a-law, -law pcm format/con- tinuous variable slope delta (cvsd) modulation for synchronous connection-oriented (sco) channel operation ? supports 8/16 khz noise suppression ? supports 8/16 khz echo cancellation ? supports modified sub-band coding (msbc) decoder for wide band speech ? built-in high definition clean audio (hca) algo- rithms for both narrow band and wide band speech processing ? packet loss concealment (plc) ? built-in audio effect algorithms to enhance audio streaming ? supports serial copy management system (scms-t) content protection packages type lga pin count 68 contact/lead pitch 0.4 dimensions 8 x 8 x 0.9 note: all dimensions are in millimeters (mm) unless specified. bluetooth ? 4.2 stereo audio soc
IS2063 ds60001432a-page 2 advance information ? 2016 microchip technology inc. peripherals ? high-speed hci-uart interface (supports up to 921,600 bps) ? built-in lithium-ion and lithium-polymer battery charger (up to 350 ma) ? integrated 1.8v and 3v configurable switching regulator and low-dropout (ldo) ? built-in adc for battery monitoring and voltage sensor ? an aux-in port for external audio input ? three led drivers operating condition ? operating voltage: 3.2v to 4.2v ? temperature range: -20c to +70c applications ? soundbars and subwoofers ? speaker phones ? headsets and headphones description the IS2063 is a stereo audio soc qualified for bluetooth v4.2 with enhanced data rate (edr). it integrates a 32-bit dsp co-processor and a codec which is dedicated for voice and audio applications. for voice applications, the cvsd encoding/decoding, 8k/ 16k noise reduction and echo cancellation are implemented. for audio applications, the sbc and aac low-complexity (aac-lc) decoding functions are used. the IS2063 soc features a 20-bit audio dac in addition to an i 2 s digital audio interface that supports up to 24-bit, 96 khz data formats. the system optimization includes an integrated battery voltage sensor, a battery charger, a switching regulator and ldos.
? 2016 microchip technology inc. advance information ds60001432a-page 3 IS2063 table of contents 1.0 device overview ............................................................................................................ ........................................... 5 2.0 audio ...................................................................................................................... ................................................. 11 3.0 transceiver ................................................................................................................ ............................................. 15 4.0 microcontroller ............................................................................................................ ............................................ 17 5.0 power management unit ...................................................................................................... .................................. 19 6.0 application information .................................................................................................... ....................................... 21 7.0 antenna placement rule ..................................................................................................... ................................... 29 8.0 electrical characteristics................................................................................................. ........................................ 31 9.0 package information ........................................................................................................ ....................................... 39 10.0 reflow profile and storage condition ...................................................................................... ............................. 43 11.0 ordering information ...................................................................................................... ....................................... 47 appendix a: reference circuit .................................................................................................. .................................... 49 appendix b: revision history................................................................................................... ..................................... 53 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation i ssues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
IS2063 ds60001432a-page 4 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 5 IS2063 1.0 device overview the IS2063 soc integrates a bluetooth 4.2 radio trans- ceiver, a power management unit (pmu), a microcon- troller (mcu), an audio codec, a crystal and a 32-bit dsp. the IS2063 soc can be configured using the ui tool. figure 1-1 illustrates a typical block diagram of the IS2063 soc. figure 1-1: IS2063 soc block diagram note: the ui tool is a windows-based utility tool, which is available for download from the microchip web site at: www.micro- chip.com/IS2063 .
IS2063 ds60001432a-page 6 advance information ? 2016 microchip technology inc. table 1-1 provides the key features of the IS2063 soc. table 1-1: IS2063 key features feature IS2063 application multi-speaker/soundbar/subwoofer stereo/mono stereo pin count 68 dimensions (mm 2 ) 8 x 8 audio dac output 2 channel dac (single-ended) snr at 2.8v (db) -98 dac (capless) snr at 2.8v (db) -96 adc snr at 2.8v (db) -92 i 2 s digital interface yes analog aux-in yes mono microphone 1 external audio amplifier interface yes uart yes led driver 3 internal dc-dc step-down regulator yes dc 5v adapter input yes battery charger (350 ma max.) yes adc for thermal charger protection no undervoltage protection (uvp) no gpio 15 button support 6 nfc (triggered by external nfc) yes eeprom 128k customized voice prompt no multitone yes dsp sound effect yes ble yes bluetooth profiles hfp 1.6 avrcp 1.6 a2dp 1.3 hsp 1.2 spp 1.2
? 2016 microchip technology inc. advance information ds60001432a-page 7 IS2063 figure 1-2 illustrates the pin diagram of the IS2063 soc. figure 1-2: IS2063 soc pin diagram
IS2063 ds60001432a-page 8 advance information ? 2016 microchip technology inc. table 1-2 provides the pin description of the IS2063 soc. users can configure these pins using the ui tool. table 1-2: IS2063 soc pin description pin no pin type name description 1 p vddao power supply (3.3v) dedicated to codec output amplifi- ers; connect to the codec_vo pin 2 o aohpm headphone common mode output/sense input 3 o aohpl left channel analog headphone output 4 p vdda power supply (3.3v) or reference voltage for external codec; connect to codec_vo pin 5 p vcom internal biasing voltage for codec, connect a 4.7 f capacitor to ground 6 i mic_n1 mic1 mono differential analog negative input 7 i mic_p1 mic1 mono differential analog positive input 8 p mic_bias electric microphone biasing voltage 9 i air right channel, single-ended analog input 10 i ail left channel, single-ended analog input 11 p vdd_core core 1.2v power input; connect to cldo_o pin; con- nect to gnd through a 1 f (x5r/x7r) capacitor 12 o p1_2 i 2 c scl (eeprom clock) 13 i/o p1_3 i 2 c sda (eeprom data sda) 14 i rst_n system reset (active-low) 15 p vdd_io i/o power supply input (3.3v); connect to ldo31_vo (pin # 24); connect to gnd through a 1 f (x5r/x7r) capacitor 16 i/o p0_1 configurable control or indication pin (internally pulled up if configured as an input) ? class1 tx control signal for external rf t/r switch, active-high 17 i p2_4 system configuration pin along with p2_0 and ean pins can be used to set the IS2063 soc in any one of these modes: ? application mode (for normal operation) ? test mode (to change eeprom values) ? write flash mode (to load a new firmware into the soc), see ta b l e 6 - 1 18 i/o p0_4 configurable control or indication pin (internally pulled up if configured as an input) ? nfc detection pin, active-low ? out_ind_1 19 i/o p1_5 configurable control or indication pin (internally pulled up if configured as an input) ? nfc detection pin, active-low ? slide switch detector, active-high ? out_ind_1 ? multi-spk master/slave mode control (fw depen- dent) 20 i hci_rxd hci uart data input 21 o hci_txd hci uart data output
? 2016 microchip technology inc. advance information ds60001432a-page 9 IS2063 22 p codec_vo ldo output for codec power 23 p ldo31_vin ldo input, connect to sys_pwr (pin # 29) 24 p ldo31_vo 3v ldo output, for vdd_io power, do not calibrate 25 p adap_in 5v power adapter input 26 p bat_in battery input, voltage range: 3.2v to 4.2v 27 i adc_in analog input 28 p sar_vdd sar 1.8v input; connect to bk_o pin 29 p sys_pwr system power output from bat_in or adap_in 30 p bk_vdd 1.8v buck vdd power input; connect to sys_pwr pin 31 p bk_lx 1.8v buck pwm/pfm output 32 p bk_o 1.8v buck feedback input 33 imfb ? multi-function button and power-on key ? uart rx ind, active-high 34 i led3 led driver 3 35 i led2 led driver 2 36 i led1 led driver 1 37 i/o p3_7 configurable control or indication pin (internally pulled up if configured as an input) uart tx_ind, active-low 38 i/o p3_5 configurable control or indication pin (internally pulled down if configured as an input) 39 i/o p0_0 configurable control or indication pin (internally pulled up if configured as an input) ? slide switch detector, active-high 40 i/o p0_3 configurable control or indication pin (internally pulled up, if configured as an input) 41 i ean external address-bus negative system configuration pin along with p2_0 and p2_4 pins, used to set the IS2063 soc in any one of the following three modes: ? application mode (for normal operation), ? test mode (to change eeprom values), and ? write flash mode (to load a new firmware into the soc), see table 6-1 42 p avdd_usb usb power input; connect to ldo31_vo pin 43 i/o dm differential data-minus usb 44 i/o dp differential data-plus usb 45 p cldo_o 1.2v core ldo output 46 p pmic_in pmu power input 47 p rfldo_o 1.28v rf ldo output 48 p vbg bandgap output reference for decoupling interference 49 p ulpc_vsus ulpc 1.2v output power, maximum loading 1 ma 50 i xo_n 16 mhz crystal input negative 51 i xo_p 16 mhz crystal input positive 52 p vcc_rf rf power input (1.28v) for both synthesizer and tx/rx block 53 i/o rtx rf path (transmit/receive) pin no pin type name description
IS2063 ds60001432a-page 10 advance information ? 2016 microchip technology inc. legend: i= input pin o= output pin i/o= input/output pin p= power pin note: all i/o pins can be configured using the ui tool. 54 i/o p3_1 configurable control or indication pin (internally pulled up if configured as an input) ? rev key (default), active-low 55 i/o p3_3 configurable control or indication pin (internally pulled up if configured as an input) ? fwd key (default), active-low 56 i/o p3_6 configurable control or indication pin (internally pulled up if configured as an input) ? multi-spk master/slave mode control (fw depen- dent) 57 i/o p0_2 configurable control or indication pin (internally pulled up if configured as an input) play/pause key (default) 58 i/o p2_0 system configuration pin along with the ean and p2_4 pins, used to set the IS2063 soc in any one of the fol- lowing modes: ? application mode (for normal operation), ? test mode (to change eeprom values), and ? write flash mode (to load a new firmware into the soc), see ta b l e 6 - 1 ? pulse/pwm signal output 59 i/o p2_7 configurable control or indication pin (internally pulled up if configured as an input) volume up key (default), active-low 60 i/o p3_0 configurable control or indication pin (internally pulled up if configured as an input) aux-in detector, active-low 61 i/o tfs0 i 2 s interface: left/right clock 62 i/o p0_5 configurable control or indication pin (internally pulled up if configured as an input) volume down key (default), active-low 63 p vdd_io i/o power supply input (3.3v); connect to ldo31_vo pin 64 i/o dr0 i 2 s interface: digital left/right data 65 i/o rfs0 i 2 s interface: left/right clock 66 i/o sclk0 i 2 s interface: bit clock 67 i/o dt0 i 2 s interface: digital left/right data 68 o aohpr headphone output, right channel 69-83 p ep exposed pads, used as ground (gnd) pins pin no pin type name description
? 2016 microchip technology inc. advance information ds60001432a-page 11 IS2063 2.0 audio the input and output audios have different stages and each stage can be programmed to vary the gain response characteristics. for microphones, both sin- gle-ended inputs and differential inputs are supported. to maintain a high quality signal, a stable bias voltage source to the condenser microphone?s fet is provided. the dc blocking capacitors can be used at both posi- tive and negative sides of the input. internally, this ana- log signal is converted to 16-bit, 8/16 khz linear pcm data. 2.1 digital signal processor digital signal processor (dsp) is used to perform speech and audio processing. the advanced speech features, such as acoustic echo cancellation and noise reduction are in-built. to reduce nonlinear distortion and to help echo cancellation, an outgoing signal level to the speaker is monitored and adjusted to avoid sat- uration of speaker output or microphone input. adap- tive filtering is also applied to track the echo path impulse in response to provide echo free and full-duplex user experience. the embedded noise reduction algorithm helps to extract clean speech signals from the noisy inputs cap- tured by the microphones and improves mutual under- standing in communication. the advanced audio features, such as multi-band dynamic range control, parametric multi-band equalizer, audio widening and virtual bass are in-built. the audio effect algorithms improve the user?s audio listening experience in terms of better quality after audio signal processing. figure 2-1 and figure 2-2 illustrate the processing flow of speaker-phone applications for speech and audio signal processing. figure 2-1: speech processing figure 2-2: audio processing
IS2063 ds60001432a-page 12 advance information ? 2016 microchip technology inc. the dsp parameters can be configured using the dsp tool. for additional information on the dsp tool, refer to ?is206x dsp application note? . 2.2 codec the built-in codec has a high signal-to-noise ratio (snr) performance and it consists of an adc, a dac and an additional analog circuitry. figure 2-3 through figure 2-6 illustrate the dynamic range and frequency response of the codec. figure 2-3: codec dac dynamic range figure 2-4: codec dac thd+n versus input power note: the dsp tool and ? is206x dsp applica- tion note ? are available for download from the microchip web site at: www.microchip.com/IS2063. note: the data corresponds to the 16 ohm load with 2.8v operating voltage and +25oc operating temperature. note: the data corresponds to the 16 ohm load with 2.8v operating voltage and +25oc operating temperature.
? 2016 microchip technology inc. advance information ds60001432a-page 13 IS2063 figure 2-5: codec dac frequenc y response (capless mode) figure 2-6: codec dac frequency response (single-ended mode) note: the dac frequency response corresponds to single-ended mode with a 47 f dc block capacitor.
IS2063 ds60001432a-page 14 advance information ? 2016 microchip technology inc. 2.3 auxiliary port the IS2063 soc supports analog (line-in) signals from the external audio source. the analog (line-in) signal can be processed by the dsp to generate different sound effects (multi-band dynamic range compression and audio widening), which can be setup by using the dsp tool. 2.4 analog speaker output the IS2063 soc supports the following speaker output modes. ? capless mode ? recommended for headphone applications in which capless output connection helps to save the bom cost by avoiding a large dc blocking capacitor. figure 2-7 illustrates the capless mode. ? single-ended mode ? used for driving an exter- nal audio amplifier where a dc blocking capacitor is required. figure 2-8 illustrates the single-ended mode. figure 2-7: analog speaker output capless mode figure 2-8: analog speaker output single-ended mode
? 2016 microchip technology inc. advance information ds60001432a-page 15 IS2063 3.0 transceiver the IS2063 soc is designed and optimized for blue- tooth 2.4 ghz systems. it contains a complete radio frequency transmitter/receiver section. an internal syn- thesizer generates a stable clock for synchronizing with another device. 3.1 transmitter the internal power amplifier (pa) has a maximum output power of +4 dbm. this is applied into class 2 or class 3 radios without an external rf pa. the transmitter performs the iq conversion to minimize the frequency drift. 3.2 receiver the low-noise amplifier (lna) operates with tr-com- bined mode for the single port application. it can save the pin on the package without having an external tx/rx switch. the adc is used to sample the input analog signal and convert it into a digital signal for demodulator analysis. a channel filter is integrated into the receiver channel before the adc to reduce the external component count and increase the anti-interference capability. the image rejection filter is used to reject the image fre- quency for the low-if architecture, and it also intended to reduce the external band pass filter (bpf) compo- nent for a super heterodyne architecture. the received signal strength indicator (rssi) signal feedback to the processor is used to control the rf out- put power to make a good trade-off for effective dis- tance and current consumption. 3.3 synthesizer synthesizer generates a clock for radio transceiver operation. the vco inside, with a tunable internal lc tank, can reduce any variation for components. a crys- tal oscillator with an internal digital trimming circuit pro- vides a stable clock for the synthesizer. 3.4 modem for bluetooth 1.2 specification and below, 1 mbps was the standard data rate based on the gaussian fre- quency shift keying (gfsk) modulation scheme. this basic rate modem meets basic data rate (bdr) requirements of bluetooth 2.0 with enhanced data rate (edr) specifications. for bluetooth 2.0 and above specifications, edr is introduced to provide the data rates of 1/2/3 mbps. for baseband, both bdr and edr utilize the same 1 mhz symbol rate and 1.6 khz slot rate. for bdr, symbol 1 represents 1-bit. however, each symbol in the payload part of the edr packet represents 2 or 3 bits. this is achieved by using two different modulations, /4 dqpsk and 8 dpsk. 3.5 adaptive frequency hopping (afh) the IS2063 soc has an afh function to avoid rf inter- ference. it has an algorithm to check the nearby inter- ference and to choose a clear channel for transceiver bluetooth signal.
IS2063 ds60001432a-page 16 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 17 IS2063 4.0 microcontroller microcontroller is built into the soc to execute the blue- tooth protocols. it operates from 16 mhz to higher fre- quencies where the firmware can dynamically adjust the trade-off between the computing power and the power consumption. in rom version, the mcu firm- ware is hard-wired to minimize the power consumption for the firmware execution and to save the external flash cost. 4.1 memory there are sufficient rom and ram to fulfill the proces- sor requirements, in which a synchronous single-port ram interface is used. the register bank, dedicated single port memory, and flash memory are connected to the processor bus. the processor coordinates with all link control procedures and the data movement hap- pens using a set of pointer registers. 4.2 external reset the IS2063 soc provides a watchdog timer (wdt) to reset the soc. it has an integrated power-on reset (por) circuit that resets all circuits to a known power-on state. this action can also be driven by an external reset signal which is used to control the device externally by forcing it into a por state. the rst_n signal input is active-low and no connection is required in most of the applications. 4.3 reference clock the IS2063 soc is composed of an integrated crystal oscillation function that uses a 16 mhz 10 ppm exter- nal crystal and two specified loading capacitors to pro- vide a high quality system reference timer source. this feature is typically used to remove the initial tolerance frequency errors associated with the crystal and its equivalent loading capacitance in mass production. frequency trim is achieved by adjusting the crystal loading capacitance through the on-chip trim capaci- tors (c trim ). the value of trimming capacitance is 200 ff (200x10 -15 f) per lsb at 5-bit word and the overall adjustable clock frequency is 40 khz (based on crystal with load capacitance, c l spec = 9 pf). figure 4-1 illus- trates the crystal connection of the IS2063 soc with two capacitors. figure 4-1: crystal connection note 1: c trim = 200 ff * (1~31); c int ~ 3 pf. 2: c l = [c l1 x c l2 )/(c l1 +c l2 )]+(c trim /2)+c int (set trim value as 16, then c trim = 3.2 pf). 3: for 16 mhz crystal, in which c l = 9 pf, we can get c l1 = c l2 = 9.1 pf). 4: for c l selection, refer to the data sheet of the crystal.
IS2063 ds60001432a-page 18 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 19 IS2063 5.0 power management unit the IS2063 soc has an integrated power manage- ment unit (pmu). the main features of the pmu are a lithium-ion and lithium-polymer battery charger and a voltage regulator. a power switch is used to switch over the power source between the battery and an adapter. also, the pmu provides current for driving three leds. 5.1 charging a battery the IS2063 soc has a built-in battery charger which is optimized for lithium-ion and lithium-polymer batteries. the battery charger includes a current sensor for charging control, user programmable current regulator and high accuracy voltage regulator. the charging current parameters are configured using the ui tool. whenever the adapter is plugged-in, the charging circuit becomes activated. reviving, pre-charging, constant current and constant voltage modes and re-charging functions are included. the maximum charging current is 350 ma. figure 5-1 illus- trates the charging curve of a battery. figure 5-1: charging curve 5.2 voltage monitoring the 10-bit successive approximation register adc (sar adc) provides a dedicated channel for battery voltage level detection. the warning level can be programmed using the ui tool. the adc provides a granular resolution to enable the mcu to take control over the charging process. 5.3 ldo the built-in low-dropout regulator (ldo) is used to convert the battery or adapter power for power supply. it also integrates hardware architecture to control the power on/off procedure. the built-in programmable ldos provide power for codec and digital i/o pads. also, it is used to buffer the high input voltage from bat- tery or adapter. this ldo requires 1 f bypass capac- itor. 5.4 switching regulator the built-in programmable output voltage regulator can convert the battery voltage to rf and baseband core power supply. this converter has a high conversion efficiency and a fast transient response. 5.5 led driver the IS2063 soc has three led drivers to control the leds. the led drivers provide enough sink current (16-step control and 0.35 ma for each step) and the led can be connected to the IS2063 soc. the led settings can be configured using the ui tool. figure 5-2 illustrates the led drivers in the IS2063 soc.
IS2063 ds60001432a-page 20 advance information ? 2016 microchip technology inc. figure 5-2: led driver 5.6 under voltage protection when the voltage of the sys_pwr pin drops below the voltage level of 2.9v, the system will shut-down auto- matically.
? 2016 microchip technology inc. advance information ds60001432a-page 21 IS2063 6.0 application information 6.1 power supply figure 6-1 illustrates the pcb connection from the bat_in pin to other voltage supply pins of the IS2063 soc. the IS2063 soc is powered through the bat_in input pin. if battery is not connected, an external power supply must be provided as an input to the adap_in pin. figure 6-1: power tree diagram note: when an external power supply is connected to the adap_in pin, the bat_in pin can be left open if battery is not connected.
IS2063 ds60001432a-page 22 advance information ? 2016 microchip technology inc. 6.2 host mcu interface figure 6-2 illustrates the uart interface between the IS2063 soc and an external mcu. figure 6-2: host mcu interface over uart the mcu can control the IS2063 soc over the uart interface and wake-up the IS2063 soc using the mfb pins. the p3_7 pin can be used to wake-up the host mcu. refer to the " uart_commandset " document for a list of functions the IS2063 soc supports and how to use the ui tool to set up the system using the uart command. note: the ?uart_commandset? document is available for download from microchip web site at: www.microchip.com/IS2063 .
? 2016 microchip technology inc. advance information ds60001432a-page 23 IS2063 figure 6-3 through figure 6-7 illustrate the timing sequences of various uart control signals. figure 6-3: power on/off sequence
IS2063 ds60001432a-page 24 advance information ? 2016 microchip technology inc. figure 6-4: rx timing se quence (power-on state) figure 6-5: timing sequence (power-off state) note 1: eeprom clock = 100 khz. 2: for a byte write, 0.01 ms x 32 clock x 2 = 640 s. 3: it is recommended to have a ramp-down time more than 640 s during the power-off sequence to ensure a safe operation of the device.
? 2016 microchip technology inc. advance information ds60001432a-page 25 IS2063 figure 6-6: timing sequence of power-on (nack) figure 6-7: reset timing sequence in no response from soc to host mcu note: when the host mcu sends a uart command and the IS2063 soc does not respond, the mcu resends the uart command. if the soc does not respond within 5 secs, the mcu will force the system to reset.
IS2063 ds60001432a-page 26 advance information ? 2016 microchip technology inc. 6.3 configuration and programming configuration and firmware programming modes are entered according to the system configuration i/o pins. table 6-1 provides the system configuration settings. the p2_0, p2_4 and ean pins have internal pull up. 6.4 general purpose i/o pins the IS2063 soc provides 10 gpios and these gpios can be configured using the ui tool. ta b l e 6 - 2 and table 6-3 provide the gpio configuration details of the IS2063 soc. the mfb pin must be configured as the power on/off key and the remaining pins can be config- ured for any one of the default functions as provided in table 6-2 and tab l e 6 - 3 . some pins can be configured to indicate or control the external devices. the most popular applications are nfc for easy pairing and buzzer for indication and external audio amplifier for loud speaker. table 6-1: system configuration settings p2_0 p2_4 ean operating mode high high flash code: low; rom code: high app mode (normal operation) low high flash code: low; rom code: high test mode (write eeprom) low low high write flash table 6-2: IS2063 i/o pin configuration i/o pin name default functions mfb power on/off p0_2 play/pause p2_7 volume up p0_5 volume down p3_3 fwd p3_1 rev table 6-3: IS2063 i/o pin (for additional functions) i/o configurable features functions p0_0/p1_5 slide switch p0_4 nfc detect p0_0/p0_4 external amp enable
? 2016 microchip technology inc. advance information ds60001432a-page 27 IS2063 6.5 i 2 s mode application the IS2063 soc provides an i 2 s digital audio output interface to connect with the external codec or dsp. it provides 8, 16, 44.1, 48, 88.2 and 96 khz sampling rates for 16-bit and 24-bit data formats. the i 2 s setting can be configured using the ui and dsp tools. the external codec or dsp interfaces with these pins: sclk0, rfs0, dr0 and dt0 (pin nos. 3, 2, 1, and 4 respectively). figure 6-8 and figure 6-9 illustrate the i 2 s connection between the IS2063 soc and an exter- nal dsp. use the dsp tool to configure the IS2063 soc as a master/slave. for additional information on timing specifications, refer to 8.1 ?timing specifications? . figure 6-8: IS2063 in i 2 s master mode figure 6-9: IS2063 in i 2 s slave mode note: the dsp and ui tools are available for download from the microchip web site at: www.microchip.com/IS2063.
IS2063 ds60001432a-page 28 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 29 IS2063 7.0 antenna placement rule for bluetooth-enabled products, the antenna place- ment affects the overall performance of the system. the antenna requires free space to radiate rf signals and it should not be surrounded by the ground plane. figure 7-1 illustrates a typical example of good and poor antenna placement on the main application board with the ground plane. figure 7-1: antenna placement examples figure 7-2 illustrates the recommended keep-out area for the pcb antenna. figure 7-2: keep out area recommended for pcb antenna for additional information on the antenna placement, refer to the specific antenna data sheet of the antenna manufacturer.
IS2063 ds60001432a-page 30 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 31 IS2063 8.0 electrical characteristics this section provides an overview of the IS2063 stereo audio soc electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the IS2063 device are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings ambient temperature under bias................................................................................................. .............. -20c to +70c storage temperature ............................................................................................................ .................. -65c to +150c digital core supply voltage vdd_core .......................................................................................... .......... 0v to +1.35v rf supply voltage vcc_rf ............... ........................................................................................ ..................0v to +1.35v sar adc supply voltage sar_vdd ................................................................................................. ............ 0v to +2.1v codec supply voltage vdda/vddao ................................................................................................ ............ 0v to +3.3v buck supply voltage bk_vdd..................................................................................................... ................... 0v to +4.3v supply voltage ldo31_vin ....................................................................................................... .................... 0v to +4.3v battery input voltage bat_in ................................................................................................... ...................... 0v to +4.3v adapter input voltage adap_in.................................................................................................. ...................... 0v to +7v note: stresses listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. the functional operation of the device at those or any other conditions and those indi- cated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
IS2063 ds60001432a-page 32 advance information ? 2016 microchip technology inc. table 8-1 through ta bl e 8 - 9 provide the recommended operating conditions and the electrical specifications of the IS2063 soc. note: the pmu output powers, bk_o, codec_vo, rfldo_o and cldo_o, can be programmed through the eeprom parameters. note 1: test condition: temperature +25 oc and wired inductor 10 h. 2: these parameters are characterized but not tested in manufacturing. table 8-1: recommended operating condition symbol parameter min. typical max. unit vdd_core digital core supply voltage 1.14 1.2 1.26 v vcc_rf rf supply voltage 1.22 1.28 1.34 v sar_vdd sar adc supply voltage 1.62 1.8 1.98 v vdda/vddao codec supply voltage 1.8 2.8 3.0 v vdd_io i/o supply voltage 3.0 3.3 3.6 v bk_vdd buck supply voltage 3 3.8 4.25 v ldo31_vin supply voltage 3 3.8 4.25 v bat_in input voltage for battery 3.2 3.8 4.25 v adap_in input voltage for adapter 4.5 5 5.5 v t operation operation temperature -20 +25 +70 oc table 8-2: buck regulato r ( 2 ) parameter min. typical max. unit input voltage 3.0 3.8 4.25 v output voltage (i load = 70 ma, v in = 4v) 1.7 1.8 2.05 v output voltage accuracy ? 5 ? % output voltage adjustable step ? 50 ? mv/step output adjustment range -0.1 ? +0.25 v average load current (i load ) 120 ? ? ma conversion efficiency (bat = 3.8v, i load = 50 ma) ? 88 ( 1 ) ?% quiescent current (pfm) ? ? 40 a output current (peak) 200 ? ? ma shutdown current ? ? <1 a
? 2016 microchip technology inc. advance information ds60001432a-page 33 IS2063 note 1: test condition: temperature +25 oc. 2: these parameters are characterized but not tested in manufacturing. note 1: headroom = v adap_in - v bat . 2: when v adap_in - v bat > 2v, the maximum fast charge current is 175 ma for thermal protection. 3: these parameters are characterized but not tested in manufacturing. note 1: test condition: bk_o = 1.8v, temperature +25 oc. 2: these parameters are characterized but not tested in manufacturing. table 8-3: low drop regulator ( 1,2 ) parameter min. typical max. unit input voltage 3.0 3.8 4.25 v output voltage codec_vo ? 2.8 ? v ldo31_vo ? 3.3 ? output accuracy (v in = 3.7v, i load = 100 ma, +27 oc) ? 5 ? % output current (average) ? ? 100 ma drop-out voltage (i load = maximum output current) ??300mv quiescent current (excluding load, i load < 1 ma) ?45 ? a shutdown current ? ? <1 a table 8-4: battery charger ( 1,3 ) parameter min. typical max. unit input voltage (adap_in) 4.5 5.0 5.5 v supply current to charger only ? 3 4.5 ma maximum battery fast charge current headroom > 0.7v (adap_in = 5v) ?350 ?ma headroom = 0.3v~0.7v (adap_in = 4.5v) (note 2) ?175 ?ma trickle charge voltage threshold ?3 ?v battery charge termination current, (% of fast charge current) ?10 ? % table 8-5: led driver ( 1,2 ) parameter min. typical max. unit open-drain voltage ? ? 3.6 v programmable current range 0 ? 5.25 ma intensity control ? 16 ? step current step ? 0.35 ? ma power down open-drain current ? ? 1 a shutdown current ? ? 1 a
IS2063 ds60001432a-page 34 advance information ? 2016 microchip technology inc. note 1: f in =1 khz, b/w=20~20 khz, a-weighted, thd+n < 0.01%, 0dbfs signal, load = 100 kohm. 2: f in = 1 khz, b/w = 20~20 khz, a-weighted, -1dbfs signal, load = 16 ohm. 3: f in = 1 khz, b/w = 20~20 khz, a-weighted, thd+n < 0.05%, 0dbfs signal, load = 16 ohm. 4: these parameters are characterized but not tested in manufacturing. table 8-6: audio codec digital to analog converter ( 4 ) t = +25 o c, vdd = 2.8v, 1 khz sine wave input, bandwidth = 20 hz~20 khz parameter (condition) min. typical max. unit output sampling rate ? 128 ? f s resolution 16 ? 20 bit output sample rate 8 ? 48 khz signal to noise ratio (note 1) (snr @capless mode) for 48 khz ?96? db signal to noise ratio (note 1) (snr @single-ended mode) for 48 khz ?98? db digital gain -54 ? 4.85 db digital gain resolution ? 2~6 ? db analog gain -28 ? 3 db analog gain resolution ? 1 ? db output voltage full-scale swing (avdd = 2.8v) 495 742.5 ? mv/rms maximum output power (16 ohm load) ? 34.5 ? mw maximum output power (32 ohm load) ? 17.2 ? mw allowed load resistive ? 16 o.c. ohm capacitive ? ? 500 pf thd+n (16 ohm load) (note 2) ?0.05? % signal to noise ratio (snr @ 16 ohm load) (note 3) ??98?db
? 2016 microchip technology inc. advance information ds60001432a-page 35 IS2063 note 1: f in =1 khz, b/w=20~20 khz, a-weighted, thd+n < 1%, 150 mv pp input. 2: these parameters are characterized but not tested in manufacturing. note 1: the rf tx power is modulation value. 2: the rf transmit power is calibrated during production using mp tool and mt8852 bluetooth test equip- ment. 3: test condition: vcc_rf = 1.28v, temperature +25 oc. note 1: test condition: vcc_rf = 1.28v, temperature +25 oc. 2: these parameters are characterized but not tested in manufacturing. table 8-7: audio codec analog to digital converter ( 2 ) t = +25 o c, vdd = 2.8v, 1 khz sine wave input, bandwidth = 20 hz~20 khz parameter (condition) min. typical max. unit resolution ? ? 16 bit output sample rate 8 ? 48 khz signal to noise ratio (note 1) (snr @mic or line-in mode) ?92?db digital gain -54 ? 4.85 db digital gain resolution ? 2~6 ? db mic boost gain ? 20 ? db analog gain ? ? 60 db analog gain resolution ? 2.0 ? db input full-scale at maximum gain (differential) ? 4 ? mv/rms input full-scale at minimum gain (differential) ? 800 ? mv/rms 3 db bandwidth ? 20 ? khz microphone mode (input impedance) ? 24 ? kohm thd+n (microphone input) at 30mvrms input ? 0.02 ? % table 8-8: transmitter se ction for bdr and edr ( 1,2 ) parameter min. typical max. bluetooth specification unit maximum rf transmit power ?2 ( 3 ) ?-6 to 4dbm edr/bdr relative transmit power -4 -1.8 1 -4 to 1 db table 8-9: receiver se ction for bdr and edr ( 1,2 ) modulation min. typical max. bluetooth specification unit sensitivity at 0.1% ber gfsk ? -89 ? -70 dbm sensitivity at 0.01% ber /4 dqpsk ? -90 ? -70 dbm 8 dpsk ? -83 ? -70 dbm
IS2063 ds60001432a-page 36 advance information ? 2016 microchip technology inc. 8.1 timing specifications figure 8-1 and figure 8-2 illustrate the timing diagram of the IS2063 soc in i 2 s and pcm modes. figure 8-1: timing diagram for i 2 s modes (master/slave) figure 8-2: timing diagram for pcm modes (master/slave) note 1: f s : 8,16, 32, 44.1, 48, 88.2 and 96 khz. 2: sclk0: 64*f s /256*f s . 3: word length: 16-bit and 24-bit.
? 2016 microchip technology inc. advance information ds60001432a-page 37 IS2063 figure 8-3 illustrates the audio interface timing diagram and tab l e 8 - 10 provides the audio interface timing specifications. figure 8-3: audio interface timing note: test conditions: slave mode, f s = 48 khz, 24-bit data and sclk0 period = 256 f s . table 8-10: audio interface timing specifications parameter symbol min. typ max. unit sclk0 duty ratio d sclk ? 50 ? % sclk0 cycle time t sclkcy 50 ?? ns sclk0 pulse width high t sclkch 20 ?? ns sclk0 pulse width low t sclkcl 20 ?? ns rfs0 set-up time to sclk0 rising edge t rfssu 10 ?? ns rfs0 hold time from sclk0 rising edge t rfsh 10 ?? ns dr0 hold time from sclk0 rising edge t dh 10 ?? ns
IS2063 ds60001432a-page 38 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 39 IS2063 9.0 package information 9.1 package marking information figure 9-1 illustrates the package marking information of the IS2063 soc. figure 9-1: package marking information
IS2063 ds60001432a-page 40 advance information ? 2016 microchip technology inc. 9.2 package details figure 9-2 and figure 9-3 illustrate the package details of the IS2063 soc. figure 9-2: IS2063 - niau package details
? 2016 microchip technology inc. advance information ds60001432a-page 41 IS2063 figure 9-3: IS2063 - sac305 package details
IS2063 ds60001432a-page 42 advance information ? 2016 microchip technology inc. 9.3 footprint dimensions figure 9-4 illustrates the footprint dimensions of the IS2063 soc. figure 9-4: IS2063 footprint dimensions
? 2016 microchip technology inc. advance information ds60001432a-page 43 IS2063 10.0 reflow profile and storage condition figure 10-1 and figure 10-2 illustrate the reflow pro- files and stencil information of the IS2063 soc. 10.1 stencil of smt assembly suggestion 10.1.1 stencil type and thickness ? laser cutting ? stainless steel ? thickness : 0.5 mm pitch, thickness more than 0.15 mm 10.1.2 aperture size and shape for terminal pad ? aspect ratio (width/thickness) is more than 1.5 ? aperture shape - the stencil aperture is designed to match the pad size on the pcb - oval-shape opening is used to get the opti- mum paste release - rounded corners to minimize the clogging - positive taper walls (5 tapering) with the bottom opening larger than the top opening 10.1.3 aperture design for thermal pad ? small multiple openings are used instead of one big opening, refer figure 10-1 ? 60 to 80% solder paste coverage ? rounded corners to minimize clogging ? positive taper walls (5 tapering) with the bottom opening larger than the top opening, see figure 10-2 figure 10-1: reflow profile aperture design figure 10-2: stencil type
IS2063 ds60001432a-page 44 advance information ? 2016 microchip technology inc. 10.2 reflow condition figure 10-3 illustrates the reflow profile and the follow- ing are its specific features: ? standard condition: ipc/jedec j-std-020 ? preheat: 150~200 ~60~180 seconds ? average ramp-up rate (+217 to peak): 1~2 /sec max ? temperature maintained above 217: 60~150 sec- onds ?time within +5 of actual peak temperature: 20 ~ 40 seconds ? peak temperature: 260 +5/-0 ? ramp-down rate (peak to +217 ): +3 /sec. max ?time +25 to peak temperature: 8 minutes max ? cycle interval: 5 minutes figure 10-3: reflow profile
? 2016 microchip technology inc. advance information ds60001432a-page 45 IS2063 10.3 storage condition users must follow these specific storage conditions for the IS2063 soc. ? calculated shelf life in the sealed bag: 24 months at <40 and <90% relative humidity (rh). ? once the bag is opened, devices that are sub- jected to reflow solder or other high temperature process must be mounted within 168 hours of fac- tory conditions, that is <30 /60% rh. figure 10-4 illustrates the IS2063 soc bag labeling details. figure 10-4: IS2063 so c storage conditions
IS2063 ds60001432a-page 46 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 47 IS2063 11.0 ordering information table 11-1 provides the ordering information of the IS2063 soc. note: the IS2063 soc can be purchased through a microchip representative. go to http://www.microchip.com/ for the ordering information. table 11-1: ordering information device bluetooth version package part number IS2063 bluetooth 4.2, bdr/edr/ble soc with integrated 1 microphone and stereo speaker output, and i 2 s digital interface 8 x 8 x 0.9 mm, 68-lga package IS2063gm
IS2063 ds60001432a-page 48 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 49 IS2063 appendix a: reference circuit figure a-1 through figure a-4 illustrate the IS2063 reference schematics for the stereo headset application. figure a-1: IS2063 reference circuit for stereo headset
IS2063 ds60001432a-page 50 advance information ? 2016 microchip technology inc. figure a-2: IS2063 reference circuit for stereo headset
? 2016 microchip technology inc. advance information ds60001432a-page 51 IS2063 figure a-3: IS2063 reference circuit for stereo headset
IS2063 ds60001432a-page 52 advance information ? 2016 microchip technology inc. figure a-4: IS2063 reference circuit for stereo headset note: all esd diodes in this schematics are reserved for the testing.
? 2016 microchip technology inc. advance information ds60001432a-page 53 IS2063 appendix b: revision history revision a (june 2016) this is the initial released version of this document.
IS2063 ds60001432a-page 54 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 55 IS2063 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
IS2063 ds60001432a-page 56 advance information ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. advance information ds60001432a-page 57 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of micr ochip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0706-5 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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