description the a6818 device combines a 32-bit cmos shift register, accompanying data latches and control circuitry, with bipolar sourcing outputs and pnp active pull-downs. designed primarily to drive vacuum-fluorescent displays, the 60 v and ?40 ma output ratings also allow this device to be used in many other peripheral power driver applications. the a6818 features an increased data-input rate (compared with the older ucn/ucq5818x) and a controlled output slew rate. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 3.3 or 5 v logic supply, typical serial data-input rates are up to 33 mhz. a cmos serial data output permits cascaded connections in applications requiring additional drive lines. similar devices are available as the a6810 (10-bit) and a6812 (20-bit). the a6818 output source drivers are npn darlingtons, capable of sourcing up to 40 ma. the controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions 26182.128f features and benefits ? controlled output slew rate ? 60 v minimum output break down ? pnp active pull-downs ? low-power cmos logic and latches ? high-speed data storage ? high data-input rate ? low output-saturation voltages ? improved replacements for sn75518n, sn75518nf, ucn5818x, and ucq5818x dabic-iv 32-bit serial input latched source driver continued on the next page? package: 44 pin plcc (suffix ep) functional block diagram not to scale a6818 mos bipolar out 1 out 2 ground dwg. fp-013-1 out 3 out n clock serial data in strobe blanking serial data out serial-parallel shift register latches v dd v bb logic supply load supply
dabic-iv 32-bit serial input latched source driver a6818 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com regulations. for inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a blanking input high. the pnp active pull-downs will sink at least 2.5 ma. three temperature ranges are available for optimum performance in commercial (suffix s-), industrial (e-), and extended industrial (k-) applications. the package style provided is the minimum-area surface-mount plcc (suffix -ep). copper lead frames, low logic- power dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. the lead (pb) free versions have 100% matte tin leadframe plating. description (continued) selection guide part number pb-free packing ambient temperature t a (c) A6818EEPTR-T yes 450 pieces/13-in. reel ?40 to 85 a6818keptr ? 450 pieces/13-in. reel ?40 to 125 a6818septr-t yes 450 pieces/13-in. reel ?20 to 85 absolute maximum ratings* characteristic symbol notes rating units logic supply voltage v dd 7.0 v driver supply voltage v bb 60 v input voltage range v in ?0.3 to v dd + 0.3 v continuous output current range i out ?40 to 15 ma operating ambient temperature t a range e ?40 to 85 oc range k ?40 to 125 oc range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 125 oc *caution: these cmos devices have input static protection (class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
dabic-iv 32-bit serial input latched source driver a6818 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja 1-layer pcb with copper limited to solder pads 54 oc/w *additional thermal information available on the allegro website. pin-out diagram typical output driver typical input circuit 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in o o o o c 2.0 1.5 1.0 25 3.0 suffix 'ep', r q ja = 54 o c/w
dabic-iv 32-bit serial input latched source driver a6818 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com truth table serial shift register contents serial latch contents output contents data clock data strobe input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n blanklng i 1 i 2 i 3 ... i n-1 i n h h r 1 r 2 ... r n-2 r n-1 r n-1 l l r 1 r 2 ... r n-2 r n-1 r n-1 x r 1 r 2 r 3 ... r n-1 r n r n x x x ... x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n h p 1 p 2 p 3 ... p n-1 p n l p 1 p 2 p 3 ... p n-1 p n x x x ... x x h l l l ... l l l = low logic level h = high logic level x = irrelevant p = present state r = previous state
dabic-iv 32-bit serial input latched source driver a6818 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c (a6818s-) or over operating temperature range (a6818e- and a6818k-), v bb = 60 v, unless otherwise noted limits @ v dd = 3.3 v limits @ v dd = 5 v characteristic symbol test conditions mln. typ. max. min. typ. max. units output leakage current i cex v out = 0 v ? <-0.1 -15 ? <-0.1 -15 a output voltage v out(1) i out = -25 ma 57.5 58.3 ? 57.5 58.3 ? v v out(0) i out = 1 ma ? 1.0 1.5 ? 1.0 1.5 v output pull-down current i out(0) v out = 5 v to v bb 2.5 5.0 ? 2.5 5.0 ? ma input voltage v in(1) 2.2 ? ? 3.3 ? ? v v in(0) ? ? 1.1 ? ? 1.7 v input current i in(1) v in = v dd ? <0.01 1.0 ? <0.01 1.0 a i in(0) v in = 0.8 v ? <-0.01 -1.0 ? <-0.01 -1.0 a input clamp voltage v ik i in = -200 a ? -0.8 -1.5 ? -0.8 -1.5 v serial data output voltage v out(1) i out = -200 a 2.8 3.05 ? 4.5 4.75 ? v v out(0) i out = 200 a ? 0.15 0.3 ? 0.15 0.3 v maximum clock frequency f c 10 33 ? 10 33 ? mhz logic supply current i dd(1) all outputs high ? 0.25 0.75 ? 0.3 1.0 ma i dd(0) all outputs low ? 0.25 0.75 ? 0.3 1.0 ma load supply current i bb(1) all outputs high, no load ? 4.5 9.0 ? 4.5 9.0 ma i bb(0) all outputs low ? 0.2 20 ? 0.2 20 a blanking -to- output delay t dis(bq) c l = 30 pf, 50% to 50% ? 0.7 2.0 ? 0.7 2.0 s t en(bq) c l = 30 pf, 50% to 50% ? 1.8 3.0 ? 1.8 3.0 s strobe -to- output delay t p(sth-ql) r l = 2.3 k ? , c l 30 pf ? 0.7 2.0 ? 0.7 2.0 s t p(sth-qh) r l = 2.3 k ? , c l 30 pf ? 1.8 3.0 ? 1.8 3.0 s output fall time t f r l = 2.3 k ? , c l 30 pf 2.4 ? 12 2.4 ? 12 s output rise time t r r l = 2.3 k ? , c l 30 pf 2.4 ? 12 2.4 ? 12 s output slew rate dv/dt r l = 2.3 k ? , c l 30 pf 4.0 ? 20 4.0 ? 20 v/ s clock -to- serial data out delay t p(ch-sqx) i out = 200 a ? 50 ? ? 50 ? ns negative current is de ned as coming out of (sourcing) the speci ed device terminal. typical data is is for design information only and is at t a = +25c.
dabic-iv 32-bit serial input latched source driver a6818 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is transferred to the shift register on the logic ?0? to logic ?1? transition of the clock in- put pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the strobe is high (serial-to-parallel conversion). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the blanking input be high during serial data entry. when the blanking input is high, the output source driv- ers are disabled (off); the pnp active pull-down sink drivers are on. the information stored in the latches is not affected by the blanking input. with the blanking input low, the outputs are controlled by the state of their respective latches. a. data active time before clock pulse (data set-up time), t su(d) ........................................... 25 ns b. data active time after clock pulse (data hold time), t h(d) ................................................ 25 ns c. clock pulse width, t w(ch) ................................................. 50 ns d. time between clock activation and strobe, t su(c) ......... 100 ns e. strobe pulse width, t w(sth) .............................................. 50 ns note ? timing is representative of a 10 mhz clock. signi cantly higher speeds are attainable.
dabic-iv 32-bit serial input latched source driver a6818 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?1998-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. package ep, 44-pin plcc 2144 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-018 ac) dimensions in inches, metric dimensions (mm) in brackets, for reference only c seating plane 0.51 4.57 max 16.59 0.08 16.59 0.08 7.75 0.36 7.75 0.36 7.75 0.36 7.75 0.36 c 0.10 44x 0.74 0.08 17.53 0.13 17.53 0.13 1.27 0.43 0.10
|
