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| ! " #$% & ' ( ) ) **+ % ," -. & /" 0 /*1/ " % " 2 " ! " 3 ) ) ** " ! , /4# 5 6 ) 6 /450 " ,, , ! /450 " " /450 " % " " 6 *7 879 mosfet driver with dead time control v in v sw pgnd prdy enable pwm v dd sgnd mosfet driver with dead time control v in v sw pgnd prdy enable pwm v dd sgnd pin # pin name pin function 1 v dd supply voltage for the internal circuitry. 2 enable when set to logic level high, internal circuitry of the device is enabled. when set to logic level low, the prdy pin is forced low, the control and sychronous switches are turned off, and the supply current is less than 10a. 3 pwm ttl-level input signal to mosfet drivers. 4 prdy power ready - this pin indicates the status of enable or v dd . this output will be driven low when enable is logic low or when v dd is less than 4.4v (typ.). when enable is logic high and v dd is greater than 4.4v (typ.), this output is driven high. this output has a 10ma source and 1ma sink capability. 5, 7 pgnd power ground - connection to the ground of bulk and filter capacitors. 6 v sw switching node - connection to the output inductor. 8 v in input voltage for the dc-dc converter. package description interface connection parts per bag parts per reel t & r orientation ip2003pbf lga 10 --- ip2003trpb f lga --- 1000 fig 12 !" # $%%&" ' downloaded from: http:/// * !"#$# # % $ !&"! ' # % % (( ! # ) * !+"! "(( )* +$,- .( / )* 0 absolute maximum ratings: parameter symbol min typ max units conditions v in to pgnd v in --1 6v v dd to pgnd v dd --6 . 0v pwm to pgnd pwm -0.3 - v dd +0.3 v not to exceed 6.0v enable to pgnd enable -0.3 - v dd +0.3 v not to exceed 6.0v output rms current i out --4 0a measured at v sw block temperature t blk -40 - 125 c capable of start up over full temperature range recommended operating conditions: parameter s y mbol min typ max units conditions supply voltage v dd 4.6 5.0 5.5 v input voltage v in 3.0 - 13.2 v output voltage v out 0.8 - 3.3 v output current i out --4 0a operating frequency fsw 300 - 1000 khz operating duty cycle d - - 85 % electrical specifications @ v dd = 5v (unless otherwise specified): parameter symbol min typ max units conditions block power loss p loss - 9.4 11.7 w v in =12v, v out =1.3v turn on delay t d(on) -6 3- i out =40a, f sw =1mhz turn off delay t d(off) -2 6- l = 0.3h v in quiescent current i q-vin --1 . 0m a enable = 0v, v in =12v v dd quiescent current i q-vdd -1 0- a enable = 0v, v dd =5v under-voltage lockout uvlo start threshold v start 4.2 4.4 4.5 v hysteresis v hvs-uvlo -1 5 0-m v enable enable input voltage high v ih 2.0 - - v input voltage low v il --0 . 8 power ready prdy logic level high v oh 4.5 4.6 - v v dd =4.6v, i load =10ma logic level low v ol -0 . 10 . 2 v dd ," 0 5 10 15 20 25 30 35 40 output current (a) 0 2 4 6 8 10 12 14 16 p o w e r l o s s ( w ) maximum typical v in = 12v v out = 1.3v f sw = 1mhz t blk = 125c l = 0.30h 0 10 20 30 40 50 60 70 80 90 100 110 120 130 pcb temperature (c) 0 4 8 12 16 20 24 28 32 36 40 o u t p u t c u r r e n t ( a ) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l = 0.30h tx downloaded from: http:/// 5 (; + , ! " < % / - , ! " < % / - , ; < % / - , ; < % / - , 5 3 4 5 6 7 8 9 10 11 12 13 input voltage (v) -1 0 1 2 3 4 5 6 7 s o a t e m p a d j u s t m e n t ( c ) 0.96 1.00 1.04 1.08 1.12 1.16 1.20 1.24 1.28 p o w e r l o s s ( n o r m a l i z e d ) v out = 1.3v i out = 40a f sw = 1mhz l = 0.3h t blk = 125c 200 300 400 500 600 700 800 900 1000 swiching frequency (khz) 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 p o w e r l o s s ( n o r m a l i z e d ) -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 s o a t e m p a d j u s t m e n t ( c ) v in = 12v v out = 1.3v i out = 40a l = 0.30h t blk = 125c 0.1 0.3 0.5 0.7 0.9 output inductance (h) 0.98 1.00 1.02 1.04 1.06 p o w e r l o s s ( n o r m a l i z e d ) -0.5 0.0 0.5 1.0 1.5 s o a t e m p a d j u s t m e n t ( c ) v in = 12v v out = 1.3v i out = 40a f sw = 1mhz t blk = 125c 250 500 750 1000 switching frequency (khz) 20 30 40 50 60 70 80 average i dd ( ma) does not include prdy current t blk = 25c 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 output voltage (v) 0.96 1.00 1.04 1.08 1.12 1.16 p o w e r l o s s ( n o r m a l i z e d ) -1.0 0.0 1.0 2.0 3.0 4.0 s o a t e m p a d j u s t m e n t ( c ) v in = 12v i out = 40a f sw = 1mhz l = 0.30h t blk = 125c downloaded from: http:/// 8 %-./$% #$ $ ( %( # 0 % (( ( 1 # #$2 ( 0 $( $% #( ! 3 #$ %2 ( 0 ( %($2( %% %% %$ # # 2 % $ %#! " ( $1 %)4 $1 ! " #(( % 1 #$ %-./ # ! " % 5 (( % # % #( ( % %-./# %671 !%$ % #% %% 5 (( %671 %-./# ! to calculate power loss for a given set of operating conditions, the following procedure should be followed: determine the maximum current for each ip2003pbf and obtain the maximum power loss from fig 1. use the curves in figs. 3, 4, 5 and 6 to obtain normalized power loss values that match the operating conditions in the application. the maximum power loss under the operating conditions is then the product of the power loss from fig. 1 and the normal- ized values. to calculate the soa for a given set of operating conditions, the following procedure should be followed: determine the maximum pcb temperature and case temperature at the maximum operating current of each ip2003pbf. obtain the soa temperature adjustments that match the operating conditions in the application from figs. 3, 4, 5 and 6. then, add the sum of the soa temperature adjustments to the tx axis intercept in fig 2. the example below explains how to calculate maximum power loss and soa. . $ 89/ 3 $ :( 8: . $ :( 8!: - 8+;<5 3 # 8!=< 8,> 8, !" 1 $ ( ? !" '( 5 $ ( $ ( !+& !9" '( 5 $ ( $ ( !9 !" '( 5 $ ( #0 !+9 ! " '( 5 $ ( # ( ! (#( 1 ) * # 8 ?1!+&1!91!+91! !+ ? 120 10 20 30 40 50 60 70 80 90 100 110 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 0 102030405060708090100110120 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3 v f sw = 1mhz l=0.3uh case temperature ( oc ) t x downloaded from: http:/// 9 t d(on) t d(off) pwm v sw 90% 10% 90% 10% / - ! = !" -./$ / @ $ ( 7!, !9" -./$ / @ $ ( !, !" -./$ / @ #0 7!, ! " -./$ / @ # ( !, 1 #$ $ @ 87!,a!,7!, a!, !&, / 8,b 8,c %(( 1$(% % %-./# @ #!&,! 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 0 1 02 03 04 05 06 07 08 09 01 0 01 1 01 2 0 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l=0.3uh t x 0 1 02 03 04 05 06 07 08 09 01 0 01 1 01 2 0 v sw p gnd prdy enable v dd a a dc v average input voltage (v in ) average input current (i in ) average output current (i out ) averaging circuit v average output voltage (v out ) dc v average vdd voltage (v dd ) a average vdd current (i dd ) ip2003 p in = v in average x i in average p dd = v dd average x i dd average p out = v out average x i out average p loss = (p in + p dd ) - p out v in pwm downloaded from: http:/// > the pcb layout and bypassing issues have been addressed with the internal design of the ip2003pbf. one of the most critical elements of proper pcb layout with ip2003pbf is the placement of the external input bypass capacitors and the routing of the connecting power tracks. the ipowir block will function normally without any additional external input bypass capacitors. however, the addition of the external capacitors will improve the long term reliable operation of the block. ' !1 ( it is recommended that the designer uses the following guidelines: 1. the diagram below suggests the addition of the input bypass capacitors either on the top side of the pcb (capacitors c1-c4) or top and bottom side (c5, c6), if placement on the bottom side is feasible. although there is a certain degree of bypassing inside the ip2003pbf, these external capacitors must be placed as close to the ipowir device as possible. 2. in the diagram below, observe the routing of the power tracks that connect the external bypass capacitors. 3. provide a mid-layer solid ground plane with connections to the top through vias. 4. refer to ir application note an-1029 to determine the size of the vias and the copper weight and thickness when designing the pcb. downloaded from: http:/// ? 2%3 223 0408 ip2003 4.8 [0.19] 2.0 [0.08] 0.15 [.006] c 2. dime ns ions are s hown in mill ime t e rs [inche s ]. 3. cont rol ling dimens ion: mil lime t e r 1. dimens ioning & t olerancing per as me y14.5m-1994. not es : b a 0.15 [.006] c 2x 2x top view bottom view package body. 5 primary datum c is seating plane. 6 bilat eral t olerance zone is applied t o each s ide of t h e 6 6 orientation cor ne r i d 11.00 [.433] 11.00 [.433] 2.31 [.0909] 2.13 [.0839] 4. land des ignat ion per jes d mo 222, s pp-010. (6) (8) y x (7) xy y (5) yx x (2),(3) l2 xy l1 f2 f1 2.032 5.588 5.588 3.048 2.921 5.334 5.715 1.778 1.1430 1.1016 0.345 0.3556 1.348 bs c 1.4732 bs c d1 e1 e2 (1) 2.1016 1.1430 (4) 1.1430 1.2827 xy y x l1 l2 l3 l3 0.332 d2 f2 f1 v d1d2 3.023 bs c 5.945 bs c e1e2 7.1167 bs c 7.289 bs c pgnd v pgnd layout notes: 1. land pat t ern on us ers pcb s hould be an ident ical mirror v enable pwm prdy image of the pattern shown in the bottom view. 2. lands should be solder mask defined. c 5 side view ee1 e2 2.4384 3.8610 2.0193 sw in dd downloaded from: http:/// @ "#$%#& '() *+)#,(#- *11 a '6 & ' 6 @*86 b' c ( 1 + *8*3> 8 )c (1 + *8*3>@1 ; *79 )./) 0 %$"# 1 2 ,34(5 4 ) / - ' , , 3 , ' /450 )./ 6 3 7 33 -7% ) = ) ) ' , )./ # 4411 8" 1# 6 1 7 " # 7 9 6)1&6) % " /50 2. -. 6 " / 2 " 6 6 , 6 6 6 6 "# : #7 1 7 fig. 12: tape & reel information 1. out line conforms t o eia-481 & eia-541. ip2003a, lga not es : 12mm feed direction 24mm 0508 ip2003a 6b7d ip2003a 6b7d 0508 ))2>*d/ downloaded from: http:/// |
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