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integrated circuit systems, inc. ics9250-28 third party brands and names are the property of their respective owners. block diagram 9250-28 rev b 10/26/00 recommended application: 810/810e and 815 type chipset. output features: ? 2 cpu (2.5v) (up to 133mhz achievable through i 2 c) 13 sdram (3.3v) (up to 133mhz achievable through i 2 c) 2 pci (3.3 v) @33.3mhz 1 ioapic (2.5v) @ 33.3 mhz 3 hublink clocks (3.3 v) @ 66.6 mhz 2 (3.3v) @ 48 mhz (non spread spectrum) 1 ref (3.3v) @ 14.318 mhz features: supports spread spectrum modulation, 0 to -0.5% down spread. i 2 c support for power management efficient power management scheme through pd# uses external 14.138 mhz crystal alternate frequency selections available through i 2 c control. functionality pin configuration 56-pin 300mil ssop * this input has a 50k pull-down to gnd. ioapic vddl gnd *fs1/ref0 vddref x1 x2 gnd vdd3v66 3v66_0 3v66_1 3v66_2 gnd vddpci pciclk0 pciclk1 gnd fs0 gnd vdda pd# sclk s data gnd vdd48 48mhz_0 48mhz_1 fs2 vddl gnd cpuclk0 cpuclk1 gnd sdram0 sdram1 vddsdr gnd sdram2 sdram3 sdram4 vddsdr gnd sdram5 sdram6 vddsdr gnd sdram7 sdram8 sdram9 vddsdr gnd sdram10 sdram11 vddsdr gnd sdram12 ics9250-28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 frequency generator & integrated buffers for celeron & p ii / iii ? 2 s f0 s f1 s fn o i t c n u f 00x e t a t s i r t 01xt s e t 100 z h m 6 6 = u p c e v i t c a z h m 0 0 1 = m a r d s 110 z h m 0 0 1 = u p c e v i t c a z h m 0 0 1 = m a r d s 10 1 z h m 3 3 1 = u p c e v i t c a z h m 3 3 1 = m a r d s 111 z h m 3 3 1 = u p c e v i t c a z h m 0 0 1 = m a r d s ref0 cpu66/100/133 [1:0] 3v66 (2:0) sdram (12:0) pciclk (1:0) ioapic pll2 48mhz (1:0) x1 x2 xtal osc control logic config reg fs(2:0) pd# 2 2 3 13 2 /2 /2 /3 /2 pll1 spread spectrum sdata sclk ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. power groups analog vddref = x1, x2 vdda = pll1 vdd48 = pll2 digital vdd3v66, vddpci vddsdr, vddl
ics9250-28 the ics9250-28 is part of a two chip clock solution for 810/810e and 815 type chipset. combined with the ics9112-17, the ics9250-28 provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces emi by 8db to 10 db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. general description pin configuration r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1c i p a o it u o. z h m 3 . 3 3 t a g n i n n u r t u p t u o k c o l c v 5 . 2 6 5 , 2l d d vr w pc i p a o i & u p c r o f y l p p u s r e w o p v 5 . 2 4 1 s fn iy t i l a n o i t c n u f t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . n i p t c e l e s n o i t c n u f 0 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 , 5 2 , 0 2 , 4 1 , 9 , 5 9 4 , 4 4 , 0 4 , 5 3 , 1 3 d d vr w py l p p u s r e w o p v 3 . 3 61 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 72 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 9 1 , 7 1 , 3 1 , 8 , 3 , 9 3 , 4 3 , 0 3 , 4 2 5 5 , 2 5 , 8 4 , 3 4 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 0 1 , 1 1 , 2 1) 0 : 2 ( 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 8 1 , 8 2) 0 , 2 ( s fn i . y t i l a n o i t c n u f t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . s n i p t c e l e s n o i t c n u f . 3 e g a p n o e l b a t y t i l a n o i t c n u f o t r e f e r e s a e l p 5 1 , 6 1] 0 : 1 [ k l c i c pt u os t u p t u o k c o l c i c p v 3 . 3 1 2# d pn i o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t . s m 3 n a h t r e t a e r g 2 2k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 3 2a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 7 2 , 6 20 _ z h m 8 4t u o. s t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 , 6 3 , 3 3 , 2 3 , 9 2 , 2 4 , 1 4 , 8 3 , 7 3 1 5 , 0 5 , 7 4 , 6 4 , 5 4 m a r d s ) 0 : 2 1 ( t u o f f o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t 2 c 3 5 , 4 5) 0 : 1 ( k l c u p ct u o g n i d n e p e d z h m 3 3 1 r o z h m 0 0 1 , z h m 6 6 . t u p t u o k c o l c s u b t s o h v 5 . 2 . s n i p ) 0 : 2 ( s f n o
ics9250-28 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz maximum allowed current clock enable configuration # d pk l c u p cm a r d sc i p a o iz h m 6 6k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o 5 1 8 n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 2 6 . 2 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p 0 = # n w d r w p ( a m 0 1a m 0 1 z h m 6 6 e v i t c a l l u f 0 1 0 = ] 0 : 2 [ s f a m 0 7a m 0 0 4 z h m 0 0 1 e v i t c a l l u f 1 1 0 = ] 0 : 2 [ s f a m 0 0 1a m 0 0 4 z h m 3 3 1 e v i t c a l l u f 1 1 1 = ] 0 : 2 [ s f a m 0 3 1a m 0 5 4
ics9250-28 byte 3: ics reserved functionality and frequency select register (default as noted in pwd) 2 s f0 s f1 s fu p cm a r d s6 6 v 3i c pz h m 8 4f e rc i p a o i 00x e t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r t 01x 2 / k l c t2 / k l c t3 / k l c t6 / k l c t2 / k l c tk l c t6 / k l c t 100 z h m 6 . 6 6z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 110 z h m 0 0 1z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 10 1 z h m 3 3 1z h m 3 3 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 111 z h m 3 3 1z h m 0 0 1z h m 6 . 6 6z h m 3 . 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 3 . 3 3 truth table note 1: for system operation, the bsel lines of the cpu will program fs0, fs2 for the appropriate cpu speed, always with sdram = 100mhz. after bios verifies the sdram is pc133 speed, then bit 0 can be written from the default 0 to 1 to change the sdram output frequency from 100mhz to 133mhz. this will only change if the cpu is at the 133mhz fsb speed as shown in this table. the cpu, 3v66, pci, and ioapic clocks will be glitch free during this transition, and only sdram will change. note 2: "ics reserved bits" must be writtern as "0". note3: undefined bits can be written either as "1 or 0" t i bn o i t p i t c s e dd w p 7 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 6 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 5 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 4 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 3 t i b) 2 e t o n ( t i b d e v r e s e r s c i 0 2 t i b) 3 e t o n ( t i b d e n i f e d n u x 1 t i b) 3 e t o n ( t i b d e n i f e d n u x 0 t i b 0 t i b0 s f1 s f k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m c i p a o i z h m 0 1 e t o n 000 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 010 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 001 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 011 2 3 . 3 3 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 100 6 6 . 6 60 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 110 0 . 0 0 10 . 0 0 16 6 . 6 63 3 . 3 33 3 . 3 3 10 1 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3 111 2 3 . 3 3 12 3 . 3 3 16 6 . 6 63 3 . 3 33 3 . 3 3
ics9250-28 byte 0: control register (1 = enable, 0 = disable) byte 1: control register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d i d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d i d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d i d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d i d e v r e s e r1) e v i t c a n i / e v i t c a ( 3 t i b- m u r t c e p s d a e r p s ) f f o = 0 / n o = 1 ( 1) e v i t c a n i / e v i t c a ( 2 t i b7 21 z h m 8 41) e v i t c a n i / e v i t c a ( 1 t i b6 20 z h m 8 41) e v i t c a n i / e v i t c a ( 0 t i b- d i d e v r e s e r0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b8 37 m a r d s1) e v i t c a n i / e v i t c a ( 6 t i b1 46 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b2 45 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b5 44 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b6 43 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b7 42 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b0 51 m a r d s1) e v i t c a n i / e v i t c a ( 0 t i b1 50 m a r d s1) e v i t c a n i / e v i t c a ( note: reserved id bits must be written as "0" byte 2: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default 3. undefined bit can be wirtten with either a "1" or "0". t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b2 1) p g a ( 2 - 6 6 v 31) e v i t c a n i / e v i t c a ( 6 t i b9 22 1 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b2 31 1 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b3 30 1 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b6 39 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b7 38 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b6 11 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a (
ics9250-28

byte 4: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default p u o r gz h m 6 6 u p c z h m 0 0 1 m a r d s z h m 0 0 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 3 3 1 m a r d s t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2 -s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3 -s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 i c p o t i c ps n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s p 0 0 5s n 0 . 1s n 0 . 0s p 0 0 5 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / nh c n y s aa / n
ics9250-28 absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ? 0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0 c to +70 c maximum case operating temperature . . . . . . +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ? 65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v i h 2v dd +0.3 v input low voltage v i l v ss -0.3 0.8 v input high current i i h v i n = v dd -5 5 a i i l1 v i n = 0 v; inputs with no pull-up resistors -5 i il2 v in = 0 v; inputs with pull-up resistors -200 c l = 0 pf; @ 66/100 mhz 138 200 c l = 0 pf; @ 100/100 mhz 126 200 c l = 0 pf; @ 133/133 mhz 172 200 c l = 0 pf; @ 133/100 mhz 141 200 c l = max loads; @ 66/100 mhz 339 400 c l = max loads; @ 100/100 mhz 328 400 c l = max loads; @ 133/133 mhz 383 450 c l = max loads; @ 133/100 mhz 340 400 c l = 0 pf; @ 66/100 mhz 9 15 c l = 0 pf; @ 100/100 mhz 11 18 c l = 0 pf; @ 133/133 mhz 13 20 c l = 0 pf; @ 133/100 mhz 13 20 c l = max loads; @ 66/100 mhz 13 35 c l = max loads; @ 100/100 mhz 23 60 c l = max loads; @ 133/133 mhz 29 60 c l = max loads; @ 133/100 mhz 30 60 i dd3.3pd c l = max loads 251 400 i dd.25pd input address vdd or gnd <1 10 input frequency f i v dd = 3.3 v 12 14.318 16 mhz transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 ma ma i dd2.5op a powerdown current operating supply current input low current a ma ma i dd3.3op
ics9250-28 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 16 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 21 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f 2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 49 55 % skew window 1 t sk2b v t = 1.25 v 45 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 135 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh2b i ol2b electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 14 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 14.5 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -108 v oh @ max = 3.135 v -9 -33 v ol @ min = 1.95 v 30 95 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.2 1.6 ns fall time 1 t f 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.2 1.6 ns duty cycle 1 d t1 v t = 1.5 v 45 49 55 % skew window 1 t sk1 v t = 1.5 v 135 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 175 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1
ics9250-28 electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 16 30 ? output impedance r dsn4b 1 v o = v dd *(0.5) 9 20 30 ? output high voltage v oh4b i oh = -1 ma 2 v output low voltage v ol4b i ol = 1 ma 0.4 v v oh @ min = 1.0 v -27 -68 v oh @ max = 2.375 v -9 -27 v ol @ min = 1.2 v 27 54 v ol @ max = 0.3 v 11 30 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f 4b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 49 55 % jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 180 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 12 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v v oh @ min = 2.0 v -54 -92 v oh @ max = 3.135 v -16 -46 v ol @ min = 1.0 v 54 68 v ol @ max = 0.4 v 29 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1 1.6 ns fall time 1 t f 3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 52 55 % skew window 1 t sk3 v t = 1.5 v 120 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc3 v t = 1.5 v 135 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh3 i ol3

ics9250-28 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 15 55 ? output impedance r dsn1b 1 v o = v dd *(0.5) 12 15 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 -106 v oh @ max = 3.135 v -14 -33 v ol @ min = 1.95 v 30 94 v ol @ max = 0.4 v 29 38 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 2 ns fall time 1 t f 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.4 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew window 1 t sk1 v t = 1.5 v 20 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 175 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ref, 48mhz_0 (pin 26) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp5b 1 v o = v dd *(0.5) 20 29 60 ? output impedance r dsn5b 1 v o = v dd *(0.5) 20 27 60 ? output high voltage v oh15 i oh = -1 ma 2.4 v output low voltage v ol5 i ol = 1 ma 0.55 v v oh @ min = 1.0 v -29 -54 v oh @ max = 3.135 v -11 -23 v ol @ min = 1.95 v 29 54 v ol @ max = 0.4 v 16 27 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.3 4 ns fall time 1 t f 5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, fixed clocks 160 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 420 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma
ics9250-28 electrical characteristics - 48mhz_1 (pin 27) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-15 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v dd *(0.5) 10 15 24 ? output impedance r dsn3b 1 v o = v dd *(0.5) 10 15 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.55 v v oh @ min = 2.0 v -54 -82 v oh @ max = 3.135 v -20 -46 v ol @ min = 1.0 v 54 95 v ol @ max = 0.4 v 28 53 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.4 1.1 1.6 ns fall time 1 t f 3 v oh = 2.4 v, v ol = 0.4 v 0.4 1.3 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 53 55 % jitter, cycle-to-cycle 1 t jcyc-cyc3b v t = 1.5 v 145 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh3 ma output low current i ol3 ma
ics9250-28 group skews (cpu 66 mhz, sdram 100mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf r efer to group offset waveforms diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk1 cpu-sdram -3 -2.7 -2 ns skew window 1 t w 1 cpu-sdram 0 165 500 ps cpu to 3v66 skew 1 t sk1 cpu-3v66 77.68ns skew window 1 t w 1 cpu-3v66 0 105 500 ps sdram to 3v66 skew 1 t sk1 sdram-3v66 -500 180 500 ps skew window 1 t w 1 sdram-3v66 0 210 500 ps 3v66 to pci skew 1 t sk1 3v66-pci 1.5 2.1 3.5 ns skew window 1 t w 1 3v66-pci 0 90 500 ps i oapic to pci skew 1 t sk1 ioapic-pci -1 -0.1 1 ns skew window 1 t w1 ioapic-pci 001ns 1 guaranteed by design, not 100% tested in production. group skews (cpu 100 mhz, sdram 100mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf r efer to group offset waveforms diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk2 cpu-sdram 4.5 4.9 5.5 ns skew window 1 t w 2 cpu-sdram 0 180 500 ps cpu to 3v66 skew 1 t sk2 cpu-3v66 4.5 5 5.5 ns skew window 1 t w 2 cpu-3v66 0 100 500 ps sdram to 3v66 skew 1 t sk2 sdram-3v66 -500 175 500 ps skew window 1 t w 2 sdram-3v66 0 200 500 ps 3v66 to pci skew 1 t sk2 3v66-pci 1.5 2.1 3.5 ns skew window 1 t w 2 3v66-pci 0 90 500 ps i oapic to pci skew 1 t sk2 ioapic-pci -1 -0.1 1 ns skew window 1 t w2 ioapic-pci 001ns 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, sdram @ 1.5 v cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v
ics9250-28 group skews (cpu 133 mhz, sdram 133mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf r efer to group offset waveforms diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk3 cpu-sdram 3.25 3.45 4.25 ns skew window 1 t w 3 cpu-sdram 0 155 500 ps cpu to 3v66 skew 1 t sk3 cpu-3v66 -500 120 500 ps skew window 1 t w 3 cpu-3v66 0 120 500 ps sdram to 3v66 skew 1 t sk3 sdram-3v66 -3.25 -3.08 -4.25 ps skew window 1 t w 3 sdram-3v66 0 175 500 ps 3v66 to pci skew 1 t sk3 3v66-pci 1.5 2.2 3.5 ns skew window 1 t w 3 3v66-pci 0 80 500 ps i oapic to pci skew 1 t sk3 ioapic-pci -1 -0.1 1 ns skew window 1 t w3 ioapic-pci 001ns 1 guaranteed by design, not 100% tested in production. group skews (cpu133 mhz, sdram 100mhz) t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% cpu & ioapic load (lumped) = 20 pf; pci, sdram, 3v66 load (lumped) = 30 pf r efer to group offset waveforms diagram for definition of transition edges. parameter symbol conditions min typ max units cpu to sdram skew 1 t sk3 cpu-sdram cpu @ 1.25 v, sdram @ 1.5 v -500 -15 500 ps skew window 1 t w 3 cpu-sdram 0 165 500 ps cpu to 3v66 skew 1 t sk3 cpu-3v66 cpu @ 1.25 v, 3v66 @ 1.5 v -500 165 500 ps skew window 1 t w 3 cpu-3v66 0 105 500 ps sdram to 3v66 skew 1 t sk3 sdram-3v66 sdram, 3v66 @ 1.5 v -500 185 500 ps skew window 1 t w 3 sdram-3v66 0 185 500 ps 3v66 to pci skew 1 t sk3 3v66-pci 3v66, pci @ 1.5 v 1.5 2.2 3.5 ns skew window 1 t w 3 3v66-pci 0 60 500 ps i oapic to pci skew 1 t sk3 ioapic-pci ioapic @ 1.25 v, pci @ 1.5 v -1 -0.1 1 ns skew window 1 t w3 ioapic-pci 001ns 1 guaranteed by design, not 100% tested in production. cpu @ 1.25 v, 3v66 @ 1.5 v sdram, 3v66 @ 1.5 v 3v66, pci @ 1.5 v ioapic @ 1.25 v, pci @ 1.5 v cpu @ 1.25 v, sdram @ 1.5 v
ics9250-28 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3v66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
ics9250-28 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write:

!

" how to read:

#

" controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to write:
ics9250-28 connections to vdd: general layout precautions: 1) use a ground plane on the top routing layer of the pcb in all areas not used by traces. 2) make all power traces and ground traces as wide as the via pad for lower inductance. notes: 1 all clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. not shown in all places to improve readability of diagram. 2 optional crystal load capacitors are recommended. they should be included in the layout but not inserted unless needed. component values: c1 : crystal load values determined by user c2 : 22f/20v/d case/tantalum avx tajd226m020r c3 : 15pf capacitor fb = fair-rite products 2512066017x1 all unmarked capacitors are 0.01f ceramic 3.3v power route ground 2.5v power route c1 c1 2 c3 1 clock load ferrite bead vdd c2 22f/20v tantalum 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 ferrite bead vdd c2 22f/20v tantalum 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
ics9250-28 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9250 y f-28-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min ma x min ma x a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min ma x min ma x 28 9.398 9.652 .370 .380 34 11.303 11.557 .445 .455 48 15.748 16.002 .620 .630 56 18.288 18.542 .720 .730 64 20.828 21.082 .820 .830 symbol see variations see variations in millimeters common dimensions in in c h es common dimensions see variations n d mm. d (inch) see variations

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