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integrated circuit systems, inc. general description features ics9250-10 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview block diagram pentium ii is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency timing generator for pentium ii systems 9250-10 rev j 6/15/99 pin configuration ? generates the following system clocks: - 3 cpu (2.5v) 66.6/100 mhz (up to 133mhz through i 2 c selection) - 9 sdram (3.3v) up to 133mhz - 8 pci (3.3 v) @33.3mhz - 2 ioapic (2.5v) @16.67 or 33.3mhz - 2 hublink clocks (3.3 v) @ 66.6 mhz - 2 usb (3.3v) @ 48 mhz ( non spread spectrum) - 1 ref (3.3v) @ 14.318 mhz ? supports spread spectrum modulation , down spread 0 to -0.5% ?i 2 c support for power management ? efficient power management scheme through pd# ? uses external 14.138 mhz crystal 56-pin 300 mil ssop the ics9250-10 is a single chip clock for intel pentium ii. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces emi by 8db to 10 db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-10 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. power groups vdd0, gnd0 = ref & crystal vdd1, gnd1 = 3v66 [1:0] vdd2, gnd2 = pciclk[7:0] vdd3, gnd3 = pll core vdd4, gnd4 = 48mhz [1:0] vdd5, gnd5 = sdram_f, sdram [7:0] vddl0, gndl0 = cpuclk [2:0] vddl1, gndl1 = ioapic [1:0] *60k ohm pull-up to vdd on indicated inputs.
2 ics9250-10 preliminary product preview pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 c i p a _ q e r fn i . y c n e u q e r f c i p a o i e h t s e n i m r e t e d s i h t . n o r e w o p t a t u p n i d e h c t a l z h m 7 6 . 6 1 = q e r f c i p a o i , d e h c t a l s i " 0 " a n e h w z h m 3 . 3 3 = q e r f c i p a o i , d e h c t a l s i " 1 " n e h w . p u - l l u p l a n r e t n i k 0 6 a s a h n i p s i h t 0 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 31 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 42 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 3 2 , 7 1 , 4 1 , 6 , 5 7 4 , 1 4 , 5 3 , 4 2 ) 5 : 0 ( d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 7 , 8] 0 : 1 [ 6 6 v 3t u ob u h r o f s t u p t u o k c o l c z h m 6 6 d e x i f v 3 . 3 , 1 2 , 0 1 , 9 , 2 4 4 , 8 3 , 3 3 , 7 2 , 2 2 ) 5 : 0 ( d d vr w py l p p u s r e w o p v 3 . 3 , 6 1 , 8 1 , 9 1 , 0 2 1 1 , 2 1 , 3 1 , 5 1 ] 0 : 7 [ k l c i c pt u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 6 2 , 5 2) 1 : 0 ( z h m 8 4t u ob s u r o f s t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 9 2 , 8 2) 1 : 0 ( s fn i t u p t u o l l a , y c n e u q e r f u p c s e n i m r e t e d . s n i p t c e l e s n o i t c n u f . 3 e g a p n o e l b a t y t i l a n o i t c n u f o t r e f e r e s a e l p . y t i l a n o i t c n u f 0 3a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 1 3k l c sn ii f o t u p n i k c o l c 2 t u p n i c 2 3# d pn i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i n w o d r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v . s m 3 n a h t r e t a e r g e b t o n l l i w , 2 4 , 0 4 , 9 3 , 7 3 , 6 3 6 4 , 5 4 , 3 4 ] 0 : 7 [ m a r d st u o d e n r u t e b n a c s t u p t u o m a r d s l l a . z h m 0 0 1 g n i n n u r t u p t u o v 3 . 3 i h g u o r h t f f o 2 c 4 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s z h m 0 0 1 g n i n n u r e e r f v 3 . 3 2 c 8 4 , 6 5] 0 : 1 [ l d n gr w pc i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 2 5 , 0 5 , 9 4] 0 : 2 [ k l c u p ct u o s f n o g n i d n e p e d z h m 0 0 1 r o z h m 6 6 . t u p t u o k c o l c s u b t s o h v 5 . 2 . 3 e g a p r e f e r s n i p ) 1 : 0 ( 3 5 , 1 5) 1 : 0 ( l d d vr w pc i p a o i & u p c r o f y l p p y u s r e w o p v 5 . 2 5 5 , 4 5] 0 : 1 [ c i p a o it u o. z h m 3 . 3 3 r o z h m 7 6 . 6 1 t a g n i n n u r s t u p t u o k c o l c v 5 . 2
3 ics9250-10 preliminary product preview functionality table 1 s f0 s fu p cm a r d s6 6 v 3k l c i c pz h m 8 40 f e rc i p a o is e t o n 00 z - i hz - i hz - i hz - i hz - i hz - i hz - i he t a t s i r t 01 2 / k l c t4 / k l c t4 / k l c t8 / k l c t2 / k l c tk l c t6 1 / k l c te d o m t s e t 10 z h m 6 6z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 7 6 . 6 1 11 z h m 0 0 1z h m 0 0 1z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1z h m 7 6 . 6 1 select functions # d pk l c u p cm a r d sc i p a o iz h m 6 6k l c i c p , f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on o 1 s f0 s fs e t o n 00 e t a t s i r t 01 e d o m t s e t 10 z h m 6 6 = u p c e v i t c a 11 z h m 0 0 1 = u p c e v i t c a clock enable configuration
4 ics9250-10 preliminary product preview power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz e 0 1 8 n o i t i d n o c n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 2 6 . 2 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a n o i t p m u s n o c y l p p u s v 5 . 2 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = 2 q d d v d n g r o 3 q d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p 0 = # n w d r w p ( a m 0 1a m 0 1 z h m 6 6 e v i t c a l l u f 0 1 = 0 , 1 l e s a m 0 7a m 0 8 2 z h m 0 0 1 e v i t c a l l u f 1 1 = 0 , 1 l e s a m 0 0 1a m 0 8 2 maximum allowed current
5 ics9250-10 preliminary product preview 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ack byte 2 ac k byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
6 ics9250-10 preliminary product preview t i bn o i t p i t c s e dd w p 7 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 6 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 5 t i b ) l a m r o n e t a r e p o o t k c o l c 0 e b o t s d e e n ( t i b d e v r e s e r s c i0 t i b ) 0 , 3 , 4 ( ) 0 , 3 , 4 ( t i b k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m x x x x 1 e t o n 0 s f ) w h ( 3 l e s ) 4 t i b ( 2 l e s ) 3 t i b ( 1 l e s ) 0 t i b ( 0000 7 6 . 6 60 0 17 6 . 6 63 3 . 3 3 0001 7 6 . 0 76 0 17 6 . 0 73 3 . 5 3 0010 6 6 . 4 72 1 17 6 . 4 73 3 . 7 3 0011 6 6 . 2 84 2 16 6 . 2 83 3 . 1 4 0100 5 . 3 65 2 . 5 95 . 3 65 7 . 1 3 0101 7 6 . 8 63 0 17 6 . 8 63 3 . 4 3 0110 7 6 . 2 79 0 17 6 . 2 73 3 . 6 3 0111 6 6 . 8 83 3 16 6 . 8 83 3 . 4 4 1000 0 0 10 0 17 6 . 6 63 3 . 3 3 100 1 6 0 16 0 17 6 . 0 73 3 . 5 3 10 10 2 1 12 1 17 6 . 4 73 3 . 7 3 10 11 4 2 14 2 16 6 . 2 83 3 . 1 4 1100 5 2 . 5 95 2 . 5 95 . 3 65 7 . 1 3 1101 3 0 13 0 17 6 . 8 63 3 . 4 3 1110 9 0 19 0 17 6 . 2 73 3 . 6 3 1111 3 3 13 3 16 6 . 8 83 3 . 4 4 2 t i b) n o i t a r e p o k c o l c l a m r o n r o f 1 e b o t s d e e n ( d e s u t o n 1 1 t i b) n o i t a r e p o k c o l c l a m r o n r o f 1 e b o t s d e e n ( d e s u t o n 1 byte 5:ics reserved functionality and frequency select register (default=0) note1: default at power-up will be for latched logic inputs to define frequency, as diplayed by bit 3.
7 ics9250-10 preliminary product preview byte 0: control register (1 = enable, 0 = disable) byte 1: control register (1 = enable, 0 = disable) byte 2: control register (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i bd e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i bd e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i bd e v r e s e r1) e v i t c a n i / e v i t c a ( 3 t i b m u r t c e p s d a e r p s ) f f o = 0 / n o = 1 ( 1) e v i t c a n i / e v i t c a ( 2 t i b6 21 z h m 8 41) e v i t c a n i / e v i t c a ( 1 t i b5 20 z h m 8 41) e v i t c a n i / e v i t c a ( 0 t i b9 42 k l c u p c1) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b6 37 m a r d s1) e v i t c a n i / e v i t c a ( 6 t i b7 36 m a r d s1) e v i t c a n i / e v i t c a ( 5 t i b9 35 m a r d s1) e v i t c a n i / e v i t c a ( 4 t i b0 44 m a r d s1) e v i t c a n i / e v i t c a ( 3 t i b2 43 m a r d s1) e v i t c a n i / e v i t c a ( 2 t i b3 42 m a r d s1) e v i t c a n i / e v i t c a ( 1 t i b5 41 m a r d s1) e v i t c a n i / e v i t c a ( 0 t i b6 40 m a r d s1) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b0 27 k l c i c p1) e v i t c a n i / e v i t c a ( 6 t i b9 16 k l c i c p1) e v i t c a n i / e v i t c a ( 5 t i b8 15 k l c i c p1) e v i t c a n i / e v i t c a ( 4 t i b6 14 k l c i c p1) e v i t c a n i / e v i t c a ( 3 t i b5 13 k l c i c p1) e v i t c a n i / e v i t c a ( 2 t i b3 12 k l c i c p1) e v i t c a n i / e v i t c a ( 1 t i b2 11 k l c i c p1) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a (
8 ics9250-10 preliminary product preview byte 3: reserved register (1 = enable, 0 = disable) byte 4: reserved register (1 = enable, 0 = disable) t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( t i b# n i pe m a nd w pn o i t p i r c s e d 7 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 6 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 5 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 4 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 3 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 2 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 1 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( 0 t i b- d e v r e s e r0) e v i t c a n i / e v i t c a ( notes: 1. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. pwd = power on default
9 ics9250-10 preliminary product preview absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3.3op c l = 0 pf; select @ 66m 60 100 ma supply current power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 400 600 m a supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l pin 7nh input capacitance 1 c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms delay t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guarenteed by design, not 100% tested in production.
10 ics9250-10 preliminary product preview electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 175 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 w output impedance r dsn2 b 1 v o = v dd *(0.5) 13.5 45 w output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 455055% skew t sk2b 1 v t = 1.25 v 175 ps t jcyc-cyc 1 v t = 1.25 v 250 ps jitter 1 guarenteed by design, not 100% tested in production.
11 ics9250-10 preliminary product preview electrical characteristics - ioapic t a = 0 - 70c;v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 30 w output impedance r dsn4 b 1 v o = v dd *(0.5) 9 30 w output high voltage v oh4 \ b i oh = -5.5 ma 2 v output low voltage v ol4 b i ol = 9.0 ma 0.4 v output high current i oh4 b v oh@ mi n = 1.0 v, v oh@ max = 2.375 v -27 -27 ma output low current i ol4 b v ol@ min = 1.2 v, v ol@ max= 0.3v 27 30 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t4b 1 v t = 1.25 v 45 55 % jitter t jcyc-cyc v t = 1.25 v 500 ps skew t sk4 1 250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 w output impedance r dsn3 1 v o = v dd *(0.5) 10 24 w output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 54 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production.
12 ics9250-10 preliminary product preview electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - ref, 48mhz_0 (pin 25) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 w output impedance r dsn5 1 v o = v dd *(0.5) 20 60 w output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.7 4 ns duty cycle d t5 1 v t = 1.5 v 45 55 % jitter t jcyc-cyc 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps skew t sk v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production.
13 ics9250-10 preliminary product preview electrical characteristics - 48mhz_1 (pin 26) t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 w output impedance r dsn3 1 v o = v dd *(0.5) 10 24 w output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 54 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production.
14 ics9250-10 preliminary product preview group offset waveforms group skews at common transition edges: (cpu = 66mhz) cpu & ioapic load (lumped) = 20pf; pci, sdram, 3v66 load (lumped) = 30pf. group symbol conditions min typ max units cpu to 3v66 s cpu1 -3 v6 6 cpu @ 1.25v, 3v66 @ 1.5v (note: 180 offset between cpu & 66mhz 0 500 ps cpu to sdram s cpu2-sdram cpu @ 1.25v, sdram @ 1.5v (note: 180 offset between cpu & 66mhz 0 500 ps 3v66 to pci s 3v66-pci 3v66 @ 1.5v, pci @ 1.5v 1.5 4 ns ioapic to pci s ioapic-pci ioapic @ 1.25v, pci @1.5v 0 500 ps 1 guarenteed by design, not 100% tested in production. group skews at common transition edges: (cpu = 100mhz) cpu & ioapic load (lumped) = 20pf; pci, sdram, 3v66 load (lumped) = 30pf. group symbol conditions min typ max units cpu to 3v66 s cpu1 -3 v6 6 cpu @ 1.25v, 3v66 @ 1.5v (note: 180 offset between cpu & 100mhz 0 500 ps cpu to sdram s cpu2-sdram cpu @ 1.25v, sdram @ 1.5v (note: 180 offset between cpu & 100mhz 0 500 ps 3v66 to pci s 3v66-pci 3v66 @ 1.5v, pci @ 1.5v 1.5 4 ns ioapic to pci s ioapic-pci ioapic @ 1.25v, pci @1.5v 0 500 ps 1 guarenteed by design, not 100% tested in production.
15 ics9250-10 preliminary product preview general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1) all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf rc termination should be used on all over 50mhz outputs. 3) optional crystal load capacitors are recommended. connections to vdd: capacitor values: c1, c2 : crystal load values determined by user c3 : 100pf ceramic all unmarked capacitors are 0.01f ceramic
16 ics9250-10 preliminary product preview ssop package product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. ordering information ics9250 y f-10 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 .d a0 2 7 .5 2 7 .0 3 7 .6 5 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .6 0 0 .5 8 0 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 .

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