revision history as4c128m32md2 - 134 ball fbga package revision details date rev 1.0 preliminary datasheet jun 201 6 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -1?103- rev.1.0 june 2016
specifications - density : 4g bits - organization : - 16m words x 32 bits x 8 banks - package : - 134-ball fbga - lead-free (rohs compliant) and halogen-free - power supply : - vdd1 = 1.8v (1.7v~1.95v) - vdd2/vddq/vddca = 1.2v (1.14v~1.3v) - hsul_12 interface (high speed unterminated logic 1.2v) - data rate : - 1066mbps rl=8 - burst lengths (bl) : 4, 8 and 16 - burst type (bt) : sequential and interleave - read latency (rl) : 3, 4, 5, 6, 7, 8 - write latency (wl) : 1, 2, 3, 4 - output driver impedanc e: 34.3/40/48/60/80/120 - operating case temperature range - commercial tc = -25c to +85c - industrial tc = -40c to +85c features - jedec lpddr2-s4b compliance - low power consumption - four-bit prefetch ddr architecture - eight internal banks for concurrent operation - double data rate architecture for command, address and data bus - bidirectional and differential data strobe per byte of data (dqs and dqs ) - dqs is edge-aligned with data for reads, center- aligned with data for writes - differential clock inputs (ck and ck ) - data mask (dm) for write data - programmable read and write latencies (rl/wl) - auto refresh and self refresh - per-bank refresh for concurrent operation - partial-array self refresh (pasr) - on-chip temperature sensor to control self refresh rate for temperature compensated self refresh (tcsr) - deep power-down mode (dpd) - selectable output drive strength (ds) - clock stop capability - dq calibration offering specific dq output patterns - zq calibration table 1. ordering information part number org temperature maxclock (mhz) package AS4C128M32MD2-18BCN 128 mx32 commercial -25c to + 85c 533 134-ball fbga table 2. speed grade information speed grade clock frequency rl trcd (ns) trp (ns) ddr2l-1066 533mhz 8 18 18 as4c128m32md2-18bin 128 mx32 industrial -40c to +85c 533 134-ball fbga AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -2?103- rev.1.0 june 2016
pin configurations - 11.5mmx11.5mm 134b fbga 1 2 3 4 5 6 7 8 9 10 a dnu dnu nb nb nb nb nb nb dnu dnu a b dnu nc nc nb vdd2 vdd1 dq31 dq29 dq26 dnu b c vdd1 vss nc nb vss vss vddq dq25 vss vddq c d vss vdd2 zq nb vddq dq30 dq27 dqs3 ' 4 6 vss d e vss ca9 ca8 nb dq28 dq24 dm3 dq15 vddq vss e f vddca ca6 ca7 nb vss dq11 dq13 dq14 dq12 vddq f g vdd2 ca5 vrefca nb ' 4 6 dqs1 dq10 dq9 dq8 vss g h vddca vss & |