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? 2016 microchip technology inc. ds20005584a-page 1 MIC4600 features ? adjustable dead time circuitry ? anti-shoot-through protection ? internal ldo for single supply operation ? input voltage range: 4.5v to 28v ? fast propagation delay ? 20 ns ? up to 1.5 mhz operation ? low voltage logic level inputs for c or fpga driven power solutions ? independent inputs for low and high side drivers ?2 gate drive capable of driving 3000 pf load with 15 ns rise and fall times ? low 450 a typical quiescent current ? 3 mm 3 mm vqfn package ? ?40 ? c to +125 ? c junction temperature range applications ? distributed power systems ? communications/networking infrastructure ? set-top box, gateways and routers ? printers and scanners ? p and fpga controlled dc-dc regulator general description the MIC4600 is a 28v half bridge mosfet driver targeted for cost sensitive applications requiring high performance such as set-top boxes, gateways, routers, computing peripherals, telecom and networking equipment. the MIC4600 operates over a supply range of 4.5v to 28v. it has an internal linear regulator which provides a regulated 5v to power the mosfet gate drive and operates up to 1.5 mhz switching frequency. the MIC4600 uses an adjustable dead time circuit to prevent shoot-through in the external high and low-side mosfets. the MIC4600 is available in a small 3mm 3mm vqfn package with a junction temperature range of ?40c to 125c. package types MIC4600 3x3 vqfn top view vin hsi dl pgnd en dh sw lsi agnd avdd vdd bst agnd delay fault nc epad 1 2 3 4 12 11 10 9 16 15 14 13 56 78 28v half-bridge mosfet driver
MIC4600 ds20005584a-page 2 ? 2016 microchip technology inc. typical application circuit functional block diagram MIC4600 3x3 vqfn + controller vdd vdd avdd en fault hsi lsi en fault hsi lsi uvlo d1 MIC4600 linear regulator vin bst sw agnd agnd dh dl delay anti-shoot thru vdd pgnd v in 4.5v to 28v 4.7f 0.1f c bst 33f lo 4.0h v out 3.3v/10 a r1 10k r2 3.24k 100f control logic timer 1.0f 105k fb 100k en fault hsi lsi uvlo MIC4600 linear regulator vin bst sw agnd agnd dh dl delay anti-shoot thru vdd pgnd control logic timer avdd vdd
? 2016 microchip technology inc. ds20005584a-page 3 MIC4600 1.0 electrical characteristics absolute maximum ratings ? v in to pgnd ....................................................................................................................... ....................... ?0.3v to +29v v dd to pgnd ....................................................................................................................... ........................ ?0.3v to +6v v sw to pgnd....................................................................................................................... ............ ?0.3v to (v in +0.3v) v bst to v sw ............................................................................................................................... .................. ?0.3v to +6v v bst to pgnd....................................................................................................................... ..................... ?0.3v to +34v v hsi, v lsi to pgnd ....................................................................................................................... .. ?0.3v to (v dd +0.3v) v fault to agnd....................................................................................................................... .................... ?0.3v to +6v v en to pgnd ....................................................................................................................... ............ ?0.3v to (v in +0.3v) pgnd to agnd................................................................................................................... ...................... ?0.3v to +0.3v esd protection on all pins ..................................................................................................... .... 2 kv hbm, 200v mm operating ratings ?? supply voltage, v in ............................................................................................................................... ..... +4.5v to +28v vdd supply voltage, v dd ......................................................................................................................... +4.5v to +5.5v enable input, v en ............................................................................................................................... ................ 0v to v in maximum power dissipation...................................................................................................... .......................... ( note 1 ) ? notice: exceeding the absolute maximum ratings may damage the device. ?? notice: the device is not guaranteed to function outside its operating ratings. note 1: specification for packaged product only. dc characteristics electrical characteristics: unless otherwise indicated, v in = v en = 12v, v bst ? v sw = 5v; t a = 25c, c vin = c vdd = 1 f. bold values indicate ?40c t j +125c. parameters sym. min. typ. max. units conditions power supply input input voltage range (v in ) 4.5 ? 28 v ? quiescent supply current ? 450 750 a hsi = v dd , lsi = 0v, r delay = 124 k , non-switching shutdown supply current ? 920 av en = 0v v dd supply voltage v dd output voltage 4.8 5 5.4 v v in = 7v to 26v, i dd = 25 ma v dd uvlo threshold 3.6 4.2 4.3 v v dd rising v dd uvlo hysteresis ? 400 ? mv ? dropout voltage (v in ? v dd ) ? 380 ? mv i dd = 25 ma, v in = 5v v dd load regulation ? 1.23 ? % i dd = 0 to 25 ma enable control en logic threshold 0.65 1.25 1.4 v rising en hysteresis ? 69 ? mv ? en input bias current ?? 2 av en = 12v note 1: specified for packaged product only.
MIC4600 ds20005584a-page 4 ? 2016 microchip technology inc. fault fault over temperature ? 150 ? c t j rising over temperature hysteresis ? 23 ? c ? fault logic level low ? 0.05 0.2 vi fault = 5 ma fault pin leakage current ? 0.01 0.1 av fault = 5.5v input control hsi logic level high 1.4 ?? v? hsi logic level low ?? 0.65 v? hsi bias current ? 0.01 0.1 av hsi = 5v lsi logic level high 1.4 ?? v? lsi logic level low ?? 0.65 v? lsi bias current ? 0.01 0.1 av lsi = 5v timing dead time ? 18.7 ? ns r delay = 105 k switching frequency range ? 1.5 mhz ? minimum allowable pulse width ? 32 ? ns ? rise time (dh, dl) ? 15 ? ns c load = 3 nf, 10%v dd to 90%v dd fall time (dh,dl) ? 13.5 ? ns c load = 3 nf, 90%v dd to 10%v dd propagation delay, rising hsi to dh ? 26 ? ns gnd to 10%xv dd propagation delay, rising lsi to dl ? 18 ? ns gnd to 10%xv dd propagation delay, falling hsi to dh ? 55 ? ns v dd to 90%xv dd propagation delay, falling lsi to dl ? 14 ? ns v dd to 90%xv dd mosfet drivers dh r ds(on) , high ? 2 3 i dh = 20 ma dh r ds(on) , low ? 1.5 3 i dh = ?20 ma dl r ds(on) , high ? 2 3 i dl = 20 ma dl r ds(on) , low ? 1 2 i dl = ?20 ma dc characteristics (continued) electrical characteristics: unless otherwise indicated, v in = v en = 12v, v bst ? v sw = 5v; t a = 25c, c vin = c vdd = 1 f. bold values indicate ?40c t j +125c. parameters sym. min. typ. max. units conditions note 1: specified for packaged product only.
? 2016 microchip technology inc. ds20005584a-page 5 MIC4600 temperature specifications ( note 1 ) parameters sym. min. typ. max. units conditions temperature ranges junction temperature t j ? +150 ? c ? lead temperature ? ? 260 ? c soldering, 10sec. junction operating temperature t j ?40 ? +125 c ? storage temperature range t a ?65 ? +150 c ? package thermal resistances thermal resistance, 3 x 3 vqfn-16ld ? ja ? 59 ? c/w ? note 1: the maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., t a , t j , ? ja ). exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125c rating. sustained junction temperatures above +125c can impact the device reliability.
MIC4600 ds20005584a-page 6 ? 2016 microchip technology inc. 2.0 timing diagram figure 2-1: MIC4600 timing waveforms. hs dh dl hsi lsi t deadtime t r t f 90% 90% 10% 10% 10% t hplh t hphl 90% t pw t lplh t lphl
? 2016 microchip technology inc. ds20005584a-page 7 MIC4600 3.0 typical performance curves note: unless otherwise indicated, v in = 12v. figure 3-1: vin quiescent current vs. input voltage. figure 3-2: vin quiescent current vs. temperature. figure 3-3: vin shutdown current vs. input voltage. figure 3-4: vin shutdown current vs.temperature. figure 3-5: vin operating current vs. frequency. figure 3-6: r ds(on) vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 200 250 300 350 400 450 500 550 600 4 8 12 16 20 24 28 vin quiescent current (a) input voltage (v) -40c 25c 125c hsi = vdd lsi = 0v sw = 0v 350 370 390 410 430 450 470 490 510 530 550 -50-25 0 255075100125 vin quiescent current (a) temperature ( c ) v in = 28v v in = 12v v in = 4.5v hsi = vdd lsi = 0v sw = 0v 0 10 20 30 40 50 4 8 12 16 20 24 28 vin shutdown current (a) input voltage (v) -40oc 25oc 125oc en = 0v sw = 0v 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 vin shutdown current (a) temperature ( c) en = 0v v in = 4.5v v in = 12v v in = 28v 0 0.5 1 1.5 2 0 200 400 600 800 1000 1200 1400 vin operating current (ma) frequency (khz) -40oc 25oc 125oc vin = 12v sw = 0v c load =0nf 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 -50 -25 0 25 50 75 100 125 r ds(on) () temperature (c) v in = 4.5v sw = 0v hsi = lsi = 0v i dl = 50ma v in = 12v
MIC4600 ds20005584a-page 8 ? 2016 microchip technology inc. note: unless otherwise indicated, v in = 12v. figure 3-7: r ds(on) vs. temperature. figure 3-8: r ds(on) vs. temperature. figure 3-9: r ds(on) vs. temperature. . figure 3-10: propagation delay vs. input voltage. figure 3-11: propagation delay vs. temperature. figure 3-12: dh rise time vs. input voltage. 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 -50-25 0 255075100125 r ds(on) ( ) temperature (c) v in = 4.5v sw = 0v hsi = lsi = 0v i dh = 50ma v in = 12v 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 -50 -25 0 25 50 75 100 125 r ds(on) () temperature (c) v in = 4.5v sw = 0v hsi = lsi = vdd i dl = -50ma v in = 12v 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 -50 -25 0 25 50 75 100 125 r ds(on) () temperature (c) v in = 4.5v sw = 0v hsi = lsi = vdd i dh =-50ma v in = 12v 10 20 30 40 50 60 70 4 8 12 16 20 24 28 delay (ns) vin (v) t hplh t hphl t lplh temp = 25c sw = 0v t lphl 10 20 30 40 50 60 70 -50-25 0 255075100125 delay (ns) temperature (c) t hplh t hphl t lplh vin = 12v sw = 0v t lphl 8 10 12 14 16 4 8 12 16 20 24 28 tr (ns) vin (v) 25c -40c 125c sw = 0v
? 2016 microchip technology inc. ds20005584a-page 9 MIC4600 figure 3-13: dh fall time vs. input voltage. figure 3-14: deadtime vs. r delay for dl to dh . figure 3-15: deadtime vs. r delay for dh to dl . figure 3-16: deadtime delay vs. temperature. 8 10 12 14 16 4 8 12 16 20 24 28 tf (ns) vin (v) 25c -40c 125c sw = 0v 0 20 40 60 80 100 120 140 0 200 400 600 800 1,000 1,200 1,400 t dead (ns) r delay (k) 4.5vin 12vin 0 20 40 60 80 100 120 140 160 0 200 400 600 800 1,000 1,200 1,400 t dead (ns) r delay (k) 4.5vin 12vin 80 85 90 95 100 105 110 -50-25 0 255075100125 t dead (ns) temperature (c) dl to dh dh to dl
MIC4600 ds20005584a-page 10 ? 2016 microchip technology inc. 4.0 functional characteristics 4.1 functional diagram figure 4-1: functional diagram. 4.2 functional description the MIC4600 is a 28v half-bridge mosfet driver with integrated ldo. it is designed to independently drive both high-side and low-side n-channel mosfets. the ldo eliminates the need for a second vdd supply voltage by generating the gate drive voltage from the input supply. the MIC4600 offers a wide 4.5v to 28v operating supply range. refer to the MIC4600 block diagram above. the high and low-side drivers contain an input buffer with hysteresis and an output buffer. the high-side output buffer includes a high-speed level-shifting circuit that is referenced to the hs pin. an external diode is used to supply v dd to the bootstrap circuit that provides the drive voltage for the high-side output. 4.2.1 startup and uvlo the uvlo circuit monitors v dd and inhibits both drivers in a low state when the supply voltage is below the uvlo threshold. hysteresis in the uvlo circuit prevents noise and circuit impedance from causing chatter during turn-on. 4.2.2 enable input a logic high on the enable pin (en) allows normal operation to occur. conversely, when a logic low is applied on the enable pin, the high and low-side driver outputs turn-off and the driver enters a low supply current shutdown mode. do not leave floating. 4.2.3 dead-time delay shoot-through occurs in a half-bridge or synchronous buck topology when both the high and low side mosfets conduct at the same time. this condition is caused by driver propagation delay variation and mosfet turn on/off times. shoot-through causes an increase in mosfet power dissipation, circuit noise and interference with power circuit operation. a resistor on the delay pin sets the break-before-make delay time between the high and low-side mosfets . see the applications section for additional information. 4.2.4 input stage both the hsi and lsi pins are referenced to the agnd pin. the voltage state of the input signal does not change the quiescent current draw of the driver. the MIC4600 has a ttl-compatible input range and can be used with input signals with amplitude less than or equal to the v dd voltage. a small amount of hysteresis improves the noise immunity of the driver inputs. 4.2.5 low-side driver figure 4-2 shows a block diagram of the low-side driver. the low-side driver is designed to drive a ground (pgnd pin) referenced n-channel mosfet. the low-side gate drive voltage equals v dd , which is typically 5v. a low driver impedance allows the external mosfet to be turned on and off quickly. the rail-to-rail drive capability of the output ensures a low r dson from the external mosfet. a high level applied to lsi pin causes the upper driver mosfet to turn on and vdd voltage is applied to the gate of the external mosfet. a low level on the lsi pin turns off the upper driver and turns on the low side driver to ground the gate of the external mosfet. en fault hsi lsi uvlo MIC4600 linear regulator vin bst sw agnd agnd dh dl delay anti-shoot thru vdd pgnd control logic timer avdd vdd
? 2016 microchip technology inc. ds20005584a-page 11 MIC4600 figure 4-2: low-side driver circuit. 4.2.6 high-side driver and bootstrap circuit a block diagram of the high-side driver and bootstrap circuit is shown in figure 4-3 . this driver is designed to drive a floating n-channel mosfet, whose source terminal is referenced to the sw pin. the output voltage of the dh pin equals vdd minus the external bootstrap diode forward voltage drop. the high-side gate drive voltage is typically 4.5v. a low-power, high-speed, level-shifting circuit isolates the low side (agnd pin) referenced circuitry from the high-side (sw pin) referenced driver. power to the high-side driver is supplied by the bootstrap circuit. figure 4-3: high-side driver and bootstrap circuit. the bootstrap circuit consists of an external diode and external capacitor, c b . in a typical application, such as the synchronous buck converter shown in figure 4-4 , the sw pin is at ground potential while the low-side mosfet is on. during this time, the diode allows capacitor c b to charge up to v dd -v f (where v f is the forward voltage drop of the diode). after the low-side mosfet is turned off and the dh pin goes high, the voltage across capacitor c b is applied to the gate of the upper external mosfet. as the upper mosfet turns on, voltage on the sw pin rises with the source of the high-side mosfet until it reaches v in . as the sw and bst pins rise, the diode is reverse biased preventing capacitor c b from discharging. figure 4-4: MIC4600 driving a synchronous buck converter. 4.2.7 thermal shutdown thermal shutdown protects the driver from damage due to excessive die temperature. if the die exceeds the high temperature threshold, the output drive is inhibited and the fault pin is asserted low. the driver automatically resumes operation, and the fault pin is de-asserted, when the die temperature cools below the lower threshold, set by the circuit?s hysteresis. if resumed operation results in reheating of the die above the high threshold, another shutdown cycle occurs. the switch continues thermal cycling until the condition has been resolved. 4.2.8 fault pin the fault signal is an n-channel open drain output, which is asserted low when the MIC4600 enters thermal shutdown. pgnd vdd dl external fet sw bst dh external fet vdd c b v in level shift
MIC4600 ds20005584a-page 12 ? 2016 microchip technology inc. 5.0 pin descriptions the descriptions of the pins are listed in table 5-1 . table 5-1: pin function table pin number pin name pin function 1v in vin supply (input): input supply to the internal ldo.the vin operating voltage range is from 4.5v to 28v. connect a decoupling capacitor between this pin and pgnd. 2en enable (input): a logic level high allows normal operation. a logic level low on this pin shuts down the drive in a low quiescent current state. the en pin must not be left floating. 3 hsi high side input (input): a logic level input that controls the high side gate drive. 4 lsi low side input (input): a logic level input that controls the low side gate drive. 5 nc no connect. not internally connected. 6 fault fault (output). the active low, open drain output pulls low during an over-temperature fault. a resistor to vdd is needed to pull this signal high. 7 delay delay (output). connect a resistor from this pin to ground to adjust the dead time (break before make). 8, 16 agnd analog ground. agnd must be connected directly to the ground planes. do not route the agnd pin to the pgnd pad on the top layer. refer to the pcb layout guidelines for details. 9 pgnd power ground. pgnd is the ground path for the MIC4600 output drivers. the pgnd pin should be connected to the source of low-side n-channel mosfet and the negative terminals of decoupling capacitors. 10 dl drive low (output). low side mosfet gate driver. 11 sw switch node (output): internal connection for the high-side mosfet source and low-side mosfet drain. due to the high speed switching on this pin, the sw pin should be routed away from sensitive nodes. 12 dh drive high (output). high side mosfet gate driver. 13 bst boost (output): bootstrapped voltage to the high-side n-channel mosfet driver. connect a schottky diode between the vdd pin and the bst pin. connect a boost capacitor between the bst pin and the sw pin. 14 vdd 5v internal linear regulator (output): vdd supplies the power mosfet gate drive supply voltage. vdd is created by internal ldo from vin. when vin < +5.5v, vdd should be tied to vin pin. a 2.2 f ceramic capacitor from the vdd pin to ground plane on pcb is required for stability . 15 avdd 5v analog input (input): avdd is the supply for the internal driver logic and control circuitry. connect the vdd output to the avdd pin. epad epad exposed thermal pad. connect to the ground plane for optimum thermal performance.
? 2016 microchip technology inc. ds20005584a-page 13 MIC4600 6.0 application information 6.1 adjustable dead time dead-time control prevents shoot-through current from flowing through the external power mosfets during switching transitions. the delay allows enough time for the high-side driver to turn off before the low-side driver turns on. it also prevents the high-side driver from turning on before the low-side driver has turned off. the dead-time between the high and low-side mosfets can be adjusted with a resistor on the delay pin. the dead-time can be approximated with the formula in equation 6-1 . see the typical performance curves section for a more precise determination of r delay vs. t dead . equation 6-1: where: t dead is the break-before-make delay between the highside and low-side gate drive signals r delay is the delay pin resistance in k . 6.2 other timing considerations make sure the input signal pulse width is greater than the minimum specified pulse width. an input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is significantly less than the input. the maximum duty cycle (ratio of high side on-time to switching period) is controlled by the minimum pulse width of the low side and by the time required for the c b capacitor to charge during the off-time. adequate time must be allowed for the c b capacitor to charge up before the high-side driver is turned on. 6.3 single input operation both outputs can be controlled from a single input signal by pulling the lsi input high to vdd and applying the input signal to the hsi pin. in this configuration, the dead-time between the dh and dl transitions is set by the resistor value connected to the delay pin. when the hsi pin goes from a low to a high, the dl pin goes low and the dh pin goes high after the dead time delay. when the hsi pin changes from a high to a low, the dh pin goes low. after the delay time, the dl pin goes high. 6.4 bootstrap diode and capacitor the gate drive voltage of the high-side driver equals the v dd voltage minus the voltage drop across the bootstrap diode. a schottky diode is recommended due to the lower forward voltage drop. power dissipation in the bootstrap diode can be calculated using the following equations. the average current drawn by repeated charging of the high-side mosfet is calculated by equation 6-2 : equation 6-2: where; q gate = total gate charge at v dd f s = gate drive switching frequency the average power dissipated by the forward voltage drop of the diode equals: equation 6-3: where; v f = diode forward voltage drop the value of v f should be taken at the peak current through the diode; however, this current is difficult to calculate because of differences in source impedances. the peak current can either be measured or the value of v f at the average current can be used, which will yield a good approximation of diode power dissipation. the voltage on the bootstrap capacitor drops each time it delivers charge to turn on the mosfet. the voltage drop depends on the gate charge required by the mosfet. most mosfet specifications specify gate charge versus v gs voltage. based on this information and a suggested capacitor voltage drop of less than 0.1v, the minimum value of bootstrap capacitance is: equation 6-4: where: q gate = total gate charge at v dd ? v bst = voltage drop at the bst pin t dead 12 10 9 ? r delay 0.9 10 10 ? ? ? + ? = i fave ?? q gate f s ? = pdiode fwd i fave ?? v f ? = c b q gate ? v bst ----------------- ?
MIC4600 ds20005584a-page 14 ? 2016 microchip technology inc. 6.5 power dissipation considerations power dissipation in the driver can be separated into two areas: ? quiescent current dissipation ? internal driver dissipation 6.6 quiescent current power dissipation power is dissipated in the MIC4600 even if nothing is being driven. the quiescent current is drawn by the bias for the internal circuitry and the level shifting circuitry. the quiescent current is proportional to operating frequency. the typical characteristic graphs show how quiescent current varies with switching frequency. the power dissipated due to quiescent current is calculated in equation 6-5 . equation 6-5: 6.7 gate driver power dissipation power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source and gate to drain capacitance of the external mosfet. figure 6-1 shows a simplified equivalent circuit of the MIC4600 driving an external high-side mosfet. figure 6-1: MIC4600 driving an external mosfet. 6.7.1 dissipation during the external mosfet turn-on energy from capacitor c b is used to charge up the input capacitance of the mosfet (c gd and c gs ). the energy delivered to the mosfet is dissipated in the three resistive components, r on , r g and r g_fet . r on is the on resistance of the upper driver mosfet in the MIC4600. r g is the series resistor (if any) between the driver ic and the mosfet. r g_fet is the gate resistance of the mosfet. r g_fet is usually listed in the power mosfet?s specifications. the esr of capacitor c b and the resistance of the connecting etch can be ignored since they are much less than r on and r g_fet . the effective capacitances of c gd and c gs are difficult to calculate because they vary non-linearly with i d , v gs , and v ds . fortunately, most power mosfet specifications include a typical graph of total gate charge vs. v gs . figure 6-2 is a typical gate charge curve for a power mosfet. this chart shows that for a gate voltage of 4.5v, the mosfet gate is charged up to 25 nc of total gate charge. the energy dissipated by the resistive components of the gate drive circuit during turn-on is calculated as noted in equation 6-6 through . equation 6-6: but: equation 6-7: so: equation 6-8: where: c iss = total gate capacitance of the mosfet figure 6-2: typical gate charge vs. v gs . the same energy is dissipated by r off , r g , and r g_fet when the driver ic turns the mosfet off. assuming r on is approximately equal to r off , the total energy and power dissipated by the resistive drive elements is illustrated in equation 6-9 . p diss _iq v dd i dd ? = sw bst dh external fet vdd c b r g r g_fet r on r off c gd c gs MIC4600 high-side driver e 1 2 -- - c iss ? v gs 2 ? = qcv ? = e 1 2 -- - q g ? v gs ? =
? 2016 microchip technology inc. ds20005584a-page 15 MIC4600 equation 6-9: and equation 6-10: where: e driver = energy dissipated per switching cycle p driver = power dissipated per switching cycle q g = total gate charge at v gs v gs = gate to source voltage on the mosfet f s = switching frequency of the gate drive circuit the power dissipated inside the driver is equal to the ratio of r on and r off to the external resistive losses in r g and r g_fet . letting r on = r off , the power dissipated in the MIC4600 due to driving the external mosfet is illustrated in equation 6-11 . equation 6-11: 6.8 total power dissipation and thermal considerations total power dissipation in the MIC4600 is equal to the power dissipation caused by driving the external mosfets and the quiescent current. equation 6-12: the die temperature can be calculated after the total power dissipation is known, as in equation 6-13 . equation 6-13: where: t a = maximum ambient temperature t j = junction temperature (c) pdiss total = power dissipation of the MIC4600 ? ja = thermal resistance from junction to ambient air 6.9 decoupling and bootstrap capacitor selection decoupling capacitors are required for both the low side (vdd) and high side (bst) supply pins. these capacitors supply the charge necessary to drive the external mosfets and also minimize the voltage ripple on these pins. the capacitor from bst to sw has two functions: it provides decoupling for the high-side driver and is the supply voltage to the high-side circuit while the external mosfet is on. ceramic capacitors are recommended because of their low impedance and small size. z5u type ceramic capacitor dielectrics are not recommended because of the large change in capacitance over temperature and voltage. a minimum value of 0.1 f is required for each of the capacitors, regardless of the mosfets being driven. larger mosfets may require larger capacitance values for proper operation. placement of the decoupling capacitors is critical. the bypass capacitor for vdd should be placed as close as possible between the vdd and pgnd pins. the bypass capacitor (c b ) for the bst supply pin must be located as close as possible between the bst and sw pins. the etch connections must be short, wide, and direct. the use of a ground plane to minimize connection impedance is recommended (refer to the grounding, component placement, and circuit layout section for more information). 6.10 grounding, component placement, and circuit layout nanosecond switching speeds and ampere peak currents in and around the MIC4600 drivers require proper placement and trace routing of all components. improper placement may cause degraded noise immunity, false switching, excessive ringing, or circuit latch-up. figure 6-3 shows the critical current paths when the driver outputs go high and turn on the external mosfets. it also helps demonstrate the need for a low impedance ground plane. charge needed to turn-on the mosfet gates comes from the decoupling capacitors c vdd and c b . current in the low-side gate driver flows from c vdd through the internal driver, into the mosfet gate, and out the source. the return connection back to the decoupling capacitor is made through the ground plane. any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the mosfet. this voltage works against the gate drive voltage and can either slow down or turn off the mosfet during the period when it should be turned on. current in the high-side driver is sourced from capacitor c b and flows into the bst pin and out the dh pin, into the gate of the high side mosfet. the return e driver q g v gs ? = p driver q g v gs ? f s ? = pdiss driver p driver r on r on r g r g _fet ++ ------------------------------------------------- ? = p disstotal p dissiq p dissdrive + = t j t a pdiss total ? ja ? + =
MIC4600 ds20005584a-page 16 ? 2016 microchip technology inc. path for the current is from the source of the mosfet and back to capacitor c b . the high-side circuit return path usually does not have a low-impedance ground plane so the etch connections in this critical path should be short and wide to minimize parasitic inductance. as with the low-side circuit, impedance between the mosfet source and the decoupling capacitor causes negative voltage feedback that fights the turn-on of the mosfet. it is important to note that capacitor c b must be placed close to the bst and sw pins. this capacitor not only provides all the energy for turn-on but it must also keep hb pin noise and ripple low for proper operation of the high-side drive circuitry. figure 6-3: turn-on current paths. figure 6-4 shows the critical current paths when the driver outputs go low and turn off the external mosfets. short, low-impedance connections are important during turn-off for the same reasons given in the turn-on explanation. current flowing through the internal diode replenishes charge in the bootstrap capacitor, c bst . figure 6-4: turn-off current paths. use a ground plane to minimize parasitic inductance and impedance of the return paths. the MIC4600 is capable of greater than 1a peak currents and any impedance between the MIC4600, the decoupling capacitors, and the external mosfet will degrade the performance of the driver. sw bst dh vdd c b level shift hsi lsi pgnd dl c vdd low-side drive turn-off current path high-side drive turn-off current path MIC4600
? 2016 microchip technology inc. ds20005584a-page 17 MIC4600 7.0 packaging information 7.1 package marking information 1 4600 624 y xxxx yww 16-lead vqfn* example legend: xx...x product code or customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. , , pin one index is identified by a dot, delta up, or delta down (triangle mark). note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. package may or may not include the corporate logo. underbar (_) symbol may not be to scale. 3 e 3 e
MIC4600 ds20005584a-page 18 ? 2016 microchip technology inc. 16-lead vqfn 3 mm x 3 mm package outline and recommended land pattern b a 0.20 c 0.20 c 0.10 c a b 0.05 c (datum b) (datum a) seating plane note 1 n 2x top view side view bottom view note 1 1 2 n 0.10 c a b 0.10 c a b microchip technology drawing c04-404b sheet 1 of 2 2x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: d e see detail a d2 e2 k 16-lead plastic quad flat, no lead package (8n) - 3x3x1.0 mm body [vqfn] wettable flanks (stepped), 0.35 mm terminal length l e 2 1 2 e 16x b c
? 2016 microchip technology inc. ds20005584a-page 19 MIC4600 16-lead vqfn 3 mm x 3 mm package outline and recommended land pattern microchip technology drawing c04-404b sheet 2 of 2 16-lead plastic quad flat, no lead package (8n) - 3x3x1.0 mm body [vqfn] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: wettable flanks (stepped), 0.35 mm terminal length ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated 3. dimensioning and tolerancing per asme y14.5m notes: dimension limits units max min nom millimeters terminal width b 0.18 0.25 0.30 pitch number of terminals overall width standoff overall length overall height a1 d e n e a 0.00 3.00 bsc 16 0.50 bsc 0.05 1.00 0.90 0.02 terminal length l 0.25 0.35 0.45 e2 d2 exposed pad width exposed pad length 1.00 1.10 1.50 0.80 3.00 bsc 1.10 1.00 1.50 terminal thickness a3 0.20 ref k- 0.20 - terminal-to-exposed pad step length l1 step height a4 c seating plane detail a 0.10 c 0.08 c 16x (a3) a l1 a4 a1 0.035 0.060 0.085 0.05 0.12 0.19
MIC4600 ds20005584a-page 20 ? 2016 microchip technology inc. 16-lead vqfn 3 mm x 3 mm package outline and recommended land pattern recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 1.50 1.50 millimeters 0.50 bsc min e max 2.60 contact pad length (x16) contact pad width (x16) y1 x1 0.50 0.30 microchip technology drawing c04-2404a nom 16-lead plastic quad flat, no lead package (8n) - 3x3x1.0 mm body [vqfn] silk screen c1 contact pad spacing 2.60 contact pad to center pad (x16) g1 0.30 thermal via diameter v thermal via pitch ev 0.30 1.00 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1. 2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: wettable flanks (stepped), 0.35 mm terminal length contact pad to contact pad (x12) g2 0.20 c1 ev ev c2 e x2 y2 x1 y1 g1 g2 ?v
? 2016 microchip technology inc. ds20005584a-page 21 MIC4600 appendix a: revision history revision a (july 2016) ? converted micrel document MIC4600 to micro- chip data sheet template ds20005584a. ? ?minor text changes throughout.
MIC4600 ds20005584a-page 22 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005584a-page 23 MIC4600 product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . examples: a) MIC4600yml-t5: 28v half-bridge mosfet driver, 2 independent ttl inputs, ?40c to +125c temperature range, rohs compliant, 16ld 3x3 vqfn, 500/ reel. b) MIC4600yml-tr: 28v half-bridge mosfet driver, 2 independent ttl inputs, ?40c to +125c temperature range, rohs compliant, 16ld 3x3 vqfn, 5000/ reel. p art no. x xx package temperature device device: MIC4600: 28v half-bridge mosfet driver temperature range: y = ?40 ? c to +125 ? c (rohs compliant) package: ml = 16-lead 3x3 vqfn media type: t5 = 500/reel tr = 5000/reel range xx media type
MIC4600 ds20005584a-page 24 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005584a-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, includ ing but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0801-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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