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mp5013a 5 v, 5 a programmable current-limit switch with over-voltage clamp and slew-rate control in tsot23-8 mp5013a rev. 1.0 www.monolithicpower.com 1 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the future of analog ic technology description the mp5013a is a protection device designed to protect circuitry on the output (source) from transients on the input (v cc ). also, it protects the input from undesired shorts and transients coming from the source. a small capacitor on dv/dt controls the slew rate that limits the inrush current at the source. dv/dt has an internal circuit that allows the customer to float this pin (no connection) and still receive 1.4 ms ramp time at the source. the maximum load at the source is current limited using a sense fet topology. an external resistor between i-limit and source controls the magnitude of the current limit. an internal charge pump drives the gate of the power device, allowing the dmos power fet to have a very low on resistance of just 36 m ? . the mp5013a protects the source from the input becoming too low or too high. under-voltage lockout ensures that the input remains above the minimum operating threshold before the power device turns on. if the input rises above the high output threshold, the mp5013a limits the source voltage. features ? 3 v to 5.5 v operating input range ? 5.7 v typical output over-voltage clamp ? absolute maximum voltage of 22 v ? input under-voltage lockout ? low inrush current during start-up ? integrated 36 m ? power fet ? enable/fault pin ? adjustable output voltage slew rate ? adjustable current limit ? thermal shutdown protection ? tsot23-8 package applications ? storage (hdds, ssds) ? hot-swap systems ? set-top boxes ? usb ports/hubs ? gaming typical application all mps parts are lead-free, halogen-free, and adhere to the rohs directive. for mps green status, please visit the mps website under qualit y assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 2 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. ordering information part number* package top marking MP5013AGJ tsot23-8 see below * for tape & reel, add suffix ?z (e.g. MP5013AGJ?z) top marking amk: product code of MP5013AGJ y: year code package reference absolute maxi mum ratings (1) vcc, source, i-limit...............?0.3 v to 22 v dv/dt, enable/fault................?0.3 v to 6 v storage temperature ............... ?65c to +155c junction temperature................................. +150c lead temperature ...................................... +260c continuous power dissipation (t a =+25c) (2) ............................................................... .1.25 w recommended operating conditions (3) input voltage operating range ......... 3 v to 5.5 v 0.5 in 2 pad ................................................. 4.2 a for minimum copper, t a = 80c ................ 2.3 a operating junction temp. (t j )........ -40c to +125c thermal resistance (4) ja jc tsot23-8 ..............................100 ..... 55 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max) the junction-to- ambient thermal resistance ja and the ambient temperature t a, the maximum allowable power dissipation at any ambient temperature is calculated using: p d (max)=(t j (max)-t a )/ ja . exceeding the maximum allowable power dissipation will produce an excessive die temperature, causing the regulato r to go into thermal shutdown. internal thermal shutdown circuitry protects the dev ice from permanent damage. reduce 0.1 watts for every 10 o c ambient temperature increase. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7 4-layer board.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 3 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. electrical characteristics v cc = 5 v, r limit = 22 ? , capacitive load = 10 f, t j = 25c, unless otherwise noted. parameters symbol condition min typ max units power fet delay time dly enabling of chip to i d = 40 ma with a 5 ? resistive load, float dv/dt 37 s t j = 25c 36 on resistance r dson t j = 85c (5) 48 m ? off-state output voltage v off v cc = 18 v, v en = 0 v, r l = 500 ? 120 mv thermal latch shutdown temperature (5) t sd 175 c under/over-voltage protection output clamp voltage v clamp over-voltage protection v cc = 8 v 5.5 5.7 5.9 v under-voltage lockout v uvlo rising edge 2.5 2.7 2.9 v under-voltage lockout (uvlo) hysteresis v hyst 0.13 v current limit (5) hold current i lim-ss 0 ? short resistance, r lim = 22 2.1 2.8 3.5 a trip current i lim-ol r lim = 22 5 a dv/dt circuit rise time r float dv/dt, output rises from 10% to 90% 1.4 ms enable/fault low-level input voltage v il output disabled 0.5 v intermediate-level input voltage v i (int) thermal fault, output disabled 0.82 1.3 1.95 v high-level input voltage v ih output enabled 2.5 v high-state maximum voltage v i (max) 4.95 v pull-up current (source) i il v enable = 0 v 15 25 35 a maximum fanout for fault signal maximum number of chips for simultaneous shutdown 3 units maximum voltage on en (6) v max vcc v total device device operational 890 950 enable shutdown 580 650 bias current i bias thermal shutdown 600 700 a minimum operating voltage for uvlo v min enable < 0.5 v 2.5 v notes: 5) guaranteed by characterization test. 6) maximum input voltage on enable/fault is 6 v if vcc 6 v. maximum input voltage on enable/fault is vcc if vcc 6 v.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 4 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics v in = 5 v, v en = 5 v, r limit = 22 , c out = 10 f, c dv/dt = float, t a = 25c, unless otherwise noted. 0 1 2 3 4 5 6 7 10 20 30 40 50 60 70 80 90100 600 650 700 750 800 850 900 950 3 3.5 4 4.5 5 5.5 300 350 400 450 500 550 600 650 3 3.5 4 4.5 5 5.5 30 35 40 45 50 55 3 3.5 4 4.5 5 5.5 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2 2.5 3 3.5 4 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5 6 3 3.5 4 4.5 5 5.5 0 3 6 9 12 15 4 8 12 16 20
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 5 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5 v, v en = 5 v, r limit = 22 , c out = 10 f, c dv/dt = float, t a = 25c, unless otherwise noted. start-up through input voltage no load v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. start-up through enable no load shutdown through input voltage no load shutdown through enable no load
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 6 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical performanc e characteristics (continued) v in = 5 v, v en = 5 v, r limit = 22 , c out = 10 f, c dv/dt = float, t a = 25c, unless otherwise noted. v out 2v/div. v in 5v/div. v en 5v/div. i out 1a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. v out 2v/div. v in 5v/div. v en 5v/div. i out 2a/div. short circuit before input voltage start-up and thermal shutdown short circuit during normal operation and thermal shutdown current limit start-up into ovp v in = 16v v out 2v/div. i out 2a/div.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 7 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pin functions pin # name description 1 i-limit current limit. use a resistor between i-limit and the source pins to set the overload and short-circuit current-limit levels. 2 enable/fault a tri-state, bi-directional interface . leave enable/fault floating to enable the output. pull enable/fault to ground (using an open drain or open collector device) to disable the output. if a thermal fault occurs, this voltage enters an intermediate state to signal that the device is in thermal shutdown. 3 dv/dt controls the slew rate of the output voltage at turn on . dv/dt has an internal capacitor that allows it to ramp up over a period of 1.4 ms. an external capacitor can be added to dv/dt to increase the ramp time. if an additional time delay is not required, dv/dt should be left open. 4 gnd ground. internal ic reference. 5,6 source source. internal power fet source. ic output. 7,8 vcc input . positive input voltage.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 8 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. functional block diagram enable/ fault vcc i-limit figure 1?functional block diagram
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 9 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. operation the mp5013a limits the inrush current to the load when a circuit card connects to a live backplane power source, thereby limiting the backplane?s voltage drop and the dv/dt of the voltage to the load. it offers an integrated solution to monitor the input voltage, output voltage, output current, and die temperature, eliminating the external current-sense power resistor, power mosfet, and thermal sensor. under-voltage lockout operation if the supply (input) is below the uvlo threshold, the output is disabled, and the enable/fault line is driven low. when the supply rises above the uvlo threshold, the output is enabled, and enable/fault is pulled high through a 25 a current source without an external pull-up resistor. the pull-up voltage is limited to 4.95 v. output over-voltage protection (ovp) if the input voltage exceeds the over-voltage protection (ovp) threshold, the output is clamped at 5.7 v (typically). current limiting when the chip is active, if the load reaches the over-current protection (ocp) threshold (trip current), or a short is present, the part switches to constant-current mode (hold current). the chip shuts down only if the over-current condition eventually triggers thermal protection. however, when the part is powered up by vcc or en, the load current should be less than the hold current. otherwise, the part cannot be turned on fully. in a typical application with a current-limiting resistor of 22 ? , the trip current is 5 a, and the hold current is 2.8 a. if the device is in normal operation and passing 2 a, it will only need to dissipate 144 mw with the low on resistance of 36 m ? . for a package dissipation of 100c/w, the temperature rise is +14c. given a 25c ambient temperature, the typical package temperature is 39c. the mp5013a requires a heat sink during constant-current mode (e.g., from a short circuit) to prevent an unwanted shutdown. (during a short-circuit condition, the chip must dissipate the power from a 5 v drop.) without an additional heat dissipation at 100c/w, the temperature will exceed the thermal threshold (+175c), and the mp5013a will shut down to force the temperature to drop. thermal protection if the temperature exceeds the thermal threshold, the mp5013a disables its output and drives the enable/fault line to the middle (mid) level (see the following ?enable/fault? section for more information). the thermal fault condition is latched, and the part will remain in a latched-off state until the power is re-started, or enable/ fault is re-set. enable/fault enable/fault is a bi-directional, three-level i/o with a weak pull-up current (25 a, typically). the three levels are low, mid, and high. it functions to enable/disable the part and to relay fault information. enable/fault as an input: 1. low and mid disable the part. 2. low, in addition to disabling the part, clears the fault flag. 3. high enables the part (if the fault flag is clear). enable/fault as an output: 1. the pull-up current will allow a ?wired nor? pull-up to enable the part (if not overridden). 2. an under-voltage condition will cause a low on enable/fault and will clear the fault flag. 3. a thermal fault will set a mid on the enable/fault and will set the fault flag.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 10 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. the enable/fault line must remain at a high level for the output to turn on. the fault flag is an internal flip-flop that can be set or re-set under the following conditions: 1. thermal shutdown: sets fault flag. 2. under-voltage: re-sets fault flag. 3. low on enable/fault: re-sets fault flag. 4. mid on enable/fault: no effect. during a thermal shutdown, enable/fault is driven to the mid level. there are 4 types of faults, and each fault has a direct and indirect effect on eanble/fault and the internal fault flag (see table 1). in a typical application, there are one or more of the mp5013a chips in a system. enable/fault lines are connected together typically. table 1?fault function influence in application fault description internal action effect on fa ult pin effect on flag effect on secondary part short/over current limits current none none none under voltage output turns off internally drives enable/fault to logic low flag is re-set disables secondary output and re-sets fault flag over voltage limits output voltage none none none thermal shutdown shutdown. the part is latched off until a uvlo or externally driven to ground. internally drives enable/fault to mid level flag is set disables secondary part output
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 11 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. application information current limit the current limit is a function of the external current-limit resistor. table 2 lists examples of current values as a function of the resistor value. rise time the rise time is a function of the capacitor (c dv/dt ) on dv/dt. table 3 lists the typical rise time as a function of capacitance. table 2?current limit vs. current limit resistor (v cc = 5 v) r limit ( ? ) 22 51 75 100 220 trip current (a) 5 3.4 2.98 2.7 2.43 hold current (a) 2.8 1.2 0.84 0.65 0.33 table 3?rise time vs. c dv/dt c dv/dt none 150 pf 470 pf 1 nf rise time (ms, typically) 1.4 5.9 15.5 31.4 * note: rise time(ms) = 0.03ms*c dv/dt (pf)+1.4ms the rise time is measured from 10% to 90% of the output voltage (see figure 2). figure 2?rise time
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 12 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. pcb layout guidelines efficient pcb layout is critical to achieve stable operation. for best results, please refer to figure 3 and follow the guidelines below: 1. place r limit close to the i-limit. 2. place c dv/dt close to dv/dt. 3. place the input capacitor close to vcc. 4. place enough copper area near vcc and source for thermal dissipation. top layer bottom layer figure 3?sample pcb layout design example table 4 shows a design example following the application guidelines for the given specifications: table 4?design example v in 5 v trip current 5 a hold current 2.8 a figure 4 shows the application schematic. the ?typical performance characteristics? section shows the circuit waveforms. for more device applications, please refer to the related evaluation board datasheet.
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch mp5013a rev. 1.0 www.monolithicpower.com 13 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. typical application circuits f mp5013a 10 c4 ns 22 ? r1 c3 c1 c2 10 f ns 1 2 3 4 5 6 7 8 figure 4?typical application schematic
mp5013a ? 5 v, 1 a-5 a progra mmable current limit switch notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp5013a rev.1.0 www.monolithicpower.com 14 6/18/2015 mps proprietary information. patent protect ed. unauthorized photocopy and duplication prohibited. ? 2012 mps. all rights reserved. package information tsot23-8 front view note: 1) all dimensions are in millimeters. 2) package length does not include mold flash, protrusion or gate burr. 3) package width does not include interlead flash or protrusion. 4) lead coplanarity (bottom of leads after forming) shall be 0.10 millimeters max. 5) jedec reference is mo-193, variation ba. 6) drawing is not to scale. 7) pin 1 is lower left pin when reading top mark from left to right, (see example top mark) top view recommended land pattern seating plane side view detail ''a'' see detail ''a'' iaaaa pin 1 id see note 7 example top mark

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