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fn6832 rev 1.00 page 1 of 11 may 16, 2011 fn6832 rev 1.00 may 16, 2011 isl9016 150ma dual ldo with low noise, high psrr, and low i q datasheet isl9016 is a high performance dual ldo capable of providing up to 150ma current on each channel. it features a low standby current and very high psrr and is stable with output capacitance of 1f to 4.7f with an esr of up to 200m . the device integrates a separate enable function for each output. the quiescent current is typically 49a when only one ldo is enabled and typically 80a when both ldos are enabled. when both ldos are under shutdown condition, the drawing current is typically less than 1a. isl9016 provides a wide input voltage range from 1.8v to 6.5v. it also has a high psrr of 80db at 1khz and 45db at 1mhz. isl9016 also provides output current limit, overheat protection, reverse current protection, as well as excellent load transient response. isl9016 is offered in a tiny 1.6mmx1.6mm 6 ld tdfn package. output voltage options are available from 1.2v to 3.3v. several combinations of voltage outputs are standard and others may be available upon request. features ? dual integrated 150ma high performance ldos ? high psrr: 80db @ 1khz and 45db @ 1mhz ? reverse current protection ?low quiescent current - 49a (single ldo enabled) /80a (dual ldos enabled) ? excellent load transient response ? typically 0.8% output voltage accuracy ? low output noise: typically 25v rms ? wide input voltage capability: 1.8v to 6.5v ? low dropout voltage: typically 120mv @ 150ma ? separate enable control for each ldo ? stable with 1f to 4.7f ceramic output capacitors ? soft-start to limit input current surge during enable ? current limit and overheat protection ? tiny 6 ld 1.6mmx1.6mm tdfn package ? pb-free (rohs compliant) applications ? pdas, cell phones and smart phones ? portable instruments, mp3/4 players, pmp, dsc ? handheld devices including medical handhelds vin gnd en2 en1 vout2 vout1 on off on off c1 c2 c3 c1, c2, c3: 1f, x5r (or x7r) ceramic capacitor r1, r2: 100k r1 r2 isl9016 vin (1.8v to 6.5v) vout1 1.2v~3.3v, 0~150ma vout2 1.2v~3.3v, 0~150ma figure 1. typical application diagram
isl9016 fn6832 rev 1.00 page 2 of 11 may 16, 2011 pin configuration isl9016 (6 ld 1.6x1.6 tdfn) top view 1 2 3 6 4 5 vin gnd en2 vout1 vout2 en1 pin descriptions pin # pin name description 1 vin supply voltage/ldo input. connect a 1f capacitor to gnd. 2 gnd gnd is the connection to system ground. connect to pcb ground plane. 3 en2 ldo2 enable pin. enable = high, disable = low. a 100k resi stor should be connected between en2 and the control voltage rail . do not leave it floating. 4 en1 ldo1 enable pin. enable = high, disable = low. a 100k resi stor should be connected between en1 and the control voltage rail . do not leave it floating. 5vout2 ldo2 output. connect capacitor with a value from 1f to 4.7f to gnd (1f recommended). 6 vout1 ldo1 output. connect capacitor with a valu e from 1f to 4.7f to gnd (1f recommended). - e-pad connect the e-pad to the system ground.
isl9016 fn6832 rev 1.00 page 3 of 11 may 16, 2011 ordering information part number (notes 1, 3) part marking vo1 voltage (v) (note 2) vo2 voltage (v) (note 2) temp range (c) package (pb-free) pkg dwg. # isl9016iruwcz-t n7 1.2 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruwgz-t n6 1.2 2.7 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruwjz-t n2 1.2 2.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruwkz-t n1 1.2 2.85 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irubwz-t r7 1.5 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irubbz-t r6 1.5 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irucwz-t r5 1.8 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irucbz-t r4 1.8 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruccz-t u7 1.8 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irufwz-t r3 2.5 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irufbz-t n8 2.5 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irufcz-t n9 2.5 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruffz-t p0 2.5 2.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irugwz-t p1 2.7 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irugcz-t r2 2.7 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruggz-t n3 2.7 2.7 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irujwz-t p2 2.8 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irujbz-t p3 2.8 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a ISL9016IRUJCZ-T n4 2.8 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irujjz-t n0 2.8 2.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irukwz-t p5 2.85 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irukfz-t p4 2.85 2.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irukkz-t n5 2.85 2.85 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irumwz-t p6 3.0 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irumbz-t p7 3.0 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irumcz-t p8 3.0 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irumkz-t p9 3.0 2.85 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016irunwz-t r0 3.3 1.2 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9016iruncz-t r1 3.3 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a notes: 1. please refer to tb347 for details on reel specifications. 2. for other output voltages, contact intersil marketing or local sales office. 3. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and tin bismuth plate - e6 termination finish, which is rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that meet or ex ceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl9016 . for more information on msl please see techbrief tb363 .
isl9016 fn6832 rev 1.00 page 4 of 11 may 16, 2011 absolute maximum rating s thermal information v in to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.1v all other pins to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in +0.3)v recommended operating conditions supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 6.5v each ldo load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . up to 150ma ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance ? ja (c/w) 6 ld tdfn package (note 5) . . . . . . . . . . . . . . . . . . . . 117.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c operating temperature range . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. electrical specifications typical specifications are measured at the following conditions: t a = +25c; v in = (v o + 0.5v) to 6.5v with a minimum v in of 1.8v; c in = 1f; c o = 1f. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 8) typ max (note 8) units dc characteristics supply voltage v in 1.8 6.5 v uvlo threshold v uv+ 1.710 1.775 v v uv- 1.55 1.62 input quiescent current quiescent condition: i o1 = 0a; i o2 = 0a i dd1 one ldo active 49 67 a i dd2 both ldo active 80 100 a shutdown current i dds @ +25c 0.1 1.0 a regulation voltage accuracy v in = v o + 0.5v to 6.5v, i o = 10a to 150ma, t a = +25 c -0.8 +0.8 % v in = v o + 0.5v to 6.5v, i o = 10a to 150ma, t a = -40 c to +85c -1.8 +1.8 % maximum output current i max each ldo, continuous 150 ma internal current limit i lim 175 265 355 ma dropout voltage (note 6) v do1 i o = 150ma; 1.2v ? v o ? 2.1v 250 425 mv v do2 i o = 150ma; 2.1v ? v o ? 2.8v 200 325 mv v do3 i o = 150ma; 2.8v ? v o 120 200 mv thermal shutdown temperature t sd+ 145 c t sd- 110 c ac characteristics ripple rejection i o = 10ma, v in = 3.7v(min), v o = 2.7v, t a = +25 c @ 1khz 80 db @ 10khz 60 db @ 100khz 50 db @ 1mhz 45 db output noise voltage v in = 4.2v, i o = 10ma, t a = +25 c, bw = 10hz to 100khz 25 v rms device start-up characteristics device enable time t en time from assertion of the enx pin to when the output voltage reaches 95% of the v o (nom) 400 600 s ldo soft-start ramp rate t ssr slope of linear portion of ldo output voltage ramp during start-up 30 60 s/v
isl9016 fn6832 rev 1.00 page 5 of 11 may 16, 2011 en pin characteristics input low voltage v il t a = -20c to +85 -0.3 0.4 v input high voltage v ih 1.1 v in + 0.3 v input leakage current i il , i ih 0.1 a reverse current characteristics output reverse leakage current (note 7) i orlc v in = 0v, v out = 5.5v 8 15 a notes: 6. v o x = 0.98*v o x(nom); valid for vox greater than 1.80v. 7. output reverse leakage current is measured with vin pin grounded and vout pin connected to 5.5v. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications typical specifications are measured at the following conditions: t a = +25c; v in = (v o + 0.5v) to 6.5v with a minimum v in of 1.8v; c in = 1f; c o = 1f. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 8) typ max (note 8) units
isl9016 fn6832 rev 1.00 page 6 of 11 may 16, 2011 typical operating performance figure 2. quiescent current vs input voltage (v out1 =2.1v, only ldo1 enabled) figure 3. quiescent current vs input voltage (v out2 =2.1v, only ldo2 enabled) figure 4. quiescent current vs input voltage (v out1 =v out2 = 2.1v, ldo1 and ldo2 enabled) figure 5. quiescent current vs input voltage (v out1 =3.3v, only ldo1 enabled) figure 6. quiescent current vs input voltage (v out2 =3.3v, only ldo2 enabled) figure 7. quiescent current vs input voltage (v out1 =v out2 = 3.3v, ldo1 and ldo2 enabled) 30 35 40 45 50 55 2.4 3.6 4.8 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c 30 35 40 45 50 55 2.4 3.6 4.8 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c 60 65 70 75 80 85 2.4 3.6 4.8 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c 30 35 40 45 50 55 3.6 4.4 5.2 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c 30 35 40 45 50 55 3.6 4.4 5.2 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c 60 65 70 75 80 85 3.6 4.4 5.2 6.0 input voltage (v) quiescent current (a) t = +85c t = +50c t = +25c t = 0c t = -25c t = -40c
isl9016 fn6832 rev 1.00 page 7 of 11 may 16, 2011 figure 8. ? v out vs input voltage (v out_nominal =1.2v, i out = 50ma) figure 9. ? v out vs input voltage (v out_nominal =1.2v, i out = 150ma) figure 10. load regulation (v in = 1.8v, v out = 1.2v) figure 11. load regulation (v in = 4.5v, v out = 3.3v) figure 12. enable operation (v in = 3.6v, v out1 = v out1 = 1.2v) figure 13. load transient response (v in = 3.6v, v out1 = v out2 = 1.2v, i out1 0.01ma to 150ma) typical operating performance (continued) -15 -10 -5 0 5 10 15 1.5 3.0 4.5 6.0 input voltage (v) ? v o (mv) t = +85c t = +25c t = -40c -20 -15 -10 -5 0 5 10 1.5 2.5 3.5 4.5 5.5 input voltage (v) ? v o (mv) t = +85c t = +25c t = -40c 1.18 1.19 1.20 1.21 1.22 0 30 60 90 120 150 load current (ma) output voltage (v) t = +85c t = +25c t = -40c 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 0 30 60 90 120 150 load current (ma) output voltage (v) t = +85c t = +25c t = -40c 5v/div en1 = en2 1v/div 1v/div v out1 v out2 100s/div 5v/div 50mv/div 50mv/div 200ma/div v out2 (ac coupled) v out1 (ac coupled) i out1 v in 1ms/div
isl9016 fn6832 rev 1.00 page 8 of 11 may 16, 2011 figure 14. load transient response (v in = 3.6v, v out1 = v out2 = 1.2v, i out2 0.01ma to 150ma) figure 15. load transient response (v in = 3.6v, v out1 = v out2 = 3.3v, i out1 0.01ma to 150ma) figure 16. load transient response (v in = 1.8v, v out1 = v out2 = 1.2v, i out1 0.01ma to 150ma) figure 17. load transient response (v in = 3.3v, v out1 = v out2 = 1.2v, i out1 0.01ma to 150ma) typical operating performance (continued) v out2 (ac coupled) v out1 (ac coupled) i out1 v in 5v/div 50mv/div 50mv/div 200ma/div 1ms/div 1ms/div v out2 (ac coupled) v out1 (ac coupled) i out1 v in 5v/div 50mv/div 50mv/div 200ma/div 1ms/div v out2 (ac coupled) v out1 (ac coupled) i out1 50mv/div 20mv/div 100ma/div 1ms/div di/dt = 150ma/s v out (ac coupled) i out 100mv/div 100ma/div 1ms/div di/dt = 150ma/s
isl9016 fn6832 rev 1.00 page 9 of 11 may 16, 2011 block diagram functional description isl9016 contains two high performance ldo?s. high performance is achieved through a circuit which delivers fast transient response to varying load conditions. in a quiescent condition, the isl9016 adjusts its biasing to achieve the lowest standby current consumption. the device also integrates current limit protection, thermal shutdown protection, reverse current protection and soft-start. thermal shutdown protects the device against overheating. soft-start limits the start-up inpu t current surges. in some certain application circuits, the output vo ltage may be externally held up, meanwhile, the input voltage could be connected to ground, or connected to some voltage lower than the output side, or be left open circuit. isl9016 features th e reverse current protection; it can limit the current flow from output to input. this protection will automatically initiate when v out is detected to be higher than v in . when v in is pulled to ground and v out is held at 5.5v, the current flow from v out to v in is typically less than 8a. enable control the isl9016 has two separate enable pins, en1 and en2, which independently enable/disable each of the ldo outputs. when both en1 and en2 are low, the whole device is in shutdown mode. in this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1ma. when one or both the en pins go high, the ldo1 and/or ldo2 will be enabled accordingly based on the voltage signal applied on its related en pin and start from the soft-start. likewise, when one or both en pins go low, ldo1 and/or ldo2 will be disabled based on the signal applied on its related en pin. a 100k (or above) pull-up resistor should be connected between enx pin and the external control voltage (as shown in the ?typical application diagram? on page 1). ldo protections isl9016 offers several protections which make it ideal for using in battery-powered application circuits. isl9016 provides short-circuit protection by limiting the output current to typical 265ma. when sh ort circuit happens, the circuit is limited at 265ma (typical). if th e short circuit lasts long enough, the die temperature increases, and the over-temperature protection circuit will turn off the output. when the die temperature reaches about +145c, the thermal protection starts working. under the overheat condition, only the ldo sourcing more than 50ma w ill be shut off. this does not affect the operation of the other ldo. if both ldos source more than 50ma and an overheat condition occurs, both ldo outputs will be disabled. once the die temperature falls back to about +110c, the disabled ldo(s) are re-enabled and soft-start automatically takes place. in certain applications, the followi ng input/output situations may occur, with output voltage externa lly held up higher than the input voltage: 1. input is pulled to ground; 2. input is left open circuit; and 3. input is pulled to some intermediate voltage isl9016 provides the reverse current protection to limit the current flow from output to input under these situations. when input is pulled to ground and output is held to 5.5v, the typical reverse current from output to input side is less than 8a. control logic short circuit thermal protection soft-start undervoltage lockout bandgap temp-sensor reference voltages vref1 vref2 vref3 vout1 en1 + vin vin en1 en2 vout2 vout1 gnd vref1 reverse current protection ldo-2 ldo-1
fn6832 rev 1.00 page 10 of 11 may 16, 2011 isl9016 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2011. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. input and output capacitors the isl9016 provides a linear regulator that has low quiescent current, fast transient response, and overall stability across the recommended operating conditions. a ceramic capacitor (x5r or x7r) with a capacitance of 1f to 4.7f with an esr up to 200m is suitable for the isl9016 to maintain its output stability. the ground connection of the output capacitor should be connected directly to the gnd pin of the device, and also placed close to the device. similarly for the input ca pacitor, usually a 1f ceramic capacitor (x5r or x7r) is suitable for most cases, but if large, fast rising-time load transient condition is expected, a higher value input capacitor may be necessary to achieve better performance. board layout recommendations a good pcb layout will be an important step to achieve good performance. it is recommended to design the board with separate ground planes for input and output, and connect both ground planes at the gnd pin of the device. consideration should be taken when placing the components and route the trace to minimize the ground impedance, as well as keep the parasitic inductance low. usually the inpu t/output capacitors should be placed close to the device with good ground connection. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl9016 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change april 26, 2011 fn6832.1 added isl9016iruccz -t to ordering information table. january 22, 2009 fn6832.0 initial release.
isl9016 fn6832 rev 1.00 page 11 of 11 may 16, 2011 ultra thin dual flat no-l ead plastic package (utdfn) b d a e 0.15 c 2x pin 1 top view 0.15 c 2x reference detail a 0.10 c 0.08 c 6x a3 c seating plane l e 46 31 bottom view side view 0.10 cab b6x detail a 0.127 +0.058 a1 a1 a 0.1270.008 64 13 m co.2 1.00 ref d2 dap size 1.30 x 0.76 e2 -0.008 terminal thickness 0.30 1.00 0.45 0.50 0.25 1.25 2.00 1.00 land pattern 6 l6.1.6x1.6a 6 lead ultra thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 - d 1.55 1.60 1.65 4 d2 0.40 0.45 0.50 - e 1.55 1.60 1.65 4 e2 0.95 1.00 1.05 - e 0.50 bsc - l 0.25 0.30 0.35 - rev. 1 6/06 notes: 1. dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length/package width are considered as special characteristics. 5. jedec reference mo-229. 6. for additional information, to assist with the pcb land patte rn design effort, see intersil technical brief tb389.

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