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ultrafast sige voltage comparators data sheet adcmp580 / adcmp581 / adcmp582 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2005C2016 analog devices, inc. all rights reserved. technical support www.analog.com features 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 ghz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (dj) 200 fs random jitter (rj) ?2 v to +3 v input range with +5 v/?5 v supplies on-chip terminations at both input pins resistor-programmable hysteresis differential latch control power supply rejection > 70 db applications automatic test equipment (ate) high speed instrumentation pulse spectroscopy medical imaging and diagnostics high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry clock and data signal restoration functional block diagram v p noninverting input v tp termination v cci v cco v ee v ee v tn termination v n inverting input le input hys q output q output le input adcmp580/ adcmp581/ adcmp582 cml/ecl/ pecl 04672-001 figure 1. general description the adcmp580 / adcmp581 / adcmp582 are ultrafast voltage comparators fabricated on the analog devices, inc. proprietary xfcb3 silicon germanium (sige) bipolar process. the adcmp580 features cml output drivers, the adcmp581 features reduced swing ecl (negative ecl) output drivers, and the adcmp582 features reduced swing pecl (positive ecl) output drivers. all three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 gbps operation with 200 fs random jitter (rj). overdrive and slew rate dispersion are typically less than 15 ps. the 5 v power supplies enable a wide ?2 v to +3 v input range with logic levels referenced to the cml/necl/pecl outputs. the inputs have 50 on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. the cml output stage is designed to directly drive 400 mv into 50 transmission lines terminated to ground. the necl output stages are designed to directly drive 400 mv into 50 terminated to ?2 v. the pecl output stages are designed to directly drive 400 mv into 50 terminated to v cco ? 2 v. high speed latch and programmable hysteresis are also provided. the differential latch input controls are also 50 terminated to an independent v tt pin to interface to either cml or ecl or to pecl logic. the adcmp580 / adcmp581 / adcmp582 are available in a 16-lead lfcsp.
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 2 of 16 table of cont ents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 timing information ......................................................................... 5 absolute maximum ratings ............................................................ 6 thermal considerations .............................................................. 6 esd ca ution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 typical application circuits .......................................................... 11 applications information .............................................................. 12 power/ground layout and bypassing ..................................... 12 adcmp580/adcmp581/adcmp582 family of output stages ............................................................................................ 12 using/disabling the latch feature ........................................... 12 optimizing high speed performance ..................................... 13 comparator propagation delay dispersion ............................... 13 comparator hysteresis .............................................................. 14 minimum input slew rate requirement ................................ 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 4 /16 rev. a to rev. b deleted figure 4; renumbered sequentially ................................. 7 changes to figure 3 and table 4 ..................................................... 7 ch anges to figure 4 .......................................................................... 8 added table 5; renumbered sequentially .................................... 8 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14 8/07 rev. 0 to rev. a changes to figure 1 .......................................................................... 1 changes to table 4 ............................................................................ 7 changes to figure 9 .......................................................................... 8 changes to figure 21 , figure 22 , and figure 23 ......................... 10 changes to using/disabling the latch feature .......................... 11 changes to comparator hysteresis section and figure 29 ....... 13 changes to ordering guide .......................................................... 14 7/05 revision 0: initial version
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 3 of 16 specifications v cci = 5.0 v; v ee = ? 5.0 v; v cco = 3.3 v; t a = 25c, unless otherwise noted. table 1 . parameter symbol test condition s/comments min typ max unit dc input characteristics input voltage range v p , v n ? 2.0 +3.0 v input differential range ? 2.0 +2.0 v input offset voltage v os ? 10.0 4 +10.0 mv offset voltage temperature coefficient v os /d t 10 v/c input bias current i p , i n open termination 15 30.0 a input bias current temperature coefficient i b /d t 50 na/c input offset current + 2 5.0 a input resistance 47 to 53 input resistance, differential mode open termination 50 k input resistance, common mode open termination 500 k active gain a v 48 db common - mode rejection ratio cmrr v cm = ? 2.0 v to +3.0 v 60 db hysteresis r hys = 1 mv latch enable characteristics latch enable input impedance z in each pin, v tt at ac ground 47 to 53 latch -to - output delay t ploh , t plol v od = 200 mv 175 ps latch minimum pulse width t pl v od = 200 mv 100 ps adcmp580 (cml) latch enable input range ? 0.8 0 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 95 ps latch hold time t h v od = 200 mv ?90 ps adcmp581 (necl) latch enable input range ? 1.8 +0.8 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 70 ps latch hold time t h v od = 200 mv ?65 ps adcmp582 (pecl) latch enable input range v cco ? 1.8 v cco ? 0.8 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 200 mv 30 ps latch hold time t h v od = 200 mv ?25 ps dc output characteristics adcmp580 (cml) output impedance z out 50 output voltage high level v oh 50 to gnd ? 0.10 0 + 0.03 v output voltage low level v ol 50 to gnd ? 0.50 ? 0.40 ? 0.35 v output voltage differential 50 to gnd 340 395 450 mv adcmp581 (necl) output voltage high level v oh 50 to ?2 v, t a = 125c ?0.99 ?0.87 ?0.75 v output voltage high level v oh 50 to ?2 v, t a = 25c ?1.06 ?0.94 ?0.82 v output voltage high level v oh 50 to ?2 v, t a = ?55c ?1.11 ?0.99 ?0.87 v output voltage low level v ol 50 to ?2 v, t a = 125 c ?1.43 ?1.26 ?1.13 v output voltage low level v ol 50 to ?2 v, t a = 25 c ?1.50 ?1.33 ?1.20 v output voltage low level v ol 50 to ?2 v, t a = ?55 c ?1.55 ?1.38 ?1.25 v output voltage differential 50 to ?2.0 v 340 395 450 mv
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 4 of 16 parameter symbol test condition s/comments min typ max unit adcmp582 (pecl) v cco = 3.3 v output voltage high level v oh 50 to v cco ? 2 v, t a = 125c v cco ? 0.99 v cco ? 0.87 v cco ? 0.75 v output voltage high level v oh 50 to v cco ? 2 v, t a = 25c v cco ? 1.06 v cco ? 0.94 v cco ? 0.82 v output voltage high level v oh 50 to v cco ? 2 v, t a = ?55c v cco ? 1.11 v cco ? 0.99 v cco ? 0.87 v output voltage low level v ol 50 to v cco ? 2 v, t a = 125 c v cco ? 1.43 v cco ? 1.26 v cco ? 1.13 v output voltage low level v ol 50 to v cco ? 2 v, t a = 25 c v cco ? 1.50 v cco ? 1.33 v cco ? 1.20 v output voltage low level v ol 50 to v cco ? 2 v, t a = ?55 c v cco ? 1.55 v cco ? 1.35 v cco ? 1.25 v output voltage differential 50 to v cco ? 2.0 v 340 395 450 mv ac performance propagation delay t pd v od = 500 mv 180 ps propagation delay temperature coefficient t pd /d t 0.25 ps/c propagation delay skew rising transition to falling transition v od = 500 mv, 5 v/ns 10 ps overdrive dispersion 50 mv < v od < 1.0 v 10 ps 10 mv < v od < 200 mv 15 ps slew rate dispersion 2 v/ns to 10 v/ns 15 ps pulse width dispersion 100 ps to 5 ns 15 ps duty cycle dispersion 5% to 95% 1.0 v/ns, 15 mhz, v cm = 0.0 v 10 ps common - mode dispersion v od = 0.2 v , ? 2 v < v cm < 3 v 5 ps/v equivalent input bandwidth 1 bw eq 0.0 v to 400 mv input , t r = t f = 25 ps, 20/80 8 ghz toggle rate >50% output swing 12.5 gbps deterministic jitter dj v od = 500 mv, 5 v/ns , prbs 31 ? 1 nrz, 5 gbps 15 ps deterministic jitter dj v od = 200 mv, 5 v/ns , prbs 31 ? 1 nrz, 10 gbps 25 ps rms random jitter rj v od = 200 mv, 5 v/ns, 1.25 ghz 0.2 ps minimum pulse width pw min t pd < 5 ps 100 ps minimum pulse width pw min t pd < 10 ps 80 ps rise/fall time t r, t f 20/80 37 ps power supply positive supply voltage v cci +4.5 +5.0 +5.5 v negative supply voltage v ee ? 5.5 ? 5.0 ? 4.5 v adcmp580 (cml) positive supply current i vcci v cci = 5.0 v, 50 to gnd 6 8 ma negative supply current i vee v ee = ? 5.0 v , 50 to gnd ?50 ?40 ?34 ma power dissipation p d 50 to gnd 230 260 mw adcmp581 (necl) positive supply current i vcci v cci = 5.0 v, 50 to ? 2 v 6 8 ma negative supply current i vee v ee = ? 5.0 v, 50 to ? 2 v ?35 ?25 ?19 ma power dissipation p d 50 to ? 2 v 155 200 mw adcmp582 (pecl) logic supply voltage v cco +2.5 +3.3 +5.0 v input supply current i vcci v cci = 5.0 v, 50 to v cco ? 2 v 6 8 ma output supply current i vcco v cco = 5.0 v, 50 to v cco ? 2 v 44 55 ma negative supply current i vee v ee = ? 5.0 v, 50 to v cco ? 2 v ?35 ?25 ?19 ma power dissipation p d 50 to v cco ? 2 v 310 350 mw power supply rejection ( v cci ) psr vcci v cci = 5.0 v + 5% ?75 db power supply rejection ( v ee ) psr vee v ee = ?5.0 v + 5% ?60 db power supply rejection ( v cco ) psr vcco v cco = 3.3 v + 5% ( adcmp582 ) ?75 db 1 equivalent input bandwidth assumes a simple first - order input response and is calculated with the following formula: bw eq = 0.22/( tr comp 2 C tr in 2 ), where tr in is the 20/80 transition time of a quasi - gaussian input edge applied to the comparator input and t r comp is the effective transition time digitized by the comparator.
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 5 of 16 timing information figure 2 shows the adcmp580 / adcmp581 / adcmp582 compare and latch timing relationships. table 2 provides the definitions of the terms shown in figure 2 . 50% 50% v n v os 50% differentia l input vo lt age la tch enable q output q output la tch enable t h t pd l t pdh t ploh t plo l t r t f v n v od t s t pl 04672-002 figure 2 . comparator timing diagram table 2 . timing descriptions mbol mbol description timing description t pdh input - to - output high delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low -to - high transition. t pdl input -to - output low delay propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high -to - low transition. t ploh latch enable -to - output high delay propagation delay measured from the 50% point of the latch enable signal low -to - high transition to the 50% point of an output low -to - high transition. t plol latch enable -to - output low delay propagation delay measured from the 50% point of the latch enable signal low -to - high transition to the 50% point of an output high -to - low transition. t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. t pl minimum latch enable pulse width minimu m time that the latch enable signal must be high to acquire an input signal change. t s minimum setup time minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% p oints. v n normal input voltage difference between the input voltages v p and v n for output true. v od voltage overdrive difference between the input voltages v p and v n for output false.
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 6 of 16 absolute maximum rat ings table 3 . parameter rating supply voltages positive supply voltage (v cci to gnd) ? 0.5 v to +6.0 v negative supply voltage (v ee to gnd) C 6.0 v to +0.5 v logic supply voltage (v cco to gnd) ? 0.5 v to +6.0 v input voltages input voltage ? 3.0 v to +4.0 v differential input voltage ? 2 v to +2 v input voltage, latch enable ? 2.5 v to +5.5 v hysteresis control pin applied voltage (hys to v ee ) ? 5.5 v to +0.5 v maximum input/output current 1 ma output current adcmp580 (cml) ? 25 ma adcmp581 (necl) ? 40 ma adcmp582 (pecl) ? 40 ma temperature operating temperature range , ambient ? 40c to +125c operating temperature, junction 125c storage temperature range ? 65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliabilit y. thermal consideratio ns the adcmp580 / adcmp581 / adcmp582 16 - lead lfcsp option has a juncti o n - to - ambient thermal resistance ( ja ) of 70c/w in still air. esd caution
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 7 of 16 pin configurations a nd function descript ions q le v tp v p v n v tn q gnd gnd v cci le v tt gnd v cci hys v ee 04672-003 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 adcmp580/ adcmp581 t op view notes 1. the metallic back surface of the package is not electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. figure 3. adcmp580 / adcmp581 pin configuration table 4 . adcmp580 / adcmp581 pin function descriptions pin no. mnemonic description 1 v tp termination resistor return pin for v p input. 2 v p noninverting analog input. 3 v n inverting analog input. 4 v tn termination resistor return pin for v n input. 5, 16 v cci positive supply voltage. 6 le latch enable input pin, inverting side. in compare mode ( le = low), the output tracks changes at the input of the comparator. in latch mode ( le = high), the output reflects the input state just prior to the comparator being placed into latch mode. le must be driven in complement with le. 7 le latch enable input pin, noninverting side. in compare mode (le = high), the output tracks changes at the input of the comparator. in latch mode (le = low), the output reflects the input state just prior to the comparator being pla ced into latch mode. le must be driven in complement with le . 8 v tt termination return pin for the le/ le input pins. for the adcmp580 (cml output stage), this pin must be connected to ground . for the adcmp581 (ecl output stage), connect this pin to the C 2 v termination potential. 9, 12 gnd digital ground pin/positive logic power supply terminal. t his pin must be connected to the gnd pin. 10 q inverting output. q is logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided that the comparator is in compare mode. see the le/ le descriptions (pin 6 to pin 7) for more information. 11 q noninverting output. q is logic high if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided that the compara tor is in compare mode. see the l e/ le descriptions (pin 6 to pin 7) for more information. 13 v ee negative power supply. 14 hys hysteresis control. leave this pin disconnected for zero hysteresis. connect this pin to the v ee supply with a suitably sized resistor to add the desired amount of hysteresis. refer to figure 8 for proper sizing of the hys hysteresis control resistor. 15 gnd anal og ground. epad exposed pad. the metallic back surface of the package is not electrically connected to any part of the circuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 8 of 16 q le v tp v p v n v tn q v cco v cco v cci le v tt gnd v cci hys v ee 04672-004 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 adcmp582 t op view notes 1. the me t allic back sur f ace of the p ackage is not electrical l y connected t o an y p art of the circui t . it can be left flo a ting for optima l electrica l isol a tion between the p ackage handle and the substr a te of the die. it can also be soldered t o the applic a tion board if improved therma l and/or mechanica l s t abilit y is desired. figure 4. adcmp582 pin configuration table 5 . adcmp58 2 pin function descriptions pin o. mnemonic description 1 v tp termination resistor return pin for v p input. 2 v p noninverting analog input. 3 v n inverting analog input. 4 v tn termination resistor return pin for v n input. 5, 16 v cci positive supply voltage. 6 le latch enable input pin, inverting side. in compare mode ( le = low), the output tracks changes at the input of the comparator. in latch mode ( le = high), the output reflects the input state just prior to the comparator being placed into latch mode. le must be driven in complement with le. 7 le latch enable input pin, noninverting side. in compare mode (le = high), the output tracks changes at the input of the comparator. in latch mode (le = low), the output reflects the input state just prior to the c omparator being placed into latch mode. le must be driven in complement with le . 8 v tt termination return pin for the le/ le input pins. for the adcmp582 (pecl output stage), connect this pin to the v cco C 2 v termination potential. 9, 12 v cco digital ground pin/positive logic power supply terminal. t his pin must be connected to the positive logic power v cco supply. 10 q inverting output. q is logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided that the comparator is in compare mode. see the le/ le descriptions (pin 6 to pin 7) for more information. 11 q noninverting output. q is logic high if the analog voltage at the noninverting input, v p , is greater than the an alog voltage at the inverting input, v n , provided that the compara tor is in compare mode. see the le/ le descriptions (pin 6 to pin 7) for more information. 13 v ee negative power supply. 14 hys hysteresis control. leave this pin disconnected for zero hysteresis. connect this pin to the v ee supply with a suitably sized resistor to add the desired amount of hysteresis. refer to figure 8 for proper sizing of the hys hysteresis control resistor. 15 gnd analog ground. epad exposed pad. the metallic back surface of the package is not electrically connected to any part of the c ircuit. it can be left floating for optimal electrical isolation between the package handle and the substrate of the die. it can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 9 of 16 typical performance characteristics v cci = 5.0 v, v ee = ?5.0 v, v cco = 3.3 v, t a = 25c, unless otherwise noted. 12 0 ?4 4 common-mode (v) bias current (a) 10 8 6 4 2 ?2 0 2 v in common-mode bias swee p 04672-006 figure 5 . bias current vs. common - mode voltage ?0.8 ?1.5 ?55 145 temper a ture (c) output (v) ?0.9 ?1.0 ?1.1 ?1.2 ?1.3 ?1.4 ?5 45 95 v ol vs. temper a ture output (necl) v oh vs. temper a ture output (necl) 04672-007 figure 6. adcmp581 output voltage vs. temperature 80 0 0 600 ?ihyst (a) hysteresis (mv) 70 60 50 40 30 20 10 100 200 300 400 500 04672-008 figure 7 . hysteresis vs. ihyst 80 0 1 10k r hys contro l resis t or (?) hysteresis (mv) 70 60 50 40 30 20 10 10 100 1k 04672-009 figure 8 . hysteresis vs. r hys control resistor 2.5 1.9 ?55 145 temper a ture (c) output (v) 2.4 2.3 2.2 2.1 2.0 ?5 45 95 v oh vs. temper a ture output (pecl) v ol vs. temper a ture output (pecl) 04672-010 figure 9. adcmp582 output voltage vs. temperature 8 0 ?2 4 common-mode (v) offset (mv) 7 6 5 4 3 1 2 0 2 +25c common-mode offset swee p ?55c common-mode offset swee p +125c common-mode offset swee p 04672-011 figure 10 . a typical v os vs. common - mode voltage
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 10 of 16 5 ?5 ?2 3 v cm (v) pro p ag a tion del a y error (ps) 4 3 2 1 0 ?1 ?2 ?3 ?4 ?1 0 1 2 lot2 char1 rise lot2 char1 f al l lot3 char1 rise lot3 char1 f al l 04672-012 figure 11 . adcmp580 prop a gation delay error vs. common - mode voltage m1 04672-013 m1 figure 12 . adcmp580 eye diagram at 7.5 gbps 18 0 0 250 overdrive (mv) dispersion (ps) 16 14 12 10 8 6 4 2 50 100 150 200 od dispersion rise od dispersion f al l 04672-014 figure 13 . dispersion vs. overdrive 45 25 ?55 125 temper a ture (c) t r / t f (ps) 43 41 39 37 35 33 31 27 29 ?35 ?15 5 25 45 65 85 105 q rise q rise q fall q fall 04672-015 figure 14 . adcmp581 t r / t f vs. temperature m1 500mv 500mv 20ps/div 04672-016 m1 figure 15 . adcmp582 eye diagram at 2.5 gbps
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 11 of 16 typical application circuits q adcmp580 q v in v p v tp v tn v n la tch inputs 50 ? 50 ? gnd 04672-017 figure 16 . zero - crossing detector with cml outputs on the adcmp580 q adcmp581 q v p v n v tt v p v t p v tn v n l a tch inputs 50 ? 50 ? 04672-018 figure 17 . lvds to a 50 back - terminated (rs) ecl receiver on the adcmp581 hys v ee 50 ? 50 ? adcmp580 0? t o 5k ? 04672-019 figure 18 . adding hysteresis using the hys control on the adcmp580 50 ? 50 ? + ? q q v in v th la tch inputs gnd adcmp580 04672-020 figure 19 . comparator with 2 to +3 v input range on the adcmp580 v p v n v ee adcmp580 50 ? 1k ? 50 ? cm l 04672-021 figure 20 . disabling the latch feature on the adcmp580 v p v n adcmp581 v tt v ee 50 ? 50 ? 750 ? rsec l v tt = ?2v 04672-022 figure 21 . disabling the latch feature on the adcmp581 v p v n v tt = v cco ? 2v v cco adcmp582 50 ? 750 ? 50 ? rspec l 04672-023 figure 22 . disabling the latch feature on the adcmp582
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 12 of 16 application s information power/ground layout and bypassing the adcmp580 / adcmp581 / adcmp582 family of comparators is designed for very high speed applications. consequently, high speed design techniques must be used to achieve the specified performance. it is critically important to use low imped ance supply planes, particularly for the negative supply (v ee ), the output supply plane (v cco ), and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. provid ing the lowest inductance return path for the switchi ng currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. a 1 f electrolytic bypass capacitor must be placed within several inches of each power supply pin to grou nd. in addition, multiple high quality 0.1 f bypass capacitors must be placed as close as possible to each of the v ee , v cci , and v cco supply pins and must be connected to the gnd plane with redundant vias. high frequency bypass capacitors must be carefully selected for minimum inductance and esr. parasitic layout inductance must be strictly avoided to maximize the effectiveness of the bypass at high frequencies. adcmp580 / adcmp581 / adcmp582 family of output stages specified propagation delay dispersion performance is achieved by using p roper transmission line terminations. the outputs of the adcmp580 family comparators are designed to directly drive 400 m v into 50 ? cable or microstrip/stripline transmis - sion lines terminated with 50 ? referenced to the proper return. the cml output stage for the adcmp580 is shown in the simplified schematic diagram in figure 23 . each output is back - terminated with 50 ? fo r best transmission line matching. the outputs of the adcmp581 / adcmp582 are illustrated in figure 24 ; they must be terminated to ?2 v for e cl outputs of adcmp581 and v cco ? 2 v for pecl o utputs of adcmp582 . as an alter native, thevenin equivalent termination networks can also be used. if these high speed signals must be routed more than a centimeter, either microstrip or stripline techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width - dependent propagation delay dispersion. q 16m a 50 ? 50 ? q gnd v ee 04672-024 figure 23 . simplified schematic diagram of the adcmp580 cml output stage gnd/v cco v ee q q 04672-025 figure 24 . simplified schematic diagram of the adcmp581 / adcmp582 ecl/pecl output stage using/disabling the latch feature the latch inputs (le/ le ) are active low for latch mode and are internally terminated with 50 ? resistors to the v tt pin. when using the adcmp580 , v tt must be connected to ground. when using the adcmp581 , v tt must be connected to ?2 v. when using the adcmp582 , v tt must be connected externally to v cco ? 2 v, preferably with its own low inductance plane. when using the adcmp580 , the latch function can be disabled by connecting the le pin to v ee with an external pull - down resistor and by leaving the le pin to g roun d . to prevent excessive power dissipa tion, the resistor must be 1 k? for the adcmp580 . when using the adcmp581 comparators, the latch can be disabled by connecting the le pin to v ee with an external 7 50 ? resistor and leaving the le pin connected to ? 2 v. the idea is to create an approximate 0.5 v offset using the internal resistor a s half of the voltage divider. connect the v tt pin as recommended.
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 13 of 16 optimizing high speed performance as with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance. for applications in a 50 environment, input and output matching have a significant impact on data-dependent (or deterministic) jitter (dj) and pulse width dispersion performance. the adcmp580 / adcmp581 / adcmp582 family of comparators provides internal 50 termination resistors for both v p and v n inputs. the return side for each termination is pinned out separately with the v tp and v tn pins, respectively. if a 50 termination is desired at one or both of the v p /v n inputs, the v tp and v tn pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. the termination potential must be carefully bypassed using ceramic capacitors as discussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. if a 50 termination is not desired, either one or both of the v tp /v tn termination pins can be left disconnected. in this case, the open pins must be left floating with no external pull downs or bypassing capacitors. for applications that require high speed operation but do not have on-chip 50 termination resistors, some reflections must be expected, because the comparator inputs can no longer provide matched impedance to the input trace leading up to the device. it then becomes important to back-match the drive source impedance to the input transmission path leading to the input to minimize multiple reflections. for applications in which the comparator is less than 1 cm from the driving signal source, the source impedance must be minimized. high source impedance in combination with parasitic input capacitance of the comparator could cause undesirable degradation in bandwidth at the input, thus degrading the overall response. it is therefore recommended that the drive source impedance be no more than 50 for best high speed performance. comparator propagation delay dispersion the adcmp580 / adcmp581 / adcmp582 family of comparators has been specifically designed to reduce propagation delay dis- persion over a wide input overdrive range of 5 mv to 500 mv. propagation delay dispersion is a change in propagation delays that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). the overall result is a higher degree of timing accuracy. propagation delay dispersion is a specification that becomes important in critical timing applications, such as data commu- nications, automatic test and measurement, instrumentation, and event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (see figure 25 and figure 26). for the adcmp580 / adcmp581 / adcmp582 family of comparators, dispersion is typically <25 ps, because the overdrive varies from 5 mv to 500 mv, and the input slew rate varies from 1 v/ns to 10 v/ns. this specification applies for both positive and negative signals because the adcmp580 / adcmp581 / adcmp582 family of comparators has almost equal delays for positive- and negative-going inputs. q/q output input voltage 500mv overdriv e 5mv overdrive dispersion v n v os 04672-026 figure 25. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 0 4672-027 figure 26. propagation delayslew rate dispersion
adcmp580/adcmp58 1/adcmp582 data sheet rev. b | page 14 of 16 comparator hysteresi s adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. the transfer function for a comparator with hystere - sis is shown in figure 27 . if the input voltage approaches the threshold from the negative direction, the comparator switches from a low to a high when the input crosses +v h /2. the new switching threshold becomes ? v h /2 . the comparator remains in the high state until the threshold ? v h /2 is crossed from the positive direction. in this manner, noise centered on 0 v input does not cause the comparator to switch states unless it exceeds the region bounded by v h /2. the custo mary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. a limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not sy mmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and can even reduce overall stability in some cases. output input 0v 0 1 +v h 2 ?v h 2 04672-028 figure 27 . comparator hysteresis transfer function the adcmp580 / adcmp581 / adcmp582 family of comparators offers a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. by connecting an external pull - down resistor from the hys pin to v ee , a variable amount of hysteres is can be applied. leaving the hys pin disconnected disables the feature, and hysteresis is then less than 1 mv, as specified. the maximum range of hysteresis that can be applied by using this method is approximately 70 m v. figure 28 illustrates the amount of applied hysteresis as a function of the external resistor value. the advantage of applying hysteresis in this manner is improved accuracy, stability, and reduced component count. an external bypass capacitor is not required on the hys pin , and it would likely degrade the jitter performance of the device. the hysteresis pin can also be driven by a current source. it is biased approximately 400 mv above v ee and has an internal series resistance of approximately 600 ?. 80 0 1 10k r hys contro l resis t or (?) com p ar a t or hysteresis (mv) 70 60 50 40 30 20 10 10 100 1k 04672-029 figure 28 . comparator hysteresis vs. r hys control resistor minimum input slew r ate requirement as with many high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. this oscil - lation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. a minimum slew rate of 50 v/s must ensure clean output transitions from the adcmp580 / adcmp581 / adcmp582 family of comparators. the slew rate may be too slow for other reasons. the extremely high bandwidth of these devices means that broadband noise ca n be a significant factor when input slew rates are low. there is 120 v of thermal noise generated over the bandwidth of the comparator by the two 50 terminations at room temperature. with a slew rate of only 50 v/ s, the inputs are inside this noise ba nd for over 2 ps, rendering the comparators jitter performance of 200 fs irrelevant. raising the slew rate of the input signal and/or reducing the bandwidth over which that resistance is seen at the input can greatly reduce jitter. devices are not charact erize d this way but simply bypassing a reference input close to the package can reduce jitter 30% in low slew rate applications.
data sheet adcmp580/adcmp581/adcmp582 rev. b | page 15 of 16 outline dimensions 1.45 1.30 sq 1.15 111808-a 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 3.10 3.00 sq 2.90 0.50 0.40 0.30 se a ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 0.30 0.23 0.18 compliant to jedec standards mo-220-weed. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 figure 29 . 16 - lead lead f rame chip scale package [lfcsp ] 3 mm 3 mm body and 0.75 mm package height (cp - 16 - 21 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adcmp580bcpz -wp ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g12 adcmp580bcpz -r2 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g12 adcmp580bcpz - rl7 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g12 adcmp581bcp z -wp ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g 11 adcmp581bcp z -r2 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g 11 adcmp581bcp z - rl7 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g 11 adcmp582bcpz -wp ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g10 adcmp582bcpz -r2 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g10 adcmp582bcpz - rl7 ?40c to +125c 16 - lead lead f rame chip scale package [lfcsp ] cp -16 -21 g10 eval - adcmp580bcp z evaluation board eval - adcmp581bcp z evaluation board eval - adcmp582bcp z evaluation board 1 z = rohs compliant part.
adcmp580/adcmp581/adcmp582 data sheet rev. b | page 16 of 16 notes ? 2005 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04672 - 0- 4/16(b)

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