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silego technology, inc. rev 1.09 000-0046400-109 revised june 3, 2015 greenpak 2 tm rev. b programmable mixed signal array SLG46400 block diagram features ? logic & mixed signal circuits ? highly versatile macro cells ? read back protection (read lock) ? 1.8v (5%) to 5v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? pb-free tdfn-12 2.5mm x 2.5mm package applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gpio gpio gpio gpio gpio gpio 2 3 4 9 10 11 12 gpi vdd 1 thermal pad connected to gnd tdfn-12 (top view) gpio gpio 5 6 gnd gpio 7 8 pin1 vdd pin2 input pin3 i/o pin4 i/o pin10 i/o pin11 i/o pin9 i/o pin12 i/o non-volatile memory sar adc acmp0 por vref pfd acmp1 rc osc programmable delay pipe delay slave spi/s2p pin5 i/o pin6 i/o pin8 i/o pin7 gnd digital comparator with pwm dcmp0 dcmp1 dcmp2 look-up tables 2-bit lut0 2-bit lut1 3-bit lut0 3-bit lut1 3-bit lut2 3-bit lut3 4-bit lut0 2-bit lut2 2-bit lut3 3-bit lut4 3-bit lut5 counter/delay generators cnt/dly0 cnt/dly1 cnt/dly2 cnt/dly3 d flip-flops/ latches dff0 dff1 dff2 dff3 ext_vref_in int_vref_out
000-0046400-109 SLG46400 table of contents 1.0 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 functional pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 programming pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.0 user programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 absolute maximum conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 electrical characteristics (1.8v 5% vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.3 electrical characteristics (3.3v 10% vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.4 electrical characteristics (5v 10% vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.0 summary of macro cell function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 i/o pins (10 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 analog comparators (2 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 voltage reference out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.6 digital comparators or pwm (3 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.7 delays/counters (4 total). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.8 programmable delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.9 pipe delay output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.10 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.11 slave spi/s2p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.12 combinatorial logic luts (11 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.13 digital storage elements (4 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.14 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.0 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 input modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.1 open drain output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.2 push pull with output enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.3 analog input and open drain output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.4 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.5 digital bi-directional input / output pin by configuring settings . . . . . . . . . 12 7.2.6 creating a digital bi-directional input / output pin using an oe signal . . . . 12 7.3 pull up/down resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
000-0046400-109 SLG46400 7.4 i/o pins register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.1 pin 2 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.2 pin 3 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.3 pin 4 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4.4 pin 5 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4.5 pin 6 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4.6 pin 8 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4.7 pin 9 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4.8 pin 10 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4.9 pin 11 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.10 pin 12 register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.0 connection matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1 connection matrix register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.0 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 adc functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 adc operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.3 adc 3-bit programmable gain amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4 adc 2-channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5 adc input voltage definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.6 adc reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.7 adc power down select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.8 adc clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.9 adc outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.9.1 adc serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.9.2 adc parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.10 adc interrupt output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.11 adc register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.0 analog comparator (acmp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.1 acmp0 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2 acmp0 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.3 acmp1 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.4 acmp1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.5 acmp output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.6 acmp 1ua input current option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.7 acmp low bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.8 acmp frequency bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.9 acmp hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.10 acmp0 & acmp1 register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.10.1 acmp0 register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
000-0046400-109 SLG46400 10.10.2 acmp1 register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.0 voltage reference out (vref out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.1 vref output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2 vref sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.3 vref functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.4 vref register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.0 digital comparator (dcmp) / pulse width modulator (pwm) . . . . . . . . . . . . . . . 35 12.1 dcmp input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.2 dcmp output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.3 pwm input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.4 pwm output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.5 dcmp0/pwm0 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.6 dcmp1/pwm1 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.7 dcmp2/pwm2 functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.8 pwm dead band control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.9 pwm dead band control timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.10 dcmp/pwm power down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.11 dcmp/pwm clock invert control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.12 dcmp/pwm register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.0 counters/delay generators (cnt/dly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.1 counter functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.2 cnt2 and cnt3 reset source select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.3 counters functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.4 counter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.5 cnt0/dly0 and cnt1/dly1 register settings . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.6 cnt2/dly2 and cnt3/dly3 register settings . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.7 cnt2 as a finite state machine (fsm0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.8 fsm0 (cnt2) functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.9 cnt3 as a finite state machine (fsm1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.10 fsm1 (cnt3) functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.11 fsm register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.12 delay cell functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.13 delay cells functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.14 delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.0 programmable delay (pdly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.1 programmable delay functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.2 vdd vs. typical time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
000-0046400-109 SLG46400 14.3 programmable delay register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.0 pipe delay (pd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15.1 pipe delay functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.2 pipe delay register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16.0 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.1 clock management functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.2 rc osc power down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.3 rc osc dividers control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.4 ring oscillator and external clock from pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.5 rc osc frequency selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 16.6 rc osc register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.0 slave spi - serial to parallel / parallel to serial converter (s2p) . . . . . . . . . . . . 55 17.1 s2p functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.2 serial to parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.3 serial to parallel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.4 parallel to serial operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.5 parallel to serial timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17.6 s2p notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17.7 s2p register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18.0 combinatorial logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.1 2-bit lut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.2 3-bit lut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18.3 4-bit lut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 19.0 digital storage elements (dffs/latches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19.1 dff/latch functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19.2 dff/latch selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.3 dff/latch register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.0 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.1 por register settings description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 20.2 por register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 21.0 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21.1 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21.2 combinatorial logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21.3 example: bi-directional pin using an oe signal . . . . . . . . . . . . . . . . . . . . . . . . . 67 22.0 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 22.1 software & hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 22.1.1 greenpak 2 designer?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
000-0046400-109 SLG46400 22.1.2 greenpak 2 programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 22.1.3 minimum system requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 22.2 development kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 22.3 project examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 23.0 package top marking system definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24.0 package drawing and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.1 12 lead tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.2 tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 24.3 carrier tape drawing and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25.0 recommended reflow soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 26.0 appendix - SLG46400 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 27.0 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 28.0 silego website & support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.1 silego technology website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.2 silego technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.2.1 contact your local sales representative . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.2.2 contact silego directly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 28.3 other information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
000-0046400-109 page 1 of 89 SLG46400 1.0 overview the SLG46400 provides a small, low power component for common ly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logi c, the i/o pins and the macro cells of the SLG46400. this highly versat ile device allows a wide variety of mixed- signal functions to be designed within a ver y small, low power single integrated circuit. the macro cells in the device include the following: ? 8-bit successive approximation register analog to digital converter (sar adc) ? power-on reset device (por) ? voltage reference (v ref ) ? rc oscillator (rc osc) ? 4 counter/delay generators (cnt/dly) ? 4 d flip-flop/latches (dff) ? 3 digital comparators (dcmp) or pulse width modulator (pwm) ? 2 analog comparators (acmp) ? 11 combinatorial look-up tables (lut) ? slave spi ? configurable i/o pins (open drain, push-pull, schmitt trigger input, low voltage digital input and analog i/o) ? delay (20ns/40ns/60ns/80ns) ? pipe delay the specific functions that can be designed using the SLG46400 include: ? power-on-rese t generators ? signal delay elements ? one-shot detection ? voltage level detectors ? voltage level-shift circuits ? battery charge controller ? led lighting control ? fan controller ? optical encoder ? level shifters ? hall effect driver ? signal de-glitches the pwm and adc macro cells also support more complex control circuits such as fan speed c ontrollers, stepper motor control - lers and interface to a wide variety of sensor devices. traditi onally these devices were designed from combinations of low complexity logic and discrete devices requiring costly board sp ace while having complex testing strategies. silego?s SLG46400 allows the functionality of these circuits to be fully tested before being mounted onto a pcb ? greatly simplifying the system design and testing procedures.
000-0046400-109 page 2 of 89 SLG46400 2.0 pin description 2.1 functional pin description 2.2 programming pin description pin # pin name function 1 vdd 1.8v to 5v supply 2 gpi general input 3 gpio general io or analog comparator 0 input 4 gpio general io or analog comparator 1 input 5 gpio general io or external clock of osc, adc, and s2p 6gpio general io or serial output data of adc and serial input/output data of s2p 7gndgnd 8 gpio general io or positive input of adc 9 gpio general io or negative input of adc 10 gpio general io or v ref output 11 gpio general io or v ref input 12 gpio general io or single-ended mode adc input selection exposed bottom pad gnd gnd pin # pin name programming description 1vddvdd 2 gpi vpp 3gpioreset 4gpion/a 5gpion/a 6gpion/a 7gndgnd 8 gpio program mode control 9gpiodie id 10 gpio nvm read mode output data 11 gpio nvm write mode input data 12 gpio nvm clock
000-0046400-109 page 3 of 89 SLG46400 3.0 user programmability the SLG46400 is a user programmable device with one-time-pro grammable (otp) memory elements that are able to construct combinatorial logic elements. three of the i/o pins provide a connection for the bit patterns into the otp on board memory. a programming development kit allows the user the ability to creat e initial devices. once the design is finalized, the programmin g code (.gp2 file) is forwarded to silego to integrate into a production process. figure 1. steps to create a custom silego greenpak device
000-0046400-109 page 4 of 89 SLG46400 4.0 ordering information part number type SLG46400v tdfn-12 SLG46400vtr tdfn-12 - tape and reel (3k units)
000-0046400-109 page 5 of 89 SLG46400 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical characteristics (1.8v 5% v dd ) parameter min. max. unit v high to gnd -0.3 7 v voltage at input pin -0.3 7 v current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 6000 -- v esd protection (charged device model) 1300 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.8 1.89 v i q quiescent current static inputs and outputs -- -- 1 a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.5 7.75 v v air analog input voltage range adc v ref 0--1.0v acmp negative input 0 -- 1.0 v v ih high-level input voltage logic input 1.1 -- -- v logic input with schmitt trigger 1.35 -- -- v low-level logic input 1.1 -- -- v v il low-level input voltage logic input -- -- 0.65 v logic input with schmitt trigger -- -- 0.45 v low-level logic input -- -- 0.50 v i ih high-level input current logic input pins; v in =1.8v -1.0 -- 1.0 a i il low-level input current logic input pins; v in =0v -1.0 -- 1.0 a v oh high-level output voltage push-pull, i oh = 100 a, 1x drive 1.66 -- -- v push-pull, i oh = 700 a, 1x drive 1.21 -- -- v push-pull, i oh = 1ma, 2x drive 1.42 -- -- v push-pull, i oh = 100 a, 2x drive 1.68 -- -- v push-pull, i oh = 700 a, 2x drive 1.53 -- -- v v ol low-level output voltage push-pull, i ol = 100 a, 1x drive -- -- 0.040 v push-pull, i ol = 700 a, 1x drive -- -- 0.415 v push-pull, i ol = 1ma, 2x drive -- -- 0.245 v push-pull, i ol = 100 a, 2x drive -- -- 0.020 v push-pull, i ol = 700 a, 2x drive -- -- 0.155 v open drain, i ol = 5ma, 1x drive -- -- 0.340 v open drain, i ol = 5ma, 2x drive -- -- 0.138 v
000-0046400-109 page 6 of 89 SLG46400 1. if startup time lower than 7 ms is requ ired, please contact silego regarding a pot ential custom mixed-signal ic with a reduce d startup time for your design. i ol low-level output current push-pull, v ol = 0.15v, 1x drive 0.34 -- -- ma push-pull, v ol = 0.15v, 2x drive 0.68 -- -- ma open drain, v ol = 0.15v, 1x drive 2.72 -- -- ma open drain, v ol = 0.15v, 2x drive 5.44 -- -- ma t su startup time after vdd reaches 1.4-1.6v level -- 7 1 -- ms symbol parameter condition/note min. typ. max. unit
000-0046400-109 page 7 of 89 SLG46400 5.3 electrical characteristics (3.3v 10% v dd ) 1. if startup time lower than 7 ms is requ ired, please contact silego regarding a pot ential custom mixed-signal ic with a reduce d startup time for your design. symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i q quiescent current static inputs and outputs -- -- 1 a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.5 7.75 v v air analog input voltage range adc 0 -- 1.0 v acmp 0 -- 1.5 v v ih high-level input voltage logic input 1.8 -- -- v logic input with schmitt trigger 2.3 -- -- v low-level logic input 1.5 -- -- v v il low-level input voltage logic input -- -- 1.10 v logic input with schmitt trigger -- -- 0.92 v low-level logic input -- -- 0.66 v i ih high-level input current logic input pins; v in =3.3v -1.0 -- 1.0 a i il low-level input current logic input pins; v in =0v -1.0 -- 1.0 a v oh high-level output voltage push-pull, i oh = 3ma, 1x drive 2.1 -- -- v push-pull, i oh = 3ma, 2x drive 2.6 -- -- v v ol low-level output voltage push-pull, i ol = 3ma, 1x drive -- -- 0.81 v push-pull, i ol = 3ma, 2x drive -- -- 0.32 v open drain, i ol = 20ma, 1x drive -- -- 0.605 v open drain, i ol = 20ma, 2x drive -- -- 0.252 v i ol low-level output current push-pull, v ol = 0.4v, 1x drive 1.836 -- -- ma push-pull, v ol = 0.4v, 2x drive 3.672 -- -- ma open drain, v ol = 0.4v, 1x drive 14.688 -- -- ma open drain, v ol = 0.4v, 2x drive 29.376 -- -- ma t su startup time after vdd reaches 1.4-1.6v level -- 7 1 -- ms
000-0046400-109 page 8 of 89 SLG46400 5.4 electrical characteristics (5v 10% v dd ) 1. if startup time lower than 7 ms is requ ired, please contact silego regarding a pot ential custom mixed-signal ic with a reduce d startup time for your design. symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5 5.5 v i q quiescent current static inputs and outputs -- -- 1 a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.5 7.75 v v air analog input voltage range adc 0 -- 1.0 v acmp 0 -- 1.5 v v ih high-level input voltage logic input 2.6 -- -- v logic input with schmitt trigger 3.2 -- -- v low-level logic input 1.7 -- -- v v il low-level input voltage logic input -- -- 1.7 v logic input with schmitt trigger -- -- 1.3 v low-level logic input -- -- 0.77 v i ih high-level input current logic input pins; v in =5v -1.0 -- 1.0 a i il low-level input current logic input pins; v in =0v -1.0 -- 1.0 a v oh high-level output voltage push-pull, i oh = 5ma, 1x drive 3.6 -- -- v push-pull, i oh = 8ma, 1x drive 2.9 -- -- v push-pull, i oh = 5ma, 2x drive 4.1 -- -- v push-pull, i oh = 8ma, 2x drive 3.8 -- -- v v ol low-level output voltage push-pull, i ol = 5ma, 1x drive -- -- 0.85 v push-pull, i ol = 8ma, 1x drive -- -- 1.20 v push-pull, i ol = 5ma, 2x drive -- -- 0.36 v push-pull, i ol = 8ma, 2x drive -- -- 0.63 v open drain, i ol = 20ma, 1x drive -- -- 0.36 v open drain, i ol = 20ma, 2x drive -- -- 0.17 v i ol low-level output current push-pull, v ol = 0.4v, 1x drive 2.745 -- -- ma push-pull, v ol = 0.4v, 2x drive 5.490 -- -- ma open drain, v ol = 0.4v, 1x drive 21.960 -- -- ma open drain, v ol = 0.4v, 2x drive 43.920 -- -- ma t su startup time after vdd reaches 1.4-1.6v level -- 7 1 -- ms
000-0046400-109 page 9 of 89 SLG46400 6.0 summary of macro cell function 6.1 i/o pins (10 total) ? digital input (low voltage or normal voltage, with or withou t schmitt trigger) ? open drain ?push pull ? analog i/o ? 50k/100k/300k pull-up/pull-down resistors 6.2 connection matrix ? digital matrix for circuit connections based on user design 6.3 analog to digital converter ? 8-bit, 10khz, successive ap proximation register adc ? dnl < 1lsb, inl < 1lsb ?v in range: 0 ~ 1v ? common mode voltage range: v pp /2 ~ v dd /2 ? 3-bit programmable gain amplifier with gain values of (1, 2, 4, 8,16x in differential mode and 0. 5, 1, 2, 4, 8x in single-ende d mode) ? spi output format 6.4 analog comparators (2 total) ? 0mv/12mv/50mv/150mv hysteresis 6.5 voltage reference out ? provides an external voltage based on either acmp0 reference or v dd /3 6.6 digital comparators or pwm (3 total) ? three 8-bit 10mhz pwms or digital comparators 6.7 delays/counters (4 total) ? delay time range: 1-16384 clock cycles (clock cycle based on rc oscillator or external clock input) ? three 14-bit delays/counte rs: range 1-16384 clock cycles ? one 8-bit delay/counter: range 1-255 clock cycles ? two counters can function as fsm counters 6.8 programmable delay ? 20ns/40ns/60ns/80ns 6.9 pipe delay output ?1 pipe ? 2/4/8/12 pipes ? 3/5/7/11 pipes 6.10 rc oscillator ? 16 frequencies ranging from 27khz ? 10mhz
000-0046400-109 page 10 of 89 SLG46400 6.11 slave spi/s2p ? supports slave spi to control dcmp/pwm/fsm counter ? adc spi output 6.12 combinatorial logic luts (11 total) ? used to create either standard or custom digital logic cells ? four 2-bit lookup tables ? six 3-bit lookup tables ? one 4-bit lookup table 6.13 digital storage elements (4 total) ? four d flip-flops or latches 6.14 power on reset ?v dd >1.6v
000-0046400-109 page 11 of 89 SLG46400 7.0 i/o pins the SLG46400 has a total of 10 mu lti-function i/o pins which can function as either a user defined input or output as well as serve as a programmable function for the one time no n-volatile memory to configure interconnect logic. normal mode pin definition is as follows: ? pin 2: input pin only ? pin 3: gpio or input for analog comparator 0 ? pin 4: gpio or input for analog comparator 1 ? pin 5: gpio or external clock input for adc, rc osc and s2p ? pin 6: gpio or adc serial output data, s2p input/output data (reg<712:711>) ? pin 8: gpio or adc in+ ? pin 9: gpio or adc in- ? pin 10: gpio or v ref output ? pin 11: gpio or v ref input ? pin 12: gpio or single-ended mode adc channel selection programming mode pin definition is as follows: ? pin 2: voltage for programming power (7.5v needed) ? pin 3: program reset ? pin 8: program mode control ? pin 9: die id ? pin 10: nvm read mode output data ? pin 11: nvm write mode input data ? pin 12: nvm clock of the ten user defined i/o pins in the SLG46400, nine pins (pin s 3, 4, 5, 6, 8, 9, 10, 11, and 12) can be used for either inpu t or output and one pin (pin 2) is defined as input only. 7.1 input modes each input pin can be configured as a digital input with/without buffered schmitt trigger, low voltage digital in (1.5v), or an alog in to control the user signals that are inputted into the SLG46400. all digital input pins will either have a logic ?1? or ?0? value inputted into the SLG46400, based on the configurat ion of the input pin which is defined by the user. figure 2. i/o pads layout pad (pin 2) pad (pins3,4,5,6,8, 9, 10, 11, 12) ext. in ext. in/out pin 2 pins 3, 4, 5, 6, 8, 9,10, 11, 12 out out digital data to SLG46400 in oe digital data to SLG46400 or digital data from SLG46400 or analog data from pin10 push-pull output enable for pins 4, 5, 6, 10, 11, 12 from matrix (for pins 3, 8, and 9, oe is controlled from reg instead of from matrix) analog data to pins 3, 4, 8, 9, 11
000-0046400-109 page 12 of 89 SLG46400 7.2 output modes pins 3, 4, 5, 6, 8, 9, 10, 11 and 12 can be configured as ei ther an open drain output or push -pull output (with output enable). additionally pin 10 can be also be configured as an analog output in the SLG46400 device. the oe functionality for each of the output pins is controlled by the connection matrix except for pins 3, 8, and 9. those pins are controlled by the following registers: reg<685> for pin3 reg<547> for pin8 reg<556> for pin9 7.2.1 open drain output the open drain output setting has a 1x current ratio. the open drain output signal from the SLG46400 design will decide the port?s output state (hi-z or ground). if the signal = 1, output will be hi-z (high impedance) if the signal = 0, output will be connected to ground pins 6 and 12 have a 2x current sinking option where the current value depends on v dd . 7.2.2 push pull with output enable the push pull with output enable setting has either a 1x or 2x current ratio and the output en able signal will make the output hi-z all output pins have push pull 2x current si nking option where the cu rrent value depends on v dd . with 1x option these currents will be one half the value of the 2x value. 7.2.3 analog input and open drain output pins 3, 4, 8, 9, and 11, can be configur ed as analog inputs/open drain outputs on th is device. using this configuration will ma ke the pin bi-directional, but the output will be open drain. this means that a logic lo w state on the pin will cause both the out put and the input to go low. 7.2.4 analog output analog output functionality is only availabl e on pin 10 and is configured via the v ref cell analog output = internal signal value 7.2.5 digital bi-directional input / output pin by configuring settings pin 4, pin 5, pin 6, pin 10, pi n 11, and pin 12 can be configured as a bi-direc tional pins by configuring the analog input and open drain output settings in the greenpak ii designer tool. this is done by going to the pin?s propertly menu in the greenpak ii designer software and changing the mo de setting to ?analog in/out and open drain?. 7.2.6 creating a digital bi-directional input / output pin using an oe signal the pins can also be configured as digital bi-directional input / output pins using an external output enable signal with the following steps:
000-0046400-109 page 13 of 89 SLG46400 1. configure the i/o pins as one of the following: a. digital input with schmitt trigger b. digital input without schmitt trigger c. low voltage digital input 2. use a control signal for the output enable on the i/o pin 3. the i/o pin will function as push pull 1x current by setting the oe signal of the pin to high. 7.3 pull up/down resistors all 10 i/o pins have the option of a 50k/ 100k/300k pull up/down resistor. resistors can be used with any of the input or output pin configurations previously defined.
000-0046400-109 page 14 of 89 SLG46400 7.4 i/o pins register settings 7.4.1 pin 2 register settings 7.4.2 pin 3 register settings table 1. pin 2 register settings signal function register bit address register definition pin 2 mode control <673:672> 00: digital in with schmitt trigger 01: digital in without schmitt trigger 10: low voltage digital in 11: reserved pin 2 pull up/down resistor value selection <675:674> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 2 pull up/down resistor <676> 0: pull down resistor 1: pull up resistor pin 2 reset enable <808> 0: disable 1: enable pin 2 edge detect mode <807> 0: rising edge 1: falling edge note: n/a of reset enable signal is ?0? pin 2 bypass <806> 0: pin 2 edge active 1: pin 2 high active note: n/a of reset enable signal is ?0? table 2. pin 3 register settings signal function register bit address register definition pin 3 initial state control <678:677> 00: output floating 01: output ground 10: output power 11: output follow input pin 3 mode control <681:679> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: 1x current open drain 110: analog input & open drain mode 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 3 pull up/down resistor value selection <683:682> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 3 pull up/down resistor <684> 0: pull down resistor 1: pull up resistor pin 3 push pull output enable <685> 0: push pull output disable 1: push pull output enable
000-0046400-109 page 15 of 89 SLG46400 7.4.3 pin 4 register settings 7.4.4 pin 5 register settings table 3. pin 4 register settings signal function register bit address register definition pin 4 initial state control <687:686> 00: output floating 01: output ground 10: output power 11: output follow input pin 4 mode control <690:688> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: analog input & open drain mode 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 4 pull up/down resistor value selection <692:691> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 4 pull up/down resistor <693> 0: pull down resistor 1: pull up resistor table 4. pin 5 register settings signal function register bit address register definition pin 5 initial state control <695:694> 00: output floating 01: output ground 10: output power 11: output follow input pin 5 mode control <698:696> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: reserved 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: reserved 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 5 pull up/down resistor value selection <700:699> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 5 pull up/down resistor <701> 0: pull down resistor 1: pull up resistor
000-0046400-109 page 16 of 89 SLG46400 7.4.5 pin 6 register settings 7.4.6 pin 8 register settings table 5. pin 6 register settings signal function register bit address register definition pin 6 initial state control <703:702> 00: output floating 01: output ground 10: output power 11: output follow input pin 6 mode control <706:704> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: reserved 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: reserved 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 6 pull up/down resistor value selection <708:707> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 6 pull up/down resistor <709> 0: pull down resistor 1: pull up resistor pin 6 open drain double current <710> 0: normal 1: double current pin6 digital output selection source <712:711> 0x: from connection matrix (out25) 10: from s2p (miso) 11: from adc serial output table 6. pin 8 register settings signal function register bit address register definition pin 8 initial state control <540:539> 00: output floating 01: output ground 10: output power 11: output follow input pin 8 mode control <543:541> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: analog input & open drain mode 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 8 pull up/down resistor value selection <545:544> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 8 pull up/down resistor <546> 0: pull down resistor 1: pull up resistor pin 8 push pull output enable <547> 0: push pull output disable 1: push pull output enable
000-0046400-109 page 17 of 89 SLG46400 7.4.7 pin 9 register settings 7.4.8 pin 10 register settings table 7. pin 9 register settings signal function register bit address register definition pin 9 initial state control <549:548> 00: output floating 01: output ground 10: output power 11: output follow input pin 9 mode control <552:550> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: analog input & open drain mode 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 9 pull up/down resistor value selection <554:553> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 9 pull up/down resistor <555> 0: pull down resistor 1: pull up resistor pin 9 push pull output enable <556> 0: push pull output disable 1: push pull output enable table 8. pin 10 register settings signal function register bit address register definition pin 10 initial state control <558:557> 00: output floating 01: output ground 10: output power 11: output follow input pin 10 mode control <561:559> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: reserved 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 10 pull up/down resistor value selection <563:562> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 10 pull up/down resistor <564> 0: pull down resistor 1: pull up resistor
000-0046400-109 page 18 of 89 SLG46400 7.4.9 pin 11 register settings 7.4.10 pin 12 register settings table 9. pin 11 register settings signal function register bit address register definition pin 11 initial state control <566:565> 00: output floating 01: output ground 10: output power 11: output follow input pin 11 mode control <569:567> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: analog io 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: analog input & open drain mode 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 11 pull up/down resistor value selection <571:570> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 11 pull up/down resistor <572> 0: pull down resistor 1: pull up resistor table 10. pin 12 register settings signal function register bit address register definition pin 12 initial state control <574:573> 00: output floating 01: output ground 10: output power 11: output follow input pin 12 mode control <577:575> 000: digital in with schmitt trigger 001: digital in without schmitt trigger 010: low voltage digital in without schmitt trigger 011: reserved 100: 2x current push pull (oe = 0 then output tristate, oe = 1 output enable) 101: open drain 110: reserved 111: 1x current push pull (oe = 0 then ou tput tristate, oe = 1 output enable) pin 12 pull up/down resistor value selection <579:578> 00: floating 01: 50k resistor 10: 100k resistor 11: 300k resistor pin 12 pull up/down resistor <580> 0: pull down resistor 1: pull up resistor pin 12 2x current open drain mode <581> 0: normal 1: double current
000-0046400-109 page 19 of 89 SLG46400 8.0 connection matrix the connection matrix in the SLG46400 is used to create the inter nal routing for the 832 register bits of the SLG46400 device once it is programmed. the registers ar e programmed from the one-time nvm cell during test mode operation. all of the connection point for each logic cell within the SLG46400 has a specif ic digital bit code assigned to it that is either set to a ctive ?high? or inactive ?low? based on the desi gn that is created. once the 832 register bits within the SLG46400 are programmed a fully custom circuit will be created. for a complete list of the SLG46400?s register table, see appendix a. 8.1 connection matrix register settings table 11. connection matrix register settings register code connection point 000000 ground 000001 lut2_0 output 000010 lut2_1 output 000011 lut2_2 output 000100 lut2_3 output 000101 lut3_0 output 000110 lut3_1 output 000111 lut3_2 output 001000 lut3_3 output 001001 lut3_4 output 001010 lut3_5 output 001011 lut4 output 001100 dff0/latch0 output 001101 dff1/latch1 output 001110 dff2/latch2 output 001111 dff3/latch3 output 010000 pin2 digital output 010001 pin3 digital output 010010 pin4 digital output 010011 pin5 digital output 010100 pin6 digital output 010101 pin8 digital output 010110 pin9 digital output 010111 pin10 digital output 011000 pin11 digital output 011001 pin12 digital output 011010 rc oscillator output 011011 rc oscillator divided by 4 output 011100 rc oscillator divided by 12 output 011101 dly0/cnt0 output 011110 dly1/cnt1 output
000-0046400-109 page 20 of 89 SLG46400 011111 dly2/cnt2 output 100000 dly3/cnt3 output 100001 edge detect output 100010 analog comparator0 output 100011 analog comparator1 output 100100 adc output 100101 digital comparator0 equal output 100110 digital comparator1 equal output 100111 digital comparator2 equal output 101000 pwm/dcmp0 out- output 101001 pwm/dcmp0 out+output 101010 pwm/dcmp1 out- output 101011 pwm/dcmp1 out+output 101100 pwm/dcmp2 out- output 101101 pwm/dcmp2 out+output 101110 reserved 101111 programmable delay output 110000 pipe delay out0 110001 pipe delay out1 110010 power detector output (pwr detect) 110011 1 pipe out 110100 dff0 negative output (nq) 110101 dff1 negative output (nq) 110110 dff2 negative output (nq) 110111 dff3 negative output (nq) 111000 ground 111001 ground 111010 ground 111011 ground 111100 ground 111101 ground 111110 power on reset (out) 111111 vdd table 11. connection matrix register settings register code connection point
000-0046400-109 page 21 of 89 SLG46400 9.0 analog-to-digital converter (adc) the analog to digital converter in the SLG46400 is an 8-bit success ive approximation register analog to digital converter (sar adc) which operates at a maximum sampling speed of 10 khz. the adc?s dnl < 1lsb and inl < 1lsb and has a v bg accuracy of 50mv. user controlled inputs and outputs of the adc are listed below: inputs: ? ch selector: single-ended mode adc selection and analog input mux control signal (pin 12) ? in+: single-ended mode input and differential mode positive input (pin8) ? in-: differential mode negative input (pin 9) ? ext. vref: adc external voltage reference input (pin 11) ? ext. clk: adc external clock input (pin 5) ? shared pd: adc power down signal outputs: ? ext_refout: adc external volt age reference output (pin 10) ? pga_out: output of the pga to acmp0 ? ser data: adc serial output (pin 6) ? par data: 8-bit adc parallel data to either the pwm or dcmp0 ? adc interrupt output (int. out) 9.1 adc functional diagram figure 3. adc functional diagram
000-0046400-109 page 22 of 89 SLG46400 9.2 adc operation modes the adc has three operating modes: ? single-ended adc operation using in+ from pin 8, when adc_sel (reg <742>) is ?0? ? differential adc operation using in+ from pin 8 and in- from pin 9, when adc_sel (reg <742>) is ?1? ? pseudo-differential adc operation using in + from pin 8 and in- from pin 9, when adc_sel (reg <742>) and adc_pseudodiff_en (reg <738>) bits are both set to ?1? 9.3 adc 3-bit progra mmable gain amplifier the front end of the adc is a pga with 3 bits for setting gain. the gain settings range from 0.5x to 16x. the pga buffers the adc in all cases except with the singled ended gain is 0.5x. singl e-ended pga operation has gain sett ings of 0.5, 1, 2, 4, and 8x, while differential operation has gain settings of 1, 2, 4, 8, and 16x. the pga gain is set by the adc_gain_control (reg<718:716>). see adc register settings table for pseudo-differential mode, the pga gain can only be 1x. 9.4 adc 2-channel selection when adc_channel_sel (reg <714>) is set to ?1?, the pga of the adc will sample either pin 8 or pin 9 on the in+ input, where the selection is cont rolled by pin 12. ? when pin 12 is set to ?0?, the adc will sample pin 9 ? when pin 12 is set to ?1?, the adc will sample pin 8 when adc_channel_sel (reg <714>) is set to ?0?, the pga of the adc will sample pin 8 on the in+ input. 9.5 adc input voltage definition the adc?s input voltage (v in_adc ) is calculated based on either the single-ended or differential operation modes the logic cell is set to. in single-ended mode v in_adc is the positive input voltage multiplied by th e gain of the pga. while in differential mode the v in_adc is the difference between the positive and negative input vo ltages multiplied by the gain of the pga plus one half of the reference voltage. figure 4. adc 2-channel selection equation 1. adc input voltage equation 1 0 in+ ch#1 (pin 8) 1 0 reg <714> ch selector (pin 12) logic 1 in+ in+ ch#2 (pin 9)

2 ref gain pga in in gain pga in adc in v g v v g v v _ _ _ single-ended mode differential mode
000-0046400-109 page 23 of 89 SLG46400 9.6 adc reference voltage the adc?s reference voltage (v ref ) is controlled by adc_vref_sel (reg <720:7 19>) and the adc_dac_vref (reg <713>). see the table 12 for reference. for optimal a dc performance, the ext_vref value should no t be greater than 1.0v. the three referenc e voltage inputs are chosen from the following: ? bandgap voltage (v bg ) of 1v or 0.778v from internal source ? 1x or 2x external user defined voltage source (pin 11) ? power divider of (0.25 or 0.5) * v dd 9.7 adc power down select mode the adc?s power down source is selected by reg <815:814> (shared with the pwm and osc). when reg <815:814> = ?01?, the adc power down is controlled by reg <813>, where if reg <813> = ?0 ?, adc is powered down, and if reg <813> = ?1?, adc operates normally. otherwise the adc power down is controlled by the connection matrix output 3 signal where a value of ?1? will drive the adc and the pga to power down mode. the SLG46400 also has a slow/fast power on mode feat ure controlled by reg<715>. when reg<715> = 0, the adc is in slow power on mode and the entire analog block is controlled by connection matrix output 3 . when reg<715> = 1, adc is in fast power on mode, where only the adc will be controlled by connection matrix output 3 and the analog block will remain on. with this feature, the first adc power on (with the rest of the analog block) will be approximatel y 20 s; the next power cycle the adc power on (adc only) time is <1ns. 9.8 adc clock source the adc clock source comes from either the internal rc oscillator (clk4adc/64) or an external clock from pin 5. the selection is made from the adc_clk_sel signal via reg <737> where: ? the rc oscillator is used when the adc_clk_sel is ?0? ? an external clock from pin 5 is used when the adc_clk_sel is ?1? the adc requires 16 clock cycles to sample the analog voltage and output the sampled data. when the internal rc oscillator is used for providing timing to the adc, a total of 1024 clo ck cycles are needed since the clk4adc signal is also divided by 64. figure 5. adc reference voltage bandgap (1v or 0.778v) 1x or 2x ext. vref (pin 11) v dd *(0.25 or 0.5) 10 00 01 reg <720:719> v ref table 12. adc reference voltage. reg 720719 v ref reg 713 0 reg 713 1 00 v bg (1v) v bg (0.778v) 01 2x ext_vref (pin 11) 1x ext_vref (pin 11) 10 power divider (0.5 * v dd ) power divider (0.25 * v dd ) 11 n/a n/a figure 6. adc clock source 1 0 ext. clk (pin 5) clk4adc/64 reg <737> clk
000-0046400-109 page 24 of 89 SLG46400 when an external clock is used on pin5, the adc will only need 16 clock cycles, as it bypasses the divide by 64 logic. 9.9 adc outputs the adc?s output can be shifted out through the s2p logic cell. the ser data produces eight single data bits over eight individual clock cycles when activated, while the par data produces an 8-bit data st ring over 16 clock cycles. 9.9.1 adc serial output the 8-bit serial data can be outputted from the SLG46400 device on pin 6. the individual 8 serial data bits can be read into an external device within the larger system design. to initialize the ser data the adc needs a power down signal, which can be configured through the connection matrix. after 3 adc_clk cycles the adc will start to output the 8-bit serial data. this pd signal needs to be held for at least 16 adc_clk cycles. the adc_clk is determined by either the SLG46400 clock, the rc oscillator/64, or an external clock (from pin 5) divide d by 64. 9.9.2 adc parallel output the 16-bit parallel data can be outputted fr om the adc logic cell to either the dcmp/pw m or fsm logic cells within the SLG46400 device. to initialize the par data the adc needs a power down signal, which can be configured through the connection matrix. after ten adc_clk cycles the adc will start to output the 16-bit parallel data. this pd signal needs to be held for at least 32 adc_c lk cycles. the adc_clk is determined by either the SLG46400 clock, the rc o scillator/64, or an external clock (from pin 5) divided by 64. 9.10 adc interrupt output timing diagram equation 2. adc input voltage equation figure 7. adc interrupt output timing diagram cycles f cycles f f osc osc adc 1024 16 64 = = 16 clk ext adc f f _ = adc using an external clock adc using internal rc oscillator 12345678910111213141516 clk d7 d0 ser data par data 16 cycles shared pd t_adc_startup = 10 s t_out_en = ~100ns ser data par data int. out
000-0046400-109 page 25 of 89 SLG46400 9.11 adc register settings table 13. adc register settings signal name signal function register bit address register definition pin6_dig_out pin 6 digital output source selection <712:711> 00/01: from connection matrix 10: serial data from the s2p/spi 11: serial data from the adc adc_dac_vref adc reference dac feedback select <713> 0: normal 1: 0.5 gain adc_channel_sel adc mux channel selection <714> 0: mux disabled, adc will sample pin 8 for in+ 1: mux enabled, adc will sample either pin 8 or 9 for in+ adc_pdmode_sel adc power down mode selection <715> 0: adc slow power on 1: adc fast power on adc_gain_control adc pga gain control <718:716> 000: single-ended (0.5x gain) or differential (n/a) 001: single-ended (1x gain) or differential (1x gain) 010: single-ended (2x gain) or differential (2x gain) 011: single-ended (4x gain) or differential (4x gain) 100: single-ended (8x gain) or differential (8x gain) 101: single-ended (n/a) or differential (16x gain) adc_vref_sel v ref setting (depends on reg <713>) <720:719> 00: v bg (1v or 0.778v) 01: 1x or 2x external voltage source 10: power divider of v dd * (0.25 or 0.5) adc_pg_en adc input pass gate charge pump enable <735> 0: passgate charge pump off 1: passgate charge pump on adc_clk_sel adc clock selection <737> 0: internal rc oscillator 1: external clock from pin 5 adc_pseudodiff_en adc pseudo differential enable <738> 0: disable 1: enable adc_sel adc mode select <742> 0: single-end operation using pin 8 1: differential mode using pins 8 & 9 dac_in_sel dac input data select <746> 0: adc normal operation 1: dac data comes from fsm1 adc_pd_control adc power down control <813> 0: adc power down 1: adc normal operation adc_pwm_osc_p d_src_sel adc/pwm/osc power down source select <815:814> 00: adc pd from matrix out <3>, pwm pd from register 01: pwm pd from matrix out <3>, adc pd from register 10: adc & pwm pd from matrix out <3> 11: osc pd from matrix out <3>, adc & pwm pd from register
000-0046400-109 page 26 of 89 SLG46400 10.0 analog comparator (acmp) there are two analog comparator (acmp) macro cells in the sl g46400. in order for the acmp cells to be used in a greenpak design the power up signals ( pwr up ) need to be active. these signals should be high to turn on the acmp and low to turn it off and each acmp can be powered seperately. when acmp is powered down, output is low. each of the two acmp cells has a negative input signal that is either created from an internal reference voltage (v ref ) or provided by way of the external sources. 10.1 acmp0 input modes acmp0?s positive input (in+) can be connected to pin3, pi n4, adc/pga out or in by setting reg <735> and by the acmp0_pga_en signal, reg<739>. the negative input (in-) of the acmp0 cell can come from the internal v ref macro cell which will generate a 50mv to 1.5v signal (only when v dd > 3.0v), a 30mv to 1.0v signal, or fr om an external voltage source that is placed on pin 11. selection is made using a 4-bit value from nvm (reg<725:722>) and the v ref band select (reg<736>).
000-0046400-109 page 27 of 89 SLG46400 10.2 acmp0 functional diagram 10.3 acmp1 functional diagram figure 8. acmp0 functional diagram figure 9. acmp1 functional diagram acmp1 reg <730:727> 1 0 pin 4 reg <812> reg <734:733> reg <747> in- in+ pwr up 0000 1111 0001 1110 1101 reg <736> 1x gain 0.5x gain to connection matrix input <35> from connection matrix output <11> reg <726> 0.05v 1.5v 0.1v pin 11 1.3v 0.03v 1.0v 0.07v pin 11 0.87v reg<736>=1 reg<736>=0 1 0 reg <745> dac fsm1 reg <746> (only if v dd >3v) 1 0 adc
000-0046400-109 page 28 of 89 SLG46400 10.4 acmp1 input modes acmp1?s positive input (in+) comes from pin 4 with selection gain of 1x or 0.5x (two 50k resistor divider). the acmp1_0.5gain_en signal (reg<747>) is used as a control signal into a mux which has the 1x and 0.5x signals as inputs. the negative input (in-) of the acmp1 cell can come from the dac or the internal v ref logic cell (selected by reg <745>) which will generate a 50mv to 1.5v signal (only when v dd > 3.0v), a 30mv to 1.0v signal, or fr om a external voltage source that is placed on pin 11 (but not more than v air parameter for correct acmp operation, see section 5.0 electrical specifications ) . selection is made using a 4-bit va lue from nvm, reg<730:727> and the v ref band select (reg<736>). reg <746> selects either the fsm1 or adc as the source of the dac. the maximum acmp output delay is 5 s based on a minimum input difference of 2mv. the acmp output is undefined for 100 s after power up. when the power supply changes its value from higher to lower or vice versa (detect value is around 2.7v), then a special internal block (power regulator) starts up/down and influences v ref . it means that acmp with internal v ref has output glitches if overvoltage is less than 50mv. 10.5 acmp output modes when in+ has a greater voltage than in-, the acmp?s output will be ?1?. ot herwise, that output will be a ?0? signal. the acmp o f the SLG46400 has an offset voltage of 5mv. 10.6 acmp 1ua input current option both acmp?s can source 1 a on their respected inputs. this feature is controlled by the following signals: acmp0_l1u_en, reg<721> for acmp0 acmp1_l1u_en, reg<726> for acmp1 when either of these signals are equal to ?1? the input will source a 1 a current. 10.7 acmp low bandwidth both acmp?s have a low bandwidth enable featur e; this is controlled by the following signals: acmp0_low_bw, reg<811> for acmp0 acmp1_low_bw, reg<812> for acmp1 when either of these signals are equal to ?1? and the input fr equency is more than 200khz, the output retains its last value.
000-0046400-109 page 29 of 89 SLG46400 10.8 acmp frequency bode plot figure 10. acmp frequency bode plot
000-0046400-109 page 30 of 89 SLG46400 10.9 acmp hysteresis both acmp?s have a hysteresis featur e, where either the addition or subtra ction of 12, 50, or 150 mv to the in- signal will change the acmp?s output value. the amount of hysteresis is controlled as shown below: acmp0_hy_en , reg<732:731> when set to ?01? will turn on the 12mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.006v ? output from ?1? becomes ?0? when in+ in- - 0.006v acmp0_hy_en , reg<732:731> when set to ?10? will turn on the 50mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.025v ? output from ?1? becomes ?0? when in+ in- - 0.025v acmp0_hy_en , reg<732:731> when set to ?11? will turn on the 150mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.075v ? output from ?1? becomes ?0? when in+ in- - 0.075v acmp1_hy_en , reg<734:733> when set to ?01? will turn on the 12mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.006v ? output from ?1? becomes ?0? when in+ in- - 0.006v acmp1_hy_en , reg<734:733> when set to ?10? will turn on the 50mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.025v ? output from ?1? becomes ?0? when in+ in- - 0.025v acmp1_hy_en , reg<734:733> when set to ?11? will turn on the 150mv hysteresis, ? output from ?0? becomes ?1? when in+ in- + 0.075v ? output from ?1? becomes ?0? when in+ in- - 0.075v
000-0046400-109 page 31 of 89 SLG46400 10.10 acmp0 & acmp1 register settings 10.10.1 acmp0 register settings table 14. acmp0 register settings signal name signal function register bit address register definition acmp0_l1u_en acmp0 1 a input current option <721> 0: disable 1: enable acmp0_vref_sel when reg<736> = 0 acmp0 in+ voltage select <725:722> 0000: 50mv 1000: 600mv 0001: 100mv 1001: 700mv 0010: 150mv 1010: 800mv 0011: 200mv 1011: 900mv 0100: 250mv 1100: 1100mv 0101: 300mv 1101: 1300mv 0110: 400mv 1110: 1500mv 0111: 500mv 1111: ext_vref (pin 11) acmp0_vref_sel when reg<736> = 1 acmp0 in+ voltage select <725:722> 0000: 30mv 1000: 400mv 0001: 70mv 1001: 470mv 0010: 100mv 1010: 530mv 0011: 130mv 1011: 600mv 0100: 170mv 1100: 730mv 0101: 200mv 1101: 870mv 0110: 270mv 1110: 1000mv 0111: 330mv 1111: ext_vref (pin 11) acmp0_hy_en acmp0 hysteresis enable <732:731> 00: disabled (0mv) 01: enabled (12mv) 10: enabled (50mv) 11: enabled (150mv) acmp_vref_bd_sel acmp v ref band select <736> 0: 50mv to 1.5v range (only if v dd > 3.0v) 1: 30mv to 1.0v range acmp0_analog_io_ pga_en acmp0 in+ source selection <739>, <735> 00: acmp0 in+ input from pin3 01: acmp0 in+ input from pin4 (pin3 analog_io_en should be disabled) 10: acmp0 in+ input from pga out 11: acmp0 in+ input from pga in acmp0_low_bw acmp0 low bandwidth enable <811> 0: disable 1: enable
000-0046400-109 page 32 of 89 SLG46400 10.10.2 acmp1 register settings table 15. acmp1 register settings signal name signal function register bit address register definition acmp1_l1u_en acmp1 1 a input current option <726> 0: disable 1: enable acmp1_vref_sel when reg<736> = 0 acmp0 in+ voltage select <730:727> 0000: 50mv 1000: 600mv 0001: 100mv 1001: 700mv 0010: 150mv 1010: 800mv 0011: 200mv 1011: 900mv 0100: 250mv 1100: 1100mv 0101: 300mv 1101: 1300mv 0110: 400mv 1110: 1500mv 0111: 500mv 1111: ext_vref (pin 11) acmp1_vref_sel when reg<736> = 1 acmp1 in+ voltage select <730:727> 0000: 30mv 1000: 400mv 0001: 70mv 1001: 470mv 0010: 100mv 1010: 530mv 0011: 130mv 1011: 600mv 0100: 170mv 1100: 730mv 0101: 200mv 1101: 870mv 0110: 270mv 1110: 1000mv 0111: 330mv 1111: ext_vref (pin 11) acmp1_hy_en acmp1 hysteresis enable <734:733> 00: disable (0mv) 01: enable (12mv) 10: enable (50mv) 11: enable (150mv) acmp_vref_bd_sel acmp v ref band select <736> 0: 50mv to 1.5v range (only if v dd > 3.0v) 1: 30mv to 1.0v range acmp1_neg_src_s el acmp1 negative source select <745> 0: from v ref 1: from dac output acmp1_dac_src_ sel dac input source select <746> 0: from adc 1: from fsm1 acmp1_pga_en acmp1's 0.5 gain enable <747> 0: disabled (in+ input from pin 4) 1: enabled acmp1_low_bw acmp1 low bandwidth enable <812> 0: disable 1: enable
000-0046400-109 page 33 of 89 SLG46400 11.0 voltage reference out (v ref out) the v ref macro cell supplies an accurate reference voltage for the SLG46400. 11.1 v ref output the output of the v ref cell can be connected to pin 10 as a buffered or non-buffered output. in order to use the v ref cell within the SLG46400, the v ref output enable signal (reg<741>) must be turned on. when the op amp output buffer is enabled through the vrefo_buf_en signal (reg<740>) the pin 10 output voltage reference?s impedance becomes 1k ? . with the op amp buffer switched out, the pi n 10 output voltage reference?s impedance is 100k ? . 11.2 v ref sources the value of v ref can be set to either use v dd /3 as a voltage source or by setting t he acmp0 to provide the desired voltage (50mv to 1.5v or 30mv to 1.0v is selectable). the v ref macro cell uses acmp0?s negative input for the desired reference voltage. 11.3 v ref functional diagram figure 11. v ref functional diagram 1 0 v dd /3 acmp0_vref power on reg <744> reg <725:722> cvref vrefo_sel reg <743> op 1 0 vrefo_buf_en reg <740> reg <741> vrefo_en out pin 10 reg <736>
000-0046400-109 page 34 of 89 SLG46400 11.4 v ref register settings refer to reg <725:722> for possible v ref configurations. table 16. v ref register settings signal name signal function register bit address register definition vrefo_band_sel v ref band select for comparators <736> 0: 50mv to 1.5v 1: 30mv to 1.0v vrefo_buf_en v ref output active buffer control <740> 0: enabled 1: disabled vref_on v ref output enable <741> 0: disabled 1: enabled vrefo_sel v ref output source select <743> 0: acmp0 reference voltage 1: v dd /3
000-0046400-109 page 35 of 89 SLG46400 12.0 digital comparator (dcmp) / pulse width modulator (pwm) the SLG46400 has three 8-bit digital comparator / pulse width mo dulator logic cells. each of these three logic cells can be eit her a digital comparator (dcmp) or a pulse width modulator (pwm) independently of how the other two logic cells are defined. both the dcmp and pwm logic can operate at up to a frequency of 10mhz. the input power for the three logic cells is controlled independently by reg<760> for dcmp0/pwm0, reg<761 > for dcmp1/pwm1 and reg<762> for dcmp2/pwm2. pwm power down control is configured by reg <8 15:814> which is also shared with the adc and osc 12.1 dcmp input modes the three dcmp logic cells have a positive (in+) and a negativ e (in-) input that are compared within the logic cell. the inp signal (connected to the in+ input) takes the value from a 4:1 mux selection between the following signals: ? 8-bit signal from the adc parallel output ? 8-bit signal from the s2p logic cell output (s2p< 15:8> for dcmp0 and dcmp1 or s2p<7:0> for dcmp2) ? 8-bit signal from the fsm0<7:0> ? 8-bit user defined signal value. the inn signal (connected to the in- input) takes the valu e from an 8-bit user defined value for the dcmp operation. 12.2 dcmp output modes the two 8-bit data inputs from in+ and in- are compared within the dcmp logic cells to produce the output and a match signal. ?if inp > inn , both out+ and out signals are equal to ?1?, and eq signal is equal to ?0? ?if inp < inn , both out+ and out signals are equal to ?0?, and eq signal is equal to ?0? ?if inp = inn , both out+ and out signals are equal to ?0?, and eq signal is equal to ?1? both the out+ and eq signals are triggered by the rising or falling edge of the ckosc signal (defined by bit reg <759>). 12.3 pwm input modes in+ for the pwm is an 8-bit data string that can be selected from one of four sources; ? 8-bit signal from the adc parallel output ? 8-bit signal from the s2p logic cell output (s2p< 15:8> for dcmp0 and dcmp1 or s2p<7:0> for dcmp2) ? 8-bit signal from the fsm0<7:0> ? 8-bit user defined signal value. in-?s 8-bit data string for all pwms is sourced from an 8-bit signal from cnt/dly1.
000-0046400-109 page 36 of 89 SLG46400 12.4 pwm output modes the output ( out+ ) duty cycle can be set to either count down to 0% or count up to 100% and each pwm is independently controlled by the value of reg<758> (pwm0), reg<818> (pwm1) , and reg<819> (pwm2). when both inputs are equal the output signal ( eq ) will go high. the outputs ( out- and out+ ) are non-overlapping. when reg<758/818/819> = ?0? ? pwm output duty cycle ranges from 0% to 99.61% and is determined by: ou tput duty cycle = in+/256 ? (in+ = 0: output duty cycle = 0/256 = 0%; in+ = 255: output duty cycl e = 255/256 = 99.61%) ? output signals are triggered by the rising or falling edge of the ckosc signal (defined by bit reg <759>). when reg<758/818/819> = ?1? ? pwm output duty cycle ranges from 0.39% to 100% and is det ermined by output duty cycle = (in+ + 1)/256 ? (in+ = 0: output duty cycle = 1/256 = 0.39%; in+ = 255: output duty cycle = 256/256 = 100%) ? output signals are triggered by the rising or falling edge of the ckosc signal (defined by bit reg <759>). when in+ = in- then eq = ?1? 12.5 dcmp0/pwm0 functional diagram figure 12. dcmp0/pwm0 functional diagram 1 0 cnt1_q<7:0> reg <769> reg <779:772> dcmp0/pwm0 in- in+ 01 00 adc<7:0> s2p<15:8> 11 10 fsm0<7:0> out- eq inn inp to connection matrix input <37> to connection matrix input <40> reg<764:763> 01 00 reg<779:772> reg<787:780> 11 10 reg<795:788> connection matrix output<9:8> reg<803:796> out+ to connection matrix input <41> reg <759> ckosc reg <758> output range select 0=0%to99.61% 1 = 0.39% to 100% reg <815:814> pwm pd select connection matrix output <3> reg <760>
000-0046400-109 page 37 of 89 SLG46400 12.6 dcmp1/pwm1 functional diagram 12.7 dcmp2/pwm2 functional diagram figure 13. dcmp1/pwm1 functional diagram figure 14. dcmp2/pwm2 functional diagram 1 0 cnt1_q<7:0> reg <770> reg <787:780> dcmp1/pwm1 in- in+ 01 00 adc<7:0> s2p<15:8> 11 10 fsm0<7:0> out- eq inn inp to connection matrix input <38> to connection matrix input <42> reg<766:765> 01 00 reg<779:772> reg<787:780> 11 10 reg<795:788> connection matrix output<9:8> reg<803:796> reg <759> out+ to connection matrix input <43> ckosc reg <818> output range select 0=0%to99.61% 1 = 0.39% to 100% reg <761> reg <815:814> pwm pd select connection matrix output <3> 1 0 cnt1_q<7:0> reg <771> reg <795:788> dcmp2/pwm2 in- in+ 01 00 adc<7:0> s2p<7:0> 11 10 fsm0<7:0> out- eq inn inp to connection matrix input <39> to connection matrix input <44> reg<768:767> out+ to connection matrix input <45> reg <795:788> reg <759> ckosc reg <819> output range select 0=0%to99.61% 1 = 0.39% to 100% reg <762> reg <815:814> pwm pd select connection matrix output <3>
000-0046400-109 page 38 of 89 SLG46400 12.8 pwm dead band control the dead band interval can be controlled with nvm bits (reg<757:755> ). the typical dead band time starts at 8ns and can go to 64ns, increasing by 8ns intervals. for the delay dead band control, the dead time control range is: t d = (reg<757:755> + 1) x 8ns 12.9 pwm dead band control timing diagram 12.10 dcmp/pwm power down control the power down source for the dcmp/pwm logic cells is sele cted by reg <815:814> (shared with the adc and pwm). when reg <815:814> = ?00?, the power down control dcmp/pwm logic cells comes from a register bit, otherwise it will come from connection matrix output 3 (in order for dcmp to turn on, this signal should be low). the dcmp/pwm logic cells can then be turned on or off individually with the appropriate register. the power down control of each logic cell is managed by the follow ing register settings: ? when reg<760> = ?0? dcmp0/pwm0 is powered down, when ?1? logic cell is on ? when reg<761> = ?0? dcmp1/pwm1 is powered down, when ?1? logic cell is on ? when reg<762> = ?0? dcmp2/pwm2 is powered down, when ?1? logic cell is on 12.11 dcmp/pwm clock invert control the three dcmp/pwm logic cells can invert the ckosc input signal during the compare or pwm function. reg<759> is used to control the three logic cells clock inversion. figure 15. pwm dead band control timing diagram pwm (out) reference out+ out- dead time dead time
000-0046400-109 page 39 of 89 SLG46400 12.12 dcmp/pwm register settings table 17. dcmp/pwm register settings signal name signal function register bit address register definition pwm_db_sel pwm deadband select <757:755> 000:8ns 100:40ns 001:16ns 101:48ns 010:24ns 110:56ns 011:32ns 111:64ns pwm0_mode_sel pwm0 mode select <758> 0: count down to 0% 1: count up to 100% pwmdcmp_clk_in pwm/dcmp clo ck invert <759> 0: disable 1: enable pwmdcmp0_pd pwm0/dcmp0 power down control <760> 0: power down 1: power on pwmdcmp1_pd pwm1/dcmp1 power down control <761> 0: power down 1: power on pwmdcmp2_pd pwm2/dcmp2 power down control <762> 0: power down 1: power on pwmdcmp0_pos_in pwm0/dcmp0 positive input source select <764:763> 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined (selected through matrix) pwmdcmp1_pos_in pwm1/dcmp1 positive input source select <766:765> 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined pwmdcmp2_pos_in pwm2/dcmp2 positive input source select <768:767> 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined pwmdcmp0_neg_in pwm0/dcmp0 negative input source select <769> 0: from cnt1 ramp (for pwm) 1: 8-bit user defined pwmdcmp1_neg_in pwm1/dcmp1 negative input source select <770> 0: from cnt1 ramp (for pwm) 1: 8-bit user defined (selected through matrix) pwmdcmp2_neg_in pwm2/dcmp2 negative input source select <771> 0: from cnt1 ramp (for pwm) 1: 8-bit user defined adc_pwm_osc_pd _src_sel adc/pwm/osc power down source select <815:814> 00: adc pd from matrix out <3>, pwm pd from register 01: pwm pd from matrix out <3>, adc pd from register 10: adc & pwm pd from matrix out <3> 11: osc pd from matrix out <3>, adc & pwm pd from register pwm1_mode_sel pwm1 mode select <818> 0: count down to 0% 1: count up to 100% pwm2_mode_sel pwm2 mode select <819> 0: count down to 0% 1: count up to 100%
000-0046400-109 page 40 of 89 SLG46400 13.0 counters/delay generators (cnt/dly) there are four configurable counters/delay generators in the SLG46400. th ree of these four logic ce lls can be either a 14-bit counter (cnt) or a delay generator (dly) and one can be a 8-bit counter or delay generator ind ependently of how the other three logic cells are defined. 13.1 counter functionality cnt0, cnt1 and cnt2 each have a 14-bit input data s ource, while cnt3 has a 8-bit input data source. cnt2 and cnt3?s inputs can be sourced from the nvm, the adc, or the s2p, while cnt0 and cnt1?s inputs can be sourced from the connection matrix. the clock can be sourced from either the internal rc oscillator (wit h data divider for cnt1) or fro m another connection matrix output. the counters output their data to either the pwm or to the s2p. the supported counter functions include (fsm only): count up, count down, keep, and load data (taken from adc, s2p or count er data). the four counters can also function as frequency dividers, fsm (cnt2 and cnt3), or pwm ramp (cnt1) , while captured data is outputted to s2p. in counter mode, it is in down mode. the count up/down, keep, and load signals in cnt2 and cnt3 must be tied to ground and the rc osc should be forced on if the clock is sour ced from the internal rc osc for the counter to work. for proper counter functionality, the force signals (cnt0_ force reg<588>, cnt1_force reg<610>, cnt2_force reg<633>, cnt3_force reg<655>) should be configured as ?1? (for ce power on) for any block configured as counter. example: for cnt3 to use the cnt/dly block in counter mode the following settings should be applied: ? cnt/dly3 output source select ( output_src_sel ) set to counter mode (reg <656> = ?1?) ? cnt3 enable ( cnt3_force ) set to force power on (reg <655> = ?1?) ? reset source ( rst_src_sel ) should be set to edge detect mode (reg<654> = ?1?) ? edge select can be set to both, falling, or rising (reg <669:668>) ? additionally, make sure that rc osc is in operating mode. the rc osc may need to be set to force on as well. since cnt1 and cnt2 can be used for a pwm ramp function, the pw m power down signal will control the force power to those macro cells. 13.2 cnt2 and cnt3 reset source select when reg <632> = ?1? (for cnt2) or reg <6 54> = ?1? (for cnt3), the reset signal for cnt2 or cnt3 is sourced from the falling and/or rising edge active signal from the connection matrix and onl y applies when used for counter function. when used in the counter function and reg <632> / reg <654> = ?0 ? then the reset signal is sourced from the por. however when the counter cells are used for a delay function, reg <632> / reg <654> must be set to 0.
000-0046400-109 page 41 of 89 SLG46400 13.3 counters functional diagram figure 16. counters functional diagram cnt0 ext_ck_sel output_src_sel cnt0_force clk_is d<13:0> counter0_end clk reg <606:593> reg <592:590> reg <588> reg <589> reg <609> cnt1 ext_ck_sel output_src_sel cnt1_force clk_is d<13:0> counter1_end clk reg <628:615> reg <614:612> reg <610> reg <611> reg <631> cnt2 counter2_end cnt3 rst_src_sel output_src_sel cnt3_force clk_is d<7:0> counter3_end clk reg <667:660> reg <659:657> reg <655> reg <656> reg <654> to connection matrix input <29> to connection matrix input <30> to connection matrix input <31> to connection matrix input <32> rst_src_sel output_src_sel cnt2_force clk_is d<13:0> clk reg <651:638> reg <637:635> reg <633> reg <634> reg <632> to pwm/dcmp out out out out clk out out out to dac
000-0046400-109 page 42 of 89 SLG46400 13.4 counter timing each of the counters behave as a freque ncy divider, where the output clock ( div_clk_out ) is result of the input clock ( clk ) being divided by the value of the counter control data (cntx_d<13: 0> + 1) for cnt0, cnt1 and cnt2. while cnt3 uses a counter control data value of (cntx_d<7:0> + 1). f clk comes from the rc oscillator which has a /4, /8, and /12 function for all counter logic cells. for cnt0: div_clk_out0 = f clk / (reg<606:593> + 1) for cnt1: div_clk_out1 = f clk / (reg<628:615> + 1) for cnt2: div_clk_out2 = f clk / (reg<651:638> + 1) for cnt3: div_clk_out2 = f clk_in / (reg<667:660> + 1) note: for proper functionality of each counter/delay cell , each respective cntx_d<13:0> or cntx_d<7:0> must have a value of greater than ?1?. an example waveform is shown below (for either cnt0, cnt1 or cnt2) where the output clock goes high for only one of the input clock?s cycles over a time period that is equal to the co unter control data (cntx_d<13:0> +1). the waveform would be the same for cnt3, except the timing would be based on 8-bits of data rather than 14-bits. figure 17. counter behavior clk out (cnt0_d<13:0> + 1) clk_in cycles loaded data n loaded data m q<13:0> 0 1 n-2 n-1 0 2 1 m-2 m-1
000-0046400-109 page 43 of 89 SLG46400 13.5 cnt0/dly0 and cnt1/dly1 register settings table 18. cnt0/dly0 and cnt1/dly1 register settings signal name signal function register bit address register definition cnt0_en cnt0 enable (force cnt0 power on) <588> 0: auto power on (power on as needed) 1: force power on (power always on) cnt_dly0_out_src _sel cnt/dly0 output source select <589> 0: delay output 1: counter output cnt0_clk_sel cnt/dly0 clock source select <592:590> 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt1 overflow output 1x0: clock/8 1x1: external clock cnt0_d<13:0> cnt0 control data/dly0 time control <606:593> 1-16384: (delay time = (counter control data + 1) / freq) dly0_d_mode_sel dly0 mode select <608:607> 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges dly0_in_sel dly0 input function select <609> 0: for delay input signal 1: for counter0 external clock cnt1_en cnt1 enable (force cnt1 power on) <610> 0: auto power on (power on as needed) 1: force power on (power always on) cnt_dly1_out_src _sel cnt/dly1 output source select <611> 0: delay output 1: counter output cnt1_clk_sel cnt/dly1 clock source select <614:612> 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt2 overflow output 1x0: clock/8 1x1: external clock cnt1_d<13:0> cnt1 control data/dly1 time control <628:615> 1-16384: (delay time = (counter control data + 1) / freq) dly1_d_mode_sel dly1 mode select <630:629> 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges dly1_in_sel dly1 input function select <631> 0: for delay input signal 1: for counter1 external clock
000-0046400-109 page 44 of 89 SLG46400 13.6 cnt2/dly2 and cnt3/dly3 register settings table 19. cnt2/dly2 and cnt3/dly3 register settings signal name signal function register bit address register definition cntdly2_rst_sel cnt/dly2 reset source select <632> 0: from delay cell 1: from edge detect when reg <633> = 1, then reg <634> must be set to 1 and dly2 input must be tied to ground cnt2_en cnt2 enable (force cnt2 power on) <633> 0: auto power on (power on as needed) 1: force power on (power always on) cnt_dly2_out_src _sel cnt/dly2 output source select <634> 0: delay output 1: counter output cnt2_clk_sel cnt/dly2 clock source select <637:635> 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt3 overflow output 1x0: clock/8 1x1: external clock cnt2_d<13:0> cnt2 control data/dly2 time control <651:638> 1-16384: (delay time = (counter control data + 1) / freq) dly2_d_mode_sel dly2 mode select <653:652> 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges cntdly3_rst_sel cnt/dly3 reset source select <654> 0: from delay cell 1: from edge detect when reg <655> = 1, then reg <656> must be set to 1 and dly3 input must be tied to ground cnt3_en cnt3 enable (force cnt3 power on) <655> 0: auto power on (power on as needed) 1: force power on (power always on) cnt_dly3_out_src _sel cnt/dly3 output source select <656> 0: delay output 1: counter output cnt3_clk_sel cnt/dly3 clock source select <659:657> 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt0 overflow output 1x0: clock/8 1x1: external clock cnt3_d<7:0> cnt3 control data/dly3 time control <667:660> 1-256: (delay time = (c ounter control data + 1) / freq) dly3_d_mode_sel dly3 mode select <669:668> 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges
000-0046400-109 page 45 of 89 SLG46400 13.7 cnt2 as a finite state machine (fsm0) cnt2 can be used as a 14-bit finite state machine, which has features for up/down/keep co ntrol and loadi ng data select. ? when up/down = ?1?: cnt2 is in up-counting mode, after por or reset, the q value will co unt from 0 to 16383, then the n is loaded (d <13:0>) and the q value count from loaded da ta n to 16383. when q is equal to 16383, out generates a single clock cycle pulse as show n in figure (fsm behavior). ? when up/down = ?0?: cnt2 is in down-counting mode, the q va lue will count from the loaded data value of n (based on reg<651:638> + 1) to 0. when q is equal to 0, out generates a single clock cycle pulse as shown in figure (fsm behavior). ? when keep = ?1?: q will stay at its current value. ? when dly in has a transition (edge mode is dependent on reg<653:652>), a narrow pulse signal will be generated which will reset the cnt2 state to ?0?. ? for fsm operation, the reset source ( rst_src_sel ) should be set to edge detect in counter mode and user will be able to select rising, falling, or both edge (if resetting is needed) , or tie reset input to ground (if resetting is not needed). ? load function is synchronous to counter?s clock signal. fo r load event to happen there should be a rising edge on the clock input of the fsm and load node should be high. 13.8 fsm0 (cnt2) functional diagram figure 18. fsm0 (cnt2) functional diagram figure 19. fsm0 behavior fsm0 (cnt2) counter2_end clk_in load up/down dly in from connection matrix output <13> out q<7:0> keep 01 00 adc <7:0> 11 10 s2p<7:0> reg <752:751> to connection matrix input <31> from connection matrix output <14> from connection matrix output <20> from connection matrix output <12> rst_src_sel output_src_sel cnt2_force clk_is in2_edge_mode_sel reg <653:652> reg <637:635> reg <633> reg <634> reg <632> reg <651:638> d<13:0> q4fsm0 <7:0> to pwm/dcmp reg <651:638> data in
000-0046400-109 page 46 of 89 SLG46400 13.9 cnt3 as a finite state machine (fsm1) cnt3 can be used as a 8-bit finite stat e machine, which has features for up/d own/keep control and lo ading data select. ? when up/down = ?1?: cnt3 is in up-counting mode, after por or reset, the q value will count from 0 to 255, then the n is loaded (d <13:0>) and the q value count from loaded data n to 255. when q is equal to 255, out generates a single clock cycle pulse as shown in figure (fsm behavior). ? when up/down = ?0?: cnt3 is in down-counting mode, the q va lue will count from the loaded data value of n (based on reg<667:660> + 1) to ?0?. when q is equal to 0, out generates a single clock cycle pulse as shown in figure (fsm behavior). ? when keep = ?1?: q will stay at its current value. ? when dly in has a transition (edge mode is dependent on reg<669:668>), a narrow pulse signal will be generated which will reset the cnt3 state to ?0?. ? for fsm operation, the reset source ( rst_src_sel ) should be set to edge detect in counter mode and user will be able to select rising, falling, or both edge (if resetting is needed) , or tie reset input to ground (if resetting is not needed). ? load function is synchronous to counter?s clock signal. fo r load event to happen there should be a rising edge on the clock input of the fsm and load node should be high. 13.10 fsm1 (cnt3) functional diagram figure 20. fsm1 (cnt3) functional diagram figure 21. fsm1 behavior fsm1 (cnt3) counter2_end clk_in load up/down dly in from connection matrix output <16> out q<7:0> keep 01 00 adc <7:0> 11 10 s2p<7:0> reg <754:753> to connection matrix input <32> from connection matrix output <17> from connection matrix output <21> from connection matrix output <15> rst_src_sel output_src_sel cnt3_force clk_is in2_edge_mode_sel reg <669:668> reg <659:657> reg <655> reg <656> reg <654> reg <667:660> d<7:0> q4adc <7:0> to adc reg <667:660> data in
000-0046400-109 page 47 of 89 SLG46400 13.11 fsm register settings 13.12 delay cell functionality the four delay cells in the SLG46400 can operate independently or they can be cascaded with one another to achieve longer time delays. dly0, dly1 and dly2 use a 14-bit data source, whil e dly3 uses a 8-bit data source. each delay cell can be triggere d from a rising edge transition, a falling edge tr ansition, or a transition in either direction. table 20. fsm register settings signal name signal function register bit address register definition fsm0_in_sel fsm0 input data select <752:751> 00: from nvm data 01: from s2p 10: reserved 11: from adc fsm1_in_sel fsm1 input data select <754:753> 00: from nvm data 01: from s2p 10: reserved 11: from adc figure 22. delay cells - long pulse, rising edge figure 23. delay cells - long pulse, falling edge figure 24. delay cells - short pulse, rising edge dly_out rising edge delay time dly_in pulse width dly_out falling edge delay time dly_in pulse width dly_out rising edge delay time dly_in pulse width
000-0046400-109 page 48 of 89 SLG46400 the clock frequency and counter data are used to set the desired output delay. each time delay cell's input and output can be sourced from any user defined signal in the SLG46400. all delay blocks have some of the registers shared with counter m ode block configuration. for co rrect delay operation, counters ? force signals (cnt0_force reg<588>, cnt1_force reg<610>, cnt 2_force reg<633>, cnt3_force reg<655>) should be set to ?0? (auto power on (power on as needed)). figure 25. delay cells - short pulse, falling edge figure 26. delay cells - short pulse, rising and falling edge dly_out falling edge delay time dly_in pulse width dly_out falling edge delay time dly_in series of pulses rising edge delay time
000-0046400-109 page 49 of 89 SLG46400 13.13 delay cells functional diagram 13.14 delay timing the delay timing of each logic cell is determined by the frequen cy of the rc oscillator and th e delay time control registers (reg<606:593> for dly0, reg<628:615> for dly1, reg<651:638> for dly2, and reg<667:660> for dly3). the formulas below list the timing delay equations for each logic cell. clock source co mes from the external clock (f rom matrix), cnt1/dly1, or rc oscillator which has a /4, /8, and /12 function. for dly0: t dly0 = (1/f osc ) * (reg<606:593> + 1) for dly1: t dly1 = (1/f osc ) * (reg<628:615> + 1) for dly2: t dly2 = (1/f osc ) * (reg<651:638> + 1) for dly3: t dly2 = (1/f osc ) * (reg<667:660> + 1) note: in order for these equations above to be valid the pulse width must be larger than the total rising and falling edge dela y times. figure 27. delay cells functional diagram dly0 reg <589> reg <608:607> reg <592:590> reg <606:593> from connection matrix in0 d<13:0> ckis <2:0> edge_dt_mode_sel output_src_sel dly_out0 reg <609> ext_ck_sel dly1 reg <611> reg <630:629> reg <614:612> reg <628:615> from connection matrix in1 d<13:0> ckis <2:0> edge_dt_mode_sel output_src_sel dly_out1 reg <631> ext_ck_sel dly2 reg <634> reg <653:652> reg <637:635> reg <651:538> from connection matrix in2 d<13:0> ckis <2:0> edge_dt_mode_sel output_src_sel dly_out2 reg <632> rst_src_sel dly3 reg <656> reg <669:668> reg <659:657> reg <667:660> from connection matrix in3 d<7:0> ckis <2:0> edge_dt_mode_sel output_src_sel dly_out3 to connection matrix input <32> reg <654> rst_src_sel to connection matrix input <31> to connection matrix input <30> to connection matrix input <29> edge detect edge detect out out out out dly in dly in dly in dly in reg <29:24> clk clk reg <35:30> clk clk
000-0046400-109 page 50 of 89 SLG46400 14.0 programmable delay (pdly) the SLG46400 has a programmable time delay logic cell availa ble that can generate a maximum delay of 200ns. the program - mable time delay cell has four delay cells with a typical value of 20ns per cell (based on a v dd of 3.3v). the delay cells are tied in series where the output of each delay cell goes to the next delay cell and to a 4-input mux that is controlled by reg<537:53 6>. 14.1 programmable delay functional diagram 14.2 vdd vs. typical time delay 14.3 programmable delay register settings figure 28. programmable delay functional diagram table 21. v dd vs. typical time delay per 1 cell. v dd (v) typical time delay (ns) 5.0v 10ns 3.3v 20ns 1.8v 50ns table 22. programmable delay register settings signal name signal function register bit address register definition pdly_sel pdly value section <537:536> 00: 1 delay cell active 01: 2 delay cells active 10: 3 delay cells active 11: 4 delay cells active delay 20ns delay 20ns delay 20ns delay 20ns from connection matrix output <6> 01 00 11 10 reg<537:536> to connection matrix input <47> out in
000-0046400-109 page 51 of 89 SLG46400 15.0 pipe delay (pd) the SLG46400 has a pipe delay logic cell available that c an generate up to three individual delays concurrently: ? a single delay stage on 1 pipe out ? 3, 5, 7, or 11 stages of delay on out0 ? 2, 4, 8, 12 stages of delay on out1 the pipe delay cell is built from 12 d flip-f lop logic cells that provide the three del ay options. the dff cells are tied in se ries where the output (q) of each delay cell goes to the next dff cell. there are delay output points for each set of the out0 and out1 outputs to a 4-input mux that is c ontrolled by reg <810:809> for out0 and reg <821:820> for out1. the 4-input mux is used to control the selectio n of the amount of delay. the overall time of the delay is based on the clock used in the SLG46400 design. each dff cell has a time delay of the inverse of the clock time (either external clock or the rc oscillator within t he SLG46400). the sum of the number of dff cells used wil l be the total time delay of the pipe delay logic cell.
000-0046400-109 page 52 of 89 SLG46400 15.1 pipe delay functional diagram 15.2 pipe delay register settings figure 29. pipe delay functional diagram table 23. pipe delay register settings signal name signal function register bit address register definition pd_sela pipe delay number select <810:809> 00: 3 pipes 01: 5 pipes 10: 7 pipes 11: 11 pipes pd_selb pipe delay number select <821:820> 00: 2 pipes 01: 4 pipes 10: 8 pipes 11: 12 pipes
000-0046400-109 page 53 of 89 SLG46400 16.0 clock management the rc oscillator (rc osc) of the slg46 400 provides an internal clock to the adc, pwm/dcmp, delays and counter logic cells. it has a frequency range of 27khz ? 10mhz which can be adjusted through the rco_freq_cont registers <586:583>. 16.1 clock management functional diagram 16.2 rc osc power down control the power down source for the rc osc logic cell is selected by reg <815:814> (shared with the dcmp and adc). when reg <815:814> = ?11?, the power down control comes from the connec tion matrix. the shared pd signal should be low in order to turn on the rc osc. this signal has the highest priority and if the rc osc is off, no other blocks of registers will be avai lable. 16.3 rc osc dividers control rc osc dividers output to matrix can be controlled through sett ing the reg <816>. when the reg <816> = ?0? than the deviders output to matrix is allowed. wh en the reg <816> = ?1? than the deviders output to matrix wi ll be disabled if no other blocks us e them (cnt, dly and so on). 16.4 ring oscillator and external clock from pin 5 in addition to the internal rc oscillator, greenpak2 has an inte rnal ring oscillator that operates on a single fixed frequency that ranges between 2 mhz and 27 mhz. this value varies from chip to chip and with vdd and temperature. to enable this function reg<587> and reg<670> should be set to ?1?. it is also possible to use the external clock signal from pin5 as the source. to enable the external clock from pin5, configure reg<587> = ?1? and reg<670> = ?0?. in either case, the ring oscillator or external clock signal will feed the adc through an internal /64 divider, the pwm/dcmp bl ocks and cnt/dly/fsm blocks through /4, /8, and /12 frequency dividers, and the matrix through /4 and /12 frequency dividers. direct connection to matrix is not possible (cnt/dly/fsm blocks and matr ix will be fed from the inter nal rc oscillator without divider s). figure 30. clock management functional diagram reg <586:583> reg <582> force osc frequency select reg <815:814> to connection matrix <26> rc oscillator pd select power down connection matrix output <3> pd selection control 1 0 external clock select reg <587> 1 0 en reg <670> ring osc. pin 5 rcosc to dly/cnt/fsm /64 to adc to pwm/dcmp /4 /8 /12 to dly/cnt/fsm to connection matrix 27 to dly/cnt/fsm to connection matrix 28 to dly/cnt/fsm external clock from pin 5 when reg <805> = 1 ckosc ext. clk shared pd
000-0046400-109 page 54 of 89 SLG46400 16.5 rc osc frequency selection 16.6 rc osc register settings table 24. rc osc typical frequency selection reg <586:583> v dd = 1.8v v dd = 3.3v v dd = 5.0v min (khz) typ (khz) max (khz) min (khz) typ (khz) max (khz) min (khz) typ (khz) max (khz) 0000 25.72 28.77 31.83 25.47 28.49 31.52 25.84 28.73 31.63 0001 50.19 55.71 61.22 49.32 54.75 60.19 49.90 55.14 60.38 0010 72.12 79.92 87.73 70.30 78.06 85.82 71.08 78.55 86.02 0011 111.24 124.85 138.46 106.95 120.57 13.20 107.76 120.89 134.01 0100 129.01 142.81 156.61 126.81 140 .46 154.11 128.28 141.46 154.64 0101 191.74 213.47 235.21 187.08 209 .01 230.94 189.17 209.85 230.53 0110 204.31 228.1 251.89 199.13 223 .17 247.21 201.40 223.92 246.45 0111 278.36 316.49 354.63 269.60 308 .17 346.74 273.93 309.07 344.21 1000 422.46 481.35 540.23 425.66 486 .70 547.74 432.35 493.01 553.67 1001 523.27 596.94 670.60 527.09 60. 85 684.60 539.47 616.26 693.05 1010 571.54 654.32 737.10 576.15 665 .78 755.41 591.66 678.24 764.81 1011 652.33 749.54 846.74 659.18 766 .24 873.30 678.30 781.37 884.43 1100 1942.36 2205.05 2467.74 1980.05 2 250.95 2521.85 2032.54 2296.34 2560.14 1101 2515.21 2866.21 3217.21 2567.59 2 932.52 3297.44 2636.11 2990.74 3345.38 1110 592.77 6478.03 7363.28 5721.18 6708. 73 7696.28 5837.26 6836.42 7835.58 1111 6866.55 8016.51 9166.46 7015.74 8337.72 9659.71 7149.45 8484.86 9820.27 table 25. rc osc register settings signal name signal function register bit address register definition rco_force force oscillator power on <582> 0: auto power on (power on as needed) 1: force power on (power always on) rco_fs oscillator frequency control <586:583> see frequency selection table rco_clk_sel external clock source select <587> 0: internal rc osc clock 1: external clock rco_ring_en ring oscilator enable <670> 0: disable 1: enable (adc/pwm/dcmp /clock/4, clock/8, and clock/12 clock source is sele cted from the ring oscillator) adc_pwm_osc_p d_src_sel adc/pwm/osc power down source select <815:814> 00: adc pd from matrix out <3>, pwm pd from register 01: pwm pd from matrix out <3>, adc pd from register 10: adc & pwm pd from matrix out <3> 11: osc pd from matrix out <3>, adc & pwm pd from register rco_div_ctrl oscillator dividers control <816> 0:oscillator dividers enabled 1: oscillator dividers diasbled
000-0046400-109 page 55 of 89 SLG46400 17.0 slave spi - serial to parallel / parallel to serial converter (s2p) the slave spi data can be communicated between the SLG46400 and the larger system design through either the serial to parallel or parallel to serial interface. the s2p has two 16-bit registers (2 bytes) that are used for data transfer. the exter nal clock signal comes from pin 5 and the ncsb (enable contro l signal) comes from th e connection matrix out. s2p uses edge detection from the dly3 signal for capturing the input data. 17.1 s2p functional diagram 17.2 serial to parallel operation for serial to parallel operation (s2p), the serial data in (mo si) comes from pin 6 of the slg4 6400. the s2p will produce a 16-b it parallel data output (s2p<15:0>) where the msb <15:8> can be used by the pwm/ dcmp0 and pwm/dcmp1 logic cells, while the lsb <7:0> can be used by the pwm/dcmp2, fsm0, and fsm1 logic cells. 17.3 serial to parallel timing diagram 17.4 parallel to serial operation for parallel to serial operation (p2s), the 8-bit parallel data in (par in<15:8>) comes from the cnt1 logic cell. pin 6 is used to output the 8-bit serial data out (miso) signal. figure 31. s2p functional diagram figure 32. serial to parallel timing diagram s2p reg <804> reg <712:711> reg <805> pin 6 mosi/miso connection matrix output <7> pin 5 sclk capture connection matrix output <21> ncsb par in <7:0> s2p <15:0> par in <15:8> q4pwm <7:0> counter1 pwm0/dcmp0/ pwm1/dcmp1 fsm0/fsm1 pwm2/dcmp2 s2p <15:8> s2p <7:0> s2p <7:0> s2p_mode_sel s2p_out_en s2p_ck_en shared with delay3 input sclk 12 mosi msb 14 11 13 8 10 7 94 63 51lsb 2 ncsb
000-0046400-109 page 56 of 89 SLG46400 17.5 parallel to serial timing diagram 17.6 s2p notes some functions of the s2p converter share logic cells within th e SLG46400, and as a result only one of these functions can be enabled at a time. the logic cells that are shared are: ? s2p serial to parallel mode or s2p parallel to serial out ? s2p parallel to serial mode or adc serial output data on pin 6 ? s2p parallel to serial mode or dly3 logic cell 17.7 s2p register settings figure 33. parallel to serial timing diagram table 26. s2p register settings signal function register bit address register definition s2p output enable (pin6) <712:711> 00: disable 01: disable 10: enable 11: disable s2p mode select <804> 0: serial input (from pin 6)/parallel output 1: parallel input (from cnt1)/serial output s2p clock enable <805> 0: disable 1: enable sclk miso msb 4 63 51lsb 2 ncsb capture
000-0046400-109 page 57 of 89 SLG46400 18.0 combinatorial logic combinatorial logic is supported via eleven lookup tables (luts) within the SLG46400. there are four 2-bit luts, six 3-bit luts and one 4-bit lut. inputs/outputs for the eleven luts are conf igured from the connection matrix with spec ific logic functions being defined by the state of nvm bits. the outputs of the elev en luts can be configured to user defined functions or the following standard digital logic devices (and, nand, or, nor, xor, xnor). 18.1 2-bit lut the four 2-bit luts within the SLG46400 each take in two input signals from the connection matrix and produce a single output. lut 2.0 inputs are shared with input and reset of the pipe delay logic cell. figure 34. 2-bit luts 2-bit lut0 in1 in0 to connection matrix input <1> out reg <453:450> from connection matrix output <45> from connection matrix output <46> 2-bit lut1 in1 in0 to connection matrix input <2> out reg <457:454> from connection matrix output <47> from connection matrix output <48> 2-bit lut2 in1 in0 to connection matrix input <3> out reg <461:458> from connection matrix output <49> from connection matrix output <50> 2-bit lut3 in1 in0 to connection matrix input <4> out reg <465:462> from connection matrix output <51> from connection matrix output <52> table 27. 2-bit lut0 truth table. in1 in0 out 0 0 reg <450> 0 1 reg <451> 1 0 reg <452> 1 1 reg <453> table 28. 2-bit lut1 truth table. in1 in0 out 0 0 reg <454> 0 1 reg <455> 1 0 reg <456> 1 1 reg <457> table 29. 2-bit lut2 truth table. in1 in0 out 0 0 reg <458> 0 1 reg <459> 1 0 reg <460> 1 1 reg <461> table 30. 2-bit lut3 truth table. in1 in0 out 0 0 reg <462> 0 1 reg <463> 1 0 reg <464> 1 1 reg <465>
000-0046400-109 page 58 of 89 SLG46400 each 2-bit lut uses a 4-bit register signal to define their output functions; 2-bit lut0 is defined by reg<453:450> 2-bit lut1 is defined by reg<457:454> 2-bit lut2 is defined by reg<461:458> 2-bit lut3 is defined by reg<465:462> the table below shows the register bits for the standard digita l logic devices (and, nand, or, nor, xor, xnor) that can be created within each of the four 2-bit lut logic cells. table 31. 2-bit lut0/lut1/lut2/lut3 standard digital functions. function msb lsb and-2 1 0 0 0 nand-2 0 1 1 1 or-2 1 1 1 0 nor-2 0 0 0 1 xor-2 0 1 1 0 xnor-2 1 0 0 1
000-0046400-109 page 59 of 89 SLG46400 18.2 3-bit lut the six 3-bit luts within the SLG46400 each take in three input signals from the connection matrix and produce a single output. figure 35. 3-bit luts 3-bit lut0 in1 in0 to connection matrix input <5> out reg <473:466> from connection matrix output <53> from connection matrix output <54> 3-bit lut1 in1 in0 to connection matrix input <6> out reg <481:474> from connection matrix output <56> from connection matrix output <57> 3-bit lut2 to connection matrix input <7> out reg <489:482> in2 from connection matrix output <58> in2 from connection matrix output <55> in1 in0 from connection matrix output <59> from connection matrix output <60> in2 from connection matrix output <61> 3-bit lut3 to connection matrix input <8> out reg <497:490> in1 in0 from connection matrix output <62> from connection matrix output <63> in2 from connection matrix output <64> 3-bit lut4 in1 in0 to connection matrix input <9> out reg <505:498> from connection matrix output <65> from connection matrix output <66> 3-bit lut5 to connection matrix input <10> out reg <513:506> in2 from connection matrix output <67> in1 in0 from connection matrix output <68> from connection matrix output <69> in2 from connection matrix output <70> table 32. 3-bit lut0 truth table. in2 in1 in0 out 0 0 0 reg <466> 0 0 1 reg <467> 0 1 0 reg <468> 0 1 1 reg <469> 1 0 0 reg <470> 1 0 1 reg <471> 1 1 0 reg <472> 1 1 1 reg <473> table 33. 3-bit lut1 truth table. in2 in1 in0 out 0 0 0 reg <474> 0 0 1 reg <475> 0 1 0 reg <476> 0 1 1 reg <477> 1 0 0 reg <478> 1 0 1 reg <479> 1 1 0 reg <480> 1 1 1 reg <481>
000-0046400-109 page 60 of 89 SLG46400 each 3-bit lut uses an 8-bit register signal to define their output functions; 3-bit lut0 is defined by reg<473:466> 3-bit lut1 is defined by reg<481:474> 3-bit lut2 is defined by reg<489:482> 3-bit lut3 is defined by reg<497:490> 3-bit lut4 is defined by reg<505:498> 3-bit lut5 is defined by reg<513:506> table 34. 3-bit lut2 truth table. in2 in1 in0 out 0 0 0 reg <482> 0 0 1 reg <483> 0 1 0 reg <484> 0 1 1 reg <485> 1 0 0 reg <486> 1 0 1 reg <487> 1 1 0 reg <488> 1 1 1 reg <489> table 35. 3-bit lut3 truth table. in2 in1 in0 out 0 0 0 reg <490> 0 0 1 reg <491> 0 1 0 reg <492> 0 1 1 reg <493> 1 0 0 reg <494> 1 0 1 reg <495> 1 1 0 reg <496> 1 1 1 reg <497> table 36. 3-bit lut4 truth table. in2 in1 in0 out 0 0 0 reg <498> 0 0 1 reg <499> 0 1 0 reg <500> 0 1 1 reg <501> 1 0 0 reg <502> 1 0 1 reg <503> 1 1 0 reg <504> 1 1 1 reg <505> table 37. 3-bit lut5 truth table. in2 in1 in0 out 0 0 0 reg <506> 0 0 1 reg <507> 0 1 0 reg <508> 0 1 1 reg <509> 1 0 0 reg <510> 1 0 1 reg <511> 1 1 0 reg <512> 1 1 1 reg <513>
000-0046400-109 page 61 of 89 SLG46400 the table below shows the register bits for the standard digita l logic devices (and, nand, or, nor, xor, xnor) that can be created within each of the six3-bit lut logic cells. table 38. 3-bit lut0/lut1/lut2/lut3/lut4/lut5 standard digital functions. function msb lsb and-3 1 0 0 0 0 0 0 0 nand-3 0 1 1 1 1 1 1 1 or-3 1 1 1 1 1 1 1 0 nor-3 0 0 0 0 0 0 0 1 xor-3 1 0 0 1 0 1 1 0 xnor-3 0 1 1 0 1 0 0 1
000-0046400-109 page 62 of 89 SLG46400 18.3 4-bit lut the one 4-bit lut within the SLG46400 takes in four input signals from the connection matrix and produces a single out - put. the 4-bit lut uses a 16-bit register signal to define the output function; 4-bit lut0 is defined by reg<529:514> the table below shows the register bits for the standard digita l logic devices (and, nand, or, nor, xor, xnor) that can be created within the 4-bit lut logic cell. figure 36. 4-bit lut 4-bit lut0 in1 in0 to connection matrix input <11> out reg <529:514> from connection matrix output <71> from connection matrix output <72> in2 from connection matrix output <73> in3 from connection matrix output <74> table 39. 4-bit lut0 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <514> 0 0 0 1 reg <515> 0 0 1 0 reg <516> 0 0 1 1 reg <517> 0 1 0 0 reg <518> 0 1 0 1 reg <519> 0 1 1 0 reg <520> 0 1 1 1 reg <521> 1 0 0 0 reg <522> 1 0 0 1 reg <523> 1 0 1 0 reg <524> 1 0 1 1 reg <525> 1 1 0 0 reg <526> 1 1 0 1 reg <527> 1 1 1 0 reg <528> 1 1 1 1 reg <529> table 40. 4-bit lut0 standard digital functions. function msb lsb and-4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 nand-4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 or-4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 nor-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 xor-4 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 xnor-4 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
000-0046400-109 page 63 of 89 SLG46400 19.0 digital storage elements (dffs/latches) there are four dff/latches logic cells within the SLG46400 avail able for design. the source and destination of the inputs and outputs for the three dff/latches are configured from the connection matrix. the operation of the d flip-flop and latch will following the functional descriptions below: dff: ck is rising edge triggered, then q = d; otherwise q will not change latch: if ck = 0, then q = d if ck = 1, then q will not change for dff/latch 0, matrix out1 will control the reset and set functions (active low) that ar e controlled from reg<531>. for dff/latch 1, matrix out18 will control the reset and set functions (active low) that are controlled from reg<533>. 19.1 dff/latch functional diagram figure 37. dff/latch functional diagram dff/ latch0 ck d to connection matrix input <12> q reg <530> from connection matrix output <37> from connection matrix output <38> dff/ latch2 ck d reg <534> from connection matrix output <41> from connection matrix output <42> dff/ latch1 ck d reg <532> from connection matrix output <39> from connection matrix output <40> dff/ latch3 ck d reg <535> from connection matrix output <43> from connection matrix output <54> 1 0 from connection matrx output <1> 1 0 reg <531> nreset nset 1 0 from connection matrx output <18> 1 0 reg <533> nreset nset to connection matrix input <52> nq to connection matrix input <13> q to connection matrix input <53> nq to connection matrix input <14> q to connection matrix input <52> nq to connection matrix input <15> q to connection matrix input <55> nq
000-0046400-109 page 64 of 89 SLG46400 19.2 dff/latch selection each of the four dff/latch logic cells have a selection bit that is used to define if the logic cell will be used as a d flip-f lop or a latch within the design. those control bits are shown in the table below. 19.3 dff/latch register settings table 41. dff/latch register settings signal function register bit address register definition dff/latch0 selection <530> 0: dff 1: latch dff0 reset or set select <531> 0: reset from connection matrix 1 1: set from connection matrix 1 dff/latch1 selection <532> 0: dff 1: latch dff1 reset or set select <533> 0: reset from connection matrix 18 1: set from connection matrix 18 dff/latch2 selection <534> 0: dff 1: latch dff/latch3 selection <535> 0: dff 1: latch
000-0046400-109 page 65 of 89 SLG46400 20.0 power on reset (por) the power on reset (por) macro cell will produce a ?1? signal as an output when the power supply (v dd ) rises to around 1.4-1.6v. the typical internal delay for por from 1. 4v to 1.6v is 6.8ms (min=4ms, max=10.47m s). the typical delay time for por to nvm data out is 500 s. for por to work properly, the max power up ramp time for v dd =1.8v is 34ms; for v dd =5v, it is 100ms. when nvm data is ready, the oscillator must be stable at the same time. if the oscillator power on is controlled by auto power on signals such as delay cells, adc, or pw m, the oscillator will need a maximum of 5 s to become stable. figure 38. power on reset timing diagram figure 39. stable oscillator wait time por4nvm v dd 1.4v ~6.8ms 500 s resetb_nvm_out ~2 s por_io 1 s por_core 1 s por_io_dly rst tri-state output pad determined by function logic initial state determined by registers s[1:0] oscillator stable <5 s oscillator power on control signals
000-0046400-109 page 66 of 89 SLG46400 20.1 por register settings description the por logic cell is controlled by setting the registers <750:748>: ? when set to ?010?: auto power detect function is on (both auto detection and the regulator for adc and acmp are on) ? when set to ?101?: v dd bypass to adc (when v dd < 2.7v, no power consumption is used by either the adc or acmp logic cells) ? when set to ?001?: regulator always on (when v dd > 2.7v, there is no auto power detection, but regulator has power for the adc & acmp logic cells). if the adc or acmp are not in use; reg <750:748> should be set to ?000? and the adc/acmp logic cells should be set to power down mode. if the adc or acmp are in use: ?if v dd is fixed and 2.7v, reg <750:748> should be set to ?101?. ?if v dd varies from 1.8v to 5.0v, reg <750:748> should be set to ?010? ?if v dd varies from 2.6v to 5.0v, reg <750:748> should be set to ?010? or ?001?. 20.2 por register settings table 42. por register settings signal function register bit address register definition por auto power detect <748> 0: enable 1: disable power divider power on <749> 0: power down 1: power on v dd bypass to adc (when v dd 2.7v turn on) <750> 0: disable 1: enable
000-0046400-109 page 67 of 89 SLG46400 21.0 application examples 21.1 system reset in the following a pplication example, a system reset pul se can be generated from a command signal (from a microprocessor) or an external reset push button. the current reset state can be sh own by adding a led into the de sign. implementing this function within the SLG46400 requires the use of an input buffer, an open drain led output driver, a de-gl itch filter, and a one-shot ci rcuit. in this example the SLG46400 replaces up to four off-the-shelf components. 21.2 combinatorial logic in this application example one SLG46400 is used to repl ace three discrete ?1g? sot23-5 packaged logic components. the SLG46400?s 2.5mm x 2.5mm tdfn packaging of this function will result in significant space savings due to fewer components used in the final pcb design. 21.3 example: bi-directio nal pin using an oe signal the example figure below shows how a bi-directional pin can be set up in the greenpak 2 designer tool by using an external signal for the output enable control signal. the input to pin 2 is controlled from an external signal, wh ich is then used to control the output enable on pin 3. ? when the signal on pin 2 = ?0?, then pin 3 will act as a digital input. in this exampl e, the signal from pin 3 is going to the logic cell (lut2. 1 in this case). figure 40. example: system reset figure 41. example: combinatorial logic pin de-glitch delay pin ext_rst# uc_rstart# pin 3.3v one-shot rstart# pin rst# in1 in2 in3 in4 out1 out2
000-0046400-109 page 68 of 89 SLG46400 ? when the signal on pin 2 = ?1?, then pin 4 will act as a push pull output with 1x current drive. in this example, a signal fro m cnt1/dly1 will be sent from the SLG46400 to the external board. figure 42. pin 4 as a bi-directional pin with pin 2 as the oe control pin4 pin2 ext. in out ext. in/out out in oe
000-0046400-109 page 69 of 89 SLG46400 22.0 development tools 22.1 software & hardware 22.1.1 greenpak 2 designer? at the core of the greenpak 2 development software suite is greenpak 2 designer, graphical sc hematic design tool used to create circuit designs within the greenpak 2 ic. greenpak 2 designer requires no programming language or complier. greenpak 2 designer software is available free of charge at http://www.silego.com/ . 22.1.2 greenpak 2 programmer greenpak 2 programmer is flexible enough and is used on the benc h in development and also suitable for factory programming. greenpak 2 programmer operates directly from greenpak 2 designer. 22.1.3 minimum system requirements ? cpu: 800mhz ? ram: 128mb ? graphics ram: 32mb ? free hard disk space: 50mb both of silego?s greenpak 2 designer and programmer software is supported in the following operating systems: ? 32-bit microsoft windows xp / vista / 7 ? 64-bit microsoft windows xp / vista / 7 ? apple mac os x windows is a registered trademark of microsoft corp oration in the united states and other countries. mac os is a trademark of apple inc., regi stered in the u.s. and other countries. ? 22.2 development kits the greenpak 2 development kit is sold directly at the silego online store. please visit at http://store.silego.com/ the greenpak 2 development kit is for prototyping and development with greenpak 2 designer. the kit contains a usb programming stick, usb extension cable and 50 SLG46400 samples. everything needed for a circuit designer to start prototyping designs with the greenpak 2 ic. 22.3 project examples additional greenpak 2 examples designs are available on the s ilego website free of charge. t hese designs can be downloaded and reviewed in the greenpak 2 designer as a quick and effi cient way to become familiar with the project development. these examples can be found at http://support.silego.com/
000-0046400-109 page 70 of 89 SLG46400 23.0 package top marking system definition part code datecode lot revision C part id field: identifies the specific device configuration C date code field: coded date of manufacture C lot code: designates lot # C assembly site/coo: specifies assembly site/country of origin C revision code: device revision xxxxx dd lll c rr coo
000-0046400-109 page 71 of 89 SLG46400 24.0 package drawing and dimensions 24.1 12 lead tdfn package jedec mo-252, variation 2525e
000-0046400-109 page 72 of 89 SLG46400 24.2 tape and reel specifications 24.3 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] tdfn 12l green 12 2.5 x 2.5 x 0.75 3,000 3,000 178 / 60 42 168 42 168 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w tdfn 12l green 2.75 2.75 1 4 4 1.55 1.75 3.5 8 p1 w e p0 a0 d0 y y b0 k0 section y-y c l f refer to eia-481 specification
000-0046400-109 page 73 of 89 SLG46400 25.0 recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow profile based on package volume of 4.6875 mm 3 (nominal). more information can be found at www.jedec.org.
000-0046400-109 page 74 of 89 SLG46400 26.0 appendix - SLG46400 register definition bit address register definition reg<5:0> clock of pipe delay reg<11:6> reset or set of dff0 reg<17:12> reset or set of dff1 reg<23:18> power down for adc/pwm/rc osc (reg<815:814> select power down block) reg<29:24> cnt2 external clock reg<35:30> cnt3 external clock reg<41:36> 20ns/40ns/60ns/80ns delay input reg<47:42> ncsb for spi reg<53:48> pwm/dcmp0 ip3 and pwm/dcmp1 in1 input mux select bit0 reg<59:54> pwm/dcmp0 ip3 and pwm/dcmp1 in1 input mux select bit1 reg<65:60> pwr up (power up) for acmp0 reg<71:66> pwr up (power up) for acmp0 reg<77:72> keep for fsm0 reg<83:78> load for fsm0 reg<89:84> up/down for fsm0 reg<95:90> keep for fsm1 reg<101:96> loadfor fsm1 reg<107:102> up/down for fsm1 reg<113:108> input for dly0 or cnt0 external clock reg<119:114> input for dly1 or cnt1 external clock reg<125:120> input for dly2 reg<131:126> input for dly3 reg<137:132> pin3 digital output source reg<143:138> pin4 digital output source reg<149:144> pin5 digital output source reg<155:150> pin6 digital output source (reg<712:711>=00) reg<161:156> pin8 digital output source reg<167:162> pin9 digital output source reg<173:168> pin10 digital output source reg<179:174> pin11 digital output source reg<185:180> pin12 digital output source reg<191:186> output enable of pin4 reg<197:192> output enable of pin5 reg<203:198> output enable of pin6 reg<209:204> output enable of pin10 reg<215:210> output enable of pin11 reg<221:216> output enable of pin12 reg<227:222> data input of dff0 reg<233:228> clock input of dff0 reg<239:234> data input of dff1 reg<245:240> clock input of dff1 reg<251:246> data input of dff2
000-0046400-109 page 75 of 89 SLG46400 reg<257:252> clock input of dff2 reg<263:258> data input of dff3 reg<269:264> clock input of dff3 reg<275:270> in0 of lut2_0 /input of pipe delay reg<281:276> in1 of lut2_0 /resetb of pipe delay reg<287:282> in0 of lut2_1 reg<293:288> in1 of lut2_1 reg<299:294> in0 of lut2_2 reg<305:300> in1 of lut2_2 reg<311:306> in0 of lut2_3 reg<317:312> in1 of lut2_3 reg<323:318> in0 of lut3_0 reg<329:324> in1 of lut3_0 reg<335:330> in2 of lut3_0 reg<341:336> in0 of lut3_1 reg<347:342> in1 of lut3_1 reg<353:348> in2 of lut3_1 reg<359:354> in0 of lut3_2 reg<365:360> in1 of lut3_2 reg<371:366> in2 of lut3_2 reg<377:372> in0 of lut3_3 reg<383:378> in1 of lut3_3 reg<389:384> in2 of lut3_3 reg<395:390> in0 of lut3_4 reg<401:396> in1 of lut3_4 reg<407:402> in2 of lut3_4 reg<413:408> in0 of lut3_5 reg<419:414> in1 of lut3_5 reg<425:420> in2 of lut3_5 reg<431:426> in0 of lut4_0 reg<437:432> in1 of lut4_0 reg<443:438> in2 of lut4_0 reg<449:444> in3 of lut4_0 reg<453:450> lut2_0 data reg<457:>454 lut2_1 data reg<461:458> lut2_2 data reg<465:462> lut2_3 data reg<473:466> lut3_0 data reg<481:474> lut3_1 data reg<489:482> lut3_2 data reg<497:490> lut3_3 data reg<505:498> lut3_4 data reg<513:506> lut3_5 data bit address register definition
000-0046400-109 page 76 of 89 SLG46400 reg<529:514> lut4 data reg<530> dff0 or latch select 0: dff function 1: latch function reg<531> dff0 nrst/nset select 0: nrst from matrix out1 1: nset from matrix out1 reg<532> dff1 or latch select 0: dff function 1: latch function reg<533> dff1 nrst/nset select 0: nrst from matrix out18 1: nset from matrix out18 reg<534> dff2 or latch select 0: dff function 1: latch function reg<535> dff3 or latch select 0: dff function 1: latch function reg<537:536> delay value select 00: 20ns 01: 40ns 10: 60ns 11: 80ns reg<538> reserved reg<540:539> pin8 initial state control 00: floating 01: ground 10: power 11: input reg<543:541> pin8 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode reg<545:544> pin8 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<546> pin8 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<547> pin8 push pull output enable 0: disable 1: enable reg<549:548> pin9 initial state control 00: floating 01: ground 10: power 11: input bit address register definition
000-0046400-109 page 77 of 89 SLG46400 reg<552:550> pin9 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode reg<554:553> pin9 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<555> pin9 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<556> pin9 push pull output enable 0: disable 1: enable reg<558:557> pin10 initial state control 00: floating 01: ground 10: power 11: input reg<561:559> pin10 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode reg<563:562> pin10 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<564> pin10 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<566:565> pin11 initial state control 00: floating 01: ground 10: power 11: input reg<569:567> pin11 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode bit address register definition
000-0046400-109 page 78 of 89 SLG46400 reg<571:570> pin11 pull up/down resi stor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<572> pin11 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<574:573> pin11 initial state control 00: floating 01: ground 10: power 11: input reg<577:575> pin12 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: reserved 100: push pull current x2 101: open drain mode 110: reserved 111: push pull mode reg<579:578> pin12 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<580> pin12 pull up/down resistor selection 0: pull down resistor 1: pull up resistor reg<581> pin12 open drain double current 0: normal current 1: double current reg<582> force rc oscillator on 0: auto power on (power on as needed) 1: force power on (power always on) reg<586:583> rc oscillator frequency control 0000: 28.66k 0001: 55.2k 0010: 78.84k 0011: 122.1k 0100: 141.58k 0101: 210.78k 0110: 225.06k 0111: 31?.24k 1000: 487.02k 1010: 666.11k 1011: 765.72k 1100: 2.25m 1101: 2.93m 1110: 6.67m 1111: 8.28m reg<587> external clock source select 0: internal oscillator clock 1: external clock bit address register definition
000-0046400-109 page 79 of 89 SLG46400 reg<588> cnt0 enable 0: disable 1: enable reg<589> cnt/dly0 output source select 0: delay output 1: counter output reg<592:590> cnt/dly0 clock source select 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt1 overflow output 1x0: clock/8 1x1: external clock (reg<609> = 1) reg<606:593> cnt0 control data/dly0 time control 1-16384: (delay time = (counter control data + 1) / freq) reg<608:607> dly0 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<609> dly0 input function select 0: for delay input signal 1: for cnt0 external clock reg<610> cnt1 enable 0: disable 1: enable reg<611> cnt/dly1 output source select 0: delay output 1: counter output reg<614:612> cnt/dly1 clock source select 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt1 overflow output 1x0: clock/8 1x1: external clock (reg<631> = 1) reg<628:615> cnt1 control data/dly1 time control 1-16384: (delay time = (counter control data + 1) / freq) reg<630:629> dly1 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<631> dly1 input function select 0: for delay input signal 1: for cnt0 external clock reg<632> cnt/dly2 reset source select 0: from delay cell 1: from edge detect reg<633> cnt2 enable 0: disable 1: enable reg<634> cnt/dly2 output source select 0: delay output 1: counter output bit address register definition
000-0046400-109 page 80 of 89 SLG46400 reg<637:635> cnt/dly2 clock source select 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt1 overflow output 1x0: clock/8 1x1: external clock reg<651:638> cnt2 control data/dly2 time control 1-16384: (delay time = (counter control data + 1) / freq) reg<653:652> dly2 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<654> cnt/dly3 reset source select 0: from delay cell 1: from edge detect reg<655> cnt3 enable 0: disable 1: enable reg<656> cnt/dly3 output source select 0: delay output 1: counter output reg<659:657> cnt/dly3 clock source select 000: internal rc osc clock 001: clock/4 010: clock/12 011: cnt1 overflow output 1x0: clock/8 1x1: external clock reg<667:660> cnt3 control data/dly3 time control 1-255: (delay time = (counter control data + 1) / freq) reg<669:668> dly3 mode select 00: delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges reg<670> ring oscillator enable 0: disable 1: enable (pwm/dcmp external clock s ource is selected from this ring osc) reg<671> reserved reg<673:672> pin2 mode control 00: digital in mode with schmitt trigger 01: digital in mode without schmitt trigger 10: low voltage digital input 11: analog in reg<675:674> pin2 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<676> pin2 pull up/down resistor 0: pull down resistor 1: pull up resistor bit address register definition
000-0046400-109 page 81 of 89 SLG46400 reg<678:677> pin3 initial state control 00: floating 01: ground 10: power 11: input reg<681:679> pin3 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode reg<683:682> pin3 pull up/down resistor value selection. 00: floating 01: 50k 10: 100k 11: 300k reg<684> pin3 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<685> pin3 push pull output enable 0: push pull output disable 1: push pull output enable reg<687:686> pin4 initial state control 00: floating 01: ground 10: power 11: input reg<690:688> pin4 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: analog io mode 100: push pull current x2 101: open drain mode 110: analog io & open drain mode 111: push pull mode reg<692:691> pin4 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<693> pin4 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<695:694> pin5 initial state control 00: floating 01: ground 10: power 11: input bit address register definition
000-0046400-109 page 82 of 89 SLG46400 reg<698:696> pin5 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: low voltage digital in mode without schmitt trigger 011: reserved 100: push pull current x2 101: open drain mode 110: reserved 111: push pull mode reg<700:699> pin5 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<701> pin5 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<703:702> pin6 initial state control 00: floating 01: ground 10: power 11: input reg<706:704> pin6 mode control 000: digital in mode with schmitt trigger 001: digital in mode without schmitt trigger 010: ;ow voltage digital in mode without schmitt trigger 011: reserved 100: push pull current x2 101: open drain mode 110: reserved 111: push pull mode reg<708:707> pin6 pull up/down resistor value selection 00: floating 01: 50k 10: 100k 11: 300k reg<709> pin6 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<710> pin6 open drain double 0: normal current 1: double current reg<712:711> pin6 digital output source selection 0x: from connection matrix (out25) 10: from s2p (miso) 11: from adc serial output reg<713> adc input gain range 0: 0 ~ 1v 1: 0 ~ 0.78v reg<714> adc mux channel selection 0: mux disabled, adc will sample pin 8 for in+ 1: mux enabled, adc will sample either pin 8 or 9 for in+ reg<715> adc power down mode select 0: adc slow power on mode 1: adc fast power on mode bit address register definition
000-0046400-109 page 83 of 89 SLG46400 reg<718:716> adc pga gain control 000: single-ended (0.5x gain) or differential (n/a) 001: single-ended (1x gain) or differential (1x gain) 010: single-ended (2x gain) or differential (2x gain) 011: single-ended (4x gain) or differential (4x gain) 100: single-ended (8x gain) or differential (8x gain) 101: single-ended (n/a) or differential (16x gain) reg<720:719> adc v ref source select (depends on reg <713>) 00: bandgap voltage v bg (1v or 0.778) 01: 1x or 2x external voltage source 10: v dd * (0.25 or 0.5) 11: none reg<721> acmp0 1ua input current option 0: disable 1: enable reg<725:722> acmp0 in- voltage select (when reg<736> = 0) 0000: 50mv 0001: 100mv 0010: 150mv 0011: 200mv 0100: 250mv 0101: 300mv 0110: 400mv 0111: 500mv 1000: 600mv 1001: 700mv 1010: 800mv 1011: 900mv 1100: 1100mv 1101: 1300mv 1110: 1500mv 1111: external (pin 11) reg<725:722> acmp0 in- voltage select (when reg<736> = 1) 0000: 30mv 0001: 70mv 0010: 100mv 0011: 130mv 0100: 170mv 0101: 200mv 0110: 270mv 0111: 330mv 1000: 400mv 1001: 470mv 1010: 530mv 1011: 600mv 1100: 730mv 1101: 870mv 1110: 1000mv 1111: external (pin 11) reg<726> acmp1 1 a input current option 0: disable 1: enable reg<730:727> acmp1 in- voltage select (when reg<736> = 0) 0000: 50mv 0001: 100mv 0010: 150mv 0011: 200mv 0100: 250mv 0101: 300mv 0110: 400mv 0111: 500mv 1000: 600mv 1001: 700mv 1010: 800mv 1011: 900mv 1100: 1100mv 1101: 1300mv 1110: 1500mv 1111: external (pin 11) reg<730:727> acmp1 in- voltage select (when reg<736> = 1) 0000: 30mv 0001: 70mv 0010: 100mv 0011: 130mv 0100: 170mv 0101: 200mv 0110: 270mv 0111: 330mv 1000: 400mv 1001: 470mv 1010: 530mv 1011: 600mv 1100: 730mv 1101: 870mv 1110: 1000mv 1111: external (pin 11) reg<732:731> acmp0 hysteresis enable 00: disabled (0mv) 01: enabled (12mv) 10: enabled (50mv) 11: enabled (150mv) reg<734:733> acmp1 hysteresis enable 00: disabled (0mv) 01: enabled (12mv) 10: enabled (50mv) 11: enabled (150mv) reg<736> acmp v ref band select 0: 50mv to 1.5v range 1: 30mv to 1v range reg<737> adc clock selection 0: internal rc oscillator 1: external clock from pin 5 bit address register definition
000-0046400-109 page 84 of 89 SLG46400 reg<738> adc pseudo diff input enable under adc diff mode 0: disabled 1: enabled reg<739>, reg<735> acmp0 in+ source selection 00: acmp0 in+ input from pin3 01: acmp0 in+ input from pin4 (pin3 analog_io_en should be disabled) 10: acmp0 in+ input from pga out 11: acmp0 in+ input from pga in reg<740> v ref output active buffer control 0: enabled 1: disabled reg<741> v ref output enable 0: acmp0 = v ref input 1: enabled reg<742> adc input mode select 0: single-end operation using pin 8 1: differential mode using pins 8 & 9 reg<743> v ref output source select 0: acmp0 reference voltage 1: v dd /3 reg<744> force bandgap on 0: disabled 1: enable reg<745> acmp1 negative input source select 0: from v ref 1: from dac output reg<746> dac input data select 0: adc normal work 1: dac data comes from fsm reg<747> acmp1 positive input divided by 2 resistor(100k) 0: disabled (ip input from pin 4) 1: enabled (ip input from adc - pga out) reg<748> por auto power detection control 0: enable 1: disable reg<749> por power divider power on (only required when us ing power divider output for external source) 0: disable 1: enable reg<750> por v dd bypass to adc (only required when v dd <=2.7v) 0: disable 1: enable reg<752:751> fsm0 input data select x0: from nvm (connection matrix) 01: from s2p 11: from adc reg<754:753> fsm1 input data select x0: from nvm (connection matrix) 01: from s2p 11: from adc reg<757:755> pwm deadband select 000:8ns 001:16ns 010:24ns 011:32ns 100:40ns 101:48ns 110:56ns 111:64ns bit address register definition
000-0046400-109 page 85 of 89 SLG46400 reg<758> pwm0 mode select 0: down to 0% 1: up to 100% reg<759> pwm/dcmp clock invert 0: disable 1: enable reg<760> pwm0/dcmp0 power down control 0: power down 1: power on reg<761> pwm1/dcmp1 power down control 0: power down 1: power on reg<762> pwm2/dcmp2 power down control 0: power down 1: power on reg<764:763> pwm0/dcmp0 positive input source select 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined (selected through matrix) reg<766:765> pwm1/dcmp1 positive input source select 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined (selected through matrix) reg<768:767> pwm2/dcmp2 positive input source select 00: from adc 01: from s2p 10: from fsm0 11: 8-bit user defined (selected through matrix) reg<769> pwm0/dcmp0 negative input source select 0: from cnt1 ramp (for pwm) 1: 8-bit user defined (selected through matrix) reg<770> pwm1/dcmp1 negative input source select 0: from cnt1 ramp (for pwm) 1: 8-bit user defined (selected through matrix) reg<771> pwm2/dcmp2 negative input source select 0: from cnt1 ramp (for pwm) 1: 8-bit user defined (selected through matrix) reg<779:772> pwm/dcmp nvm data pwm_reg0 reg<787:780> pwm/dcmp nvm data pwm_reg1 reg<795:788> pwm/dcmp nvm data pwm_reg2 reg<803:796> pwm/dcmp nvm data pwm_reg3 reg<804> s2p or p2s mode select 0: serial in parallel output to chip internal 1: parallel in from chip serial out reg<805> spi clock /osc external clock enable 0: disable 1: enable reg<806> bypass the pin2 0: pin2 edge active 1: pin2 high active bit address register definition
000-0046400-109 page 86 of 89 SLG46400 reg<807> pin2 edge detect mode 0: rising edge 1: falling edge reg<808> pin2 reset enable 0: disable 1: enable reg<810:809> pipe number select from co nnection matrix out <48> 00: 3 pipes 01: 5 pipes 10: 7 pipes 11: 11 pipes reg<811> acmp0 low bandwidth enable 0: disable 1: enable reg<812> acmp1 low bandwidth enable 0: disable 1: enable reg<813> adc power down control register when reg<815: 814>=?01?. adc power power is controlled by reg<813>, otherwise, adc power down is controlled by connection matrix out<3>. when reg <814> = ?1?: 0: adc power on 1: adc power down <815:814> adc/pwm/osc power down source selection 00: adc power down from matrix out <3>, pwm power down from register 01: pwm power down from matrix out <3>, adc power down from reg <813> 10: adc & pwm power down from matrix out <3> 11: osc power down from matrix out <3>, pwm & adc power down from register reg<816> oscillator dividers control 0:oscillator dividers enabled 1: oscillator dividers diasbled reg<817> dff0/latch0 output polarity control 0: do not invert output polarity 1: invert output polarity reg<818> pwm1 mode select 0: down to 0% 1: up to 100% reg<819> pwm2 mode select 0: down to 0% 1: up to 100% reg<821:820> pipe number select from co nnection matrix out <49> 00: 2 pipes 01: 4 pipes 10: 8 pipes 11: 12 pipes reg<829:822> 8-bit pattern id reg<830> nvm data read disable 0: disable 1: enable reg<831> nvm power down 0: none 1: power down bit address register definition
000-0046400-109 page 87 of 89 SLG46400 27.0 revision history date version change 6/3/2015 1.09 fixed package name tape and reel spec 10/8/2014 1.08 fixed typo in tape and reel spec 8/6/2014 1.07 fixed esd information 11/21/2013 1.06 added esd ratings and msl to absolute maximum conditions 9/24/2013 1.05 updated conditions for v air in electriical characteristics for clarity. updated section 13 to clarify counter functionality. 7/16/2013 1.04 fixed typo in section 15.1 diagram 06/04/2013 1.03 updated 3bit lut and 4bit lut standard digital functions tables 02/05/2013 1.02 SLG46400 rev. b: updated adc functional diagram (figure 3) updated acmp0 in+ source selection information and acmp0 functional diagram (sec - tion 10.1 and figure 8) updated acmp0 register settings (reg<735> and reg<739>) corrected fsm0 and fsm1 up/down operatio n descriptions (sections 13.7 and 13.9, figures 19 and 21) added frequency dividers control function description (section 16.3) updated rc osc register settings updated rc osc typical frequency selection, table 24 updated register definition (rc os c frequency control, reg<586:583>) updated register definition (acmp0 in + source selection, reg<739, 735>) updated register definition (rc osc dividers control, reg<816>) 11/19/2012 1.01 updated electrical characteristics table (vil values) fixed typo in section 10.9 (less than or equal sign) 9/19/2012 1.0 fixed typo in section 10.9 description 7/27/2012 0.92 fixed typo in electrical characteristics table updated section 12.2 for clarification 7/16/2012 0.91 editorial changes for clarification and typo fixes throughout renamed signal names to match greenpak designer software moved bi-directional pin example to section 21.0 6/27/2012 0.9 updated electrical characteristics table corrected section 9.4 regarding 2-channe l selection (pin 12 instead of pin 2) updated section10.0 to clarify acmp power down operation and fixed acmp hysteresis values in sections 6.4, 10.9, and 10.10.1 updated section 12.10 regarding poiwer down control renamed section 16.0 rc oscillator to clock ma nagement and clarified operation and updated block diagram. updated section 13.12 to include short pulse delay time diagrams. removed application example regarding time delay updated register map 6/8/2012 0.85 updated section 13.4 added note regarding minimum value of the register setting for the cnt/dly cells 3/20/2012 0.84 editorial changes for clarification and typo fixes throughout 1/27/2012 0.83 editorial changes for clarification and typo fixes throughout updated section 9.9 adc outputs updated section 13.1 counter functionality updated section 13.7 and 13. 9 regarding fsm operation updated recommended soldering profile information 12/5/2011 0.82 added recommended soldering profile information 11/3/2011 0.81 added bi-directional pin information 9/19/2011 0.8 production release 9/18/2011 0.53 general updates
000-0046400-109 page 88 of 89 SLG46400 10/20/2010 0.1 preliminary datasheet date version change
000-0046400-109 page 89 of 89 SLG46400 28.0 silego website & support 28.1 silego technology website silego technology provides on line support via our website at http://www.silego.com/ .this web site is used as a means to make files and information easily available to customers. for more information regarding silego greenpak a nd other silego green products, please visit: http://greenpak.silego.com/ http://greenfet.silego.com/ http://greenpak2.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ products are also available for purchase directly from silego at the silego online store at http://store.silego.com/ . 28.2 silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the sil ego website or can be r equested directly at info@silego.com . for specific greenpak design or applications ques tions and support please send email requests to greenpak@silego.com users of silego products can receive assistance through several channels: 28.2.1 contact your local sales representative customers can contact their local sales re presentative or field application engineer (fae) for support. local sales offices are also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com 28.2.2 contact silego directly silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following weblink: http://support.silego.com/ 28.3 other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices a nd representatives are all available at http://www.silego.com/ this product has been designed and qualif ied for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technolo gy does not assume any liabili ty arising out of such appli - cations or uses of its products. silego technology reserves th e right to improve product design, functions and reliability without notice .

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