1 description lt c2358/lt c2357/ lt c2353 /lt c2333: 16-/18-bit, octal, quad and dual 200ksps/350ksps/550ksps/800ksps sar adcs demonstration circuit 2365a highlights the ltc ? 2358 family of buffered input adcs. the ltc2358/ltc2357/ LTC2353/ltc2333 are low noise, high speed, 16-/18- bit successive approximation register (sar) adcs with integrated front end buffers. these adcs accept a wide common mode range. pico-amp inputs and high cmrr enable these adcs to connect directly to a wide range of sensors without compromising measurement accuracy. the following text refers to the ltc2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. the ltc2358-18 has a flexible softspan? interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. an internal 2.048v reference and 2x buffer simplify basic operation while an external reference can be used to increase the input range and the snr of the adc. the dc2365 a demonstrates the dc and ac performance of the ltc2358 -18 in conjunction with the dc590/ dc2026 and dc890 data collection boards. use the dc590/dc2026 to demonstrate dc performance such as peak-to-peak noise and dc linearity. use the dc890 if precise sampling rates are required or to demonstrate ac performance such as snr, thd, sinad and sfdr. the dc2365 a is intended to demonstrate recommended grounding, component placement and selection, routing and bypassing for this adc. a simple driver circuit for the analog inputs is also presented. design files for this circuit board including schematics, bom and layout are available at http://www.linear.com/ demo/dc2365a l , lt, ltc, ltm, linear technology, linduino and the linear logo are registered trademarks and softspan, pscope and quikeval are trademarks of of analog devices, inc. all other trademarks are the property of their respective owners. dc2365afa demo manual dc2365a
2 board photo ?16v gnd +16v clk 100mhz max, 2.5v p-p dc590 or dc2026 dc890 10.24v default input levels 10.24v dc2365 f01 figure?1. dc2365a connection diagram dc2365afa demo manual dc2365a
3 dc890 quick start procedure check to make sure that all switches and jumpers are set to their default settings as described in the dc2365a jumpers section of this manual. the default connections configure the adc to use the onboard reference and regula - tors to generate all the required bias voltages. the analog inputs by default are dc-coupled. connect the dc2365a to a dc890 usb high speed data collection board using connector p1 . then, connect the dc890 to a host pc with a standard usb a/b cable. apply 16v to the indicated terminals. then apply a low jitter signal source to j5 and j6. use j7 to route the signal sources of j5 and j6 to the desired ain0Cain7 inputs. observe the recommended input voltage range for each analog input. connect a low jitter 2.5v p-p sine wave or square wave to connector j1. see table 1 for the appropriate clock frequency. note that j1 has a 50 termination resistor to ground. run the pscope? software (pscope.exe version k94 or later) which can be downloaded from www.linear.com/ designtools/software. complete software documentation is available from the help menu. updates can be downloaded from the tools menu. check for updates periodically as new features may be added. the pscope software should recognize the dc2365a and configure itself automatically. click the collect button (figure?2) to begin acquiring data. the collect button then changes to pause, which can be clicked to stop data acquisition. assembly options table 1. dc2365a assembly options assembly version u1 part number max conversion rate number of channels number of bits max clkin frequency clkin/fs ratio dc2365a-a ltc2358-18 200ksps 8 simultaneous 18 60mhz 300 dc2365a-b ltc2357-18 350ksps 4 simultaneous 18 60.2mhz 172 dc2365a-c LTC2353-18 550ksps 2 simultaneous 18 49.5mhz 90 dc2365a-d ltc2333-18 800ksps 8 multiplexed 18 50.4mhz 63 dc2365a-e ltc2358-16 200ksps 8 simultaneous 16 60mhz 300 dc2365a-f ltc2357-16 350ksps 4 simultaneous 16 60.2mhz 172 dc2365a-g LTC2353-16 550ksps 2 simultaneous 16 49.5mhz 90 dc2365a-h ltc2333-16 800ksps 8 multiplexed 16 50.4mhz 63 dc2365afa demo manual dc2365a
4 dc890 quick start procedure figure?2. pscope screen capture dc2365afa demo manual dc2365a
5 dc590/dc2026 quick start procedure important! to avoid damage to the dc2365a, make sure that vccio ( jp6 of the dc590, jp3 of the dc2026) of the dc590/dc2026 is set to 3.3v before connecting the dc590/dc2026 to the dc2365a. to use the dc590/dc2026 with the dc2365a, it is nec - essary to apply 16v and ground to the 16v and gnd terminals of the dc2365a. connect the dc590/dc2026 to a host pc with a standard usb a/b cable. connect the dc2365a to a dc590/dc2026 usb serial controller using the supplied 14- conductor ribbon cable. apply a signal source to j5 and j6. use j7 to route the signal sources of j5 and j6 to the desired ain0Cain7 inputs. no clock is required on j1 when using the dc590/dc2026. the clock signal is provided by the dc590/dc2026. run the quikeval? software (quikeval.exe version k108 or later) which is available from www.linear.com/designtools/ software . the correct control panel will be loaded au - tomatically. click the collect button (figure?3) to begin reading the adc. figure?3. quikeval screen capture dc2365afa demo manual dc2365a
6 dc2365a setup dc power the dc2365 a requires 16vdc and draws +80ma/C6ma. most of the supply current is consumed by the cpld, regulators and discrete logic on the board. the 16vdc input voltage powers the adc through lt1763 and lt1964 regulators which provide protection against accidental reverse bias. additional regulators provide power for the cpld and external reference. clock source you must provide a low jitter 2.5v p-p sine or square wave to the clock input, j1. the clock input is ac coupled so the dc level of the clock signal is not important. a generator such as the rohde & schwarz s mb100a high speed clock source is recommended to drive the clock input. even a good generator can start to produce noticeable jitter at low frequencies. therefore it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate. the ratio of clock frequency to conversion rate is shown in table 1. if the clock input is to be driven with logic, it is recommended that the 49.9 termination resistor (r4) be removed. driving r4 with discrete logic may result in slow rising edges. these slow rising edges may compromise the snr of the converter in the presence of high-amplitude higher frequency input signals. data output parallel data output from this board ( 0v to 2.5v default), if not connected to the dc890, can be acquired by a logic analyzer, and subsequently imported into a spreadsheet, or mathematical package depending on what form of digital signal processing is desired. alternatively, the data can be fed directly into an application circuit. use pin 50 of p1 to latch the data. the data should be latched using the negative edge of this signal. the data output signal levels at p1 can also be increased to 0v to 3.3v if the application circuit requires a higher voltage. this is accomplished by moving jp2 to the 3.3v position. reference the default reference is the ltc2358-18 internal 4.096v reference. alternatively, if a higher reference voltage is de - sired, the ltc6655-5 reference (u7 ) can be used by setting the ref jumper (jp1 ) to the ext position and installing a 0 resistor in the r7 position as shown in figure?4. this should result in better snr performance but may slightly degrade the thd performance of the ltc2358-18. v + 5v c13 1f c12 2.2f c15 1f 50v c11 47f 10v 1210 x7r refin refbuf 1921 r7 0 refbuf refbuf e1 dc2365 f04 shdn vin gnd gnd gnd vout_f vout_s gnd 8 7 6 5 1 2 3 4 u7 ltc6655bhms8-5 1 2 3 int ext jp1 ref figure?4. external reference option for dc2365a analog inputs all eight inputs have the same driver circuitry. an example of the default driver circuit for the analog inputs of the ltc2358-18 on the dc2365 a is shown in figure?5. the circuit of figure?5 provides a pseudo-differential output to channel 0 of the ltc2358-18 with a maximum 10.24v input voltage. alternatively, the jumpers for ai n0 at jp5 and j7 can be removed and ain0 can be driven fully dif - ferentially externally through a twisted pair cable at the provided terminals at jp5 . fully differential drive should provide a slight improvement in thd performance. dc890 data collection for sinad, thd or snr testing, a low noise, low distor - tion generator such as the b&k type 1051 or stanford resear ch s r1 should be used. a low jitter rf oscillator such as the rohde & schwarz s mb100a is used to drive the clock input. this demo board is tested in house by attempting to duplicate the fft plot shown in typical dc2365afa demo manual dc2365a
7 dc2365a setup performance characteristics section of the ltc2358-18 data sheet. this involves using a 60mhz clock source along with a sinusoidal generator at a frequency of ap - proximately 2khz . the input signal level is approximately C 1dbfs . a typical fft obtained with the dc2365 a is shown in figure?2. note that to calculate the real snr, the signal level (f1 amplitude? =?C1.023db ) has to be added back to the snr that pscope displays. with the example shown in figure?2, this means that the actual snr would be 96.76db instead of the 95.74db that pscope displays. taking the rms sum of the recalculated snr and the thd yields a sinad of 96.58db which is fairly close to the typical number for this adc. to change the default settings for the ltc2358-18 in pscope, click on the set demo bd options button in the pscope tool bar shown in figure? 6. this will open the configure channels menu of figure?7. in this menu it is possible to set the input softspan range setting for each channel. there is also a button to return pscope to the default dc2365 a settings which are optimized for the default hardware settings of the dc2365a. there are a number of scenarios that can produce mislead - ing results when evaluating an adc. one that is common is feeding the converter with an input frequency, that is a sub-multiple of the sample rate, and which will only exercises a small subset of the possible output codes. the proper method is to pick an m/n frequency for the input sine wave frequency. n is the number of samples in the fft. m is a prime number between one and n/2. multiply m/n by the sample rate to obtain the input sine wave frequency. another scenario that can yield poor results is if you do not have a signal generator capable of ppm frequency accuracy or if it cannot be locked to the clock frequency. you can use an fft with windowing to reduce the leakage or spreading of the fundamental to get a close approximation of the adc performance. if an amplifier or clock source with poor phase noise is used, the windowing will not improve the snr. figure?5. 10.24v pseudo-differential dc coupled driver c96 opt r108 0 c112 opt c97 opt r109 0 c95 opt 0805 r107 0 0603 c94 opt 0805 r106 0 0603 bnc bnc j5 j7 hd3x8-100 j6 dc2365 f05 1 3 5 2 4 6 17 9 18 10 19 11 20 12 21 13 22 14 23 15 24 16 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 1 2 3 4 5 6 7 8 ? jp5 hd1x3-100 ain0 ain0 ? ain0 + v in2 v in1 v in2 10.24v max v in1 10.24v max + dc2365afa demo manual dc2365a
8 dc2365a setup figure?6. pscope tool bar figure?7. pscope channel configuration menu figure?8. quikeval channel configuration menu dc2365afa demo manual dc2365a
9 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. dc2365a setup dc2365a jumpers dc2365a connectors dc590/dc2026 data collection due to the relatively low and somewhat unpredictable sample rate of the dc590 / dc2026 , its usefulness is limited to noise measurement and data collection of slowly moving signals. a typical data capture and histogram are shown in figure?3. to change the default settings for the ltc2358-18 in quikeval, click on the channel config button. this will open the config dialog menu of figure?8. using the config dialog menu, it is possible to set the input signal range for each sequence. there is also a button to return quikeval to the default dc2365a settings which are optimized for the default hardware settings of the dc2365a. layout as with any high performance adc, this part is sensitive to layout. the area immediately surrounding the adc on the dc2365 a should be used as a guideline for place - ment and routing of the various components associated with the adc. here are some things to remember when laying out a board for the ltc2358 -18. a ground plane is necessary to obtain maximum performance. keep bypass capacitors as close to supply pins as possible. use indi - vidual low impedance returns for all bypass capacitors. use of a symmetrical layout around the analog inputs will minimize the effects of parasitic elements. shield analog input traces with ground to minimize coupling from other traces. keep traces as short as possible. component selection when driving a low noise, low distortion adc such as the l t c2358 -18, component selection is important so as to not degrade performance. resistors should have low values to minimize noise and distortion. metal film resistors are recommended to reduce distortion caused by self heating. because of their low voltage coefficients, to further reduce distortion, np0 or silver mica capacitors should be used. any buffer used to drive the ltc2358-18 should have low distortion and low noise such as the lt1355 or ltc2057. definitions jp1: ref selects int or ext reference for the adc. the default setting is int. jp2: vccio sets the output levels at p1 to either 3.3v or 2.5v . use 2.5v to interface to the dc890 which is the default setting. use 3.3v to interface to the dc2026. jp3: i/o selects lvds or cmos logic levels. the default setting is cmos. lvds is not supported at this time. jp4: eeprom is for factory use only. the default position is wp. jp5-jp12: can be used to short either the + or C input of ain0-ain7 to ground. the individual ain inputs can also be driven directly through these terminals. the default is to short the C input of ain0Cain7 to ground. definitions p1: dc890 interface is used to communicate with the dc890 controller. j1: clk provides the master clock for the dc2365a when interfaced to the dc890. this is not used for quikeval. j2: fpga program is used to program the fpga. this is for factory use only. j3: jtag is for factory use only. j4: dc590/dc2026 interface is used to communicate with the dc2026 linduino ? controller or dc590. j5 and j6: v in1 , v in2 provide analog input voltages to ain0Cain7 of the adc. j7: routes the signals of j5 and j6 to ain0Cain7. dc2365afa demo manual dc2365a
10 ? linear technology corporation 2016 lt 0517 rev a ? printed in usa demonstration board important notice linear technology corporation (ltc) provides the enclosed product(s) under the following as is conditions: this demonstration board (demo board) kit being sold or provided by linear technology is intended for use for engineering development or evaluation purposes only and is not provided by ltc for commercial use. as such, the demo board herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. as a prototype, this product does not fall within the scope of the european union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. if this evaluation kit does not meet the specifications recited in the demo board manual the kit may be returned within 30 days from the date of delivery for a full refund. the foregoing warranty is the exclusive warranty made by the seller to buyer and is in lieu of all other warranties, expressed, implied, or statutory, including any warranty of merchantability or fitness for any particular purpose. except to the extent of this indemnity, neither party shall be liable to the other for any indirect, special, incidental, or consequential damages. the user assumes all responsibility and liability for proper and safe handling of the goods. further, the user releases ltc from all claims arising from the handling or use of the goods. due to the open construction of the product, it is the users responsibility to take any and all appropriate precautions with regard to electrostatic discharge. also be aware that the products herein may not be regulatory compliant or agency certified (fcc, ul, ce, etc.). no license is granted under any patent right or other intellectual property whatsoeve r. ltc assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. ltc currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. please read the demo board manual prior to handling the product. persons handling this product must have electronics training and observe good laboratory practice standards. common sense is encouraged. this notice contains important safety information about temperatures and voltages. for further safety concerns, please contact a ltc application engineer. mailing address: linear technology 1630 mccarthy blvd. milpitas, ca 95035 copyright ? 2004, linear technology corporation dc2365afa demo manual dc2365a
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