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L4992 triple output power supply controller dual pwm buck controllers (3.3v and 5.1v) 12v/120ma linear regulator dual synch rectifiers drivers 96% efficiency achievable 50 m a (@ 12v) stand by consumption 5.5v to 25v supply voltage excellent load transient response disable pulse skipping function power management: - under and overvoltage output detection - power good signal - separated disable thermal shutdown package: tqfp32 application notebook and subnotebook com- puters pen top and portable equipment communicating computers description the L4992 is a sophisticated dual pwm step- down controller and power monitor intended for notebook computer and/or battery powered equipment. the device produces regulated +3.3v, +5.1v and 12v supplies for use in portable and pcmcia applications. the internal architecture allows to operate with minimum external components count. a very high switching frequency (200/300 khz or externally synchronizable) optimizes their physical dimen- sions. synchronous rectification and pulse skipping mode for the buck sections optimise the overall efficiency over a wide load current range (96% ef- ficiency @1a/5.1v and 93% efficiency @ 0.05a/5.1v. the two high performance pwm controllers for +3.3v and +5.1v lines are monitored for overvol- tage, undervoltage and overcurrent conditions. on detection of a fault, a power good signal is generated and a specific shutdown procedure takes place to prevent physical damage and data corruption. a disable function allows to manage the output power sections separately, optimising the quies- cent consumption of the ic in stand-by conditions. june 2000 ? sync power management & system supervisor 5.5v to 25v 3.3v 5.1v power section L4992 m p memory peripherals 12v ldo 5.1v ldo 3.39v ref d96in429a power good system block diagram tqfp32 ordering number: L4992 1/26
absolute maximum ratings symbol parameter value unit v in power supply voltage on v in 0 to 25 v v i maximum pin voltage to pins 1, 24, 25, 32 -0.5 to (v in +5) v i in input current except v13in and v in -1 to +1 ma i out output current digital output -15 to +15 ma t j junction temperature -55 to 150 c thermal data symbol parameter value unit r th j-amb thermal resistance junction -ambient 60 c/w slope + - + - + - ? error summing i5sns v5sns 6 5 vref 7 comp5 1 32 31 h5strap h5gate h5src 30 29 r5gate pgnd5 hside lside control logic over current comparator zero crossing comparator pulse skipping comparator + - + - + - soft i5sns v5sns 8 soft5 slope + - + - + - ? error summing i3sns v3sns 19 20 vref 18 comp3 24 25 26 h3strap h3gate h3src 27 28 r3gate pgnd3 hside lside control logic over current comparator zero crossing comparator pulse skipping comparator + - + - + - soft i3sns v3sns 17 soft3 linear regulator switch comparator v5sns 4.7v w5sw reg5 3 4 2 vin vref vref buffer overvolt comparator undervolt comparator power management & system supervisor 12 vref 13 sgnd 13v + - + - 13v uv comp 16 11 10 14 9 run3 run5 pwrok noskip crst v13in 21 + - reg12 22 vref oscillator & synchronization osc 15 reg12 ldo d96in375 + - reg5 reg5 block diagram 1 2 3 5 6 4 7 8 11 12 13 14 15 16 32 30 31 29 28 27 26 25 19 18 17 24 23 22 20 21 i5sns v5sns v5sw vin h5strap reg5 comp5 soft5 crst run5 pwrok vref sgnd noskip osc run3 h5gate r5gate h5src pgnd5 pgnd3 r3gate h3src h3gate i3sns comp3 soft3 h3strap (*) reg12 v3sns v13in d96in377 910 (*)to be connected to pin13 pin connection (top view) L4992 2/26
pin functions n. name description 1 h5strap +5.1v section bootstrap capacitor connection 2v in device supply voltage. from 5.5 to 25v 3 reg5 +5v regulator supply. used mainly for bootstrap capacitors. it should be bypassed to ground. 4 v5sw alternative device supply voltage. when the +5.1v section is operating, the device is no longer powered through v in but through this pin. 5 v5sns this pin connects to the (-) input of the +5.1v internal current sense comparator 6 i5sns this pin connects to the (+) input of the +5.1v internal current sense comparator 7 comp5 feedback input for the +5.1v section. 8 soft5 soft-start input of the +5.1v section. the soft-start time is programmed by an external capacitor connected between this pin and sgnd. approximately, 1ms/nf @ full load. 9 crst input used for start-up and shut-down timing. a capacitor defines a time of 2ms/nf. 10 pwrok power-good diagnostic signal. this output is driven high when both switching sections are enabled and running properly, after a delay defined by the crst capacitor. 11 run5 control input to enable/disable the 5.1v section. a high level (>2.4v) enables this section, a low level (<0.8v) shuts it down 12 vref internal +3.39v high accuracy voltage generator. it can source 5ma to external load. bypass to ground with a 4.7 m f capacitor to reduce noise. 13 sgnd signal ground. reference for internal logic circuitry. it must be routed separately from high current returns. 14 noskip pulse skipping mode control. a high level (>2.4v) disables pulse skipping at low load current, a low level (<0.8v) enables it. 15 osc oscillator frequency control: connect to 2.5v to select 300khz operation, to ground or to 5v for 200khz operation. a proper external signal can synchronize the oscillator 16 run3 control input to enable/disable the +3.3v section. a high level (>2.4v) enables this section, a low level (>0.8v) shuts it down. 17 soft3 soft-start input for the 3.3v section. the soft-start time is programmed by an external capacitor connected between this pin and gnd. approximately, 1ms/nf @full load. 18 comp3 feedback input for the +3.3v section 19 i3sns this pin connects to the (+) input of the +3.3v internal current sense comparator 20 v3sns this pin connects to the (-) input of the +3.3v internal current sense comparator 21 v13in 12v regulator input supply voltage, included between 13 and 20v. this voltage can be supplied by a flyback winding on +3.3v inductor 22 reg12 12v regulator output voltage. it can source up to 150ma to an external load 23 sgnd to be connected to pin 13 24 h3strap +3.3v section bootstrap capacitor connection 25 h3gate gate- driver output for the +3.3v high-side n-mos 26 h3src +3.3v high-side n-mos source connection 27 r3gate gate- driver output for the +3.3v low- side n-mos (synchronous rectifier). 28 pgnd3 current return for +3.3v section drivers 29 pgnd5 current return for +5.1v section drivers 30 r5gate gate-driver output for the +5.1v low-side n-mos (synchronous rectifier). 31 h5src +5.1v high-side n-mos source connection 32 h5gate gate-driver output for the +5.1v high-side n-mos L4992 3/26
electrical characteristics (v in = 12v; t j = 25c; v osc = gnd; unless otherwise specified.) symbol parameter test condition min. typ. max. unit dc characteristics v in input supply voltage 5.5 25 v i 2 operating quiescent current r5gate = r3gate = open h5gate = h3gate = open run3 = run5 = reg5 (drivers off) 1.35 ma i 2 stand-by current run3 = run5 = gnd v in = 12v v in = 20v 50 60 100 120 m a +5.1v pwm controller section v 5out (*) v5sns feedback voltage v in = 5.5 to 20v; v i5sns - v v5sns = 0 to 70mv 4.85 5.13 5.25 v v 6 - v 5 over-current threshold voltage vsoft5 = 4v 80 100 120 mv v 6 - v 5 pulse skipping mode thereshold voltage v in > 6.8v 14 26 38 mv v in < 5.8v 7 13 19 mv v 5 over voltage threshold on v5sns 5.35 5.55 5.77 v under voltage threshold on v5sns 4.54 4.69 4.87 v +3.3v pwm controller section v 3out (*) v3sns feedback voltage v in = 5.5 to 20v; v i3sns - v v3sns = 0 to 70mv 3.285 3.39 3.495 v v 19 - v 20 over current threshold voltage vsoft3 = 4v 80 100 120 mv v 19 - v 20 pulse skipping mode threshold voltage v in = 5.5 to 20v; 14 26 38 mv v 20 over voltage threshold on v3sns 3.55 3.7 3.85 v under voltage threshold on v3sns 3.02 3.14 3.27 v pwm controllers characteristics (both sections) f osc switching frequency accuracy osc = reg5/2 255 300 345 khz osc = 0 or reg5 170 200 230 khz v 15 voltage range for 300khz operation 2.4 2.6 v t off dead time 300 375 450 ns t ov overvoltage propagation time v5sns to pwrok or v3sns to pwrok 1.25 m s t uv undervoltage propagation time v5sns to pwrok or v3sns to pwrok 1.5 m s i 8 , i 17 soft start charge current 3.2 4 4.8 m a v 8 , v 17 soft start clamp voltage 4 v (*) guaranteed by design, not tested in production L4992 4/26
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit high and low side gate driver (both sections) i 25 , i 27, i 32 , i 30 source output peak current c load = 1nf 0.2 0.5 a sink output peak current c load = 1nf 0.2 0.5 a r h r dson resistance (or impedance) driver out high 7 w r l r dson resistance (or impedance) driver out low 5 w v oh output high voltage hstrap = reg5 i source = 10ma; hsrc = gnd 4.40 5.3 5.61 v v ol output low voltage hstrap = reg5 i sink = 10ma hsrc = gnd 0.5 v t cc cross-conduction delay 30 75 130 ns 12v linear regulator section v 21 input voltage range 13 20 v v 22 output voltage i 22 = 0 to 120ma 11.54 12.0 12.48 v i 22 current limiting v reg12 = 12v 120 ma short circuit current v reg12 = 0v 150 ma v cp input voltage clamp i clamp = 100 m a16 v "one shot" activation threshold v 13in falling 12.88 13.7 14.52 v "one shot" pulse 1.5 m s internal regulator (vreg5) and reference voltage v 3 vreg5 output voltage v in = 5.5 to 20v i load = 0 to 5ma 4.5 5.3 5.61 v i 3 total current capability vreg5 = 5.3v v reg5 = 6v 25 70 ma switch-over threshold voltage 4.3 4.53 4.7 v v 12 reference voltage 3.35 3.39 3.43 v v in = 5.5 to 20v i load = 1 to 5ma 3.32 3.39 3.46 v i 12 source current at reference voltage 5ma power good and enable function v 16 , v 11 run3, run5, enable voltage high level 2.4 v v 16 , v 11 run3, run5, disable voltage low level 0.8 v t 10 power good delay c crst = 100nf 160 200 240 ms t 27 , t 30 shutdown delay time before low side activation (except over-voltage fault) c crst = 100nf, 160 200 240 ms crst timing rate 2 ms/nf power good high level i pwrok = 40 m a 4.1 v power good lowlevel i pwrok = 320 m a 0.4 v synchronization synchronisation pulse width 400 ns synchronisation input voltage (falling edge transition) 5v L4992 5/26
detailed functional description in the L4992 block diagram six fundamental functional blocks can be identified: 3.3v step-down pwm switching regulator (pins 17 to 20, 24 to 27). 5.1v step-down pwm switching regulator (pins 1, 4 to 8, 30 to 32). 12v low drop-out linear regulator (pins 21,22). 5v low drop-out linear regulator (pin 3). 3.3v reference voltage generator (pin 12). power management section (pins 9 to 11, 14,16). the chip is supplied through pin vin (2), typically by a battery pack or the output of an ac-dc adapter, with a voltage that can range from 5.5 to 25v. the return of the bias current of the device is the signal ground pin sgnd (13), which references the internal logic circuitry. the drivers of the external mosfets have their separate current return for each section, namely the power ground pins pgnd3 (28) and pgnd5 (29). take care of keeping separate the routes of signal ground and the two power ground pins when laying out the pcb (see "layout and grounding" section). the two pwm regulators share the internal oscillator, programmable or synchronizable through pin osc (15). +3.3v and +5.1v pwm regulators each pwm regulator includes control circuitry as well as gate-drive circuits for a step-down dc-dc con- verter in buck topology using synchronous rectification and current mode control. the two regulators are independent and almost identical. as one can see in the block diagram, they share only the oscillator and the internal supply and differ for the pre-set output voltages and for the con- trol circuit that links the +3.3v section to the operation of the 12v linear regulator (see the relevant sec- tion). each converter can be turned on and off independently: run3 and run5 are control inputs which dis- able the relevant section when a low logic level (below 0.8 v) is applied and enable its operation with a high logic level (above 2.4 v). when both inputs are low the device is in stand-by condition and its cur- rent consumption is extremely reduced (less than 120 m a over the entire input voltage range). oscillator the oscillator, which does not require any external timing component, controls the pwm switching fre- quency. this can be either 200 or 300 khz, depending on the logic state of the control pin osc, or else can be synchronized by an external oscillator. if osc is grounded or connected to pin reg5 (5v) the oscillator works at 200khz. by connecting osc to a 2.5 v voltage, 300 khz operation will be selected. instead, if pin osc is fed with an external signal like the one shown in fig. 1, the oscillator will be synchronized by its falling edges. considering the spread of the oscillator, synchronization can be guaranteed for frequencies above 230khz. even though a maximum frequency value is in practice imposed by efficiency considerations it should be noticed that increasing frequency too much arises problems (noise, subharmonic oscillation, etc.) without significant benefits in terms of external component size reduction and better dynamic per- formance. the oscillator imposes a time interval (300 ns min.), during which the high-side mosfet is definitely off, to recharge the bootstrap capacitor (see "mosfets drivers" section). this, implies a limit on the maximum duty cycle (88.5% @ fsw = 300khz, 92.6% @ fsw = 200khz, worst case) which, in turn, im- poses a limit on the minimum operating input voltage. pwm regulation the control loop does not employ a traditional error amplifier in favour of an error summing comparator which sums the reference voltage, the feedback signal, the voltage drop across an external sense resis- tor and a slope compensation ramp (to avoid subharmonic oscillation with duty cycles greater then 50%) with the appropriate signs. the output latch of both controllers is set by every pulse coming from the oscillator. that turns off the low-side mosfet (synchronous rectifier) and, after a short delay (typ. 75 ns) to prevent cross-conduc- tion, turns on the high-side one, thus allowing energy to be drawn from the input source and stored in the inductor. L4992 6/26
t t t 5v osc 0v h5gate h3gate d97in574 400ns min. figure 1: synchronization signal and operation. detailed functional description (continued) clock s r q q _ reg5 hstrap l rsense e.s. + - + - - + vref slope comp. vin rf cf co esr ro figure 2: L4992 control loop. the error summing, by comparing the above mentioned signals, determines the moment in which the output latch is to be reset. the high-side mosfet is then turned off and the synchronous rectifier is turned on after the appropriate delay (typ. 75 ns), thus making the inductor current recirculate. this state is maintained until the next oscillator pulse. with reference to the schematic of fig. 2, the open-loop transfer function of such a kind of control system, under the assumption of an ideal slope compensation, is: f ( s ) = a r o r sense 1 + s esr c o ( 1 + s r o c o ) ( 1 + s r f c f ) where a is the gain of the error summing comparator, which is 2 by design. the system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-by- cycle basis. actually, in case of line or load changes, few switching cycles can be sufficient for the tran- sient to expire. the operation above illustrated is modified during particular or anomalous conditions. leaving out other circumstances (described in "protections" section) for the moment, consider when the load current is low enough or during the first switching cycles at start-up: the inductor current may become discontinuous, that is it is zero during the last part of each cycle. in such a case, a "zero current comparator" detects the event and turns off the synchronous rectifier, avoiding inductor current reversal and reproducing the natural turn-off of a diode when reverse biased. both mosfets stay in off state until the next oscillator pulse. L4992 7/26
synchronous rectification. very high efficiency is achieved at high load current with the synchronous rectification technique, which is particularly advantageous because of the low output voltage. the low-side mosfet, that is the syn- chronous rectifier, is selected with a very low on-resistance, so that the paralleled schottky diode is not turned on, except for the small time in which neither mosfet is conducting. the effect is a considerable reduction of power loss during the recirculation period. although the schottky might appear to be redundant, it is not in a system where a very high efficiency is required. in fact, its lower threshold prevents the lossy body-diode of the synchronous rectifier mosfet from turning on during the above mentioned dead-time. both conduction and reverse recovery losses are cut down and efficiency can improve of 1-2% in some cases. besides a small diode is sufficient since it conducts for a very short time. as for the 3.3v section only, the synchronous rectifier is also involved in the 12 v linear regulator opera- tion (see the relevant section). see also the "power management" to see how both synchronous rectifi- ers are used to ensure zero voltage output in stand-by conditions or in case of overvoltage. pulse-skipping operation. to achieve high efficiency at light load current as well, under this condition the regulators change their operation (unless this feature is disabled): they abandon pwm and enter the so-called pulse-skipping mode, in which a single switching cycle takes place every many oscillator periods. the "light load condition" is detected when the voltage across the external sense resistor (v rsense ) does not exceed 26mv while the high-side mosfet is conducting. when the reset signal of the output latch comes from the error summing comparator while v rsense is below this value, it is ignored and the actual reset is driven as soon as v rsense reaches 26mv. this gives some extra energy that maintains the output voltage above its nominal value for a while. the oscillator pulses now set the output latch only when the feedback signal indicates that the output voltage has fallen below its nominal value. in this way, most of oscillator pulses is skipped and the resulting switching frequency is much lower, as expressed by the fol- lowing relationship: f ps = k r sense 2 l i out v out ? ? 1 - v out v in ? ? where k = 3.2 10 3 and f ps is in hz. as a result, the losses due to switching and to gate-drive, which mostly account for power dissipation at low output power, are considerably reduced. the +5.1v section can work with the input voltage very close to the output one, where the current waveform may be so flat to prevent pulse-skipping from being activated. to avoid this, the pulse-skip- ping threshold (of the +5.1v section only) is roughly halved at low input voltages, as shown in fig. 3. under this condition, in the above formula the constant k becomes 12.8 10 3 . when in pulse-skipping, the output voltage is some ten mv higher than in pwm mode, just be- cause of its mode of operation. if this "load regula- tion" effect is undesirable for any reason, the pulse skipping feature can be disabled (see "power management" section) to the detriment of effi- ciency at light load. mosfets drivers to get the gate-drive voltage for the high-side n-channel mosfet a bootstrap technique is employed. a capacitor is alternately charged through a diode from the 5v reg5 line when the high-side mosfet is off and then connected to its gate-source leads by the internal floating driver to turn the mosfet on. the reg5 line is used to drive the synchronous rectifier as well, and therefore the use of low-threshold vth vin 26 mv 13 mv 5.5v 5.8v 6.3v 20v figure 3: pulse-skipping threshold vs. input voltage (+5.1v section only). detailed functional description (continued) L4992 8/26
mosfets (the so-called "logic-level" devices) is highly recommended. the drivers are of "dynamic" type, which means they do not give origin to current consumption when they are in static conditions (on or off), but only during transitions. this feature is aimed at minimizing the power consumption of the device even during stand-by when both low-side mosfets are on. protections each converter is fully protected against fault conditions. a monitoring system checks for overvoltages of the output, quickly disabling both converters in case such an event occurs. this condition is latched and to allow the device to start again either the supply voltage has to be removed or both run3 and run5 pins have to be driven low. undervoltage conditions are detected as well but do not cause interruption of the operation of the convert- ers. only pwrok signal (at pin 10) reveals the anomaly with a low output level. if the chip overheats (above 135 c typ.) the device stops operating as long as the temperature falls below a safe value (105 c typ.). the overtemperature condition is signalled by a low level on pwrok as well. a current limitation comparator prevents from excessive current in case of overload or short-circuit. it in- tervenes as the voltage vrsense exceeds 100 mv, turning off the high-side switch before the error sum- ming does. by the way, this also gives the designer the ability to program the maximum operating current by selecting an appropriate sense resistor. this pulse-by-pulse limitation gives a quasi-constant current characteristic. if a "folded back" charac- teristic, like the one shown in fig. 4a, is desired the external circuit of fig. 4b can be used. the circuits acts on the current limitation and is extremely simple and cheap. the advantage of such a technique i that a short circuit will cause a current much lower than the maximum to flow. th e stress of the power components will be very little and no overheating will occur. the part values shown in fig. 4b produce ifold = 1a in the demo board (see the relevant section). inrush current at start-up is reduced with soft-start. an external capacitor (one for each converter) is charged by an internal 4 m a current generator and its linearly ramping voltage increases the setpoint of the current limit comparator, starting from zero up to the final value of 100 mv. thus duty cycle reaches gradually its steady-state value and dangerous current peaks as well as overshoots of the output voltage are avoided. +12 v linear regulator the +12v linear regulator is capable of delivering up to 120 ma to an external load through pin reg12. it is supplied from pin v13in which accepts voltages included in the range of 13 to 20v. if the application works with input voltages included between 14 and 20v, the supply for the regulator can be obtained directly from the input source. if such is not the case, the most convenient way to get the supply is to use an auxiliary winding on the 3.3 v section inductor with a catch diode, ds, and a filter capacitor, cs, as shown in fig. 5. this winding delivers energy to pin v13in during the recirculation pe- riod of each switching cycle with a voltage determined by the turns ratio n and little dependent on the in- put voltage. detailed functional description (continued) L4992 31(26) 32(25) r sense 100 w 6.8k w (3.9k w ) c o 5v(3.3v) d98in815 l 30(27) 1n4148 12 6(19) 5(20) v in (b) i fold i max v ref -v f -0.1 v o i o (a) figure 4. L4992 9/26
an auxiliary winding could be used also on the choke of the +5.1v section, either to power the +12v lin- ear regulator or to derive a further supplemental output, however the 3.3 v section has been provided with some features aimed at ensuring a proper operation under all circumstances. for a correct operation of the regulator, the voltage at pin v13in must not be too low. the flyback con- nection of the two windings ensures a well regulated voltage, provided there is good magnetic coupling. the coupled inductors configuration, however, is not able to sustain the auxiliary voltage if the main out- put is lightly loaded: the secondary voltage drops and the system goes out of regulation. to overcome this problem, when the v13in voltage falls below a certain threshold (13.7 v +/- 5%) be- cause of too light a load on the 3.3v section, the relevant synchronous rectifier is turned on for 1.5 m s max. during the interval in which the inductor current is zero ("one-shot" feature, see fig. 6). in this way, the inductor current reverses and draws from the output capacitor energy which is forward transferred to the auxiliary output. in case the 3.3v section is working at full load and the linear regulator is lightly loaded, the voltage at pin v13in can exceed the expected value. in fact, ds and cs act as a peak-holding circuit and v13in is in- fluenced by the voltage spikes at switching transients. an internal clamp limits the voltage but, in case of intervention, the chip power dissipation will rise. when the 3.3v regulator is disabled, the linear regulator is disabled as well and is placed in a low-power mode to reduce device consumption. detailed functional description (continued) 1 n d s c s to v13in 3.3v d97in575 figure 5: 12v regulator supply with auxiliary winding. t t t h3gate l3gate il d97in576a 1.5 m s t v13in 13.7v figure 6: "one shot" feature to sustain v13in voltage. L4992 10/26
+5 v linear regulator & +3.3 v reference voltage generator this low drop-out regulator powers almost all the internal circuitry, that is the +3.3v reference voltage generator, amplifiers, comparators, digital logic, and mosfet drivers. its output is externally available through pin reg5. the typical external use of this generator is to charge the bootstrap capacitors used to produce the gate- drive voltage for the high-side mosfets of both pwm converters. at start-up and when the 5v section is not operating, this regulator is powered by the chip input voltage. to reduce power consumption, the linear regulator is turned off and the reg5 pin is internally connected to the 5v pwm regulator output via v5sw pin, when the 5v pwm regulator is active and its output volt- age is above the switchover threshold, 4.5v. the 5v regulator is always active, even if both pwm regulators are disabled, as long as power is applied to the chip. the 3.3v reference voltage generator, which is active only when either pwm converter is enabled, pro- vides comparison levels for threshold detection and device operation. it is allowed to source up to 5ma to an external load from its buffered output, externally available through pin vref. if either reg5 or vref does not deliver the correct voltage, the device is shut down. power management the L4992 is provided with some control pins suitable to perform some functions which are commonly used or sometimes required in battery-operated equipment. besides, it features controlled timing se- quences in case of turn-on/off and device shutdown for a safe and reliable behaviour under all condi- tions. as above mentioned, run3 and run5 pins allow to disable separately both pwm converters by means of logic signals (likely coming from a m p) as mentioned earlier. noskip can disable the pulse-skipping feature: when it is held high neither of the pwm regulators is al- lowed to enter this kind of operation. the pwrok output signal drives low immediately when either pwm regulator output falls below its own undervoltage threshold or when either of them is disabled. it is high when both regulator run properly. a capacitor connected between crst and ground fixes a time, in the order of 2ms/nf, which delays the transition low-high of pwrok. this happens at start-up or after recovering an undervoltage condition, provided both run3 and run5 are high. the delay starts from the moment in which the output voltage has reached its correct value for both sections. the same delay intervenes also in another circumstance: when a section is disabled (because its run is driven low or owing to a thermal shutdown), the relevant synchronous rectifier is turned on after the above delay in order to make sure that the load is no longer supplied. this delay, however, does not intervene in case of overvoltage: the synchronous rectifier is immediately turned on after the shutdown, thus acting as a built-in "crowbar". all these timing sequences are illustrated in fig 7. detailed functional description (continued) L4992 11/26
detailed functional description (continued) t t t run3 vout3 run5 d97in577 t vout5 t crst pwrok t t t t run3 vout3 h3gate t r3gate t crst t pwrok t run5 t vout5 t h5gate t r5gate a) turn-on timing sequence b) shutdown timing sequence (1) t t t run3 vout3 h3gate t r3gate t crst t pwrok t run5 t vout5 t h5gate t r5gate c) shutdown timing sequence (2) t h3gate t r3gate t vout3 t pwrok t vout5 crst t h5gate t r5gate d) ovp timing sequence figure 7: L4992 controlled timing sequences. L4992 12/26
basically, the application circuit topology is fixed, and the design procedure concerns only the selection of the component values suitable for the voltage and current requirements of the specific application. the design data one needs to know are therefore: input voltage range: the minimum (v inmin ) and the maximum (v inmax ) voltage under which the applica- tion is expected to operate; maximum load current for each of the three sections: - i out3 for the +3.3v section; - i out5 for the +5.1v section: - i out12 for the +12v section; maximum peak-to-peak ripple amplitude of the output voltage for each switching section: - v rpp3 for the +3.3v section; - v rpp5 for the +5.1v section; the operating frequency f sw (200/300 khz or externally synchronized). it is worth doing some preliminary considerations. the selection of the switching frequency depends on the requirements of the application. if the aim is to minimize the size of the external components, 300 khz will be chosen. for low input voltage applications 200 khz is preferred, since it leads to a higher maximum duty cycle. as for the switching regulators, the inductance value of the output filter affects the inductor current ripple: the higher the inductance the lower the ripple. this implies a lower current sense resistor value (for a given i out ), lower core losses and a lower output voltage ripple (for a given output capacitor) but, on the other hand, more copper losses and a worse transient behaviour due to load changes. usually the maxi- mum ripple peak-to-peak amplitude (which occurs at v inmax ) is chosen between 15% and 50% of the full load current. it is convenient to introduce a ripple factor coefficient, rf, that is therefore a number be- tween 0.15 and 0.5. as for the linear regulator, its input voltage v inlin should not fall below 13v and therefore the auxiliary winding should be dimensioned to get this voltage with a certain margin (say, 14v). conversely, an higher input voltage leads to higher losses inside the regulator, to the detriment of efficiency, and to higher total current on the +3.3v inductor. besides it implies a higher turns ratio and therefore a worse magnetic coupling, which affect energy transfer during flyback. switching regulators +5.1v inductor to define the inductor, it is necessary to determine firstly the inductance value. its minimum value is given by: l 5min = 5.1 ( v in max - 5.1 ) v in max f sw i out5 rf and a value l5 > l5 min should be selected. core geometry selection is connected to the requirements of the specific application in terms of space utilization and other practical issues like ease of mounting, availability and so on. as to the material, the choice should be directed towards ferrite, molypermalloy or kool m m ? , to achieve high efficiency. these materials provide low core losses (ferrite in particular), so that the design can be concentrated on pre- venting saturation and limiting copper losses. saturation must be avoided even at maximum peak current: i l5pk = i out5 + 5.1 ( v in max - 5.1 ) 2 f sw l 5 v in max to limit copper losses, the winding dc resistance, r l , should be as low as possible (in the range of m w ). ac losses can usually be neglected. a practical criterion to minimize dc resistance could be to use the largest wire that fits the selected core. anyway the best solution, whenever possible, is to use an off-the-shelf inductor which meets the require- ments in terms of inductance and maximum dc current. nowadays there is a broad range of products design procedure L4992 13/26
offered by manufacturer, also for surface mount assemblies. +3.3 v transformer the primary winding carries the secondary power as well, thus the total primary average current is: i tot3 = i out3 + v inlin i out12 3.3 where v inlin is the voltage generated during the recirculation of the primary and fed into the input of the +12v linear regulator. the turns ratio 1:n of the transformer is chosen so that v inlin is above 13v. to re- duce the turns ratio in order to minimize stray parameters, the secondary is referred to the 3.3v output, and therefore the minimum value is given by: n min = v inlin - 3.3 + v f 3.3 where v f is the forward drop across the rectifier (assume 1v to be conservative). make sure the secon- dary is connected with the proper polarity (see fig. 6). the minimum primary inductance value can be expressed as: l 3pmin = 3 4 3.3 ( v in - 3.3 ) 2 v in f sw [i tot3 rf ( v in - 3.3 ) - n v in i out12 ] where rf, to get positive values for l 3pmin , must satisfy the inequality: rf > n v in i out12 i tot3 ( v in - 3.3 ) and where v in can be either v inmin or v inmax , whichever gives the higher value for l 3pmin . with a primary inductance l 3p > l 3pmin the primary peak current, which must not saturate the magnetic core, will be: i l3pk = i tot3 + 3.3 ( v in max - 3.3 ) 2 f sw l 3p v in max + n i out12 as to the transformer realization, the considerations regarding to the +5.1v inductor can be here repeated. power mosfets and schottky diodes since the gate drivers of the L4992 are powered by a 5v bus , the use of logic-level mosfets is highly recommended, especially for high current applications. their breakdown voltage v (br)dss must be greater than v inmax with a certain margin, so the selection will address 20v or 30v devices. the r ds(on) can be selected once the allowable power dissipation has been established. by selecting identical power mosfets as the main switch and the synchronous rectifier, the total power they dissi- pate does not depend on the duty cycle. thus, if p on is this power loss (few percent of the rated output power), the required r ds(on) (@ 25 c) can be derived from: r ds ( on ) = p on i out 2 ( 1 + a d t ) where i out is either i tot3 or i out5 , according to the section under consideration, a is the temperature coeffi- cient of r ds(on) (typically, a = 5 10 -3 c -1 for these low-voltage classes) and d t the admitted tempera- ture rise. it is worth noticing, however, that generally the lower r ds(on) , the higher is the gate charge q g , which leads to a higher gate drive consumption. in fact, each switching cycle, a charge q g moves from the in- put source to ground, resulting in an equivalent drive current: i g = q g f sw design procedure (continued) L4992 14/26
which affects efficiency at low load currents. besides, this current is drawn from the reg5 line whose source capability, i src (25ma min), must not be exceeded, thus a further constraint concernes the mos- fet total gate charge (@ v gs = 5v); q g i src 4 f sw , assuming four identical mosfets. the schottky diode to be placed in parallel to the synchronous rectifier must have a reverse voltage vrrm greater than vinmax. since it conducts for less than 5% of the switching period, the current rating can be much lower than iout. the selection criterion should be: v f (schottky) < v f (body-diode) @ i = i lpk sense resistors the sense resistor of each section is selected according to their respective maximum output current. the current sense comparator limits the inductor peak current and therefore the maximum dc output current is the peak value less half of the peak-to-peak ripple. the intervention threshold is set at 100 mv for both sections, thus the resistor values should be: r sense5 = 100 i l5pk [m w] r sense3 = 100 i l3pk [m w] since the comparator threshold that triggers pulse-skipping mode is 26mv, the output current at which the system enters this kind of operation is approximately one fourth of the maximum output current. the sense resistors values are in the low milliohms thus it is important to take correctly the current sense signals. make sure that the kelvin connections between the current sense pins of the ic and the sense resistor do not carry the output current. input capacitors a pulsed current (with zero average value) flows through the input capacitor of a buck converter. the ac component of this current is quite high and dissipates a considerable amount of power on the esr of the capacitor: p cin = esr i out 2 v out ( v in - v out ) v in 2 it is easy to find that pcin has a maximum equal to (1/2) iout (@ vin=2 vout, that is, 50% duty cycle). the input capacitor of each section, therefore, should be selected for a rms ripple current rating as high as half the respective maximum output current. the capacitance value is not very important but in reality a minimum value must be ensured for stability reasons. in fact, switching regulators exhibit a negative input impedance that, at low frequencies, is: z in ( dc ) = - v in 2 v out i out thus, if the impedance of the power source is not well below the absolute value of z in(dc) at frequencies up to the bandwidth of the regulator control loop, there is the possibility for oscillations. to ensure stabil- ity, the following condition must be satisfied: c in >> l eq esr in | z in ( dc ) | where l eq is the inductance of the circuit upstream the switching regulator input and esr in is related to the input capacitor itself. the use of high performance electrolytic capacitors is recommended. if a higher cost is of no concern, os-con capacitors are an excellent choice because they offer the smallest size for a given esr or cur- rent rating. tantalum capacitors do not tolerate pulsed current, so their use is not advisable. design procedure (continued) L4992 15/26
output capacitors the output capacitor selection is based on the output voltage ripple requirements. this ripple is related to the current ripple through the inductor and is almost entirely due to the esr of the output capacitor. therefore, the goal is to achieve an esr lower than a certain value, regardless of the actual capacitance value. the maximum current ripple of the +5.1v section is: d i l5 = 2 (i l5pk - i out5 ) considering the values obtained in the paragraph "+5.1 v inductor". as for the +3.3v, the maximum ripple is given by: d i l3 = n i out12 v in v in - 3.3 + 3 4 3.3 ( v in - 3.3 ) f sw l 3p v in where v in is v inmin or v inmax , as selected in the "+3.3v transformer" section. anyhow, the maximum esr will be: esr x v rppx d i lx where the subscript x refers to either section. in pulse-skipping operation, the capacitive component of the output ripple is comparable to the resistive one, thus both should be considered: v rppx ( r ) = 0.025 esr x r sense x v rppx ( c ) = 3.1 10 - 6 l x c outx 1 r sensex 2 ? ? 1 v in min - v out - 1 v out ? ? if specification on the output ripple under pulse-skipping condition is also given, c outx and esr x must comply with it as well. further constraints on the minimum output capacitance can arise from specifications regarding the maxi- mum undershoot, d v - out , or overshoot, d v + out , due to a step-load change d i out : c out > l d i out 2 d v out - ( v in min d max - v out ) ; c out > l d i out 2 d v out + v out whichever is greater, and where d max is the maximum duty cycle and the quantities are relevant either to the +3.3v or +5.1v section. high performance capacitors should be employed to reduce the capacitance needed for a given esr, to avoid paralleling several parts with a considerable waste of space. although excellent electrolytic capaci- tors are available, os-con or tantalums may be preferred especially if very compact design is required, or in case of surface mount assemblies. multilayer ceramic capacitors with extremely low esr are now available, but they have a large spread of the capacitance value, so they should be paralleled with an- other more stable, high-esr capacitor. miscellaneous components the feedback loop has virtually unlimited bandwidth, thus a filter is necessary to make the system insen- sitive to the switching frequency ripple and, in general, to prevent noise from disturbing the correct op- eration of the error summing comparator. anyway, the cut-off frequency of this filter can be very high, so that line and load transient response is extremely fast. this filter is a simple r-c type where resistance and capacitance can be chosen for a typical 3db cut-off frequency of 60 khz. as to the bootstrap diodes, even though small signal p-n diodes might be effectively used, it is preferable to employ low-power schottky rectifiers, since that increase slightly the gate drive voltage, in favour of ef- ficiency. the bootstrap capacitor can be a 100nf film capacitor. the soft-start capacitors determine the time during which the current limitation circuit moves gradually the setpoint from zero up to 100 mv in order to limit the current inflow at start-up. this ramp lasts approximately 1 ms per nf of soft-start capacitance (10 to 100 nf typical values), but the actual time necessary to the out- put voltage to reach the steady-state value depends on the load current and the output filter capacitance. there are some critical points of the ic that may require by-pass capacitors to prevent noise from dis- design procedure (continued) L4992 16/26
turbing the circuit. these points are the reference voltage vref, the ic supply pin vin, the reg5 line and the alternative supply pin v5sw. use film capacitors suitable for ac decoupling. +12 v linear regulator catch diode the diode which steers the current generated by the secondary winding of the +3.3v transformer should be a p-n fast-recovery one, with a breakdown voltage greater than: v rr = (v inlin - 3.3) + n (v in max - 3.3) with a certain safety margin. the diode has to withstand a pulsed current whose peak value is approxi- mately: i 13pk @ i out12 v in min v in min - 3.3 , while its rms value is given by: i 13rms = i out12 ? ``````` v in min v in min - 3.3 the dc value is obviously i out12 . filter capacitors the most stringent requirement on the input filter capacitor (connected between v13in and ground) is its rms ripple current rating, which should be at least: i 13ac = i out12 ? ``````` ` 3.3 v in min - 3.3 the working voltage should be higher than the voltage generated when the regulator is lightly loaded. also for this part the use of high quality electrolytic or os-con capacitors is advised. layout and grounding the electrical design is only the first step in the development of a switching converter. since currents ranging from m amperes to some amperes, both dc and switched, live together on the same circuit- board, the pcb layout is vital for a correct operation of the circuit but is not an easy task. a proper layout process generally includes careful component placing, proper grounding, correct traces routing, and appropriate trace widths. fortunately, since low voltages are involved in this kind of applica- tions, isolation requirements are of no concern. referring to literature for a detailed analysis of this matter, only few important points will be here reminded. 1) all current returns (signal ground, power ground, etc.) should be mutually isolated and should be con- nected only at a single ground point. ground planes may be extremely useful both to arrange properly current returns and to minimize radiation (see next 2 points), even though they cannot solve every problem 2) noise coupling between adjacent circuitry can be reduced minimizing the area of the loop where cur- rent flows. this is particularly important where there are high pulsed currents, that is the circuit includ- ing the input filter capacitor, the power switch, the synchronous rectifier and the output capacitor. the next priority should be given to the gate drive circuits. 3) magnetic field radiation (and stray inductance) can be reduced by keeping all traces which carry switched currents as short as possible. 4) the kelvin-connected traces of current sense should be kept short and close together. 5) for high current paths, the traces could be doubled on the other side of the pcb whenever possible: this will reduce both the resistance and the inductance of the wiring. 6) in general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. from this viewpoint, particular care should be taken of the high impedance paths (feedback input, current sense traces...). it could be a good idea to route signal traces on one design procedure (continued) L4992 17/26
pcb side and power traces on the other side. 7) use heavy copper traces: this will reduce their resistance, increasing overall efficiency and will im- prove their heat-sinking ability. L4992 eval-kit the L4992 eval kit is a fully assembled and tested demonstration board that implements a standard application circuit, configured according to the following specifications: input voltage range: 6 to 25 v 3.3v output: i out3 = 3 a, v rpp3 30 mv 5.1v output: i out5 = 3 a, v rpp5 50 mv 12 v output: i out12 = 120 ma switching frequency: f sw = 300 khz the electrical schematic, illustrated in fig. 9, shows that some pull-up/down resistor are added to the components strictly needed in a real application. along with a quad dip-switch, they allow to set manually the logic signals that control the chip operation. these signals are in the present case: - switch 1: run5 (0= 5.1v off, 1= 5.1v on) - switch 2: noskip (0= pulse-skipping on, 1= pulse-skipping off) - switch 3: osc (0= 200 khz, 1= 300 khz) - switch 4: run3 (0= 3.3v off, 1= 3.3v on) the demonstration board is delivered with the switches configured as illustrated in fig. 8. switches 1 and 4 enable/disable the two pwm sections (switch 4 manages the +12v linear regulator as well). they must be set on 1 to turn on the regulators. please note that as long as each regulator is disabled, the relevant low-side mosfet is in on state. hence, if the load is capable of sourcing current, it will be short-circuited to ground through the choke and the low-side mos. although the default switching frequency is 300 khz (switch 3 set on 1) and the passive components have been selected for this frequency, the demo board will work satisfactorily at 200 khz as well. actu- ally, at 200 khz the regulators exhibit the maximum efficiency and the maximum extension of the input voltage range downwards. on the other hand, the output ripple is greater and the dynamic behaviour slightly worse. the demostration board, as it is, does not provide an interface for synchronization. anyway, it is possible to synchronize the oscillator (with an appropriate signal: 5v amplitude pulses, spaced out by 400 ns min.), provided the switch is set on 1, simply by feeding the signal into the middle of the divider r8-r9. in this way, synchronization can be achieved at a frequency higher than 300 khz. to synchronize the oscil- lator to a frequency between 200 and 300 khz, heavier interventions on the board are needed. design procedure (continued) 1234 0 1 figure 8: default switches configuration L4992 18/26
L4992 29 30 31 32 1 2 3 24 25 26 27 28 19 20 18 16 15 22 10 13 12 9 17 8 6 5 4 7 11 14 l1 r1 v out1 5.1v/3a c3 r3 c16 c7 d1 q1 q3 c1 c5 d3 r5 r6 s3 s4 c9 c11 c12 c13 c14 c15 d4 c6 c2 q2 q4 c8 d2 t1 pwrok c18 reg12 r2 r8 r7 s2 s1 r9 c17 d5 r4 c10 c4 v in =6 to 25v +- v out2 3.3v/3a v out3 12v/0.12a d96in426a 21 figure 9a: evaluation board circuit. design procedure (continued) table 1: L4992 eval-kit parts list component refer. value description resistors r1 25m w 1%, 0.5w. dale. p.n. wsl-2512r0251 r2 20m w 1%, 0.5w. dale. p.n. wsl-2512r0201 r3, r4 270 w 1%,smd r5, r6, r7, r8, r9 1m w smd capacitors c1, c2 100 m f 20v. sanyo os-con. p.n. 20sa100k c3, c4 220 m f 10v. sanyo os-con. p.n. 10sa220k c5, c6, c12, c13 100 m f smd c7, c8, c15, c16 1 m f smd c9, c10, c11 10nf smd c14, c18 4.7 m f 16v. tantalum. smd c17 15 m f 25v. sanyo os-con. p.n. 25sc15m magnetics l1 10 m h 2.65a. sumida. p.n. cdr125-100 t1 10 m h 1:4 ratio. transpower. p.n. tti5902 mosfets q1, q2, q3, q4 si9410dy siliconix diodes d1, d2 tmbyv10-40 st. melf package d3, d4 tmmbat46 st. minimelf package d5 smbyw01-200 st.sod6 package switches s1, s2, s3, s4 - quad dip-switch L4992 19/26
figure 9b: pcb and component layout of the evaluation board of figure 9a. design procedure (continued) signal ground plane top layer + silk (56 x 61mm) power ground plane bottom layer L4992 20/26
pulse-skipping operation is enabled by default in order to maximize efficiency also in low load current range. the transition between pwm and pulse-skipping occurs approximately below 1a, however there is a region in which the two operation modes coexist rather than a definite boundary. that can be seen on the scope as an irregularity of the waveforms but does not have much influence both on output ripple and efficiency. those who do not appreciate asynchronous operation of the pulse-skipping mode can disable it for both regulators, by setting switch 2 on 1. that maintains pwm operation up to very low output currents where, however, the regulation becomes incompatible with the switching frequency. this means that the mini- mum on-time of the high-side mosfet is too long for the thruput energy level at the operating fre- quency. thus the control system begins skipping conduction cycles to avoid the output voltage drifting upwards. table 1 shows the complete L4992 eval kit parts list. critical components characteristics are given in detail. demo board evaluation the following diagrams and tables show the typical performance of the demonstration board in terms of efficiency, line regulation and load regulation. the 12v linear regulator and reg5 are also characterized. table 2: pwm regulators: optimum efficiency parameter test condition value unit +3.3v maximum efficiency run3 = run5 = high, noskip = low vin = 6v, iout = 0.5 a, f sw = 200 khz vin = 6v, iout = 1a, f sw = 300 khz 95.2 94.6 % +5.1v maximum efficiency run3 = low, noskip = low vin = 6v, iout = 1a, f sw = 200 khz vin = 6v, iout = 1a, f sw = 300 khz 96.4 95.8 % design procedure (continued) table 3: pwm regulators: line and load regulation. parameter test condition value unit +3.3v line regulation run5 = low, noskip = low, 6 < vin < 20v iout = 0.1 a, f sw = 200 khz iout =1a, f sw = 200 khz 2 15 mv +5.1v line regulation run3 = low, noskip = low, 6 < vin < 20v iout = 0.1a, f sw = 200 khz iout = 1a, f sw = 200 khz 3 20 mv +3.3v load regulation run5 = low, noskip = low, 5 ma < iout < 3a vin = 6 v, f sw = 200 khz vin = 15v, f sw = 200 khz 85 70 mv +5.1v load regulation run3 = low, noskip = low, 5 ma < iout < 3a vin = 6 v, f sw = 200 khz vin = 15v, f sw = 200 khz 90 75 mv L4992 21/26
0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 50 60 70 80 90 d96in421 eff. (%) vin=6v vin=20v vin=15v v o =5.1v f sw =300khz run3=gnd noskip=gnd figure 13: demo board efficiency vs output cur- rent 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 50 60 70 80 90 d96in420 eff. (%) vin=6v vin=20v vin=15v v o =5.1v f sw =200khz run3=gnd noskip=gnd figure 12: demo board efficiency vs output cur- rent demo board-evaluation (continued) 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 5.02 5.04 5.06 5.08 5.10 5.12 v o (v) vin=6v vin=20v vin=15v d97in579 figure 10: 5.1v output (run3=low, run5 = high, osc = gnd, noskip = low) 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 3.30 3.32 v o (v) vin=6v vin=20v vin=15v d97in580 3.34 3.36 3.38 figure 11: 3.3v output (run3=high, run5 = low, osc = gnd, noskip = low) 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 50 60 70 80 90 d96in423a eff. (%) vin=6v vin=20v vin=15v v o =3.3v f sw =300khz run5=gnd noskip=gnd figure 15: demo board efficiency vs output cur- rent 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i o (a) 50 60 70 80 90 d96in422a eff. (%) vin=6v vin=20v vin=15v v o =3.3v f sw =200khz run5=gnd noskip=gnd figure 14: demo board efficiency vs output cur- rent L4992 22/26
0.001 0.005 0.01 0.05 0.5 0.1 1 10 100 f s (khz) d96in428a vin=6v vin=20v v o =5.1v osc=2.5v i o (a) 0.1 figure 19: switching frequency vs output cur- rent (pulse skipping) 0.001 0.005 0.01 0.05 0.5 0.1 1 10 100 f s (khz) d96in427a vin=6v vin=20v v o =3.3v reg12=open osc=2.5v i o (a) 0.1 figure 18: switching frequency vs output cur- rent (pulse skipping) 0.001 0.005 0.01 0.05 0.1 0.5 1 5 i out5 (a) 87 88 89 90 91 92 eff. (%) vin=6v vin=20v d97in581 93 figure 16: demo board overall efficiency (iout3 = 3a, reg12 = open, osc = gnd) 0.001 0.005 0.01 0.05 0.1 0.5 1 5i out3 (a) 89 90 eff. (%) vin=6v vin=20v d97in582 91 92 93 figure 17: demo board overall efficiency (iout5 = 3a, reg12 = open, osc = gnd) demo board-evaluation (continued) 0 20406080100i out (ma) 4.85 4.90 4.95 5.00 5.05 v out (v) d97in583 figure 20: reg5 regulator characteristic (vin = 6v, run3 = run5 = low, tj = 25c) 0 50 100 150 200 i out (ma) 0 2 4 6 8 10 12 v out (v) d97in584 figure 21: 12v linear regulator characteristic (v13in = 15v, run3 = high, tj = 25 c) L4992 23/26
L4992 29 30 31 32 1 2 3 24 25 26 27 28 19 20 18 16 15 22 10 13 12 9 17 8 6 5 4 7 11 14 l1 r1 v out1 5.1v/3a c3 r3 c16 c7 d1 q1 q3 c1 c5 d3 r5 r6 s3 s4 c9 c11 c12 c13 c14 c15 d4 c6 c2 q2 q4 c8 d2 t1 pwrok c18 reg12 r2 r8 r7 s2 s1 r9 c17 d5 r4 c10 c4 v out2 3.3v/3a v out3 12v/0.12a d98in813 21 12v bus 5v bus application ideas figure 22: application with split supply L4992 22 7(18) 5(20) 6(19) r b r sense r a r3(r4) c9 (c10) c18 12v min. load v o <5.1v (v o <3.3v) d98in814 r b balances zcd comparator figure 23: low output voltage. L4992 24/26
tqfp32 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 9.00 0.354 d1 7.00 0.276 d3 5.60 0.220 e 0.80 0.031 e 9.00 0.354 e1 7.00 0.276 e3 5.60 0.220 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0 (min.), 7 (max.) a a2 a1 b seating plane c 8 9 16 17 24 25 32 e3 d3 e1 e d1 d e 1 k b tqfp32 l l1 0.10mm .004 outline and mechanical data L4992 25/26
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com L4992 26/26

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