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cyusb306x ez-usb ? cx3: mipi csi-2 to superspeed usb bridge controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-87516 rev. *l revised june 22, 2017 ez-usb ? cx3: mipi csi-2 to superspeed usb bridge controller features universal serial bu s (usb) integration ? usb 3.0 and usb 2.0 peripherals, compliant with usb 3.0 specification 1.0 ? 5-gbps usb 3.0 phy co mpliant with pipe 3.0 ? thirty-two physical endpoints mipi csi-2 rx interface ? mipi csi-2 compliant (ver sion 1.01, revision 0.04 ? 2 nd april 2009) ? supports up to four data lanes (cyusb3065 supports up to four lanes; cyusb3064 supports up to two lanes) ? each lane supports up to 1 gbps (cyusb3065 supports up to four lanes; cyusb3064 supports up to two lanes) ? cci interface for image sensor configuration supports the following video data formats: ? user-defined 8-bit ? raw8/10/12/14 ? yuv422 (ccir/itu 8/10bit), yuv444 ? rgb888/666/565 fully accessible 32-bit cpu ? arm926ej-s core with 200-mhz operation ? 512-kb or 256-kb embedded sram additional connectivity to the following peripherals: ? i 2 c master controller at 1 mhz ? i 2 s master (transmitter only) at sampling frequencies of 32 khz, 44.1 khz, and 48 khz ? uart support of up to 4 mbps ? spi master at 33 mhz twelve gpios ultra-low-power in core power-down mode independent power domains for core and i/o ? core operation at 1.2 v ? i 2 s, uart, and spi operation at 1.8 to 3.3 v ? i 2 c, i/o operation at 1.8 to 3.3 v 10 10 mm, 0.8-mm pitch pb-free ball grid array (bga) package ez-usb ? software development kit (sdk) for easy code development applications digital video cameras digital still cameras webcams scanners video conference systems gesture-based control surveillance cameras medical imag ing devices video ip phones usb microscopes industrial cameras
cyusb306x document number: 001-87516 rev. *l page 2 of 37 logic block diagram cpu arm926ej-s program ram 32 eps jtag usb port i2c i 2 c_scl i 2 c_sda i2s clkin_32 clkin reset# ssrx- ssrx+ sstx- sstx+ d+ d- tdi td0 tck trst tms hs/fs peripheral ss peripheral uart spi i 2 s_clk i 2 s_sd i 2 s_ws i 2 s_mclk miso mosi ssn sck tx rx cts rts mipi csi-2 rx interface refclk mclk xrst xshutdown cp / cm d0p / d0m d1p / d1m d2p / d2m d3p / d3m
cyusb306x document number: 001-87516 rev. *l page 3 of 37 more information cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate t he device into your design. for a comprehensive list of resources refer to the cypress web page for cx3 at www.cypress.com/cx3 . overview: usb portfolio , usb roadmap usb 3.0 product selectors: fx3 , fx3s , cx3 , gx3 , hx3 , west bridge benicia application notes: cypress offers a large number of usb appli- cation notes covering a broad range of topics, from basic to advanced level. recommended application notes for getting started with cx3 are: ? an75705 - getting started with ez-usb fx3 ? an90369 - how to interface a mipi csi-2 image sensor with ez-usb? cx3 ? an75779 - how to implement an image sensor interface with ez-usb? fx3? in a usb video class (uvc) framework ? an76405 - ez-usb fx3 boot options ? an70707 - ez-usb fx3/fx3s hardware design guidelines and schematic checklist ? an86947 - optimizing usb 3.0 throughput with ez-usb fx3 code examples: ? usb superspeed technical reference manual (trm): ? ez-usb? cx3 technical reference manual knowledge base articles: ? cx3 firmware: frequently asked questions - kba91297 ? cx3 hardware: frequently asked questions - kba91295 ? cx3 application software / usb driver: frequently asked questions - kba91298 ? knowledge base - cypress semiconductor cage code - kba89258 development kits: ? ascella - cypress? cx3? thine? isp 13mp reference de- sign kit (rdk) ? denebola - usb 3.0 uvc reference design kit (rdk) models: ? cx3 device orcad schematic symbol ? cyusb306x - ibis ez-usb software development kit cypress delivers the complete firmware stack for cx3, in order to easily integrate superspeed usb into any embedded mipi image sensor application. the software development kit (fx3 sdk) comes with tools, drivers and application examples, which help accelerate application development. the fx3 sdk setup includes cx3 apis and example firmware for omnivision ov5640 and aptina as0260 image sensor interface. the eclipse plugin for the fx3 sdk accelerates cx3 firmware development for any other image sensor.
cyusb306x document number: 001-87516 rev. *l page 4 of 37 contents functional overview ........................................................ 5 application examples .................................................. 5 usb interface ...... .............. .............. .............. ........... ......... 6 renumeration ..................... ........................................ 6 vbus overvoltage protection ... .............. ........... ......... 6 mipi csi-2 rx interf ace ............... .............. .............. ......... 7 additional outputs ....................................................... 7 cpu .................................................................................... 7 jtag interface .................................................................. 7 other interfaces ................................................................ 7 uart interface ............................................................ 7 i2c interface ................................................................ 7 i2s interface ................................................................ 8 spi interface ................................................................ 8 boot options ..................................................................... 8 reset .................................................................................. 8 hard reset .................................................................. 8 soft reset .................................................................... 8 clocking ............................................................................ 9 32-khz watchdog timer clock i nput ............. .............. 9 power ............................................................................... 10 power modes ............................................................ 10 configuration options ................................................... 13 digital i/os ....................................................................... 13 gpios ............................................................................... 13 emi ................................................................................... 13 system-level esd ....... .............. .............. .............. .......... 13 pin configuration ........................................................... 14 pin description ............................................................... 15 absolute maximum ratings .......................................... 17 operating conditions ..................................................... 17 dc specifications ........................................................... 17 mipi d-phy electrical characteristics .......................... 18 ac timing parameters ......... .......................................... 19 mipi data to clock timing reference ....................... 19 reference clock specifications ................................. 19 mipi csi signal low power ac characteristics ....... 20 ac specifications ...................................................... 20 serial peripherals timing ... ....................................... 21 reset sequence ......... .............. .............. .............. ........... 26 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagram ............................................................ 28 acronyms ........................................................................ 29 document conventions ................................................. 29 units of measure ....................................................... 29 errata ............................................................................... 30 part numbers affected .............................................. 30 qualification status ................................................... 30 errata summary .................... .................................... 30 document history page ................................................. 34 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc?solutions ....................................................... 37 cypress developer community ................................. 37 technical support ................. .................................... 37
cyusb306x document number: 001-87516 rev. *l page 5 of 37 functional overview cypress?s ez-usb cx3 is the next-generation bridge controller that can connect devices with th e mobile industry processor interface ? camera serial interf ace 2 (mipi csi-2) interface to any usb 3.0 host. cx3 has a 4-lane csi-2 receiver with up to 1 gbps on each lane. it supports video data formats such as raw8/10/12/14, yuv422 (ccir/itu 8/10-bit), rgb888/666 /565, and user-defined 8-bit. cx3 has integrated the usb 3.0 and usb 2.0 physical layers (phys) along with a 32-bit ar m926ej-s microprocessor for powerful data processing and for building custom applications. cx3 contains 512 kb of on-chip sram (see ordering information on page 27 ) for code and data. ez-usb cx3 also provides interfaces to connect to serial peripherals such as uart, spi, i 2 c, and i 2 s. cx3 comes with application development tools. the software development kit comes with application examples for acceler- ating time-to-market. cx3 complies with the usb 3.0 v1.0 specification and is also backward compatible with usb 2.0. it also complies with the mipi csi-2 v1.01, revision 0.04 specification dated 2 nd april 2009. application examples in a typical application (see figure 1 ), cx3 acts as the main processor and connects to an image sensor, an audio device, or camera control devices amongst others. figure 1. ez-usb cx3 example application image sensor ez-usb cx3 autofocus, pan, tilt, zoom, shutter control, lighting, etc. audio input audio output usb host clock 6-40 mhz clock 19.2 mhz power subsystem u s b mipi csi-2 rx i 2 c i 2 s spi refclk clkin v dd
cyusb306x document number: 001-87516 rev. *l page 6 of 37 usb interface cx3 complies with the following s pecifications and supports the following features: supports usb peripheral functionality compliant with usb 3.0 specification, revision 1.0, and is also backward compatible with the usb 2.0 specification. as a peripheral, cx3 is capable of superspeed, high-speed, and full-speed. supports up to 16 in and 16 out endpoints supports the usb 3.0 streams feature as a usb peripheral, cx3 supports usb-attached storage (uas), usb video class (uvc), and media transfer protocol (mtp) usb peripheral classes. as a usb peripheral, all other device classes are supported only in pass-through mode when handled entirely by a host processor external to the device. figure 2. usb interface signals renumeration because of cx3?s soft configurat ion, one chip can take on the identities of multiple distinct usb devices. when first plugged into usb, cx3 enumerates automatically with the cypress vendor id (0x04b4) and downloads the firmware and usb descriptors over the usb interface. the downloaded firmware executes an electrical disconnect and connect. cx3 enumerates again, this time as a device defined by the downloaded information. th is patented two-step process, called renumeration, happens instantly when the device is plugged in. vbus overvoltage protection the maximum input voltage on cx3's vusb pin is 6 v. a charger can supply up to 9 v on vusb. in this case, an external overvoltage protection (ovp) device is required to protect cx3 from damage on vusb. figure 3 shows the system application diagram with an ovp device connected on vusb. refer to dc specifications on page 17 for the operating range of vusb. note: the vbus pin of the usb connector should be connected to the vusb pin of cx3. figure 3. system diagra m with ovp device for vusb ez-usb cx3 vusb usb interface ssrx- ssrx+ sstx- sstx+ d- d+ power subsystem usb connector ez-usb cx3 usb-port 1 8 2 3 4 5 6 7 9 vusb gnd ssrx- ssrx+ sstx- sstx+ d- d+ vdd vddio1 cvddq vddio2 vddio3 avdd ovp device u3txvddq u3rxvddq
cyusb306x document number: 001-87516 rev. *l page 7 of 37 mipi csi-2 rx interface the mobile industry processor interface (mipi) association defined the camera serial interface 2 (csi-2) standard to enable image data to be sent on high-bandwidth serial lines. cx3 implements a mipi csi-2 receiver with the following features: 1. it can receive clock and data in 1, 2, 3, or 4 lanes. (cyusb3065 part supports up to four lanes; cyusb3064 part supports up to two lanes) 2. up to 1 gbps of data on each csi lane is supported (total maximum bandwidth should not exceed 2.4 gbps). 3. video formats such as raw8/10/12/14, yuv422 (ccir/itu 8/10-bit), rgb888/666/565, and user-defined 8-bit are supported 4. a cci interface (compatible with 100-khz or 400-khz i 2 c interface with 7-bit addressing) is provided to configure the sensor. 5. gpios are available for synchronization of external flash or lighting system with image sensors to illuminate the scene that improves the image quality by improving signal to noise ratio. 6. gpios can also be used to synchronize the image sensor with external events, so that image can be captured based on external event. 7. serial interfaces (such as i 2 c, i 2 s, spi, uart) are available to implement camera functions such as auto focus and pan, tilt, zoom (ptz) additional outputs in addition to the standard mipi csi-2 signals, the following three additional outputs are provided: 1. xrst: this can be used to reset the image sensor 2. xshutdown: this pin can be used to put the sensor to a standby/shutdown mode 3. mclk: this pin can provide the clock output. it can be used only for testing the image sensor. for production, use an external clock generator as clock input for image sensors. cpu cx3 has an on-chip 32-bit, 200-mhz arm926ej-s core cpu. the core has direct access to 16 kb of instruction tightly coupled memory (tcm) and 8 kb of data tcm. the arm926ej-s core provides a jtag interface for firmware debugging. cx3 offers the following advantages: integrates 512 kb of embedded sram for code and data and 8 kb of instruction cache and data cache. implements efficient and flexible dma connectivity between the various peripherals (such as, usb, csi-2 rx, i 2 s, spi, and uart), requiring firmware only to configure data accesses between peripherals, which are then managed by the dma fabric. allows easy application development on industry-standard development tools for arm926ej-s. examples of the cx3 firmware are available with the cypress ez-usb cx3 development kit. software apis that can be ported to an external processor are available with the cypress ez-usb cx3 software development kit. jtag interface cx3?s jtag interface has a standard five-pin interface to connect to a jtag debugger in order to debug firmware through the cpu-core's on-chip-debug circuitry. industry-standard debugging tools for the arm926ej-s core can be used for the cx3 application development. other interfaces cx3 supports the following serial peripherals: uart i 2 c i 2 s spi the cyusb306x pin list on page 15 shows the details of how these interfaces are mapped. uart interface the uart interface of cx3 suppor ts full-duplex communication. it includes the signals noted in table 1 . the uart is capable of generatin g a range of baud rates, from 300 bps to 4608 kbps, selectable by the firmware. if flow control is enabled, then cx3's uart only transmits data when the cts input is asserted. in addition to this, cx3's uart asserts the rts output signal, when it is ready to receive data. i 2 c interface cx3?s i 2 c interface is compatible with the i 2 c bus specification revision 3. this i 2 c interface is capable of operating only as i 2 c master; therefore, it may be used to communicate with other i 2 c slave devices. for example, cx3 may boot from an eeprom connected to the i 2 c interface, as a selectable boot option. cx3?s i 2 c master controller also supports multi-master mode functionality. the power supply for the i 2 c interface is v ddio1 , which is a separate power domain from the other serial peripherals. this gives the i 2 c interface the flexibility to operate at a different voltage than the other serial interfaces. table 1. uart interface signals signal description tx output signal rx input signal cts flow control rts flow control
cyusb306x document number: 001-87516 rev. *l page 8 of 37 the i 2 c controller supports bus frequencies of 400 khz, and 1 mhz. when v ddio1 is 1.8 v, 2.5 v, or 3.3 v, the operating frequencies supported are 400 khz and 1 mhz. the i 2 c controller supports the clock-stretc hing feature to enable slower devices to exercise flow control. the i 2 c interface?s scl and sda signals require external pull-up resistors. the pull-up resist ors must be connected to v ddio1 . note: i 2 c addresses with the pattern 0x0000111x are used inter- nally and no slave devices with those addresses should be connected to the bus. i 2 s interface cx3 has an i 2 s port to support external audio codec devices. cx3 functions as i 2 s master as transmitter only. the i 2 s interface consists of four signals: clock line (i2s_clk), serial data line (i2s_sd), word select line (i2s_ws), and master system clock (i2s_mclk). cx3 c an generate t he system clock as an output on i2s_mclk or accept an external system clock input on i2s_mclk. the sampling frequencies supported by the i 2 s interface are 32 khz, 44.1 khz, and 48 khz. spi interface cx3 supports an spi master interface on the serial peripherals port. the maximum operation frequency is 33 mhz. the spi controller supports four modes of spi communication (see spi timing specification on page 24 for details on the modes) with the start-stop clock. this controller is a single-master controller with a sing le automated ssn control. it supports transaction sizes ranging from 4 bits to 32 bits. boot options cx3 can load boot images from va rious sources, selected by the configuration of the pmode pi ns. following are the cx3 boot options: boot from usb boot from i 2 c boot from spi (spi devices supported are m25p16 (16 mbit), m25p80 (8 mbit), and m25p40 (4 mbit)) or their equivalents reset hard reset a hard reset is initiated by asserting the r eset# pin on cx3. the specific reset sequence and timing requirements are detailed in figure 11 on page 26 and table 14 on page 26 . all i/os are tristated during a hard reset. an additional reset pin called mipi_reset is provided that resets the mipi csi-2 core. it should be pulled down with a resistor for normal operation. soft reset there are two types of soft reset: cpu reset ? the cpu program counter is reset. firmware does not need to be reloaded following a cpu reset. whole device reset ? this reset is identical to hard reset. the firmware must be reloaded following a whole device reset. table 2. cx3 booting options pmode[2:0] [1] boot from f11 usb boot f1f i 2 c, on failure, usb boot is enabled 1ff i 2 c only 0f1 spi, on failure, usb boot is enabled note 1. f indicates floating.
cyusb306x document number: 001-87516 rev. *l page 9 of 37 clocking cx3 requires two clocks for normal operation: 1. a 19.2-mhz clock to be connected at the clkin pin 2. a 6-mhz to 40-mhz clock to be connected at the refclk pin clock inputs to cx3 must meet the phase noise and jitter require- ments specified in table 3 on page 9 . the input clock frequency is independent of the clock and data rate of the cx3 core or any of the device interfaces (including the csi-2 rx port). the internal pll applies the appropriate clock-multiply option depending on the input frequency. note: refclk and clkin must have either separate clock inputs or if the same source is used, the clock must be passed through a buffer with two outputs and then connected to the clock pins. 32-khz watchdog timer clock input cx3 includes a watchdog timer. the watchdog timer can be used to interrupt the arm926ej-s co re, automatically wake up the cx3 in standby mode, and reset the arm926ej-s core. the watchdog timer runs a 32-khz clock, which may be optionally supplied from an external source on a dedicated cx3 pin. the firmware can disable the watchdog timer. ta b l e 4 provides the requirements for the optional 32-khz clock input table 3. cx3 input clock specifications parameter description specification units min max phase noise 100-hz offset ? ?75 db 1-khz offset ? ?104 db 10-khz offset ? ?120 db 100-khz offset ? ?128 db 1-mhz offset ? ?130 db maximum frequency deviation ? ? 150 ppm duty cycle ? 30 70 % overshoot ? ? 3 % undershoot ? ? ?3 % rise time/fall time ? ? 3 ns table 4. 32-khz clock input requirements parameter min max units duty cycle 40 60 % frequency deviation ? 200 ppm rise time/fall time ? 200 ns
cyusb306x document number: 001-87516 rev. *l page 10 of 37 power cx3 has the following power supply domains: io_vddq : this is a group of independent supply domains for digital i/os. ? v ddio1 : gpio, i 2 c, jtag, xrst, xshutdown and ref- clk ? v ddio2 : uart and i 2 s (except mclk) ? v ddio3 : i 2 s_mclk and spi ? c vddq : clkin ? v dd_mipi : mipi csi-2 clock and data lanes v dd : this is the supply voltage for the logic core. the nominal supply-voltage level is 1.2 v. this supplies the core logic circuits. the same supply must also be used for the following: ? a vdd : this is the 1.2 v supply for the pll, crystal oscillator, and other core analog circuits. ? u3txvddq/u3rxvddq : these are the 1.2 v supply volt- ages for the usb 3.0 interface. vusb : this is the 4 v to 6 v power supply for the usb i/o and analog circuits. this supply powers the usb transceiver through cx3?s internal voltage regulator. vusb is internally regulated to 3.3 v. note : the different power supplies have to be powered on or off in a specific sequence as illustrated in figure 4 . power modes cx3 supports the following power modes: normal mode: this is the full-f unctional operating mode. the internal cpu clock and the internal plls are enabled in this mode. ? normal operating power consumption does not exceed the sum of i cc core max and i cc usb max (see dc specifications on page 17 for current consumption specifications). ? the i/o power supplies v ddio2 and v ddio3 can be turned off when the corresponding interface is not in use. v ddio1 should never be turned off for normal operation. low-power modes (see table 5 on page 11 ): ? suspend mode with usb 3.0 phy enabled ? standby mode ? core power-down mode figure 4. power-up sequence vusb (vbus) vdd (vdd, avdd, vdd_mipi) vddio1 cvddq, vddio2, vddio3 clk_in, refclk reset# mipi_reset >= 1 ms xrst (image sens or reset) user programmable in firmware <= 10 ms <= 10 ms
cyusb306x document number: 001-87516 rev. *l page 11 of 37 table 5. entry and exit methods for low-power modes low-power mode characteristics methods of entry methods of exit suspend mode with usb 3.0 phy enabled power consumption in this mode does not exceed i sb1 usb 3.0 phy is enabled and is in u3 mode (one of the suspend modes defined by the usb 3.0 specification). this one block alone is operational with its internal clock, while all other clocks are shut down all i/os maintain their previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on or off individually the states of the configuration registers, buffer memory, and all internal ram are maintained all transactions must be completed before cx3 enters suspend mode (state of outstanding transactions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on arm926ej-s core can put cx3 into the suspend mode. for example, on usb suspend condition, the firmware may decide to put cx3 into suspend mode d+ transitioning to low or high d- transitioning to low or high resume condition on ssrx detection of vbus level detect on uart_cts (programmable polarity) assertion of reset# standby mode the power consumption in this mode does not exceed isb3 all configuration register settings and program/data ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed. therefore, the external processor should take care that the data needed is read before putting cx3 into the standby mode the program counter is reset after waking up from the standby mode gpio pins maintain their configuration internal pll is turned off usb transceiver is turned off arm926ej-s core is powered down. upon wakeup, the core re-starts and runs the program stored in the program/data ram power supply for the wakeup source and core power must be retained. all other power domains can be turned on or off individually the firmware executing on arm926ej-s core or external processor configures the appropriate register detection of vbus level detect on uart_cts (programmable polarity) assertion of reset#
cyusb306x document number: 001-87516 rev. *l page 12 of 37 core power-down mode the power consumption in this mode does not exceed isb 4 core power is turned off all buffer memory, configuration registers, and the program ram do not maintain state. after exiting this mode, reload the firmware in this mode, all other power domains can be turned on or off individually turn off v dd reapply v dd assertion of reset# table 5. entry and exit methods for low-power modes (continued) low-power mode characteristics methods of entry methods of exit
cyusb306x document number: 001-87516 rev. *l page 13 of 37 configuration options configuration options are availa ble for specific usage models. contact cypress marketing ( usb3@cypress.com ) for details. digital i/os cx3 has internal firmware-controlled pull-up or pull-down resistors on all digital i/o pins. an internal 50-k ? resistor pulls the pins high, while an internal 10-k ? resistor pulls the pins low to prevent them from floating. the i/o pins may have the following states: tristated (high-z) weak pull-up (via internal 50 k ? ) pull-down (via internal 10 k ? ) hold (i/o hold its value) when in low-power modes the jtag tdi, tmc, and trst# signals have fixed 50-k ? internal pull-ups, and the tck signal has a fixed 10-k ? pull-down resistor. all unused i/os should be pulled high by using the internal pull-up resistors. all unused outputs should be left floating. all i/os can be driven at full-strength, three-quarter strength, half-strength, or quarter-str ength. these driv e strengths are configured separately for each interface. gpios cx3 provides 12 pins for general purpose i/o (for example, can be used for lighting, sync-in, sync-out and so on). see pin configuration on page 14 for pinout details. all gpio pins support an external load of up to 16 pf for every pin. emi cx3 can meet emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consumer electronics at system level. cx3 can tolerate reasonable emi, conducted by the aggressor, outlined by these specifications and continue to function as expected. system-level esd cx3 has built-in esd protection on the d+, d?, and gnd pins on the usb interface. the esd protection levels provided on these ports are: 2.2-kv human body model (hbm) based on jesd22-a114 specification 6-kv contact discharge and 8-kv air gap discharge based on iec61000-4-2 level 3a us ing external system-level protection devices 8-kv contact discharge and 15-kv air gap discharge based on iec61000-4-2 level 4c us ing external system-level protection devices this protection ensures that the device continues to function after esd events up to the levels stated in this section. the ssrx+, ssrx?, sstx+, and sst x? pins only have up to 2.2-kv hbm internal esd protection.
cyusb306x document number: 001-87516 rev. *l page 14 of 37 pin configuration legend figure 5. cx3 ball map (top view) a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 u3vssq u3rxvddq ssrxm ssrxp sstxp sstxm avdd vss dp dm gpio[24] b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 vddio3 vss gpio[23] gpio[21] u3txvddq cvddq avss vss vss vdd trst# c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 spi_ssn / gpio[54] spi_miso / gpio[55] vdd gpio[26] reset# gpio[18] gpio[19] gpio[22] gpio[45] tdo i2s_mclk / gpio[57] d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 i2s_clk / gpio[50] i2s_sd / gpio[51] i2s_ws / gpio[52] spi_sck / gpio[53] spi_mosi / gpio[56] clkin_32 clkin vss i2c_scl i2c_sda gpio[17] e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 uart_cts / gpio[47] vss vddio2 uart_rx / gpio[49] uart_tx / gpio[48] gpio[20] tdi tms vdd vusb vss f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 dnu refclk gpio[44] xrst uart_rts / gpio[46] tck dnu dnu dnu dnu vdd g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 vss xshutdow n mclk pmode[0] / gpio[30] gpio[25] hsync_test dnu dnu dnu dnu vss h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 vdd dnu dnu pmode[1] / gpio[31] vsync_test mipi reset dnu pclk_test dnu dnu vddio1 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 dnu dnu dnu dnu mipi_d0p mipi_d1p 1 1. unused mipi input data lanes to be connected to gnd. mipi_cp mipi_d2p 1, 2 mipi_d2n 1, 2 2. the signals mipi_d2n, mipi_d2p, mipi_d3n, and mipi_d3p are not av ailable in the cyusb3064 part. these pins should be left "op en" in the customer board. dnu vdd k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 dnu dnu vss vss mipi_d0n mipi_d1n 1 mipi_cn mipi_d3n 1, 2 dnu dnu dnu l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 vss vss vss pmode[2] / gpio[32] vdd_mipi vss vdd mipi_d3p 1, 2 vddio1 dnu vss ground usb phy power supply; clock power supply power supply
cyusb306x document number: 001-87516 rev. *l page 15 of 37 pin description table 6. cyusb306x pin list cx3 pin# pin name i/o f10 dnu i/o f9 dnu i/o f7 dnu i/o g10 dnu i/o g9 dnu i/o f8 dnu i/o h10 dnu i/o h9 dnu i/o j10 dnu i/o h7 dnu i/o k11 dnu i/o l10 dnu i/o k10 dnu i/o k9 dnu i/o g7 dnu i/o g8 dnu i/o k2 dnu i/o j4 dnu i/o k1 dnu i/o j2 dnu i/o j3 dnu i/o j1 dnu i/o h2 dnu i/o h3 dnu i/o g6 hsync_test i/o h5 vsync_test i/o h8 pclk_test i/o vddio1 power domain d11 gpio[17] i/o c6 gpio[18] i/o c7 gpio[19] i/o e6 gpio[20] i/o b4 gpio[21] i/o c8 gpio[22] i/o b3 gpio[23] i/o a11 gpio[24] i/o g5 gpio[25] i/o c4 gpio[26] i/o f3 gpio[44] i/o c9 gpio[45] i/o g4 pmode[0] / gpio[30] i/o h4 pmode[1] / gpio[31] i/o l4 pmode[2] / gpio[32] i/o f1 dnu i/o h6 mipi reset i/o c5 reset# i f4 xrst o g2 xshutdown o g3 mclk o vddio2 power domain f5 uart_rts / gpio[46] i/o e1 uart_cts / gpio[47] i/o e5 uart_tx / gpio[48] i/o e4 uart_rx / gpio[49] i/o d1 i2s_clk / gpio[50] i/o d2 i2s_sd / gpio[51] i/o d3 i2s_ws / gpio[52] i/o vddio3 power domain d4 spi_sck / gpio[53] i/o c1 spi_ssn / gpio[54] i/o c2 spi_miso / gpio[55] i/o d5 spi_mosi / gpio[56] i/o c11 i2s_mclk / gpio[57] i/o usb port (u3txvddq/u3rxvddq power domain) a3 ssrxm i a4 ssrxp i a6 sstxm o a5 sstxp o usb port (vusb power domain) a9 dp i/o a10 dm i/o vddio1 power domain f2 refclk i vdd_mipi power domain j7 mipi_cp i table 6. cyusb306x pin list (continued) cx3 pin# pin name i/o
cyusb306x document number: 001-87516 rev. *l page 16 of 37 k7 mipi_cn i j5 mipi_d0p i k5 mipi_d0n i j6 mipi_d1p 1 i k6 mipi_d1n 1 i j9 mipi_d2n 1, 2 i j8 mipi_d2p 1, 2 i l8 mipi_d3p 1, 2 i k8 mipi_d3n 1, 2 i cvddq power domain d7 clkin i d6 clkin_32 i vddio1 power domain d9 i2c_scl i/o d10 i2c_sda i/o e7 tdi i c10 tdo o b11 trst# i e8 tms i f6 tck i power domains e10 vusb pwr a1 u3vssq pwr h11 vddio1 pwr l9 vddio1 pwr e3 vddio2 pwr b1 vddio3 pwr b6 cvddq pwr b5 u3txvddq pwr a2 u3rxvddq pwr a7 avdd pwr b7 avss pwr l5 vdd_mipi pwr b10 vdd pwr j11 vdd pwr c3 vdd pwr e9 vdd pwr f11 vdd pwr h1 vdd pwr table 6. cyusb306x pin list (continued) cx3 pin# pin name i/o l7 vdd pwr d8 vss pwr e2 vss pwr e11 vss pwr g1 vss pwr a8 vss pwr g11 vss pwr l1 vss pwr b8 vss pwr l6 vss pwr b2 vss pwr l11 vss pwr b9 vss pwr k4 vss pwr l3 vss pwr k3 vss pwr l2 vss pwr 1. unused mipi input data lanes to be connected to gnd. 2. the signals mipi_d2n, mipi_d2p, mipi _d3n, and mipi_d3p are not available in the cyusb3064 part. these pins should be left "open" in the customer board. table 6. cyusb306x pin list (continued) cx3 pin# pin name i/o
cyusb306x document number: 001-87516 rev. *l page 17 of 37 absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. storage temperature ......................... ...... ?65 c to +150 c supply voltage to ground potential v dd , a vddq ................................................................. 1.25 v v ddio1 , v ddio2 , v ddio3 ............................................. ...3.6 v u3tx vddq , u3rx vddq ......................................... .....1.25 v dc input voltage to any inpu t pin ............ ...............v cc + 0.3 dc voltage applied to outputs in high z state (v cc is the corresponding i/ o voltage) ... ........ .......v cc + 0.3 maximum latch-up current ........................................ 140 ma maximum output short-circuit current for all i/o configurations. (v out = 0 v) .................. ?100 ma operating conditions t a (ambient temperature under bias) industrial ................................................... ?40 c to +85 c v dd , a vddq , u3tx vddq , u3rx vddq supply voltage .............................................1.15 v to 1.25 v v usb supply voltage ..............................................4 v to 6 v v ddio1 , v ddio2 , v ddio3 , c vddq supply voltage .................................................1.7 v to 3.6 v dc specifications parameter description min max units notes v dd core voltage supply 1.15 1.25 v 1.2-v typical a vdd analog voltage supply 1.15 1.25 v 1.2-v typical v dd_mipi mipi bridge d-phy supply voltage 1.15 1.25 v 1.2-v typical v ddio1 i 2 c, jtag and gpio power domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v ddio2 uart/i 2 s power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v ddio3 spi/i 2 s power supply domain 1.7 3.6 v 1.8-, 2.5-, and 3.3-v typical v usb usb voltage supply 4 6 v 5-v typical u3tx vddq usb 3.0 1.2-v supply 1.15 1.25 v 1.2-v typical. a 22-f bypass capacitor is required on this power supply. u3rx vddq usb 3.0 1.2-v supply 1.15 1.25 v 1.2-v typical. a 22-f bypass capacitor is required on this power supply. c vddq clock voltage supply 1.7 3.6 v 1.8-, 3.3-v typical v ih1 input high voltage 1 0.625 v cc v cc + 0.3 v for 2.0 v ? v cc ? 3.6 v (except usb and mipi csi-2 pins).v cc is the corresponding i/o voltage supply. v ih2 input high voltage 2 v cc ? 0.4 v cc + 0.3 v for 1.7 v ? v cc ?? 2.0 v (except usb usb and mipi csi-2 pins).v cc is the corresponding i/o voltage supply. v il input low voltage ?0.3 0.25 v cc v v cc is the corresponding i/o voltage supply. v oh output high voltage 0.9 v cc ?v i oh (max) = ?100 a tested at quarter drive strength. v cc is the corresponding i/o voltage supply. v ol output low voltage ? 0.1 v cc v i ol (min) = +100 a tested at quarter drive strength. v cc is the corresponding i/o voltage supply.
cyusb306x document number: 001-87516 rev. *l page 18 of 37 i ix input leakage current for all pins except sstxp/ssxm/ssrxp/ssrxm ?1 1 a all i/o signals held at v ddq (for i/os with a pull-up or pull-down resistor connected, the leakage current increases by v ddq /r pu or v ddq /r pd ) i oz output high-z leakage current for all pins except sstxp/ ssxm/ ssrxp/ssrxm and mipi csi-2 signals ?1 1 a all i/o signals held at v ddq i cc core core and analog voltage operating current ? 192 ma total current through a vdd , v dd i cc usb usb voltage supply operating current ?60ma ? i sb1 total suspend current during suspend mode with usb 3.0 phy enabled core: 558.35 a ? a core current is measured through v dd , a vdd and v dd_mipi . i/o current is measured through v ddio1 to v ddio3 . usb current is measured through v usb , u3tx vddq and u3rx vddq . i/o: 4.58 a ? a usb: 4672 a ? a i sb3 total standby current during core power-down mode core: 148.31 a ? a i/o: 3.16 a ? a usb: 15.8 a ? a v ramp voltage ramp rate on core and i/o supplies 0.2 12 v/ms voltage ramp must be monotonic v n noise level permitted on v dd and i/o supplies ? 100 mv max p-p noise level permitted on all supplies except a vdd v n_avdd noise level permitted on a vdd supply ?20mv max p-p noise level permitted on a vdd dc specifications (continued) parameter description min max units notes mipi d-phy electrical characteristics parameter description spec unit min nom max mipi d-phy rx dc characteristics v pin pin signal voltage range ?50 ? 1350 mv v ih logic 1 input voltage 880 ? ? mv v il logic 0 input voltage ? ? 550 mv v cmrx (dc) common-mode voltage hs receiver mode 70 ? 330 mv v idth differential input high threshold ? 70 mv v idtl differential input low threshold ?70 ? ? mv v ihhs single-ended input high voltage ? 460 mv v ilhs single-ended input low voltage ?40 ? ? mv
cyusb306x document number: 001-87516 rev. *l page 19 of 37 ac timing parameters mipi data to clock timing reference figure 6. mipi csi signal data to clock timing reference reference clock specifications t setup t hold 0.5ui inst + t skew reference time 1 ui inst t clkp clkp clkn table 7. mipi data to clock timing reference parameter description min max units t skew data to clock skew meas ured at the transmitter ?0.15 0.15 ui inst t setup data to clock setup time at receiver 0.15 ? ui inst t hold clock to data hold time at receiver 0.15 ? ui inst ui inst one data bit time (instantaneous) 1 12.5 ns t clkp period of dual data rate clock 2 25 ns table 8. reference clock specifications parameter description min max units notes refclk reference clock frequency 6 40 mhz ? refclkdutycyl duty cycle 40% 60% ? ? refclkpj reference clock input period jitter -100 100 ps ?
cyusb306x document number: 001-87516 rev. *l page 20 of 37 mipi csi signal low power ac characteristics figure 7. mipi csi bus input glitch rejection ac specifications 2*t lpx 2*t lpx e spike e spike t min-rx t min-rx v ih v il input output table 9. mipi csi signal low power ac characteristics parameter description min max units notes e spike input noise rejection ? 300 v.ps time-voltage integration of a spike above v il when being in lp-0 or below v ih when being in lp-1 state. an impulse less than this will not change the receiver state. t min-rx minimum pulse width response 20 ? ns an input pulse greater than this shall toggle the output. v int peak interference amplitude ? 200 mv ? f int interference frequency 450 ? mhz ? t lpx length of any low power state period 50 ? ns ? table 10. ac specifications parameter description min max units details / conditions ? v cmrx(hf) common-mode interference beyond 450 mhz ? 100 mv ? v cmrx(hf) is the peak amp. of a sine wave superimposed on the receiver inputs. ? v cmrx(lf) common-mode interference beyond 50 - 450 mhz -50 50 mv excluding static ground shift of 50 mv. voltage difference compared to the dc average common-mode potential
cyusb306x document number: 001-87516 rev. *l page 21 of 37 serial peripherals timing i 2 c timing figure 8. i 2 c timing definition table 11. i 2 c timing parameters [2] parameter description min max units i 2 c standard mode parameters f scl scl clock frequency 0 100 khz t hd:sta hold time start condition 4 ? s t low low period of the scl 4.7 ? s t high high period of the scl 4 ? s t su:sta setup time for a repeated start condition 4.7 ? s t hd:dat data hold time 0 ? s t su:dat data setup time 250 ? ns t r rise time of both sda and scl signals ? 1000 ns t f fall time of both sda and scl signals ? 300 ns t su:sto setup time for stop condition 4 ? s t buf bus free time between a stop and start condition 4.7 ? s t vd:dat data valid time ? 3.45 s t vd:ack data valid ack ? 3.45 s t sp pulse width of spikes that must be suppressed by input filter n/a n/a note 2. all parameters guaranteed by design and validated through characterization.
cyusb306x document number: 001-87516 rev. *l page 22 of 37 i 2 c fast mode parameters f scl scl clock frequency 0 400 khz t hd:sta hold time start condition 0.6 ? s t low low period of the scl 1.3 ? s t high high period of the scl 0.6 ? s t su:sta setup time for a repeated start condition 0.6 ? s t hd:dat data hold time 0 ? s t su:dat data setup time 100 ? ns t r rise time of both sda and scl signals ? 300 ns t f fall time of both sda and scl signals ? 300 ns t su:sto setup time for stop condition 0.6 ? s t buf bus free time between a stop and start condition 1.3 ? s t vd:dat data valid time ? 0.9 s t vd:ack data valid ack ? 0.9 s t sp pulse width of spikes that must be suppressed by input filter 0 50 ns i 2 c fast mode plus parameters f scl scl clock frequency 0 1000 khz t hd:sta hold time start condition 0.26 ? s t low low period of the scl 0.5 ? s t high high period of the scl 0.26 ? s t su:sta setup time for a repeated start condition 0.26 ? s t hd:dat data hold time 0 ? s t su:dat data setup time 50 ? ns t r rise time of both sda and scl signals ? 120 ns t f fall time of both sda and scl signals ? 120 ns t su:sto setup time for stop condition 0.26 ? s t buf bus-free time between a stop and start condition 0.5 ? s t vd:dat data valid time ? 0.45 s t vd:ack data valid ack ? 0.55 s t sp pulse width of spikes that must be suppressed by input filter 0 50 ns table 11. i 2 c timing parameters [2] (continued) parameter description min max units
cyusb306x document number: 001-87516 rev. *l page 23 of 37 i 2 s timing diagram figure 9. i 2 s transmit cycle t t t tr t tf t tl t thd t td t th sck sa, ws (output) table 12. i 2 s timing parameters [3] parameter description min max units t t i 2 s transmitter clock cycle t tr ? ns t tl i 2 s transmitter cycle low period 0.35 t tr ? ns t th i 2 s transmitter cycle high period 0.35 t tr ? ns t tr i 2 s transmitter rise time ? 0.15 t tr ns t tf i 2 s transmitter fall time ? 0.15 t tr ns t thd i 2 s transmitter data hold time 0 ? ns t td i 2 s transmitter delay time ? 0.8 t t ns note t t is selectable throug h clock gears. max t tr is designed for 96-khz codec at 32 bits to be 326 ns (3.072 mhz). note 3. all parameters guaranteed by design and validated through characterization.
cyusb306x document number: 001-87516 rev. *l page 24 of 37 spi timing specification figure 10. spi timing lsb lsb msb msb lsb lsb msb msb t lead t sck t sdd t hoi t wsck t wsck t lag t d v t rf t ssnh t dis t sdi t lead t sck t wsck t wsck t lag t rf t ssnh t sdi t dis t dv t hoi ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) spi master timing for cpha = 0 spi master timing for cpha = 1 t di t di
cyusb306x document number: 001-87516 rev. *l page 25 of 37 table 13. spi timing parameters [4] parameter description min max units f op operating frequency 0 33 mhz t sck cycle time 30 ? ns t wsck clock high/low time 13.5 ? ns t lead ssn-sck lead time 1/2 t sck [5] ? 5 1.5 t sck [5] + 5 ns t lag enable lag time 0.5 1.5 t sck [5] + 5 ns t rf rise/fall time ? 8 ns t sdd output ssn to valid data delay time ? 5 ns t dv output data valid time ? 5 ns t di output data invalid 0 ? ns t ssnh minimum ssn high time 10 ? ns t sdi data setup time input 8 ? ns t hoi data hold time input 0 ? ns t dis disable data output on ssn high 0 ? ns notes 4. all parameters guaranteed by design and validated through characterization. 5. depends on lag and lead sett ing in the spi_config register.
cyusb306x document number: 001-87516 rev. *l page 26 of 37 reset sequence cx3?s hard reset sequence requirement s are specified in this section. figure 11. reset sequence table 14. reset and standby timing parameters parameter definition conditions min (ms) max (ms) t rpw minimum reset# pulse width clock input 1 ? t rh minimum high on reset# ? 5 ? t rr reset recovery time (after which the boot loader begins firmware download) clock input 1 ? t sby time to enter standby/suspend mode (from the time main_clock_en/ main_power_en bit is set) ? ? 1 t wu time to wakeup from standby clock input 1 ? t wh minimum time before standby/suspend source may be reasserted ? 5 ? vdd (core) xvddq clkin reset# mandatory reset pulse hard reset t rpw t rh standby/ suspend source standby/suspend source is asserted (main_power_en/ main_clk_en bit is set) standby/suspend source is deasserted t sby t wu clkin must be stable before exiting standby/suspend t rr t wh
cyusb306x document number: 001-87516 rev. *l page 27 of 37 ordering information ordering code definitions table 15. ordering information ordering code mipi csi-2 lanes package type temperature grade cyusb3065-bzxi 4 121-ball bga industrial CYUSB3065-BZXC 4 121-ball bga commercial cyusb3064-bzxi 2 121-ball bga industrial cyusb3064-bzxc 2 121-ball bga commercial temperature grade: i = industrial c = commercial pb-free package type: bz = 121-ball bga x = 4 for up to 2 mipi csi-2 lanes x = 5 for up to 4 mipi csi-2 lanes density: base part number for usb 3.0 marketing code: usb = usb controller company id: cy = cypress cy bz usb 3 x - i 06x
cyusb306x document number: 001-87516 rev. *l page 28 of 37 package diagram figure 12. 121-ball bga (10 10 1.7 mm) package outline, 001-87293 001-87293 **
cyusb306x document number: 001-87516 rev. *l page 29 of 37 acronyms document conventions units of measure table 16. acronyms used in this document acronym description csi - 2 camera serial interface - 2 dma direct memory access dnu do not use hnp host negotiation protocol mipi mobile industry processor interface mmc multimedia card mtp media transfer protocol pll phase locked loop pmic power management ic sd secure digital sdio secure digital input / output slc single-level cell spi serial peripheral interface srp session request protocol usb universal serial bus wlcsp wafer level chip scale package table 17. units of measure symbol unit of measure c degree celsius mbps megabits per second mbps megabytes per second mhz megahertz a microampere s microsecond ma milliampere ms millisecond ns nanosecond ? ohm pf picofarad vvolt
cyusb306x document number: 001-87516 rev. *l page 30 of 37 errata this section describes the errata for cx3. details include erra ta trigger conditions, scope of impact, available workaround, an d silicon revision applicability. contact your local cypr ess sales representative if you have questions. part numbers affected qualification status product status: production errata summary the following table defines the errata applicability to availa ble ez-usb cx3 superspeed usb controller family devices. 1. turning off vddio1 during normal, suspend, and standby modes causes the cx3 to stop working. problem definition turning off the vddio1 during normal, suspend, and standby modes will cause th e cx3 to stop working. parameters affected n/a trigger conditions this condition is triggered when the vddio1 is turned off during normal, suspend, and standby modes. scope of impact cx3 stops working. workaround vddio1 must stay on during normal, suspend, and standby modes. fix status no fix. workaround is required. part number device characteristics cyusb306x-xxxx all variants items [part number] silicon revision fix status 1. turning off vddio1 during normal, suspend, and standby modes causes t he cx3 to stop working. cyusb306x-xxxx all workaround provided 2. usb enumeration failure in usb boot mode when cx3 is self-powered. cyusb306x-xxxx all workaround provided 3. extra zlp is generated by the commit action in the gpif ii state. cyusb306x-xxxx all workaround provided 4. invalid pid sequence in usb 2.0 isoc data transfer. cyusb306x-xxxx all workaround provided 5. usb data transfer errors are seen when zlp is followed by data packet within same microframe. cyusb306x-xxxx all workaround provided 6. bus collision is seen when the i2c block is used as a master in the i2c multi-master configuration. cyusb306x-xxxx all use cx3 in single-master configuration
cyusb306x document number: 001-87516 rev. *l page 31 of 37 2. usb enumeration failure in usb boot mode when cx3 is self-powered. problem definition cx3 device may not enumerate in usb boot mode when it is self-powered. the boot loader is designed for bus power mode. it does not make use of the vusb pin on the usb connector to de tect the usb connection and expe ct that usb bus is connected to host if it is powered. if cx3 is not al ready connected to the usb host when it is powered, then it enters into low-power mod e and does not wake up when connected to usb host. parameters affected n/a trigger conditions this condition is triggered when cx 3 is self-powered in usb boot mode. scope of impact device does not enumerate workaround reset the device after connecting to usb host. fix status no fix. workaround is required. 3. extra zlp is generated by the commit action in the gpif ii state. problem definition when commit action is used in a gpif-ii state without in _data action then an extra zero length packet (zlp) is committed along with the data packets. parameters affected n/a trigger conditions this condition is triggered when commit acti on is used in a state without in_data action. scope of impact extra zlp is generated. workaround use in_data action along with commit action in the same state. fix status no fix. workaround is required.
cyusb306x document number: 001-87516 rev. *l page 32 of 37 4. invalid pid sequence in usb 2.0 isoc data transfer. problem definition when the cx3 device is functioning as a high speed usb device with high bandwidth isochronous endpoints, the pid sequence of the iso data packets is governed solely by the isomult settin g. the length of the data packet is not considered while genera ting the pid sequence during each microframe. for example, even if a short packet is being sent on an endpoint with mult set to 2; the pid used will be data2. parameters affected n/a trigger conditions this condition is triggered when high ba ndwidth isoc transfer endpoints are used. scope of impact isoc data transfers failure. workaround this problem can be worked around by reconfiguring the endpoint with a lower is omult setting prior to sending short packets, an d then switching back to the original value. fix status no fix. workaround is required. 5. usb data transfer errors are seen when zlp is followed by data packet within same microframe. problem definition some data transfer errors may be seen if a zero length packet is followed very quickly (within one microframe or 125 s) by another data packet on a burst enabled usb in endpoint operating at super speed. parameters affected n/a trigger conditions this condition is triggered in superspeed transfer with zlps. scope of impact data failure and lower data speed. workaround the solution is to ensure that some time is allowed to elapse between a zlp and the next data packet on burst enabled usb in endpoints. if this cannot be ensured at the data source, th e cyu3pdmachannelsetsuspend() api can be used to suspend the corresponding usb dma socket on seeing the eop condition. the channel operation can then be resumed as soon as the suspend callback is received. fix status no fix. workaround is required.
cyusb306x document number: 001-87516 rev. *l page 33 of 37 6. bus collision is seen when the i 2 c block is used as a master in the i 2 c multi-master configuration. problem definition when cx3 is used as a master in the i 2 c multi-master configuration, there can be occasional bus collisions. parameters affected na trigger conditions this condition is triggered only when the cx3 i 2 c block operates in multi-master configuration. scope of impact the cx3 i 2 c block can transmit data when the i 2 c bus is not idle leading to bus collision. workaround use cx3 as a single master. fix status no fix.
cyusb306x document number: 001-87516 rev. *l page 34 of 37 document history page document title: cyusb306x, ez-usb ? cx3: mipi csi-2 to supers peed usb bridge controller document number: 001-87516 revision ecn orig. of change submission date description of change ** 3994736 kumr 05/09/2013 new datasheet *a 4065766 kumr 07/17/2013 updated logic block diagram . updated pin description . updated dc specifications . replaced ?vbus? and ?vbatt? by ?vusb? in all instances across the document. updated in new template. *b 4080302 kumr 07/29/2013 updated status as ?preliminary?. *c 4088328 kumr 08/06/2013 updated pin configuration (updated figure ). *d 4113754 kumr 09/04/2013 updated clocking : added a note at the bottom of section. updated pin description . updated table 6 . updated dc specifications : updated description of v ddio2 parameter. updated description of v ddio3 parameter. changed maximum value of i cc core parameter from 200 ma to 380 ma. *e 4188453 kumr 11/14/2013 changed stat us from preliminary to final. updated features : updated description. updated applications : updated description. updated logic block diagram . updated functional overview . updated mipi csi-2 rx interface . updated additional outputs : updated description. updated reset . updated soft reset : updated description. updated power . updated power modes . updated table 5 . updated ?methods of entry? corresponding to ?suspend mode with usb 3.0 phy enabled?. updated ?characteristics? corresponding to ?standby mode?. updated emi : updated description. updated system-level esd : updated description. updated pin configuration : updated details of g4, h4, l4, f1, f5 , e1, e5, e4, d1, d2, d3, d4, c1, c2, d5, c11 pins in figure . updated pin description . updated details in ?pin name? column for g4, h4, l4, f1, f5, e1, e5, e4, d1, d2, d3, d4, c1, c2, d5, c11 pins. updated absolute maximum ratings : removed ?ambient temperature with power applied?. removed ?static discharge voltage esd protection levels?. renamed ?latch-up current? as ?max imum latch-up current? and updated the values. updated dc specifications : updated details in ?notes? column corresponding to v ih1 and v ih2 parameters. updated description of i oz parameter. updated minimum value of i sb1 and i sb3 parameters. updated details in ?notes? column corresponding to i sb1 and i sb3 parameters. added mipi d-phy electrical characteristics . updated ac timing parameters . updated mipi data to clock timing reference .
cyusb306x document number: 001-87516 rev. *l page 35 of 37 *e (cont.) 4188453 kumr 11/14/2013 updated figure 6 . updated table 7 . updated minimum value of ui inst parameter. updated maximum value of t clkp parameter. updated mipi csi signal low power ac characteristics : updated figure 7 . updated serial peripherals timing . updated i2c timing . updated table 11 : removed ?(not supported at i2c_vddq = 1.2 v)? in ?i 2 c fast mode plus parameters? sub-heading. updated reset sequence . updated table 14 . removed ?crystal input? condition for t rpw , t rr , t wu parameters. updated figure 11 . updated ordering information : updated part numbers. *f 4214952 raja 03/12/2014 updated features . updated functional overview . updated application examples . updated figure 1 . updated configuration options : added email. updated pin description . updated caption of table 6 . updated dc specifications : updated maximum value of v il parameter. updated maximum value of v ramp parameter. updated ac timing parameters . updated mipi csi signal low power ac characteristics . updated table 9 . updated details in ?notes? column. updated to new template. *g 4417040 kumr 06/23/2014 updated power : updated details of io_vddq power supply domain. updated dc specifications : updated maximum value of i cc core parameter. *h 4467092 raja 08/06/2014 added new pa rt numbers: 2 and 4 mipi csi- 2 lane parts with industrial and commercial temperature grades. hsync, vsync, pclk test points mentio ned in the pin configuration table mclk - signal description updated. updated information for cyusb3064 part number: mipi_d2p, mipi_d2n, mipi_d3p, mipi_d3n signals not available. *i 4862446 rago 08/13/2015 added footnote 1, and updated pin configuration ( figure 5 ) and pin description ( ta b l e 6 ) to indicate grounding of unused mipi lanes. *j 4974015 rago 10/19/2015 added more information . *k 5283275 rago 05/24/2016 updated to new template. completing sunset review. document history page (continued) document title: cyusb306x, ez-usb ? cx3: mipi csi-2 to supers peed usb bridge controller document number: 001-87516 revision ecn orig. of change submission date description of change
cyusb306x document number: 001-87516 rev. *l page 36 of 37 *l 5464498 raja 06/22/2017 updated power : updated description. updated operating conditions : replaced ?3.2 v? with ?4 v? in operating conditions corresponding to ?v usb supply voltage?. updated dc specifications : changed minimum value of v usb parameter from 3.2 v to 4 v. added errata . updated to new template. document history page (continued) document title: cyusb306x, ez-usb ? cx3: mipi csi-2 to supers peed usb bridge controller document number: 001-87516 revision ecn orig. of change submission date description of change
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