View 8V41N010_8918133.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet clock generator for cavium processors 8V41N010 8V41N010 revision 1 06/30/15 1 ?2015 integrated device technology, inc. general description the 8V41N010 is a pll-based clock generator specifically designed for cavium networks octeon ii processors. this high performance device is optimized to generate the processor core reference clock, the pci-express, srio, xaui, serdes reference clocks and the clocks for both the gigabit ethernet mac and phy. the output fre- quencies are generated from a 25mhz external input source or an external 25mhz parallel resonant crystal. the industrial temperature range of the 8V41N010 supports telecommunication, networking, and storage requirements. features ? eight selectable 100mhz and 156.25mhz clocks for pci express, srio and gbe, hcsl interface levels ? one single-ended qf lvcmos/lvttl clock output at 50mhz ? selectable external crystal or differential (single-ended) input source ? crystal oscillator interface designed for 25mhz, parallel resonant crystal ? differential clk, nclk input pair that can accept: lvpecl, lvds, lvhstl, hcsl input levels ? internal resistor bias on nclk pin allows the user to drive clk input with external single-ended (lvcmos/ lvttl) input levels ? full 3.3v supply mode ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging pin assignment 72-pin, 10mm x 10mm vfqfn package 8xxxxxx nc v ddo nc nc gnd nc fsel_e1 ref_sel v dd xtal_in xtal_out pll_sel nc fsel_a1 clk nclk nc fsel_b1 v ddo_qe iref oe_d gnd nc nc nqd0 qd0 v ddo_qd v dd oe_c gnd nqc1 qc1 nqc0 qc0 v ddo_qc oe_b qe0 nqe0 qe1 nqe1 gnd oe_e nc fsel_c1 gnd v dda nc fsel_d1 v dd nmr v ddo nc gnd nc gnd nc nc nqb0 qb0 v ddo_qb oe_a gnd nqa1 qa1 nqa0 qa0 v ddo_qa gnd v dd gnd qf v ddo_qf 8V41N010 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 101112131415161718 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 note: exposed pad must always be connected to gnd. note: pin 1 is located at bottom left corner as shown.
clock generator for cavium pr ocessors 2 revision 1 06/30/15 8V41N010 data sheet block diagram qa0 nqa0 qf 50mhz qa1 nqa1 qb0 nqb0 qc0 nqc0 qc1 nqc1 qd0 nqd0 clk nclk qe0 nqe0 qe1 nqe1 nmr fsel_a1 fsel_b1 fsel_c1 fsel_d1 fsel_e1 pll_sel ref_sel oe_e oe_d oe_c oe_b oe_a xtal_in xtal_out i_ref 1 0 femtoclock ng vco 0 = 100mhz 1 = 156.25mhz 0 = 100mhz 1 = 156.25mhz 0 = 100mhz 1 = 156.25mhz 0 = 100mhz 1 = 156.25mhz 0 = 100mhz 1 = 156.25mhz clock output control logic 1 0 pulldown pulldown pulldown pulldown pulldown pullup pullup pulldown osc pu/pd pullup pullup pullup pullup pullup pulldown
revision 1 06/30/15 3 clock generator for cavium processors 8V41N010 data sheet pin descriptions and characteristics table 1. pin descriptions number name type description 1 nc unused no internal connection. 2v ddo power output supply. 3 nc unused no internal connection. 4 nc unused no internal connection. 5 gnd power power supply ground. 6 nc unused no internal connection. 7 fsel_e1 input pulldown selects the qex, nqex output frequen cy. lvcmos/lvttl interface levels. 0 = 100mhz (default) 1 = 156.25mhz 8 ref_sel input pullup input source control pin. lvcmos/lvttl interface levels. 0 = clk, nclk 1 = xtal (default) 9v dd power core supply. 10 xtal_in crystal input parallel resonant crystal input. 11 xtal_out crystal output parallel resonant crystal output. 12 pll_sel input pullup pll bypass control pin. lvcmos/lvttl interface levels. 0 = bypass mode 1 = pll mode (default) 13 nc unused no internal connection. 14 fsel_a1 input pulldown selects the qax, nqax output frequen cy. lvcmos/lvttl interface levels. 0 = 100mhz (default) 1 = 156.25mhz 15 clk input pulldown non-inverting differential clock input. 16 nclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v dd /2. 17 nc unused no internal connection. 18 fsel_b1 input pulldown selects the qbx, nqbx output frequen cy. lvcmos/lvttl interface levels. 0 = 100mhz (default) 1 = 156.25mhz 19 v ddo_qf power qf output supply (lvcmos/lvttl). 20 qf output single-ended output. 3.3v lvcmos/lvttl interface levels. 21 gnd power power supply ground. 22 v dd power core supply. 23 gnd power power supply ground. 24 v ddo_qa power bank a (hcsl) output supply. 25 qa0 output bank a differential out put pair. hcsl interface levels. 26 nqa0 output bank a differential output pair. hcsl interface levels. 27 qa1 output bank a differential out put pair. hcsl interface levels. 28 nqa1 output bank a differential output pair. hcsl interface levels. 29 gnd power power supply ground. 30 oe_a input pullup active high output enable for bank a outputs. lvcmos/lvttl interface levels. 0 = bank a outputs disabled/high impedance 1 = bank a outputs enabled (default)
clock generator for cavium pr ocessors 4 revision 1 06/30/15 8V41N010 data sheet 31 v ddo_qb power bank b (hcsl) output supply. 32 qb0 output bank b differential out put pair. hcsl interface levels. 33 nqb0 output bank b differential output pair. hcsl interface levels. 34 nc unused no internal connection. 35 nc unused no internal connection. 36 gnd power power supply ground. 37 oe_b input pullup active high output enable for bank b outputs. lvcmos/lvttl interface levels. 0 = bank b outputs disabled/high impedance 38 v ddo_qc power bank c (hcsl) output supply. 39 qc0 output bank c differential output pair. hcsl interface levels. 40 nqc0 output bank c differential output pair. hcsl interface levels. 41 qc1 output bank c differential output pair. hcsl interface levels. 42 nqc1 output bank c differential output pair. hcsl interface levels. 43 gnd power power supply ground. 44 oe_c input pullup active high output enable for bank c ou tputs. lvcmos/lvttl interface levels. 0 = bank c outputs disabled/high impedance 1 = bank c outputs enabled (default) 45 v dd power core supply. 46 v ddo_qd power bank d (hcsl) output supply. 47 qd0 output bank d differential output pair. hcsl interface levels. 48 nqd0 output bank d differential output pair. hcsl interface levels. 49 nc unused no internal connection. 50 nc unused no internal connection. 51 gnd power power supply ground. 52 oe_d input pullup active high output enable for bank d ou tputs. lvcmos/lvttl interface levels. 0 = bank d outputs disabled/high impedance 53 iref input external fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for differential current-mode. 54 v ddo_qe power bank e (hcsl) output supply. 55 qe0 output bank e differential output pair. hcsl interface levels. 56 nqe0 output bank e differential output pair. hcsl interface levels. 57 qe1 output bank e differential output pair. hcsl interface levels. 58 nqe1 output bank e differential output pair. hcsl interface levels. 59 gnd power power supply ground. 60 oe_e input pullup active high output enable for bank e outputs. lvcmos/lvttl interface levels. 0 = bank e outputs disabled/high impedance 1 = bank e outputs enabled (default) 61 nc unused no internal connection. 62 fsel_c1 input pulldown selects the qcx, nqcx output frequen cy. lvcmos/lvttl interface levels. 0 = 100mhz (default) 1 = 156.25mhz 63 gnd power power supply ground. 64 v dda power analog supply. table 1. pin descriptions number name type description , continued
revision 1 06/30/15 5 clock generator for cavium processors 8V41N010 data sheet note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3a. fsel_x control input function table note: fsel_x denotes fsel_a, _b, _c, _d, _e. note: any two outputs operated at the same frequency will be synchronous. table 3b. pll_sel control input function table table 3c. ref_sel control input function table table 3d. oe_[a:e] control input function table 65 nc unused no internal connection. 66 fsel_d1 input pulldown selects the qdx, nqdx output frequen cy. lvcmos/lvttl interface levels. 0 = 100mhz (default) 1 = 156.25mhz 67 v dd power core supply. 68 nmr input pulldown active low master reset. lv cmos/lvttl interface levels. 0 = reset. the internal dividers are reset causing the true outputs qx to go low and the inverted outputs nqx to go high. (default) 1 = active. the internal dividers and the outputs are active. 69 v ddo power output supply. 70 nc unused no internal connection. 71 gnd power power supply ground. 72 nc unused no internal connection. epad gnd _ep power exposed pad of package. connect to gnd. symbol parameter test conditio ns minimum typical maximum units c in input capacitance clk, nclk 2.5 pf control pins 6 pf r pullup input pullup resistor 50 k ? r pulldown input pulldown resistor 50 k ? r out output impedance qf v ddo_qf = 3.465v 15 ? table 1. pin descriptions number name type description input output frequency fsel_x1 q[ax:ex], nq[ax:ex] 0 (default) 100mhz 1156.25mhz input operation pll_sel 0 pll bypass 1 (default) pll mode input clock source ref_sel 0 clk, nclk 1 (default) xtal_in, xtal_out input outputs oe_[a:e] q[ax:ex], nq[ax:ex] 0 high-impedance 1 (default) enabled
clock generator for cavium pr ocessors 6 revision 1 06/30/15 8V41N010 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics item rating supply voltage, v dd 3.6v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo_qx 1 + 0.5v note 1. v ddo_qx denotes: v ddo_qa, v ddo_qb, v ddo_qc, v ddo_qd, v ddo_qe, v ddo_qf. maximum junction temperature, t jmax 125c storage temperature, t stg -65 ? c to 150 ? c table 4a. power supply dc characteristics, v dd = 3.3v 5%, v ddo_q[a:e] = v ddo_qf = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo_qx 1 note 1. v ddo_qx denotes v ddo_q[a:e], v ddo_qf. output supply voltage 3.135 3.3 3.465 v i dd power supply current 193 235 ma i dda analog supply current 36 47 ma i ddo_qx 2 note 2. i ddo_qx denotes i ddo_q[a:e] + i ddo_qf. output supply current no load 24 30 ma
revision 1 06/30/15 7 clock generator for cavium processors 8V41N010 data sheet table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo_q[a:e] = v ddo_qf = 3.3v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5. table 5. crystal characteristics table 6. input frequency characteristics, v dd = v ddo_q[a:e] = v ddo_qf = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current nmr, fsel_a1, fsel_b1, fsel_c1, fsel_d1, fsel_e1 v dd = v in = 3.465v 150 a ref_sel, pll_sel, oe_a, oe_b, oe_c, oe_d, oe_e v dd = v in = 3.465v 10 ua i il input low current nmr, fsel_a1, fsel_b1, fsel_c1, fsel_d1, fsel_e1 v dd = 3.465v, v in = 0v -10 a ref_sel, pll_sel, oe_a, oe_b, oe_c, oe_d, oe_e v dd = 3.465v, v in = 0v -150 ua v oh output high voltage v ddo_qf = 3.465v 2.6 v v ol output low voltage v ddo_qf = 3.465v 0.6 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v dd = v in = 3.465v 150 a i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak input voltage 1 note 1. v il should not be less than -0.3v. 0.15 1.3 v v cmr common mode input voltage 12 note 2. common mode voltage is defined as v ih . 0.5 v dd ? 0.85 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? load capacitance (cl) 12 pf shunt capacitance 7pf symbol parameter test conditio ns minimum typical maximum units f in input frequency clk, nclk 25 mhz xtal_in, xtal_out 25 mhz
clock generator for cavium pr ocessors 8 revision 1 06/30/15 8V41N010 data sheet ac electrical characteristics table 7a. pci express jitter specifications, v dd = v ddo_q[a:e] = 3.3v 5%, t a = -40c to 85c 1 2 note 1. electrical parameters are guarant eed over the specified ambient operating tem perature range, which is established when the device is mounted in a test socket with maintained transverse airf low greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. for additional information, refer to the pci express application note section in the datasheet. note 2. design target specifications. symbol parameter test condit ions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak 3 4 note 3. peak-to-peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci e xpress gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 4. this parameter is guaranteed by characterization. not tested in production. ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 6.97 11.18 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms 3 5 note 5. rms jitter after applying the two evaluation bands to t he two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t refclk_h- f_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 0.70 1.84 3.10 ps t refclk_lf_rms (pcie gen 2) phase jitter rms 3 4 ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.03 0.07 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms 3 6 note 6. rms jitter after applying system transfer function for th e common clock architecture. this specification is based on th e pci ex- press base specification revision 0.7, october 2009 and is subject to change pending the final release version of the specification. ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.16 0.49 0.8 ps
revision 1 06/30/15 9 clock generator for cavium processors 8V41N010 data sheet table 7b. hcsl ac characteristics, v dd = v ddo_q[a:e] = v ddo_qf = 3.3v 5%, t a = -40c to 85c 1 2 3 note 1. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the devi ce is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reache d under these conditions. note 2. all parameters measured at f out and in pll mode unless noted otherwise. note 3. refer to applications section for info rmation on peak-to-peak jitter calculations. symbol parameter test conditions minimum typical maximum units f out output frequency q[a:e], nq[a:e] fsel_x1 = 0 100 mhz fsel_x1 = 1 156.25 mhz v rb ring-back voltage margin 4 5 note 4. measurement taken from differential waveform. note 5. t stable is the time the differential clock must maintain a minimum 150 mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv range. see parameter measurement information section. q[a:e], nq[a:e] -100 100 mv t stable time before v rb is allowed 1 2 q[a:e], nq[a:e] 500 ps v max absolute max output voltage 6 7 note 6. measurement taken from single-ended waveform. note 7. defined as the maximum instantaneous voltage including overshoot. q[a:e], nq[a:e] 1150 mv v min absolute min output voltage 3 8 note 8. defined as the minimum instantaneous voltage including undershoot. q[a:e], nq[a:e] -300 mv v cross absolute crossing voltage 3 9 10 note 9. measured at the crossing point where the in stantaneous voltage value of the rising e dge of q[ax:ex] equals the falling edge of nq[ax:ex] note 10. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to al l cross- ing points for this measurement. q[a:e], nq[a:e] 175 550 mv ? v cross total variation of v cross over all edges 3 6 11 note 11. defined as the total variation of all crossi ng voltages of rising q[ax:ex] and fallin g nq[ax:ex]. this is the maximum allowed v ari- ance in vcross for any particular system. q[a:e], nq[a:e] 140 mv t slew+ rising edge rate 1 12 note 12. measured from -150mv to +150mv on the differential waveform (derived from q[ax:ex] minus nq[ax:ex]). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential z ero crossing q[a:e], nq[a:e] 0.6 4.0 v/ns t slew- falling edge rate 1 9 q[a:e], nq[a:e] 0.6 4.0 v/ns odc output duty cycle q[a:e], nq[a:e] 48 50 52 % tjit(?) rms phase jitter, (random) 13 note 13. measurements taken with 25mhz xtal as input source and spur off q[a:e], nq[a:e] 100mhz, integration range: (12khz to 20mhz) 0.32 0.45 ps 156.25mhz, integration range: (12khz to 20mhz) 0.30 0.45 ps tjit(rms) jitter, rms q[a:e], nq[a:e] = 100mhz or 156.25mhz, 25mhz xtal, pll mode 14 note 14. all differential outputs are running at the same frequency. 2.6 ps tjit(p-p) jitter, (peak-to-peak) 15 note 15. tjit(p-p) is a calculated value given rms multiplier = 7.438. for detailed description of algorithm, please refer to section, ?ap- plications information? , peak-to-peak jitter calculations . 19 ps
clock generator for cavium proc essors 10 revision 1 06/30/15 8V41N010 data sheet table 7c. lvcmos ac characteristics, v dd = v ddo_q[a:e] = v ddo_qf = 3.3v 5%, t a = -40c to 85c 1 note 1. electrical parameters are guaranteed over the specifie d ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f out output frequency qf 50 mhz tr/tf output rise/fall time qf 20% to 80% 180 700 ps odc output duty cycle qf 47 50 53 % tjit(?) rms phase jitter, (random) 2 note 2. measurements taken with 25mhz xtal as input source and spur off. qf 50mhz, integration range: (12khz to 20mhz) 0.35 0.45 ps tjit(r j ) random jitter, rms 3 note 3. measurements taken with wavecrest sia-3000 analyzer. qf q[a:e], nq[a:e] = 156.25mhz, 25mhz xtal, pll mode 2ps tjit(d j ) deterministic jitter, pk-to-pk 4 qf q[a:e], nq[a:e] = 156.25mhz, 25mhz xtal, pll mode 3ps
revision 1 06/30/15 11 clock generator for cavium processors 8V41N010 data sheet typical phase noise at 156.25mhz noise power (dbc/hz) offset frequency (hz)
clock generator for cavium proc essors 12 revision 1 06/30/15 8V41N010 data sheet applications information peak-to-peak jitter calculations a standard deviation of a statistical population or data set is the square root of its variance. a standard deviation is used to calculate the probability of an anomaly or to predict a failure. many times, the term "root mean square" (rms) is used synonymously for standard deviation. this is accurate when referring to the square root of the mean squared deviation of a signal from a given baseline and when the data set contains a gaussian distribution with no deterministic components. a low standard deviatio n indicates that the data set is close to the mean with little variation. a large standard deviation indicates that the data set is spread out and has a large variation from the mean. a standard deviation is required when calculating peak-to-peak jitter. since true peak-to-peak jitter is random and unbounded, it is important to always associate a bit error ratio (ber) when specifying a peak-to-peak jitter limit. without it, the specification does not have a boundary and will continue get larger with sample size. given that a ber is application specific, many frequency timing devices specify jitter as an rms. this allows the peak-to-peak jitter to be calculated for the specific application and ber requirement. because a standard deviation is the variation from the mean of the data set, it is important to always calculate the peak-to-peak jitter using the typical rms value. ta b l e 8 shows the ber with its appropriate rms multiplier. there are two columns for the rms multiplier, one should be used if your signal is data and the other should be used if the signal is a repetitive clock signal. the difference between the two is the data transition density (dtd). the dtd is the number of rising or falling transitions divided by the total number of bits. for a clock signal, they are equal, hence the dtd is 1. for data, on average, most common encoding standards have a 0.5 dtd. table 8. ber table once the ber is chosen, there are two circumstances to consider. is the data set purely gaussian or does it contains any deterministic component? if it is gaussian, then the peak to peak jitter can be calculated by simply multiplying the rms multiplier with the typical rms specification. for example, if a 10 -12 ber is required for a clock signal, multiply 14.260 times the typical jitter specification. jitter (peak-to-peak) = rms mu ltiplier * rms (typical) if the datasheet contains determini stic components, then the random jitter (r j ) and deterministic jitter (d j ) must be separated and analyzed separately. r j, also known as gaussian jitter, is not bounded and the peak-to-peak will continue to get larger as the sample size increases. alternatively, peak-to-peak value of d j is bounded and can easily be observed and predicted. therefore, the peak to peak jitter for the random component must be added to the deterministic component. this is called total jitter (t j ). total jitter (peak-to-peak) = [r ms multiplier * random jitter (r j )] + deterministic jitter (d j ) the total jitter equation is not specific to one type of jitter classification. it can be used to calculate ber on various types of rms jitter. it is important that the user understands their jitter requirement to ensure they are ca lculating the correct ber for their jitter requirement. note: use r j and d j values from ac characteristics tables 7b and 7c to calculate t j . ber rms multiplier data, ?dtd = 0.5? rms multiplier clock, ?dtd = 1? 10 -3 6.180 6.582 10 -4 7.438 7.782 10 -5 8.530 8.834 10 -6 9.507 9.784 10 -7 10.399 10.654 10 -8 11.224 11.462 10 -9 11.996 12.218 10 -10 12.723 12.934 10 -11 13.412 13.614 10 -12 14.069 14.260 10 -13 14.698 14.882 10 -14 15.301 15.478 10 -15 15.883 16.028
revision 1 06/30/15 13 clock generator for cavium processors 8V41N010 data sheet wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
clock generator for cavium proc essors 14 revision 1 06/30/15 8V41N010 data sheet 3.3v differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driv en by a 3.3v lvds driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v hcsl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t
revision 1 06/30/15 15 clock generator for cavium processors 8V41N010 data sheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 3a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 3b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminati on with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3a. general diagram for lvcmos driver to xtal input interface figure 3b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
clock generator for cavium proc essors 16 revision 1 06/30/15 8V41N010 data sheet recommended termination figure 4a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 4a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 4b is the recommended termination for applications where a point-to-point connection can be us ed. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 4b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
revision 1 06/30/15 17 clock generator for cavium processors 8V41N010 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvcmos outputs all unused lvcmos outputs can be le ft floating. there should be no trace attached. differential outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
clock generator for cavium proc essors 18 revision 1 06/30/15 8V41N010 data sheet pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the ent ire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
revision 1 06/30/15 19 clock generator for cavium processors 8V41N010 data sheet schematic example figure 8 (next page) shows an example of 8V41N010 application schematic. in this example, the device is operated at v dd = v dda = v ddo_qx = 3.3v. the schematic example focuses on functional connections and is not configurat ion specific. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. a 12pf parallel resonant 25mhz crystal is used. for this device, the crystal load capacitors are required for proper operation. the load capacitance, c1 = c2 = 2pf, are recommended for frequency accuracy. depending on the variatio n of the parasitic stray capacity of the printed circuit board traces between the crystal and the xtal_in and xtal_out pins, the values of c1 and c2 might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specificat ions can be used, but this will require adjusting c1 and c2. when designing the circuit board, return the capacitors to ground though a single point contact close to the package. two fox crystal options are shown in the schematic for design flexibility. the epad provides a low thermal impedance connection between the internal device and the pcb. it also provides an electrical connection to the die and must be connected to ground. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the 8V41N010 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1f capacitor in each power pi n filter should be placed on the device side. the other components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter st arts to attenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices.
clock generator for cavium proc essors 20 revision 1 06/30/15 8V41N010 data sheet figure 8. 8V41N010 schematic example place each 0.1uf bypass cap directly adjacent to the corresponding vddo pin. to logic input pins to logic input pins set logic input to '1' logic control input examples set logic input to '0' place each 0.1uf bypass cap directly adjacent to its corresponding vdd or vdda pin. 0" to 18" 0.5" to 3.5" 1" to 14" hcsl termination pci express add-in card optional pci express point-to-point connection cmos source termination fox p/n: 277lf-25-99 fox fx325bs alternate crystal 25mhz(12pf) vdd vdd clk nclk xtal_in xtal_out ref_sel pll_sel nmr oe_a oe_b oe_c oe_d oe_e vdda qa0 nqa0 nqe1 qe1 qf qa1 nqa1 qb0 nqb0 qc0 nqc0 qc1 nqc1 qd0 nqd0 qe0 nqe0 fsel_b1 fsel_a1 fsel_d1 fsel_c1 fsel_e1 xtal_out xtal_in vdd vdd 3.3v 3.3v r12 50 zo = 50 rd1 not install r8 50 rd2 1k hcsl_receiver + - c16 0.1uf idt8V41N010 u1 nc 13 nc 17 nc 61 nc 65 nc 6 nc 72 nc 1 fsel_e1 7 fsel_a1 14 fsel_b1 18 fsel_c1 62 fsel_d1 66 vddo 69 gnd 36 gnd 29 gnd 43 gnd 51 gnd 59 gnd 63 gnd 71 vdd 67 nc 4 nc 3 vddo 2 nc 70 xtal_in 10 xtal_out 11 ref_sel 8 pll_sel 12 clk 15 nclk 16 oe_a 30 oe_b 37 oe_c 44 oe_d 52 iref 53 oe_e 60 nmr 68 qa0 25 nqa0 26 qa1 27 nqa1 28 qb0 32 nqb0 33 nc 34 nc 35 qc0 39 nqc0 40 qc1 41 nqc1 42 qd0 47 nqd0 48 nc 49 nc 50 qe0 55 nqe0 56 qe1 57 nqe1 58 qf 20 vdda 64 vdd 9 vdd 22 vdd 45 vddo_qa 24 vddo_qb 31 vddo_qc 38 vddo_qd 46 vddo_qe 54 vddo_qf 19 gnd 5 gnd 21 gnd 23 epad 73 zo = 50 c14 0.1uf c2 2pf fb2 blm18bb221sn1 1 2 hcsl_receiver + - r13 33 c11 10uf c10 0.1uf fb1 blm18bb221sn1 1 2 c9 10uf c20 0.1uf c21 0.1uf zo = 50 ohm c1 2pf c19 0.1uf zo = 50 ohm x1 25mhz (12pf) c13 0.1uf c5 0.1uf c8 0.1uf r14 33 c15 0.1uf c18 0.1uf c12 0.1uf c1 2pf ru1 1k c6 0.1uf c7 0.1uf lvcmos receiver r5 5 zo = 50 ru2 not install r1 50 zo = 50 r2 50 r4 475 x2 1 3 2 4 r10 33 c4 0.1uf r7 33 zo = 50 zo = 50 r9 50 r11 50 r6 33 c17 10uf r3 50 +3.3v pecl driver zo = 50 c2 2pf c3 0.1uf
revision 1 06/30/15 21 clock generator for cavium processors 8V41N010 data sheet power considerations this section provides information on power dissipation and juncti on temperature for the 8V41N010. equations and example calcula tions are also provided. 1. power dissipation. the total power dissipation for the 8V41N010 is the sum of the core power plus the analog power plus the power dissipated due t o loading. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to loading. ? power (core) max = v dd_max * (i dd + i dda )= 3.465v * (235ma + 47ma) = 977.13mw ? power (hcsl) max = (3.465v ? 17ma * 50) 17ma = 44.5mw per output ? total power (hcsl) max = 44.5mw * 8 = 356mw ? power (pre-driver) max = 3.465v * 30ma = 103.95mw lvcmos driver power dissipation ? output impedance r out power dissipation due to loading 50 ? to v ddo_qx / 2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 15 ? )] = 26.65ma ? power dissipation on the r out per lvcmos output power (lvcmos) = r out * (i out ) 2 = 15 ? * (26.65ma) 2 = 10.65mw per output ? total power dissipation on the r out total power (r out ) = 10.65mw * 1 = 10.65mw ? total power dissipation ? total powe r = power (core) + total power (hcsl) + power (pre-driver) + total power (r out ) = 977.13mw + 356mw + 103.95mw + 10.65mw = 1447.73mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 26.6c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.448w * 26.6c/w = 123.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 9. thermal resistance ? ja for 72 lead vfqfn, forced convection ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 26.6c/w 20c/w 17.9c/w
clock generator for cavium proc essors 22 revision 1 06/30/15 8V41N010 data sheet 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 7. figure 7. hcsl driver circuit and termination hcsl is a current steering output which sour ces a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out since v out = i out * r l power = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v ddo v out r l 50 ic ? i out = 17ma r ref = 475 1%
revision 1 06/30/15 23 clock generator for cavium processors 8V41N010 data sheet reliability information table 10. ? ja vs. air flow table for a 72 lead vfqfn transistor count the transistor count for 8V41N010 is: 175,936 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 26.6c/w 20c/w 17.9c/w
clock generator for cavium proc essors 24 revision 1 06/30/15 8V41N010 data sheet 72-lead vfqfn (nl) package ou tline and package dimensions table 8. package dimensions for 72-lead package 1 symbol dimensions min nom max d 10.00 bsc e 10.00 bsc d2 5.80 5.90 6.00 e2 5.80 5.90 6.00 k0.20- - l 0.30 0.40 0.50 a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a2 0.00 0.65 1.00 a3 0.2 ref b0.18 0.25 0.30 e0.50 bsc note 1. the drawing and dimens ion data originates from idt package outline drawing psc-4208, rev 04. all dimensions and tolerances conform to ansi y14.5-1944. all dimensions are in millimeters. index area (pin1 identifier)
clock generator for cavium proc essors 25 revision 1 06/30/15 8V41N010 data sheet ordering information table 11. ordering information part/order number marking package shipping packaging temperature 8V41N010nlgi idt8V41N010nlgi 72 lead vfqfn, lead-free tray -40 ? c to 85 ? c 8V41N010nlgi8 idt8V41N010nlgi 72 lead vfqfn, lead-free tape & reel -40 ? c to 85 ? c
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2015 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

▲Up To Search▲

Price & Availability of 8V41N010

	To Download 8V41N010 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .