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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. may 2017 docid029173 rev 2 1/263 STM32L496XX ultra-low-power arm ? cortex ? -m4 32-bit mcu+fpu, 100dmips, up to 1mb flash, 320kb sram, usb otg fs, audio, ext. smps datasheet - preliminary data features ? ultra-low-power with flexpowercontrol ? 1.71 v to 3.6 v power supply ? -40 c to 85/125 c temperature range ? 320 na in v bat mode: supply for rtc and 32x32-bit backup registers ? 25 na shutdown mode (5 wakeup pins) ? 108 na standby mode (5 wakeup pins) ? 426 na standby mode with rtc ? 2.57 a stop 2 mode, 2.86 a stop 2 with rtc ? 91 a/mhz run mode (ldo mode) ? 37 a/mhz run mode (@3.3 v smps mode) ? batch acquisition mode (bam) ? 5 s wakeup from stop mode ? brown out reset (bor) in all modes except shutdown ? interconnect matrix ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0- wait-state execution from flash memory, frequency up to 80 mhz, mpu, 100 dmips and dsp instructions ? performance benchmark ? 1.25 dmips/mhz (drystone 2.1) ? 273.55 coremark ? (3.42 coremark/mhz @ 80 mhz) ? energy benchmark ? 217 ulpbench? score ? 16 x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2 x 16-bit basic, 2 x lo w-power 16-bit timers (available in stop mode), 2 x watchdogs, systick timer ? rtc with hw calendar, alarms and calibration ? up to 136 fast i/os, most 5 v-tolerant, up to 14 i/os with independent supply down to 1.08 v ? dedicated chrom-art accelerator? for enhanced graphic content creation (dma2d) ? 8- to 14-bit camera interface up to 32 mhz (black&white) or 10 mhz (color) ? memories ? up to 1 mb flash, 2 banks read-while- write, proprietary code readout protection ? 320 kb of sram including 64 kb with hardware parity check ? external memory interface for static memories supporting sram, psram, nor and nand memories ? dual-flash quad spi memory interface ? clock sources ? 4 to 48 mhz crystal oscillator ? 32 khz crystal osc illator for rtc (lse) ? internal 16 mhz factory-trimmed rc (1%) ? internal low-power 32 khz rc (5%) ? internal multispeed 100 khz to 48 mhz oscillator, auto-trimmed by lse (better than 0.25% accuracy) ? internal 48 mhz with clock recovery ? 3 plls for system clock, usb, audio, adc ? lcd 8 40 or 4 44 with step-up converter ? up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors ? 4 x digital filters for sigma delta modulator ? rich analog peripherals (independent supply) ? 3 12-bit adc 5 msps, up to 16-bit with hardware oversampling, 200 a/msps ? 2 x 12-bit dac, low-power sample and hold ufbga132 (7 7) lqfp144 (20 20) ufbga169 (7 x 7) wlcsp100 lqfp100 (14 x 14) lqfp64 (10 x 10) www.st.com
STM32L496XX 2/263 docid029173 rev 2 ? 2 x operational amplif iers with built-in pga ? 2 x ultra-low-power comparators ? 20 x communication interfaces ? usb otg 2.0 full-speed, lpm and bcd ? 2 x sais (serial audio interface) ? 4 x i2c fm+(1 mbit /s), smbus/pmbus ? 5 x u(s)arts (iso 7816, lin, irda, modem) ?1 x lpuart ? 3 x spis (4 x spis with the quad spi) ? 2 x can (2.0b active) and sdmmc ? swpmi single wire pr otocol master i/f ? irtim (infrared interface) ? 14-channel dma controller ? true random number generator ? crc calculation unit, 96-bit unique id ? development support: serial wire debug (swd), jtag, embedded trace macrocell? ? table 1. device summary reference part numbers STM32L496XX stm32l496ag, stm32l496qg, stm32l496rg, stm32l496vg, stm32l496zg, stm32l496ae, stm32l496qe, stm32l496re, stm32l496ve, stm32l496ze
docid029173 rev 2 3/263 STM32L496XX contents 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 arm ? cortex ? -m4 core with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 18 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 22 3.10 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.5 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.10.6 vbat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.11 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.13 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.14 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.15 chrom-art accelerator? (dma2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.16.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 40 3.16.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 40 3.17 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.17.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.17.2 internal voltage reference (vrefint) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
contents STM32L496XX 4/263 docid029173 rev 2 3.17.3 vbat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.18 digital to analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.19 voltage reference buffer (vrefbuf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.20 comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.21 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.22 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.23 liquid crystal display controller (lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.24 digital filter for sigma-delta modulators (dfsdm) . . . . . . . . . . . . . . . . . . 45 3.25 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.26 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.27 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.27.1 advanced-control timer (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.27.2 general-purpose timers (tim2, tim3, tim4, tim5, tim15, tim16, tim17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.27.3 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.27.4 low-power timer (lptim1 and lptim2) . . . . . . . . . . . . . . . . . . . . . . . . 49 3.27.5 infrared interface (irtim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.6 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.7 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.8 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.28 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51 3.29 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.30 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 53 3.31 low-power universal asynchronous rece iver transmitter (lpuart) . . . . 54 3.32 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.33 serial audio interfaces (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.34 single wire protocol master interface (swpmi) . . . . . . . . . . . . . . . . . . . . 56 3.35 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.36 secure digital input/output and multimediacards interface (sdmmc) . . . 57 3.37 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 57 3.38 clock recovery system (crs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.39 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 58 3.40 dual-flash quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . 59 3.41 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
docid029173 rev 2 5/263 STM32L496XX contents 6 3.41.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.41.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . 115 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . 115 6.3.4 embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.6 wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.3.16 analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.17 analog-to-digital converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 173 6.3.18 digital-to-analog converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 186
contents STM32L496XX 6/263 docid029173 rev 2 6.3.19 voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 191 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.3.21 operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 6.3.24 lcd controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 6.3.25 dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.26 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.27 communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 204 6.3.28 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 6.3.29 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 233 6.3.30 swpmi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 6.3.31 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 234 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.1 ufbga169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.2 lqfp144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.3 ufbga132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.4 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 7.5 wlcsp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.6 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 7.7 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 7.7.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 7.7.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 258 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
docid029173 rev 2 7/263 STM32L496XX list of tables 10 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. STM32L496XX family device features and periphera l counts . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19 table 4. STM32L496XX modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6. STM32L496XX peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. dma implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 11. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12. STM32L496XX usart/uart/lpuart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 13. sai implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 14. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 15. STM32L496XX pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) . . . . . . . . . . . . . . . . . . . . . 86 table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) . . . . . . . . . . . . . . . . . . . . . 95 table 18. STM32L496XX memory map and peripheral register boundary addresses . . . . . . . . . . . 105 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 24. embedded reset and power control block characteri stics. . . . . . . . . . . . . . . . . . . . . . . . . 115 table 25. embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 26. current consumption in run and lo w-power run modes, code with data processing running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . 120 table 27. current consumption in run modes, code with data processing running from flash, (art enable cache on prefetch off) and power supplied (by external smps (vdd12 = 1.10 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 28. current consumption in run and low-power run modes, code with data processing running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 29. current consumption in run modes, code with data processing running from flash, art disable and power supplied by external smps (vdd12 = 1.10 v). . . . . . . . . . . . . . 123 table 30. current consumption in run and lo w-power run modes, code with data processing running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 31. current consumption in run, code with data processing running from sram1 and power supplied by external smps (vdd12 = 1.10 v) . . . . . . . . . . . . . . . . . 125 table 32. typical current consumption in run a nd low-power run modes, with different codes running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . 126 table 33. typical current consumption in run, with different codes running from flash, art enable (cache on prefetch off) and power supplied (by external smps (vdd12 = 1.10 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 34. typical current consumption in run, with different codes running from flash, art enable (cache on prefetch off) and power supplied (by external smps (vdd12 = 1.05 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 35. typical current consumption in run a nd low-power run modes, with different codes running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
list of tables STM32L496XX 8/263 docid029173 rev 2 table 36. typical current consumption in ru n modes, with different codesrunning from flash, art disable and power supplied by ex ternal smps (vdd12 = 1.10 v) . . . . . . . . 128 table 37. typical current consumption in ru n modes, with different codesrunning from flash, art disable and power supplied by ex ternal smps (vdd12 = 1.05 v) . . . . . . . . 128 table 38. typical current consumption in run a nd low-power run modes, with different codes running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 39. typical current consumption in run, with different codesrunning from sram1 and power supplied by external smps (vdd12 = 1.10 v) . . . . . . . . . . . . . . . . . 129 table 40. typical current consumption in run, with different codesrunning from sram1 and power supplied by external smps (vdd12 = 1.05 v) . . . . . . . . . . . . . . . . . 130 table 41. current consumption in sleep and low-power sleep modes, flash on . . . . . . . . . . . . . 131 table 42. current consumption in sl eep, flash on and power supplied by external smps (vdd12 = 1.10 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 43. current consumption in low-power sleep modes, flash in power-down . . . . . . . . . . . . . 133 table 44. current consumption in stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 45. current consumption in stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 46. current consumption in stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 47. current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 48. current consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 49. current consumption in vbat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 50. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 51. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 52. regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 53. wakeup time using usart/lpuart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 54. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 55. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 56. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 57. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 58. hsi16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 59. msi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 table 60. hsi48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 61. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 62. pll, pllsai1, pllsai2 characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 63. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 64. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 65. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 66. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 67. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 table 68. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 69. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 70. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 71. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 72. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 73. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 74. analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 75. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 76. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 77. adc accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 78. adc accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 79. adc accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 80. adc accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 81. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
docid029173 rev 2 9/263 STM32L496XX list of tables 10 table 82. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 83. vrefbuf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 84. comp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 85. opamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 86. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 87. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 88. v bat charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 89. lcd controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 90. dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 91. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 92. iwdg min/max timeout period at 32 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 93. wwdg min/max timeout value at 80 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 94. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 95. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 96. quad spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 97. quadspi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 98. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 99. sd / mmc dynamic characteristics, vdd=2.7 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 100. emmc dynamic characteristics, vdd = 1.71 v to 1.9 v . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 101. usb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 102. asynchronous non-multiplexed sram/psram/n or read timings . . . . . . . . . . . . . . . . . 218 table 103. asynchronous non-multiplexed sram/psram /nor read-nwait timings . . . . . . . . . . . 218 table 104. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 219 table 105. asynchronous non-multiplexed sram/psram /nor write-nwait timings. . . . . . . . . . . 220 table 106. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 107. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 221 table 108. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 109. asynchronous multiplexed psram/nor write-nw ait timings . . . . . . . . . . . . . . . . . . . . 223 table 110. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 111. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 112. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 228 table 113. synchronous non-multiplexed ps ram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 114. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 115. switching characteristics for nand flash write cycl es. . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 116. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 117. swpmi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 table 118. sd / mmc dynamic characteristics, vdd=2.7 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 119. sd / mmc dynamic characteristics, vdd=1.71 v to 1.9 v . . . . . . . . . . . . . . . . . . . . . . . . 235 table 120. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 121. ufbga169 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 238 table 122. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 123. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 124. ufbga132 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 246 table 125. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 126. wlcsp100l ?4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 127. wlcsp100l recommended pcb design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . 253 table 128. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat
list of tables STM32L496XX 10/263 docid029173 rev 2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 table 129. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 table 130. STM32L496XX ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 131. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
docid029173 rev 2 11/263 STM32L496XX list of figures 12 list of figures figure 1. STM32L496XX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2. multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 4. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 5. voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6. stm32l496ax ufbga169 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 7. stm32l496ax, external smps device, ufbga169 pinout (1) . . . . . . . . . . . . . . . . . . . . . . 61 figure 8. stm32l496zx lqfp144 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 9. stm32l496zx, external smps device, lqfp144 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 10. stm32l496qx ufbga132 ballout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 11. stm32l496vx lqfp100 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 12. stm32l496vx wlcsp100 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 13. stm32l496vx, external smps device, wlcsp100 pinout (1) . . . . . . . . . . . . . . . . . . . . . . 66 figure 14. stm32l496rx lqfp64 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 15. STM32L496XX memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 figure 16. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 17. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 18. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 19. current consumption measur ement scheme with and without external smps power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 20. vrefint versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 21. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 22. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 23. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 figure 24. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 25. hsi16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 26. typical current consumption versus msi frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 27. hsi48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 28. i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 29. i/o ac characteristics definition (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 30. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 31. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 32. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 33. 12-bit buffered / non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 34. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 35. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 36. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 07 figure 37. quad spi timing diagram - sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 38. quad spi timing diagram - ddr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 39. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 40. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 41. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 42. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 43. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 217 figure 44. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 219 figure 45. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 220 figure 46. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 222 figure 47. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
list of figures STM32L496XX 12/263 docid029173 rev 2 figure 48. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 49. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 50. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 51. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 52. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 53. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 231 figure 54. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 232 figure 55. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 56. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 57. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 58. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 figure 59. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 60. ufbga169 marking (package top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 61. ufbga169, external smps device, marking (pa ckage top view) . . . . . . . . . . . . . . . . . . 240 figure 62. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 241 figure 63. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 figure 64. lqfp144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 figure 65. lqfp144, external smps device, marking (packa ge top view) . . . . . . . . . . . . . . . . . . . . 244 figure 66. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 67. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 figure 68. ufbga132 marking (package top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 figure 69. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 248 figure 70. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 figure 71. lqfp100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 figure 72. wlcsp100l ? 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 73. wlcsp100l ? 100l, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 figure 74. wlcsp100l marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure 75. wlcsp100, external smps device, marking (p ackage top view) . . . . . . . . . . . . . . . . . . 254 figure 76. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 255 figure 77. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 figure 78. lqfp64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
docid029173 rev 2 13/263 STM32L496XX introduction 60 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the STM32L496XX microcontrollers. this document should be read in conjun ction with the stm32l4x6 reference manual (rm0351). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from the www.arm.com website.
description STM32L496XX 14/263 docid029173 rev 2 2 description the STM32L496XX devices are the ultra-low- power microcontrollers based on the high- performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 80 mhz. the cortex-m4 core features a floating point un it (fpu) single precision which supports all arm single-precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protec tion unit (mpu) which enhances application security. the STM32L496XX devices embed high-speed memories (up to 1 mbyte of flash memory, 320 kbyte of sram), a flexible external memory controller (fsmc) for static memories (for devices with packages of 100 pins and mo re), a quad spi flash memories interface (available on all packages) and an extens ive range of enhanced i/os and peripherals connected to two apb buses, two ahb bus es and a 32-bit multi-ahb bus matrix. the STM32L496XX devices embed several pr otection mechanisms for embedded flash memory and sram: readout protection, writ e protection, proprietary code readout protection and firewall. the devices offer up to three fast 12-bit adcs (5 msps), two comparators, two operational amplifiers, two dac channels, an internal vo ltage reference buffer, a low-power rtc, two general-purpose 32-bit timer, two 16-bit pw m timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. the devices support four digital filters for external sigma delta modulators (dfsdm). in addition, up to 24 capacitive sensing chan nels are available. the devices also embed an integrated lcd driver 8x40 or 4x44, with internal step-up converter. they also feature standard and advanced communication interfaces. ? four i2cs ? three spis ? three usarts, two uarts and one low-power uart. ? two sais (serial audio interfaces) ? one sdmmc ? two can ? one usb otg full-speed ? one swpmi (single wire protocol master interface) ? camera interface ? dma2d controller the STM32L496XX operates in the -40 to +85 c (+105 c junction), -40 to +125 c (+130 c junction) temperature ranges from a 1.71 to 3.6 v v dd power supply when using internal ldo regulator and a 1.05 to 1.32v v dd12 power supply when using external smps supply. a comprehensive set of power-saving modes allows the design of low-power applications. some independent power supplies are supported: analog independent supply input for adc, dac, opamps and comparators, 3.3 v dedicated supply input for usb and up to 14 i/os can be supplied independently down to 1.08v. a vbat input allows to backup the rtc and backup registers. dedicated v dd12 power supplies can be used to bypass the internal ldo regulator when connected to an external smps.
docid029173 rev 2 15/263 STM32L496XX description 60 the STM32L496XX family offers six packages from 64-pin to 169-pin packages. table 2. STM32L496XX family device features and peripheral counts peripheral stm32l496ax stm32l496zx stm32l496qx stm32l496vx stm32l496rx flash memory 512kb 1mb 512kb 1mb 512kb 1mb 512kb 1mb 512kb 1mb sram 320 kb external memory controller for static memories yes yes yes yes (1) no quad spi yes timers advanced control 2 (16-bit) general purpose 5 (16-bit) 2 (32-bit) basic 2 (16-bit) low power 2 (16-bit) systick timer 1 watchdog timers (independent window) 2 comm. interfaces spi 3 i 2 c4 usart uart lpuart 3 2 1 sai 2 can 2 usb otg fs yes sdmmc yes swpmi yes digital filters for sigma- delta modulators yes (4 filters) number of channels 8 rtc yes tamper pins 3 camera interface yes yes (2) chrom-art accelerator? yes lcd com x seg yes 8x40 or 4x44
description STM32L496XX 16/263 docid029173 rev 2 random generator yes gpios (3) wakeup pins nb of i/os down to 1.08 v 136 5 14 115 5 14 110 5 14 83 5 0 52 4 0 capacitive sensing number of channels 24 24 24 21 21 12-bit adcs number of channels 3 24 3 24 3 19 3 16 3 16 12-bit dac channels 2 internal voltage reference buffer yes analog comparator 2 operational amplifiers 2 max. cpu frequency 80 mhz operating voltage (v dd ) 1.71 to 3.6 v operating voltage (v dd12 ) 1.05 to 1.32 v operating temperature ambient operating temperature: -40 to 85 c / -40 to 125 c junction temperature: -40 to 105 c / -40 to 130 c packages ufbga169 lqfp144 ufbga132 lqfp100 wlcsp100 lqfp64 1. for the lqfp100 and wlcsp100 packages, only fmc bank1 is available. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. 2. only up to 13 data bits. 3. in case external smps package type is used, 2 gpio's are replaced by vdd12 pins to c onnect the smps power supplies hence reducing the number of available gpio's by 2. table 2. STM32L496XX family device features and peripheral counts (continued) peripheral stm32l496ax stm32l496zx stm32l496qx stm32l496vx stm32l496rx
docid029173 rev 2 17/263 STM32L496XX description 60 figure 1. STM32L496XX block diagram note: af: alternate function on i/o pins. 06y9 h^ kd' )odvk xswr 0% )oh[leohvwdwlfphpru\frqwuroohu)60& 65$0365$0125)odvk 1$1')odvk *3,23257$ $+%$3% (;7,7:.83 $) 3$>@ 7,03:0 frpsofkdqqhov7,0b&+>@1 fkdqqhov7,0b&+>@ (75%.,1%.,1dv$) 86$57 5;7;&.&76 576dv$) 63, 026,0,62 6&.166dv$) $3% 0 +] $3% 0+] 026,0,626&.166dv$) '$&b287 ,7) ::'* 57&b76 26&b,1 26&b287 9''$966$ 9''9661567 vpfdug ,u'$ e 6',200& '>@ &0'&.dv$) 9%$7 wr9 6&/6'$60%$dv$) -7$* 6: $50&ruwh[0 0+] )38 19,& (70 038 75$&(&/. 75$&('>@ '0$ $57 $&&(/ &$&+( &/.1(>@1/1%/>@ $>@'>@12(1:( 1:$,71&(,17dv$) 51* '3 '0 6&/6'$,171,'9%8662) ),)2 # 9''$ %25 6xsso\ vxshuylvlrq 39'390 ,qw uhvhw ;7$/n+] 0$1 $*7 57& )&/. 6wdqge\ lqwhuidfh ,:'* #9%$7 #9'' #9'' $:8 5hvhw forfn frqwuro 3&/.[ 9'' wr9 966 9rowdjh uhjxodwru wr9 9'' 3rzhupdqdjhphqw #9'' 57&b7$03[ %dfnxsuhjlvwhu $+%exvpdwul[ 7,0 fkdqqhov frpsofkdqqho%.,1dv $) '$& '$& 7,0 7,0 d/d? d/d? d/de d/d? h^zd? h^zd? ,&60%86 '%86 $3%0+]pd[ 65$0.% 65$0.% 1-7567-7', -7&.6:&/. -7'26:'-7'2 ,%86 6%86 '0$ 3%>@ 3&>@ 3'>@ 3(>@ 3)>@ 3*>@ 3+>@ *3,23257% *3,23257& *3,23257' *3,23257( *3,23257) *3,23257* *3,23257+ 7,03:0 e e 7,0 e 7,0 e frpso&kdqqhov7,0b&+>@1 fkdqqhov7,0b&+>@ (75%.,1%.,1dv$) fkdqqho frpsofkdqqho%.,1dv$) fkdqqho frpsofkdqqho%.,1dv$) '$&b287 e e 6&/6'$60%$dv$) 6&/6'$60%$dv$) 026,0,626&.166dv$) 7;5;dv$) 5;7;&76576dv$) 5;7;&76576dv$) 5;7;&.&76576dv$) 5;7;&.&76576dv$) vpfdug ,u'$ vpfdug ,u'$ e e e e fkdqqhov(75dv$) fkdqqhov(75dv$) fkdqqhov(75dv$) fkdqqhov(75dv$) $+%$3% 26&b,1 26&b287 +&/.[ ;7$/26& 0+] dqdorjlqsxwvfrpprqwrwkh$'&v 95() 86$5 7 0%sv 7hpshudwxuhvhqvru $'& $'& $'& ,) ,7) #9''$ dqdorjlqsxwvfrpprqwrwkh$'& dqdorjlqsxwviru$'& 6$, 0&/.b$6'b$)6b$6&.b$(;7&/. 0&/.b%6'b%)6b%6&.b%dv$) 6$, 0&/.b$6'b$)6b$6&.b$(;7&/. 0&/.b%6'b%)6b%6&.b%dv$) ')6'0 6'&.,1>@6''$7,1>@ 6'&.2876'75,*dv$) d}z?v?]vp}v??}oo? *urxsvrifkdqqhovpd[dv$) 287,11,13 >??e /38$57 ^twd/ >wd/d >wd/d? 6(*[&20[dv$) 5;7;&76576dv$) 6:3 ,1,1287(75dv$) ,1287(75dv$) z,^/ z>^/ w>>???? d^/ y^w/uu}??]v??( '>@'>@ &/.&/.&6 #9''86% &203 ,13,11287 &203 ,13,11287 #9''$ 57&b287 9'',29''86% &/&k w,z $+%0+] z 287,11,13 ,&60%86 ,&60%86 2s$ps 63 63 8$57 8$57 /&'%rrvwhu 9 /&' 9 /&' 9wr9 w??d, $+%0+] 2s$ps #9''$ )luhzdoo 95()%xiihu #9''$ #9'' &dphud,qwhuidfh &/&k +6<1&96<1& 3,;&/.'>@ &+520$57 '0$' &/&k 3,>@ *3,23257, 7;5;dv$) e[&$1 6&/6'$60%$dv$) ,&60%86 ,^/e? e[&$1 ),)2 z^ &56b6<1& 9'' 9'' wr9 2qo\dydlodeohzkhqxvlqjh[whuqdo6036vxsso\prgh
functional overview STM32L496XX 18/263 docid029173 rev 2 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc processor features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the STM32L496XX family is compatible with all arm tools and software. figure 1 shows the general block diagram of the STM32L496XX family devices. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 processors. it balances the in herent performance advantage of the arm ? cortex ? -m4 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor near 100 dmips performance at 80mhz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 80 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
docid029173 rev 2 19/263 STM32L496XX functional overview 60 3.4 embedded flash memory STM32L496XX devices feature up to 1 mbyte of embedded flash memory available for storing programs and data. the flash memory is divided into two banks allowing read- while-write operations. this feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. the dual bank boot is also supported. each bank contains 256 pages of 2 kbyte. flexible protections can be configured thanks to option bytes: ? readout protection (rdp) to protect the wh ole memory. three levels are available: ? level 0: no readout protection ? level 1: memory readout protection: th e flash memory cannot be read from or written to if either debug features are co nnected, boot in ram or bootloader is selected ? level 2: chip readout protection: debug features (cortex-m4 jtag and serial wire), boot in ram and bootloader sele ction are disabled (jtag fuse). this selection is irreversible. ? write protection (wrp): the protected ar ea is protected against erasing and programming. two areas per bank can be selected, with 2-kbyte granularity. ? proprietary code readout protection (pcro p): a part of the flash memory can be protected against read and write from third pa rties. the protected area is execute-only: it can only be reached by the stm32 cpu, as an instruction co de, while all other accesses (dma, debug and cpu data read, wr ite and erase) are strictly prohibited. one area per bank can be selected, with 64-b it granularity. an additional option bit (pcrop_rdp) allows to select if the pcro p area is erased or not when the rdp protection is changed from level 1 to level 0. table 3. access status versus readout protection level and execution modes area protection level user execution debug, boot from ram or boot from system memory (loader) read write erase read write erase main memory 1 yes yes yes no no no 2 yes yes yes n/a n/a n/a system memory 1 yes no no yes no no 2 yes no no n/a n/a n/a option bytes 1 yes yes yes yes yes yes 2 yes no no n/a n/a n/a backup registers 1yesyesn/a (1) 1. erased when rdp change from level 1 to level 0. no no n/a (1) 2 yes yes n/a n/a n/a n/a sram2 1 yes yes yes (1) no no no (1) 2 yes yes yes n/a n/a n/a
functional overview STM32L496XX 20/263 docid029173 rev 2 the whole non-volatile memory embeds the error correction code (ecc) feature supporting: ? single error detection and correction ? double error detection. ? the address of the ecc fail can be read in the ecc register 3.5 embedded sram STM32L496XX devices feature 320 kbyte of embedded sram. this sram is split into two blocks: ? 256 kbyte mapped at address 0x2000 0000 (sram1) ? 64 kbyte located at address 0x1000 0000 with hardware parity check (sram2). this memory is also mapped at address 0x2004 0000, offering a contiguous address space with the sram1. this block is accessed through the icode/dcode buses for maximum performance. these 64 kbyte sram can also be retained in standby mode. the sram2 can be write-protec ted with 1 kbyte granularity. the memory can be accessed in read/writ e at cpu clock speed with 0 wait states.
docid029173 rev 2 21/263 STM32L496XX functional overview 60 3.6 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cpu, dmas and the dma2d) and the slaves (flash memory, ram, fmc, quadspi, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high speed peripherals work simultaneously. figure 2. multi-ahb bus matrix 3.7 firewall the device embeds a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. each illegal access generates a reset which kills immediat ely the detected intrusion. 06y9 $50 ? &257(; ? 0zlwk)38 '0$ '0$ )0& $+% shulskhudov $+% shulskhudov 65$0 )/$6+ 0% $&&(/ 6 6 6 6 6 0 0 0 0 0 0 0 ,&rgh '&rgh 48$'63, 0 '0$' 6 %xv0dwul[6 .% .% 65$0
functional overview STM32L496XX 22/263 docid029173 rev 2 the firewall main features are the following: ? three segments can be protected and de fined thanks to the firewall registers: ? code segment (located in flash or sram 1 if defined as ex ecutable protected area) ? non-volatile data segment (located in flash) ? volatile data segment (located in sram1) ? the start address and the length of each segments are configurable: ? code segment: up to 1024 kbyte with granularity of 256 bytes ? non-volatile data segment: up to 1024 kbyte with granularity of 256 bytes ? volatile data segment: up to 256 kbyte of sram1 with a granularity of 64 bytes ? specific mechanism implemented to open th e firewall to get access to the protected areas (call gate entry sequence) ? volatile data segment can be shared or not with the non-protected code ? volatile data segment can be executed or not depending on the firewall configuration the flash readout protection must be set to le vel 2 in order to reach the expected level of protection. 3.8 boot modes at startup, boot0 pin and nboot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram boot0 value may come from the ph3-boot0 pin or from an option bit depending on the value of a user option bit to free the gpio pad if needed. a flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. the boot loader is located in system memory. it is used to reprogram the flash memory by using usart, i2c, spi, can and usb otg fs in device mode through dfu (device firmware upgrade). 3.9 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location.
docid029173 rev 2 23/263 STM32L496XX functional overview 60 3.10 power supply management 3.10.1 power supply schemes ? v dd = 1.71 to 3.6 v: external power supply for i/os (v ddio1 ), the internal regulator and the system analog such as reset, power mana gement and internal clocks. it is provided externally through vdd pins. ? v dd12 = 1.05 to 1.32 v: external power supply bypassing internal regulator when connected to an external smps. it is provi ded externally through vdd12 pins and only available on packages with the external smps supply option. vdd12 does not require any external decoupling capacitance and cannot support any external load. ? v dda = 1.62 v (adcs/comps) / 1.8 (dacs/opamps ) to 3.6 v: external analog power supply for adcs, dacs, opamps, comparators and voltage reference buffer. the v dda voltage level is independent from the v dd voltage. ? v ddusb = 3.0 to 3.6 v: external independent power supply for usb transceivers. the v ddusb voltage level is independent from the v dd voltage. ? v ddio2 = 1.08 to 3.6 v: external power su pply for 14 i/os (pg[15:2]). the v ddio2 voltage level is independent from the v dd voltage. ? v lcd = 2.5 to 3.6 v: the lcd controller can be powered either externally through vlcd pin, or internally from an internal voltage generated by the embedded step-up converter. ? v bat = 1.55 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. note: when the functions supplied by v dda , v ddusb or v ddio2 are not used, these supplies should preferably be shorted to v dd . note: if these supplies are tied to ground, the i/os supplied by these power supplies are not 5 v tolerant (refer to table 19: voltage characteristics ). note: v ddiox is the i/os general purpos e digital functions supply. v ddiox represents v ddio1 or v ddio2 , with v ddio1 = v dd . v ddio2 supply voltage level is independent from v ddio1 .
functional overview STM32L496XX 24/263 docid029173 rev 2 figure 3. power supply overview 3.10.2 power supply supervisor the device has an integrated ultra-low-power brown-out reset (bor) active in all modes except shutdown and ensuring proper operation after power-on and during power down. the device remains in reset mode when the monitored supply voltage v dd is below a specified threshold, without the need for an external reset circuit. the lowest bor level is 1.71 v at power on, and other higher thresholds can be selected through option bytes.the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and co mpares it to the vpvd threshold. an interrupt can be generated when v dd drops below the vpvd th reshold and/or when v dd is higher than the vpvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. in addition, the device embeds a periph eral voltage monitor which compares the independent supply voltages v dda , v ddusb , v ddio2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 06y9 9 ''$ grpdlq %dfnxsgrpdlq '$frqyhuwhuv $'frqyhuwhuv 6wdqge\flufxlwu\ :dnhxsorjlf ,:'* 9rowdjhuhjxodwru /rzyrowdjhghwhfwru /6(fu\vwdo.rvf %.3uhjlvwhuv 5&&%'&5uhjlvwhu 57& frpsdudwruv rshudwlrqdodpsolilhuv 9rowdjhuhihuhqfhexiihu ,2ulqj 9 &25( grpdlq 7hpsvhqvru 5hvhweorfn 3//+6,06, /&' 9 /&' 86%wudqvfhlyhuv 9 ''86% 9 '',2 9 '',2 ,2ulqj 3*>@ 9 '',2 9 ''$ 9 66$ 9 66 9 66 9 '',2 grpdlq 9 '' grpdlq 9 &25( 9 66 9 '' 9 %$7 &ruh 'ljlwdo shulskhudov 0hprulhv 9 ''
docid029173 rev 2 25/263 STM32L496XX functional overview 60 3.10.3 voltage regulator two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (mr) and the low-power regulator (lpr). ? the mr is used in the run and sleep modes and in the stop 0 mode. ? the lpr is used in low-power run, low-power sleep, stop 1 and stop 2 modes. it is also used to supply the 64 kbyte sram2 in standby with ram2 retention. ? both regulators are in power-down in standby and shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the ultralow-power STM32L496XX supports dynam ic voltage scaling to optimize its power consumption in run mode. the voltage from the main regulator that supplies the logic (v core ) can be adjusted according to the sy stem?s maximum operating frequency. there are two power consumption ranges: ? range 1 with the cpu running at up to 80 mhz. ? range 2 with a maximum cpu frequency of 26 mhz. all peripheral clocks are also limited to 26 mhz. the v core can be supplied by the low-power regulator, the main regulator being switched off. the system is then in low-power run mode. ? low-power run mode with the cpu running at up to 2 mhz. peripherals with independent clock can be clocked by hsi16. when the mr is in use, the STM32L496XX with the external smps option allows to force an external v core supply on the vdd12 supply pins. when v dd12 is forced by an external source and is higher than the output of the internal ldo, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down dc/dc converter. 3.10.4 low-power modes the ultra-low-power STM32L496XX supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.
functional overview STM32L496XX 26/263 docid029173 rev 2 table 4. STM32L496XX modes overview mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time run mr range 1 yes on (4) on any all n/a 108 a/mhz n/a smps range 2 high 40 a/mhz (5) mr range2 all except otg_fs, rng 93 a/mhz smps range 2 low 39 a/mhz (6) lprun lpr yes on (4) on any except pll all except otg_fs, rng n/a 129 a/mhz to range 1: 4 s to range 2: 64 s sleep mr range 1 no on (4) on (7) any all any interrupt or event 32 a/mhz 6 cycles smps range 2 high 11.5 a/mhz (5) mr range2 all except otg_fs, rng 30 a/mhz smps range 2 low 13 a/mhz (6) lpsleep lpr no on (4) on (7) any except pll all except otg_fs, rng any interrupt or event 51 a/mhz 6 cycles stop 0 mr range 1 (8) no off on lse lsi bor, pvd, pvm rtc,lcd, iwdg compx (x=1,2) dacx (x=1,2) opampx (x=1,2) usartx (x=1...5) (9) lpuart1 (9) i2cx (x=1...4) (10) lptimx (x=1,2) *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc, lcd, iwdg compx (x=1..2) usartx (x=1...5) (9) lpuart1 (9) i2cx (x=1...4) (10) lptimx (x=1,2) otg_fs (11) swpmi1 (12) tbd 2.7 s in sram 6.2 s in flash mr range 2 (8) 127 a
STM32L496XX functional overview docid029173 rev 2 27/263 stop 1 lpr no off on lse lsi bor, pvd, pvm rtc, lcd, iwdg compx (x=1,2) dacx (x=1,2) opampx (x=1,2) usartx (x=1...5) (9) lpuart1 (9) i2cx (x=1...4) (10) lptimx (x=1,2) *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc, lcd, iwdg compx (x=1..2) usartx (x=1...5) (9) lpuart1 (9) i2cx (x=1...4) (10) lptimx (x=1,2) otg_fs (11) swpmi1 (12) 11.2 a w/o rtc 11.8 a w rtc 6.6 s in sram 7.8 s in flash stop 2 lpr no off on lse lsi bor, pvd, pvm rtc, lcd, iwdg compx (x=1..2) i2c3 (10) lpuart1 (9) lptim1 *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc, lcd, iwdg compx (x=1..2) i2c3 (10) lpuart1 (9) lptim1 2.57 a w/o rtc 2.86 a w/rtc 6.8 s in sram 8.2 s in flash table 4. STM32L496XX modes overview (continued) mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time
functional overview STM32L496XX 28/263 docid029173 rev 2 standby lpr power ed off off sram 2 on lse lsi bor, rtc, iwdg *** all other peripherals are powered off. *** i/o configuration can be floating, pull-up or pull-down reset pin 5 i/os (wkupx) (13) bor, rtc, iwdg 0.48 a w/o rtc 0.78 a w/ rtc 15.3 s off power ed off 0.11 a w/o rtc 0.42 a w/ rtc shutdown off power ed off off power ed off lse rtc *** all other peripherals are powered off. *** i/o configuration can be floating, pull-up or pull- down (14) reset pin 5 i/os (wkupx) (14) rtc 0.03 a w/o rtc 0.23 a w/ rtc 306 s 1. lpr means main regulator is of f and low-power regulator is on. 2. all peripherals can be active or cl ock gated to save power consumption. 3. typical current at v dd = 1.8 v, 25c. consumptions values provided running from sram, flash memory off, 80 mhz in range 1, 26 mhz in range 2, 2 mhz i n lprun/lpsleep. 4. the flash memory can be put in power-down and it s clock can be gated off w hen executing from sram. 5. theoretical value based on v dd = 3.3 v, dc/dc efficiency of 85%, v core = 1.10 v 6. theoretical value based on v dd = 3.3 v, dc/dc efficiency of 85%, v core = 1.05 v 7. the sram1 and sram2 clocks can be gated on or off independently. 8. smps mode can be used in stop0 mode, but no significant power gain can be expected. 9. u(s)art and lpuart reception is functional in stop mode, and generates a wakeup interrupt on start, address match or received frame event. 10. i2c address detection is functional in stop mode, and g enerates a wakeup interrupt in case of address match. 11. otg_fs wakeup by resume from suspend and attach detection protocol event. 12. swpmi1 wakeup by resume from suspend. 13. the i/os with wakeup from standby/shutdown capability are: pa0, pc13, pe6, pa2, pc5. 14. i/os can be configured with internal pull- up, pull-down or floating in shutdown mode but the configuration is lost when exit ing the shutdown mode. table 4. STM32L496XX modes overview (continued) mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time
docid029173 rev 2 29/263 STM32L496XX functional overview 60 by default, the microcontroller is in run mode af ter a system or a power reset. it is up to the user to select one of the low-power modes described below: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? low-power run mode this mode is achieved with v core supplied by the low-power regulator to minimize the regulator's operating current. the code can be executed from sram or from flash, and the cpu frequency is limited to 2 mhz. the peripherals with independent clock can be clocked by hsi16. ? low-power sleep mode this mode is entered from the low-power run mode. only the cpu clock is stopped. when wakeup is triggered by an event or an interrupt, the system reverts to the low- power run mode. ? stop 0, stop 1 and stop 2 modes stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the v core domain are stopped, the pll, the msi rc, the hsi16 rc and the hse crystal oscilla tors are disabled. the lse or lsi is still running. the rtc can remain active (stop mode with rtc, stop mode without rtc). some peripherals with wakeup capability can enable the hsi16 rc during stop mode to detect their wakeup condition. three stop modes are available: stop 0, stop 1 and stop 2 modes. in stop 2 mode, most of the v core domain is put in a lower leakage mode. stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than stop 2. in stop 0 mode, the main regulator remains on, allowing a very fast wakeup time but with much higher consumption. the system clock when exiting from stop 0, stop1 or stop2 modes can be either msi up to 48 mhz or hsi16, depending on software configuration. ? standby mode the standby mode is used to achieve t he lowest power consumption with bor. the internal regulator is swit ched off so that the v core domain is powered off. the pll, the msi rc, the hsi16 rc and the hse crystal oscillators are also switched off. the rtc can remain active (standby mo de with rtc, standby mode without rtc). the brown-out reset (bor) always remains active in standby mode. the state of each i/o during standby mode can be selected by software: i/o with internal pull-up, internal pull-down or floating. after entering standby mode, sram1 and register contents are lost except for registers in the backup domain and standby circuitry. optionally, sram2 can be retained in standby mode, supplied by the low-power regulator (standby with ram2 retention mode). the device exits standby mode when an external reset (nrst pin), an iwdg reset, wkup pin event (configurable rising or fallin g edge), or an rtc event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on lse (css on lse). the system clock after wakeup is msi up to 8 mhz.
functional overview STM32L496XX 30/263 docid029173 rev 2 ? shutdown mode the shutdown mode allows to achieve the lowest power consumption. the internal regulator is switched off so that the v core domain is powered off. the pll, the hsi16, the msi, the lsi and the hse oscillators are also switched off. the rtc can remain active (shutdown mode with rtc, shutdown mode without rtc). the bor is not available in shutdown mode . no power voltage monitoring is possible in this mode, therefore the switch to backup domain is not supported. sram1, sram2 and register contents are lost except for registers in the backup domain. the device exits shutdown mode when an external reset (nrst pin), a wkup pin event (configurable rising or falling edge), or an rtc ev ent occurs (alarm, periodic wakeup, timestamp, tamper). the system clock after wakeup is msi at 4 mhz.
docid029173 rev 2 31/263 STM32L496XX functional overview 60 table 5. functionalities depending on the working mode (1) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability cpu y - y - - -- -- -- -- flash memory (up to 1 mb) o (2) o (2) o (2) o (2) - -- -- -- -- sram1 (256 kb) y y (3) yy (3) y -y -- -- -- sram2 (64 kb) y y (3) yy (3) y -y -o (4) -- -- fsmc oooo- -- -- -- -- quad spi o o o o - -- -- -- -- backup registers y y y y y -y -y -y -y brown-out reset (bor) yyyyy yy yy y- -- programmable voltage detector (pvd) ooooo oo o- -- -- peripheral voltage monitor (pvmx; x=1,2,3,4) ooooo oo o- -- -- dma oooo- -- -- -- -- dma2d oooo- -- -- -- -- high speed internal (hsi16) oooo (5) - (5) -- -- -- oscillator hsi48 o o - - - -- -- -- -- high speed external (hse) oooo- -- -- -- -- low speed internal (lsi) ooooo -o -o -- -- low speed external (lse) ooooo -o -o -o -o multi-speed internal (msi) oooo- -- -- -- -- clock security system (css) oooo- -- -- -- -- clock security system on lse ooooo oo oo o- -- rtc / auto wakeup o o o o o oo oo oo oo
functional overview STM32L496XX 32/263 docid029173 rev 2 number of rtc tamper pins 33333 o3 o3 o3 o3 camera interface o o o o - -- -- -- -- lcd ooooo oo o- -- -- usb otg fs o (8) o (8) --- o- -- -- -- usartx (x=1,2,3,4,5) ooooo (6) o (6) - -- -- -- low-power uart (lpuart) ooooo (6) o (6) o (6) o (6) - -- -- i2cx (x=1,2,4) o o o o o (7) o (7) - -- -- -- i2c3 ooooo (7) o (7) o (7) o (7) - -- -- spix (x=1,2,3) o o o o - -- -- -- -- can(x=1,2) o o o o - -- -- -- -- sdmmc1 o o o o - -- -- -- -- swpmi1 oooo- o- -- -- -- saix (x=1,2) o o o o - -- -- -- -- dfsdm1 oooo- -- -- -- -- adcx (x=1,2,3) o o o o - -- -- -- -- dacx (x=1,2) o o o o o -- -- -- -- vrefbuf o o o o o -- -- -- -- opampx (x=1,2) o o o o o -- -- -- -- compx (x=1,2) o o o o o oo o- -- -- temperature sensor o o o o - -- -- -- -- timers (timx) o o o o - -- -- -- -- low-power timer 1 (lptim1) ooooo oo o- -- -- low-power timer 2 (lptim2) ooooo o- -- -- -- independent watchdog (iwdg) ooooo oo oo o- -- window watchdog (wwdg) oooo- -- -- -- -- table 5. functionalities depending on the working mode (1) (continued) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability
docid029173 rev 2 33/263 STM32L496XX functional overview 60 3.10.5 reset mode in order to improve the consumption under reset, the i/os state under and after reset is ?analog state? (the i/o schmitt trigger is disabl e). in addition, the internal reset pull-up is deactivated when the reset source is internal. 3.10.6 vbat operation the vbat pin allows to power the device vbat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. the vbat pin supplies the rtc with lse and the backup registers. three anti- tamper detection pins are available in vbat mode. vbat operation is automatically activated when v dd is not present. systick timer o o o o - -- -- -- -- touch sensing controller (tsc) oooo- -- -- -- -- random number generator (rng) o (8) o (8) --- -- -- -- -- crc calculation unit o o o o - -- -- -- -- gpios ooooo oo o (9) 5 pins (10) (11) 5 pins (10) - 1. legend: y = yes (enable). o = optional (disable by default. can be enabled by software). - = not available. 2. the flash can be configured in power-down m ode. by default, it is not in power-down mode. 3. the sram clock can be gated on or off. 4. sram2 content is preserved when the bit rrs is set in pwr_cr3 register. 5. some peripherals with wakeup from stop capability can r equest hsi16 to be enabled. in this case, hsi16 is woken up by the peripheral, and only feeds the peripheral which requested it. hsi16 is automatically put of f when the peripheral does not need it anymore. 6. uart and lpuart reception is functional in stop mode, and generates a wakeup interrupt on start, address match or received frame event. 7. i2c address detection is functional in stop mode, and generates a wakeup interrupt in case of address match. 8. voltage scaling range 1 only. 9. i/os can be configured with internal pul l-up, pull-down or floating in standby mode. 10. the i/os with wakeup from standby/shutdown capability are: pa0, pc13, pe6, pa2, pc5. 11. i/os can be configured with internal pull-up, pull-down or floating in shutdown mode but the configuration is lost when exiting the shutdown mode. table 5. functionalities depending on the working mode (1) (continued) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability
functional overview STM32L496XX 34/263 docid029173 rev 2 an internal vbat battery charging circuit is embedded and can be activated when v dd is present. note: when the microcontroller is supplied from vba t, external interrupts and rtc alarm/events do not exit it from vbat operation. 3.11 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. depending on peripherals, these interconnecti ons can operate in run, sleep, low-power run and sleep, stop 0, stop 1 and stop 2 modes. table 6. STM32L496XX peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2 timx timx timers synchronization or chaining y y y y - - adcx dacx dfsdm1 conversion triggers y y y y - - dma memory to memory transfer trigger y y y y - - compx comparator output blanking y y y y - - tim16/tim17 irtim infrared inte rface output generation y y y y - - compx tim1, 8 tim2, 3 timer input channel, trigger, break from analog signals comparison yyyy - - lptimerx low-power timer triggered by analog signals comparison yyyyy y (1) adcx tim1, 8 timer triggered by analog watchdog y y y y - - rtc tim16 timer input channel from rtc events y y y y - - lptimerx low-power timer triggered by rtc alarms or tampers yyyyy y (1) all clocks sources (internal and external) tim2 tim15, 16, 17 clock source used as input channel for rc measurement and trimming yyyy - - usb tim2 timer triggered by usb sof y y - - - -
docid029173 rev 2 35/263 STM32L496XX functional overview 60 css cpu (hard fault) ram (parity error) flash memory (ecc error) compx pvd dfsdm1 (analog watchdog, short circuit detection) tim1,8 tim15,16,17 timer break y y y y - - gpio timx external trigger y y y y - - lptimerx external trigger y y y y y y (1) adcx dacx dfsdm1 conversion external trigger y y y y - - 1. lptim1 only. table 6. STM32L496XX peripherals interconnect matrix (continued) interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2
functional overview STM32L496XX 36/263 docid029173 rev 2 3.12 clocks and startup the clock controller (see figure 4 ) distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robust ness. it features: ? clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source: four different clock sources can be used to drive the master clock sysclk: ? 4-48 mhz high-speed external crystal or ceramic resonator (hse) , that can supply a pll. the hse can also be configured in bypass mode for an external clock. ? 16 mhz high-speed internal rc oscillator (h si16), trimmable by software, that can supply a pll ? multispeed internal rc oscillator (msi), tr immable by software, able to generate 12 frequencies from 100 khz to 48 mhz. when a 32.768 khz clock source is available in the system (lse), the msi fr equency can be automatically trimmed by hardware to reach better than 0.25% accuracy. in this mode the msi can feed the usb device, saving the need of an exte rnal high-speed crystal (hse). the msi can supply a pll. ? system pll which can be fed by hse, hsi16 or msi, with a maximum frequency at 80 mhz. ? rc48 with clock recovery system (hsi48): in ternal 48 mhz clock source (hsi48)can be used to drive the usb, the sdmmc or the rng peripherals. this clock can be output on the mco. ? auxiliary clock source: two ultralow-power clock sources that can be used to drive the lcd controller and the real-time clock: ? 32.768 khz low-speed external crystal (lse), supporting four drive capability modes. the lse can also be configured in bypass mode for an external clock. ? 32 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock accura cy is 5% accuracy. ? peripheral clock sources: several peripherals (usb, sdmmc, rng, sai, usarts, i2cs, lptimers, adc, swpmi) have their ow n independent clock whatever the system clock. three plls, each having three i ndependent outputs allowing the highest flexibility, can generate independent cl ocks for the adc, the usb/sdmmc/rng and the two sais. ? startup clock: after reset, the microcontroller restar ts by default with an internal 4 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master clock is automatically switched to hsi16 and a software
docid029173 rev 2 37/263 STM32L496XX functional overview 60 interrupt is generated if enabled. lse failure can also be detected and generated an interrupt. ? clock-out capability: ? mco: microcontroller clock output: it outputs one of the internal clocks for external use by the application ? lsco: low speed clock output: it outputs lsi or lse in all low-power modes (except vbat). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the ma ximum frequency of the ahb and the apb domains is 80 mhz.
functional overview STM32L496XX 38/263 docid029173 rev 2 figure 4. clock tree 06y9 6<6&/. 0&2 /6&2 3// 6$,b(;7&/. 0+]forfnwr86%51*6'00& wr$'& wr,:'* wr57&dqg/&' wr3:5 +&/. wr$+%exvfruhphpru\dqg'0$ )&/.&ruwh[iuhhuxqqlqjforfn wr&ruwh[v\vwhpwlphu wr$3%shulskhudov wr$3%shulskhudov 3&/. 3&/. wr6$, wr6$, /6( +6, 6<6&/. wr86$57[ ; wr/38$57 wr,&[ [ wr/37,0[ [ 6$,b(;7&/. wr6:30, wr7,0[ [ 26&b287 26&b,1 06, +6, +6( +6( 06, +6, 06, 6<6&/. >^k^ ??x?l, l?? ,wz^ lu?uxx?? l? wwz^ lu?ueu?u ?}??? +6, 6<6&/. /6, /6( +6, +6, w?wz^ lu?ueu?u wr7,0[ [ ?}??? wr 86$57 /6( +6, 6<6&/. lw ly lz 3//6$, lw ly lz ld d^/z l,te?d, ,^/z d, ,^k^ ere?d, o}l ??}? 26&b287 26&b,1 : >^/z??l, o}l ?}? }v??}o 3//6$,&/. 3//0&/. 3//&/. 3//6$,&/. 3//0&/. 3//$'&&/. 3//6$,&/. 3//$'&&/. +6, +6, +6, 3//6$, lw ly lz ,^/ze?d, z^ +6, /6, /6( +6( 6<6&/. 3//&/. +6, +6, 06,
docid029173 rev 2 39/263 STM32L496XX functional overview 60 3.13 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. fast i/o toggling can be achieved thanks to their mapping on the ahb2 bus. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.14 direct memory a ccess controller (dma) the device embeds 2 dmas. refer to table 7: dma implementation for the features implementation. direct memory access (dma) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. data can be quickly moved by dma without any cpu actions. this keeps cpu resources free for other operations. the two dma controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. each has an arbiter for handling the priority between dma requests. the dma supports: ? 14 independently configurable channels (requests) ? each channel is connected to dedicated hardware dma requests, software trigger is also supported on each channel. this configuration is done by software. ? priorities between requests from channels of one dma are software programmable (4 levels consisting of very high, high, medi um, low) or hardware in case of equality (request 1 has priority over request 2, etc.) ? independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. source/destination addresses must be aligned on the data size. ? support for circular buffer management ? 3 event flags (dma half transfer, dma transfer complete and dma transfer error) logically ored together in a single interrupt request for each channel ? memory-to-memory transfer ? peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers ? access to flash, sram, apb and ahb pe ripherals as source and destination ? programmable number of data to be transferred: up to 65536. table 7. dma implementation dma features dma1 dma2 number of regular channels 7 7
functional overview STM32L496XX 40/263 docid029173 rev 2 3.15 chrom-art accelerator? (dma2d) the chrom-art accelerator? (dma2d) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conv ersion. it supports the following functions: ? rectangle filling with a fixed color ? rectangle copy ? rectangle copy with pixel format conversion ? rectangle composition with blending and pixel format conversion. various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. it embeds dedicated memory to store color lookup tables. an interrupt can be generated when an operation is complete or at a programmed watermark. all the operations are fully automatized and are running independently from the cpu or the dmas. 3.16 interrupts and events 3.16.1 nested vectored inte rrupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 90 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.16.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 41 edge det ector lines used to generate interrupt/event requests and wake-up the system from stop mode. each external line can be independently configur ed to select the trigger event (rising edge, fa lling edge, both) and can be masked independently a pending register main tains the status of the interrupt requests. the internal lines are connected to peripherals with wakeup fr om stop mode capability. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 136 gpios can be connected to the 16 external interrupt lines.
docid029173 rev 2 41/263 STM32L496XX functional overview 60 3.17 analog to digital converter (adc) the device embeds 3 successive approximati on analog-to-digital converters with the following features: ? 12-bit native resolution , with built-in calibration ? 5.33 msps maximum conversion rate with full resolution ? down to 18.75 ns sampling time ? increased conversion rate for lower resolution (up to 8.88 msps for 6-bit resolution) ? up to 24 external channels, some of them shared between adc1 and adc2, or adc1, adc2 and adc3. ? 5 internal channels: internal reference volt age, temperature sensor, vbat/3, dac1 and dac2 outputs. ? one external reference pin is available on some package, allowing the input voltage range to be independent from the power supply ? single-ended and differential mode inputs ? low-power design ? capable of low-current operation at lo w conversion rate (consumption decreases linearly with speed) ? dual clock domain architecture: adc speed independent from cpu frequency ? highly versatile digital interface ? single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions ? handles two adc converters for du al mode operation (simultaneous or interleaved sampling modes) ? each adc support multiple trigger inputs for synchronization with on-chip timers and external signals ? results stored into 3 data register or in ram with dma controller support ? data pre-processing: left/right alignment and per channel offset compensation ? built-in oversampling unit for enhanced snr ? channel-wise programmable sampling time ? three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers ? hardware assistant to prepare the context of the injected channels to allow fast context switching 3.17.1 temperature sensor the temperature sensor (ts) generates a voltage v ts that varies linearly with temperature. the temperature sensor is internally conn ected to the adc1_in17 and adc3_in17 input channels which is used to convert the sens or output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
functional overview STM32L496XX 42/263 docid029173 rev 2 to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.17.2 internal voltage reference (v refint ) the internal voltage reference (vrefint) provides a stable (bandgap) voltage output for the adc and comparators. vrefint is inte rnally connected to the adc1_in0 input channel. the precise voltage of vrefint is individually measured for each part by st during production test and stored in the system memory area. it is a ccessible in read-only mode. 3.17.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in18 or adc3_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the vbat pin is internally connected to a bridge divider by 3. as a c onsequence, the converted digital value is one third the v bat voltage. 3.18 digital to analog converter (dac) two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inve rting configuration. table 8. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75a8 - 0x1fff 75a9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75ca - 0x1fff 75cb table 9. internal voltage reference calibration values calibration value name description memory address vrefint raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75aa - 0x1fff 75ab
docid029173 rev 2 43/263 STM32L496XX functional overview 60 this digital interface supp orts the following features: ? up to two dac output channels ? 8-bit or 12-bit output mode ? buffer offset calibration (factory and user trimming) ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? sample and hold low-power mode, with internal or external capacitor the dac channels are triggered through the ti mer update outputs that are also connected to different dma channels. 3.19 voltage referenc e buffer (vrefbuf) the STM32L496XX devices embed an voltage reference buffer which can be used as voltage reference for adcs, dacs and also as voltage reference for external components through the vref+ pin. the internal voltage reference buffer supports two voltages: ? 2.048 v ? 2.5 v an external voltage reference can be provided through the vref+ pin when the internal voltage reference buffer is off. the vref+ pin is double-bonded with vdda on some packages. in these packages the internal voltage reference buffer is not available. figure 5. voltage reference buffer 06y9 95()%8) /rziuhtxhqf\ fxwriifdsdflwru '$&$'& %dqgjds 9 ''$ q) 95()
functional overview STM32L496XX 44/263 docid029173 rev 2 3.20 comparators (comp) the STM32L496XX devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hyster esis and speed (low speed for low-power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output channels ? internal reference voltage or submultiple (1/4, 1/2, 3/4). all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.21 operational amplifier (opamp) the STM32L496XX embeds two operational amplifiers with external or internal follower routing and pga capability. the operational amplifier features: ? low input bias current ? low offset voltage ? low-power mode ? rail-to-rail input 3.22 touch sensing controller (tsc) the touch sensing controller provides a simple solution for adding capacitive sensing functionality to any a pplication. capacitive sensing technology is able to detect finger presence near an electrode which is protecte d from direct touch by a dielectric (glass, plastic, ...). the capacitive va riation introduced by the finger (or any conductive object) is measured using a proven implementation base d on a surface charge transfer acquisition principle. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application.
docid029173 rev 2 45/263 STM32L496XX functional overview 60 the main features of the touch sensing controller are the following: ? proven and robust surface charge transfer acquisition principle ? supports up to 24 capacitive sensing channels ? up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time ? spread spectrum feature to improve system robustness in noisy environments ? full hardware management of the charge transfer acquisition sequence ? programmable charge transfer frequency ? programmable sampling capacitor i/o pin ? programmable channel i/o pin ? programmable max count value to avoid long acquisition when a channel is faulty ? dedicated end of acquisiti on and max count er ror flags with inte rrupt capability ? one sampling capacitor for up to 3 capaciti ve sensing channels to reduce the system components ? compatible with proximity, touchkey, linear and rotary touch sensor implementation ? designed to operate with stmtouch touch sensing firmware library note: the number of capacitive sensing channels is dependent on the size of the packages and subject to i/ o availability. 3.23 liquid crystal di splay controller (lcd) the lcd drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. ? internal step-up converter to guarantee functi onality and contrast control irrespective of v dd . this converter can be deactivated, in whic h case the vlcd pin is used to provide the voltage to the lcd ? supports static, 1/2, 1/3, 1/4 and 1/8 duty ? supports static, 1/2, 1/3 and 1/4 bias ? phase inversion to reduce power consumption and emi ? integrated voltage outp ut buffers for higher lcd driving capability ? up to 8 pixels can be programmed to blink ? unneeded segments and common pins can be used as general i/o pins ? lcd ram can be updated at any time owing to a double-buffer ? the lcd controller can operate in stop mode 3.24 digital filter for sigm a-delta modulators (dfsdm) the device embeds one dfsdm with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. the dfsdm peripheral is dedicated to interface the external ? modulators to microcontroller and then to perform digital f iltering of the received data streams (which represent analog value on ? modulators inputs). dfsdm can also interface pdm (pulse density modulation) microphones and perform pdm to pcm conversion and filtering in
functional overview STM32L496XX 46/263 docid029173 rev 2 hardware. dfsdm features optio nal parallel data stream inputs from microcontrollers memory (through dma/cpu transfers into dfsdm or from internal adcs). dfsdm transceivers support several serial interface formats (to support various ? modulators). dfsdm digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final adc resolution. the dfsdm peripheral supports: ? 8 multiplexed input digital serial channels: ? configurable spi interface to connect various sd modulator(s) ? configurable manchester coded 1 wire interface support ? pdm (pulse density modulation) microphone input support ? maximum input clock frequency up to 20 mhz (10 mhz for manchester coding) ? clock output for sd modulator(s): 0..20 mhz ? alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): ? internal sources: adcs data or device memory data streams (dma) ? 4 digital filter modules with adjustable digital signal processing: ?sinc x filter: filter order/type (1..5), oversampling ratio (up to 1..1024) ? integrator: oversampling ratio (1..256) ? up to 24-bit output data resolution, signed output data format ? automatic data offset correction (offset stored in register by user) ? continuous or single conversion ? start-of-conversion triggered by: ? software trigger ? internal timers ? external events ? start-of-conversion synchronously with fi rst digital filter module (dfsdm1_flt0) ? analog watchdog feature: ? low value and high value data threshold registers ? dedicated configurable sincx digital filter (order = 1..3, oversampling ratio = 1..32) ? input from final output data or from selected input digital serial channels ? continuous monitoring independently from standard conversion ? short circuit detector to detect saturated analog input values (bottom and top range): ? up to 8-bit counter to detect 1..256 cons ecutive 0?s or 1?s on serial data stream ? monitoring continuously each input serial channel ? break signal generation on analog watchdog ev ent or on short circuit detector event ? extremes detector: ? storage of minimum and maximum values of final conversion data ? refreshed by software ? dma capability to read th e final conversion data ? interrupts: end of conversion, overrun, ana log watchdog, short circuit, input serial channel clock absence ? ?regular? or ?injected? conversions: ? ?regular? conversions can be requested at any time or even in continuous mode
docid029173 rev 2 47/263 STM32L496XX functional overview 60 without having any impact on the timing of ?injected? conversions ? ?injected? conversions for precise timi ng and with high conversion priority 3.25 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 3.26 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 3.27 timers and watchdogs the STM32L496XX includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers , two watchdog timers and a systick timer. the table below compares the features of t he advanced control, gener al purpose and basic timers. table 10. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 3 general- purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1
functional overview STM32L496XX 48/263 docid029173 rev 2 3.27.1 advanced-control timer (tim1, tim8) the advanced-control timer can each be se en as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead- times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose timx timers (described in section 3.27.2 ) using the same architecture, so th e advanced-control timers can work together with the timx timers via the time r link feature for synchronization or event chaining. general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no table 10. timer feature comparison (continued) timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs
docid029173 rev 2 49/263 STM32L496XX functional overview 60 3.27.2 general-purpose timers (tim2, tim3, tim4, tim5 , tim15, tim16, tim17) there are up to seven synchronizable general-purpose timers embedded in the STM32L496XX (see table 10 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2, tim3, tim4 and tim5 they are full-featured general-purpose timers: ? tim2 and tim5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and tim4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. these timers feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. they can work to gether, or with the other general-purpose timers via the timer link feature fo r synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 they are general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.27.3 basic timers (tim6 and tim7) the basic timers are mainly used for dac tri gger generation. they can also be used as generic 16-bit timebases. 3.27.4 low-power timer (lptim1 and lptim2) the devices embed two low-power timers. these timers have an independent clock and are running in stop mode if they are clocked by lse, lsi or an external cl ock. they are able to wakeup the system from stop mode. lptim1 is active in stop 0, stop 1 and stop 2 modes. lptim2 is active in stop 0 and stop 1 mode.
functional overview STM32L496XX 50/263 docid029173 rev 2 this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous/ one shot mode ? selectable software/ hardware input trigger ? selectable clock source ? internal clock sources: l se, lsi, hsi16 or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by pulse counter application). ? programmable digital glitch filter ? encoder mode (lptim1 only) 3.27.5 infrared interface (irtim) the STM32L496XX includes one infrared interfac e (irtim). it can be used with an infrared led to perform remote contro l functions. it uses tim16 an d tim17 output channels to generate output signal waveforms on ir_out pin. 3.27.6 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc (lsi) and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.27.7 system window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.27.8 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source
docid029173 rev 2 51/263 STM32L496XX functional overview 60 3.28 real-time clock (rtc ) and backup registers the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap ye ar), 30, and 31 days of the month. ? two programmable alarms. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to vbat mode. ? 17-bit auto-reload wakeup timer (wut) for periodic events with programmable resolution and period. the rtc and the 32 backup registers are supplied through a switch that takes power either from the v dd supply when present or from the vbat pin. the backup registers are 32-bit registers used to store 128 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby or shutdown mode. the rtc clock sources can be: ? a 32.768 khz external crystal (lse) ? an external resonator or oscillator (lse) ? the internal low power rc oscillator (l si, with typical frequency of 32 khz) ? the high-speed external clock (hse) divided by 32. the rtc is functional in vbat m ode and in all low-power modes when it is clocked by the lse. when clocked by the lsi, the rtc is not functional in vbat mode, but is functional in all low-power modes except shutdown mode. all rtc events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes.
functional overview STM32L496XX 52/263 docid029173 rev 2 3.29 inter-integrated circuit interface (i 2 c) the device embeds 4 i2c. refer to table 11: i2c implementation for the features implementation. the i 2 c bus interface handles communications bet ween the microcontroller and the serial i 2 c bus. it co ntrols all i 2 c bus-specific sequencing, protocol, arbitration and timing. the i2c peripheral supports: ? i 2 c-bus specification and user manual re v. 5 compatibility: ? slave and master modes , multimaster capability ? standard-mode (sm), with a bitrate up to 100 kbit/s ? fast-mode (fm), with a bitrate up to 400 kbit/s ? fast-mode plus (fm+), with a bitrate up to 1 mbit/s and 20 ma output drive i/os ? 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses ? programmable setup and hold times ? optional clock stretching ? system management bus (smbus) spec ification rev 2.0 compatibility: ? hardware pec (packet error checking) generation and verification with ack control ? address resolution protocol (arp) support ? smbus alert ? power system management protocol (pmbus tm ) specification rev 1.1 compatibility ? independent clock: a choice of independent clock sources allowing the i2c communication speed to be independent from the pclk reprogramming. refer to figure 4: clock tree . ? wakeup from stop mode on address match ? programmable analog and digital noise filters ? 1-byte buffer with dma capability table 11. i2c implementation i2c features (1) 1. x: supported i2c1 i2c2 i2c3 i2c4 standard-mode (up to 100 kbit/s) x x x x fast-mode (up to 400 kbit/s) x x x x fast-mode plus with 20ma output drive i/os (up to 1 mbit/s) x x x x programmable analog and digital noise filters x x x x smbus/pmbus hardware support x x x x independent clock x x x x wakeup from stop0, stop 1 mode on address match x x x x wakeup from stop 2 mode on address match - - x -
docid029173 rev 2 53/263 STM32L496XX functional overview 60 3.30 universal synchronous/asynch ronous receiver transmitter (usart) the STM32L496XX devices have three embedded universal synchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4, uart5). these interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. they pr ovide hardware m anagement of the cts and rts signals, and rs485 driver enable. they are able to communicate at speeds of up to 10mbit/s. usart1, usart2 and usart3 also provide smart card mode (iso 7816 compliant) and spi-like communication capability. all usart have a clock domain independent from the cpu clock, allowing the usartx (x=1,2,3,4,5) to wake up the mcu from stop mode using baudrates up to 204 kbaud. the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame all usart interfaces can be served by the dma controller. table 12. STM32L496XX us art/uart/lpuart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 lpuart1 hardware flow control for modem xxxxx x continuous communication using dma xxxxx x multiprocessor communication xxxxx x synchronous mode x x x - - - smartcard mode x x x - - - single-wire half-dupl ex communication xxxxx x irda sir endec block xxxxx - lin mode xxxxx - dual clock domain xxxxx x wakeup from stop 0 / stop 1 modes xxxxx x wakeup from stop 2 mode ----- x receiver timeout interrupt xxxxx - modbus communication xxxxx - auto baud rate detection x (4 modes) - driver enable xxxxx x lpuart/usart data length 7, 8 and 9 bits 1. x = supported.
functional overview STM32L496XX 54/263 docid029173 rev 2 3.31 low-power universal asynchr onous receiver transmitter (lpuart) the device embeds one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock, and can wakeup the system from stop mode using baudrates up to 220 kbaud. the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller.
docid029173 rev 2 55/263 STM32L496XX functional overview 60 3.32 serial peripheral interface (spi) three spi interfaces allow communication up to 40 mbits/s in master and up to 24 mbits/s slave modes, in half-duplex, full-duplex and simplex modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. the spi interfaces support nss pulse mode, ti mode and hardware crc calculation. all spi interfaces can be served by the dma controller. 3.33 serial audio interfaces (sai) the device embeds 2 sai. refer to table 13: sai implementation for the features implementation. the sai bus interface handles communications between the microcontroller and the serial audio protocol. the sai peripheral supports: ? two independent audio sub-blocks which can be transmitters or receivers with their respective fifo. ? 8-word integrated fifos for each audio sub-block. ? synchronous or asynchronous mode between the audio sub-blocks. ? master or slave configuration inde pendent for both audio sub-blocks. ? clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. ? data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. ? peripheral with large configurability and flexib ility allowing to target as example the following audio protocol: i2s, lsb or msb-ju stified, pcm/dsp, td m, ac?97 and spdif out. ? up to 16 slots available with configurable size and with th e possibility to select which ones are active in the audio frame. ? number of bits by frame may be configurable. ? frame synchronization active level conf igurable (offset, bit length, level). ? first active bit position in the slot is configurable. ? lsb first or msb first for data transfer. ? mute mode. ? stereo/mono audio frame capability. ? communication clock strobing edge configurable (sck). ? error flags with associated interrupts if enabled respectively. ? overrun and underrun detection. ? anticipated frame synchronization signal detection in slave mode. ? late frame synchronization signal detection in slave mode. ? codec not ready for the ac?97 mode in reception. ? interruption sources when enabled: ?errors. ? fifo requests. ? dma interface with 2 dedicated channels to handle access to the dedicated integrated fifo of each sai audio sub-block.
functional overview STM32L496XX 56/263 docid029173 rev 2 3.34 single wire protocol master interface (swpmi) the single wire protocol master interface (swp mi) is the master interface corresponding to the contactless frontend (clf) defined in the et si ts 102 613 technical specification. the main features are: ? full-duplex communication mode ? automatic swp bus state management (active, suspend, resume) ? configurable bitrate up to 2 mbit/s ? automatic sof, eof and crc handling swpmi can be served by the dma controller. 3.35 controller area network (can) the two cans are compliant with the 2.0a and b (active) specifications with a bit rate up to 1mbit/s. they can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. table 13. sai implementation sai features (1) 1. x: supported sai1 sai2 i2s, lsb or msb-justified, pcm/dsp, tdm, ac?97 x x mute mode x x stereo/mono audio frame capability. x x 16 slots x x data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit x x fifo size x (8 word) x (8 word) spdif x x
docid029173 rev 2 57/263 STM32L496XX functional overview 60 dual can peripheral configuration is available. the can peripheral supports: ? supports can protocol version 2.0 a, b active ? bit rates up to 1 mbit/s ? transmission ? three transmit mailboxes ? configurable transmit priority ? reception ? two receive fifos with three stages ? scalable filter banks: 28 filter banks shared between can1 and can2 ? identifier list feature ? configurable fifo overrun ? time-triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? time stamp sent in last two data bytes ? management ? maskable interrupts ? software-efficient mailbox mapping at a unique address space 3.36 secure digital input/output and multimediacards interface (sdmmc) the card host interface (sdmmc) provides an interface between th e apb peripheral bus and multimediacards (mmcs), sd memory cards and sdio cards. the sdmmc features include the following: ? full compliance with multimediacard system specification version 4.2. card support for three different databus modes: 1-bit (default), 4-bit and 8-bit ? full compatibility with previous versions of multimed iacards (forward compatibility) ? full compliance with sd memory card specifications version 2.0 ? full compliance with sd i/o card specification version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit ? data transfer up to 48 mhz for the 8 bit mode ? data write and read with dma capability 3.37 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg c ontroller requires a dedicated 48 mhz clock that can be provided by the internal mult ispeed oscillator (msi) automati cally trimmed by 32.768 khz external oscillator (lse).this allows to use the usb device without external high speed crystal (hse).
functional overview STM32L496XX 58/263 docid029173 rev 2 the synchronization for this oscillator can also be taken from the u sb data stream itself (sof signalization) which allows crystal less operation. the major features are: ? combined rx and tx fifo size of 1.25 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 1 bidirectional control endpoint + 5 in endpoints + 5 out endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? software configurable to otg 1.3 and otg 2.0 modes of operation ? otg 2.0 supports adp (att ach detection protocol) ? usb 2.0 lpm (link power management) support ? battery charging specific ation revision 1.2 support ? internal fs otg phy support for otg/host modes, a power switch is needed in case bus-powered devices are connected. 3.38 clock recover y system (crs) the STM32L496XX devices embed a special block which allows automatic trimming of the internal 48 mhz oscillator to guarantee its optima l accuracy over the whole device operational range. this automatic trimming is based on the external synchronization signal, which could be either derived fr om usb sof signalization, fr om lse oscillator, from an external signal on crs_sync pin or generated by user software. for faster lock-in during startup it is also possible to combine autom atic trimming with manual trimming action. 3.39 flexible static me mory controller (fsmc) the flexible static memory controller (f smc) includes two memory controllers: ? the nor/psram memory controller ? the nand/memory controller this memory controller is also named flexible memory controller (fmc). the main features of the fmc controller are the following: ? interface with static-memory mapped devices including: ? static random access memory (sram) ? nor flash memory/onenand flash memory ? psram (4 memory banks) ? nand flash memory with ecc hardware to check up to 8 kbyte of data ? 8-,16- bit data bus width ? independent chip select control for each memory bank ? independent configuration for each memory bank ? write fifo ? the maximum fmc_clk frequency for synchronous accesses is hclk/2.
docid029173 rev 2 59/263 STM32L496XX functional overview 60 lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.40 dual-flash quad spi memory interface (quadspi) the dual-flash quad spi is a specialized commu nication interface targeting single, dual or quad spi flash memories. it can operat e in any of the three following modes: ? indirect mode: all the operations are performed using the quadspi registers ? status polling mode: the exter nal flash status register is periodically read and an interrupt can be generated in case of flag setting ? memory-mapped mode: the external flash is memory mapped and is seen by the system as if it were an internal memory both throughput and capacity can be increased two-fold using dual-flash mode, where two quad spi flash memories are accessed simultaneously. the dual-flash quad spi interface supports: ? three functional modes: indirect , status-polling, and memory-mapped ? dual-flash mode, where 8 bits can be sent /received simultaneously by accessing two flash memories in parallel. ? sdr and ddr support ? fully programmable opcode for both indirect and memory mapped mode ? fully programmable frame format for both indirect and memory mapped mode ? each of the 5 following phases can be conf igured independently (enable, length, single/dual/quad communication) ? instruction phase ? address phase ? alternate bytes phase ? dummy cycles phase ? data phase ? integrated fifo for reception and transmission ? 8, 16, and 32-bit data accesses are allowed ? dma channel for indirect mode operations ? programmable masking for external flash flag management ? timeout management ? interrupt generation on fifo threshold, tim eout, status match, operation complete, and access error
functional overview STM32L496XX 60/263 docid029173 rev 2 3.41 development support 3.41.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.41.2 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the STM32L496XX through a small number of etm pins to an external hardware trace port analyzer (tpa) device. real-time instruction and data flow activity be recorded and then formatted for display on the host computer th at runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
docid029173 rev 2 61/263 STM32L496XX pinouts and pin description 108 4 pinouts and pin description figure 6. stm32l496ax ufbga169 pinout (1) 1. the above figure shows the package top view. figure 7. stm32l496ax, external smps device, ufbga169 pinout (1) 1. the above figure shows the package top view. 06y9 3, 3+ 9'' 3( 3% 3% 966 9'' 3$ 3$ 3$ 3, $ % & ' ( ) * + - . / 0 3, 3, 966 3( 3% 9'',2 3* 3' 3, 3, 3, 3+ 9'' 966 3, 3% 3% 3' 3+ 3, 3, 966 3( 3( 3( 3, 3+ 3+ 3& 9%$7 3( 3, 3+ 9''86% 3& 26&b,1 966 3& 9'',2 3& 26&b287 9'' 3* 3& 3+26&b,1 966 1567 3* 3' 966 3+ 26&b287 3& 3& 3* 3* 3* 3& 966$95() 3$ 3$ 3% 3( 3+ 3' 3' 3' 95() 9''$ 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 9'' 23$03b9, 10 3$ 966 3$ 3) 3) 966 3( 3+ 3+ 966 3% 3% 3% 3* 3' 3* 3' 3' 3& 3' 3& 3* 3' 3( 3+%227 3) 3$ 3& 3$ 3* 3' 3) 3) 3) 3& 3$ 3& 3* 3* 3) 3) 3% 3* 3* 3( 3) 3& 3( 3* 3* 3( 3& 3& 3) 3( 3+ 3+ 9'' 3$ 3$ 966 9'' 9'' 3' 3' 966 3% 1 3$ 3$ 9'' 23$03b9, 10 3% 3) 9'' 3( 3% 3+ 9'' 3% 3% 06y9 3, 3+ 9'' 3( 3% 3% 966 9'' 3$ 3$ 3$ 3, $ % & ' ( ) * + - . / 0 3, 3, 966 3( 3% 9'',2 3* 3' 3, 3, 3, 3+ 9'' 966 3, 3% 3% 3' 3+ 3, 3, 966 3( 3( 3( 3, 3+ 3+ 3& 9%$7 3( 3, 3+ 9''86% 3& 26&b,1 966 3& 9'',2 3& 26&b287 9'' 3* 3& 3+26&b,1 966 1567 3* 3' 966 3+ 26&b287 3& 3& 3* 3* 3* 3& 966$95() 3$ 3% 3( 3+ 3' 3' 3' 95() 9''$ 3$ 3$ 3% 3) 3( 3( 3+ 3' 3' 9'' 23$03b9, 10 3$ 966 3$ 3) 3) 966 3( 3+ 9'' 966 3% 3% 3% 3* 3' 9'' 3' 3' 3& 3' 3& 3* 3' 3( 3+%227 3) 3$ 3& 3$ 3* 3' 3) 3) 3) 3& 3$ 3& 3* 3* 3) 3) 3% 3* 3* 3( 3) 3( 3* 3* 3( 3& 3& 3) 3( 3+ 3+ 9'' 3$ 3$ 966 9'' 9'' 3' 3' 966 3% 1 3$ 3$ 9'' 23$03b9, 10 3% 3) 9'' 3( 3% 3+ 9'' 3% 3% 3$ 3&
pinouts and pin description STM32L496XX 62/263 docid029173 rev 2 figure 8. stm32l496zx lqfp144 pinout (1) 1. the above figure shows the package top view. 06y9 /4)3 3) 3+26&b,1 3+26&b287 1567 3& 3& 3& 3& 966$ 95() 95() 9''$ 3$ 3$ 3$ 3) 3) 3) 9'' 3) 3) 3) 966 3) 966 9'' 3$ 3& 3) 3$ 3$ 3% 966 3) 3$ 3& 9'' 3) 3( 3% 3% 3* 3( 966 3) 3) 3* 3( 9'' 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3* 3* 966 3* 3* 3& 3& 9'',2 3* 3* 9'' 966 3% 3% 3% 3( 3( 3% 9'',2 3* 3% 3+%227 966 3* 3* 3% 3% 3* 3' 9'' 3* 3* 3* 3' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 3$ 966 9''86% 3$ 3$ 3& 3& 3$ 3$ 3$ 3( 3% 966 3% 3( 3( 3( 3( 9'' 3( 3$ 3) 3) 9%$7 3&26&b,1 3) 3( 3( 3& 3&26&b287 3( 3( 3(
docid029173 rev 2 63/263 STM32L496XX pinouts and pin description 108 figure 9. stm32l496zx, external smps device, lqfp144 pinout (1) 1. the above figure shows the package top view. 06y9 /4)3 3) 3+26&b,1 3+26&b287 1567 3& 3& 3& 3& 966$ 95() 95() 9''$ 3$ 3$ 3$ 3) 3) 3) 9'' 3) 3) 3) 966 3) 966 9'' 3$ 3& 3) 3$ 3$ 3% 966 3) 3$ 3& 9'' 3) 3( 3% 3% 3* 3( 966 3) 3) 3* 3( 9'' 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3* 3* 966 3* 3* 3& 3& 9'',2 3* 3* 9'' 966 3( 3+%227 3% 9'' 3( 3% 9'',2 3* 3% 3% 966 3* 3* 3% 3% 3* 3' 9'' 3% 3* 3* 3' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 3$ 966 9''86% 3$ 3$ 3& 3& 3$ 3$ 3$ 3( 3% 966 9'' 3( 3( 3( 3( 9'' 3( 3$ 3) 3) 9%$7 3&26&b,1 3) 3( 3( 3& 3&26&b287 3( 3( 3(
pinouts and pin description STM32L496XX 64/263 docid029173 rev 2 figure 10. stm32l496qx ufbga132 ballout (1) 1. the above figure shows the package top view. 06y9 3+%227 3% 9'' 3) 3$ 3$ 3$ 23$03b 9,10 3) 3) 3* 3* 3( 3( 3% 3' 3' 3% 3% 3$ 3$ 3$ 3$ $ % & ' ( ) * + - . / 0 3( 3( 3% 3% 3' 3' 3' 3' 3& 3& 3$ 3& 3( 3( 3% 3' 3' 3& 9''86% 3$ 3& 26&b,1 3( 966 3$ 3$ 3& 3& 26&b287 9%$7 966 3& 3& 3& 3+26&b,1 966 966 966 3+ 26&b287 9'' 9'' 9'' 3& 1567 9'' 3' 3' 3' 966$95() 3& 3& 3' 3' 3' 3* 3& 3$ 3& 3' 3' 3% 3% 3% 95() 3$ 3$ 3& 3% 3( 3( 3( 3% 3% 3% 9''$ 3$ 23$03b 9,10 3% 3% 3( 3( 3( 3( 3( 3( 3* 3* 3) 3) 3* 3* 3* 966 966 9'' 9'',2 3) 3* 3$ 3* 3) 3) 3) 3) 3) 3* 3* 3* 3* 3* 3*
docid029173 rev 2 65/263 STM32L496XX pinouts and pin description 108 figure 11. stm32l496vx lqfp100 pinout (1) 1. the above figure shows the package top view. 06y9 /4)3 966 3+26&b,1 3+26&b287 1567 3& 3& 3& 3& 966$ 95() 95() 9''$ 3$ 3$ 3$ 3&26&b287 9'' 3( 9%$7 3&26&b,1 3( 3( 3( 3( 3& 3$ 966 3$ 3& 3% 9'' 3$ 3& 3( 3( 3$ 3$ 3( 3( 3( 3% 3% 3( 3% 966 3( 3( 3( 3% 9'' 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3$ 3& 3$ 3$ 3$ 9'' 966 9''86% 3$ 3$ 9'' 966 3% 3% 3% 3( 3( 3% 3' 3' 3% 3+%227 3' 3' 3& 3% 3% 3' 3& 3$ 3' 3' 3' 3& 3$
pinouts and pin description STM32L496XX 66/263 docid029173 rev 2 figure 12. stm32l496vx wlcsp100 pinout (1) 1. the above figure shows the package top view. figure 13. stm32l496vx, external smps device, wlcsp100 pinout (1) 1. the above figure shows the package top view. 06y9 9''86% 3$ 3' 9'' 3* 9'',2 3% 3% 966 9'' $ % & ' ( ) * + - . 966 3$ 3' 3' 3* 3* 3% 3% 3( 3( 3$ 3$ 3& 3& 3' 3( 3& 9%$7 3$ 3$ 3$ 3& 26&b,1 3& 3& 3$ 3& 26&b287 9'' 3& 3' 3' 3% 3% 3' 3& 3% 3% 3% 9''$ 9'' 966 3% 3( 3( 3& 3$ 966 3& 3' 3* 3% 3% 3% 3( 966 3' 3' 3+%227 3( 1567 9'' 3& 3' 3% 3$ 3& 3& 3& 3' 3( 3( 3$ 95() 95() 3$ 3+26&b,1 3+ 26&b287 3( 3( 3& 3$ 3$ 966$ 3( 3( 3% 3$ 9'' 3$ 3( 3% 06y9 9''86% 3$ 3' 9'' 3* 9'',2 3% 3% 9'' 9'' $ % & ' ( ) * + - . 966 3$ 3' 3' 3' 3* 3% 3% 966 3( 3$ 3$ 3& 3& 3' 3( 3& 9%$7 3$ 3$ 3$ 3& 26&b,1 3& 3& 3$ 966 9'' 3' 3' 3' 3% 3% 3% 95() 3% 9'' 3% 9''$ 9'' 966 3% 3( 3( 3& 3$ 966 3& 3' 3* 3+%227 3' 3% 3( 3& 26&b287 3& 3* 3% 3( 3( 9'' 3' 3& 3% 3& 3& 1567 3+ 26&b287 3' 3( 3( 3$ 3$ 3$ 3& 3+26&b,1 3& 3( 3( 3% 3$ 3$ 966$ 3( 3( 3% 3$ 9'' 3$ 3( 3%
docid029173 rev 2 67/263 STM32L496XX pinouts and pin description 108 figure 14. stm32l496rx lqfp64 pinout (1) 1. the above figure shows the package top view. 069 /4)3 9%$7 3&26&b,1 3&26&b287 3+26&b,1 3+26&b287 1567 3& 3& 3& 3& 966$95() 9''$95() 3$ 3$ 3$ 3& 3$ 966 3$ 3& 3% 9'' 3$ 3& 3% 3$ 3$ 966 3% 3% 3% 9'' 9''86% 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 966 9'' 966 3+%227 3% 3& 3% 3% 3% 3& 3% 3% 3$ 3% 3' 3& 3$
pinouts and pin description STM32L496XX 68/263 docid029173 rev 2 table 14. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below th e pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tt 3.6 v tolerant i/o rst bidirectional reset pin with embedded weak pull-up resistor option for tt or ft i/os _f (1) i/o, fm+ capable _l (2) i/o, with lcd function supplied by v lcd _u (3) i/o, with usb function supplied by v ddusb _a (4) i/o, with analog switch function supplied by v dda _s (5) i/o supplied only by v ddio2 notes unless otherwise specified by a note, all i/os are set as analog inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers 1. the related i/o structures in table 15 are: ft_f, ft_fa, ft_fl, ft_fla. 2. the related i/o structures in table 15 are: ft_l, ft_fl, ft_lu. 3. the related i/o structures in table 15 are: ft_u, ft_lu. 4. the related i/o structures in table 15 are: ft_a, ft_la, ft_fa, ft_fla, tt_a, tt_la. 5. the related i/o structures in table 15 are: ft_s, ft_fs.
STM32L496XX pinouts and pin description docid029173 rev 2 69/263 table 15. STM32L496XX pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions - - - - - - - c3 c3 pi11 i/o ft - eventout - - b9 c8 1 b2 1 1 d3 d3 pe2 i/o ft_l - traceck, tim3_etr, tsc_g7_io1, lcd_seg38, fmc_a23, sai1_mclk_a, eventout - - b10 b10 2 a1 2 2 d2 d2 pe3 i/o ft_l - traced0, tim3_ch1, tsc_g7_io2, lcd_seg39, fmc_a19, sai1_sd_b, eventout - - c8 e7 3 b1 3 3 d1 d1 pe4 i/o ft - traced1, tim3_ch2, dfsdm1_datin3, tsc_g7_io3, dcmi_d4, fmc_a20, sai1_fs_a, eventout - - d8 e8 4 c2 4 4 e4 e4 pe5 i/o ft - traced2, tim3_ch3, dfsdm1_ckin3, tsc_g7_io4, dcmi_d6, fmc_a21, sai1_sck_a, eventout - - e7 d8 5 d2 5 5 e3 e3 pe6 i/o ft - traced3, tim3_ch4, dcmi_d7, fmc_a22, sai1_sd_a, eventout rtc_tamp3/wkup3 1 c10 c10 6 e2 6 6 e2 e2 vbat s - - - - 2 c9 c9 7 c1 7 7 e1 e1 pc13 i/o ft - eventout rtc_tamp1/rtc_ts/ rtc_out/wkup2 3d10d108 d1 8 8 f1 f1 pc14- osc32_in (pc14) i/o ft - eventout osc32_in 4e10d9 9 e1 9 9 g1g1 pc15- osc32_out (pc15) i/o ft - eventout osc32_out
pinouts and pin description STM32L496XX 70/263 docid029173 rev 2 - - - - d6 10 10 f5 f5 pf0 i/o ft_f - i2c2_sda, fmc_a0, eventout - - - - - d5 11 11 f4 f4 pf1 i/o ft_f - i2c2_scl, fmc_a1, eventout - - - - - d4 12 12 f3 f3 pf2 i/o ft - i2c2_smba, fmc_a2, eventout - - - - - e4 13 13 g3 g3 pf3 i/o ft_a - fmc_a3, eventout adc3_in6 - - - - f3 14 14 g4 g4 pf4 i/o ft_a - fmc_a4, eventout adc3_in7 - - - - f4 15 15 g5 g5 pf5 i/o ft_a - fmc_a5, eventout adc3_in8 - d9 e10 10 f2 16 16 f2 f2 vss s - - - - - e9e911 g2 17 17g2g2 vdd s - -- - -----1818-- pf6 i/oft_a- tim5_etr, tim5_ch1, quadspi_bk1_io3, sai1_sd_b, eventout adc3_in9 -----1919-- pf7 i/oft_a- tim5_ch2, quadspi_bk1_io2, sai1_mclk_b, eventout adc3_in10 -----2020-- pf8 i/oft_a- tim5_ch3, quadspi_bk1_io0, sai1_sck_b, eventout adc3_in11 -----2121-- pf9 i/oft_a- tim5_ch4, quadspi_bk1_io1, sai1_fs_b, tim15_ch1, eventout adc3_in12 -----2222h4h4 pf10 i/oft_a- quadspi_clk, dcmi_d11, tim15_ch2, eventout adc3_in13 table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 71/263 5f10f1012 f1 23 23h1h1 ph0-osc_in (ph0) i/o ft - eventout osc_in 6 g10 f9 13 g1 24 24 j1 j1 ph1-osc_out (ph1) i/o ft - eventout osc_out 7 e8 f8 14 h2 25 25 h3 h3 nrst i/o rst - - - 8 f9 g10 15 h1 26 26 j2 j2 pc0 i/o ft_fla - lptim1_in1, i2c4_scl, i2c3_scl, dfsdm1_datin4, lpuart1_rx, lcd_seg18, lptim2_in1, eventout adc123_in1 9 f8 f7 16 j2 27 27 j3 j3 pc1 i/o ft_fla - traced0, lptim1_out, i2c4_sda, spi2_mosi, i2c3_sda, dfsdm1_ckin4, lpuart1_tx, quadspi_bk2_io0, lcd_seg19, sai1_sd_a, eventout adc123_in2 10 h10 g9 17 j3 28 28 j4 j4 pc2 i/o ft_la - lptim1_in2, spi2_miso, dfsdm1_ckout, quadspi_bk2_io1, lcd_seg20, eventout adc123_in3 11 f7 f6 18 k2 29 29 k1 k1 pc3 i/o ft_la - lptim1_etr, spi2_mosi, quadspi_bk2_io2, lcd_vlcd, sai1_sd_a, lptim2_etr, eventout adc123_in4 - h9 h9 19 - 30 30 - - vssa s - - - - -g8- 20 - 3131 - - vref- s - -- - 12 - - - j1 - - k2 k2 vssa/vref- s - - - - - g7 h10 21 l1 32 32 l1 l1 vref+ s - - - vrefbuf_out table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 72/263 docid029173 rev 2 -j10j1022m13333l2l2 vdda s - -- - 13 - - - - - - - - vdda/vref+ - - - - - 14 g9 g8 23 l2 34 34 k3 k3 pa0 i/o ft_a - tim2_ch1, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, sai1_extclk, tim2_etr, eventout opamp1_vinp, adc12_in5, rtc_tamp2/wkup1 - - - - m3 - - m1 m1 opamp1_vinm i tt - - - 15 h8 g7 24 m2 35 35 n2 n2 pa1 i/o ft_la (1) tim2_ch2, tim5_ch2, i2c1_smba, spi1_sck, usart2_rts_de, uart4_rx, lcd_seg0, tim15_ch1n, eventout opamp1_vinm, adc12_in6 16 h7 h8 25 k3 36 36 n1 n1 pa2 i/o ft_la - tim2_ch3, tim5_ch3, usart2_tx, lpuart1_tx, quadspi_bk1_ncs, lcd_seg1, sai2_extclk, tim15_ch1, eventout adc12_in7, wkup4/lsco 17 j9 j9 26 l3 37 37 m2 m2 pa3 i/o tt_la - tim2_ch4, tim5_ch4, usart2_rx, lpuart1_rx, quadspi_clk, lcd_seg2, sai1_mclk_a, tim15_ch2, eventout opamp1_vout, adc12_in8 18 k10 k10 27 e3 38 38 h2 h2 vss s - - - - 19 j8 j8 28 h3 39 39 g13 g13 vdd s - - - - 20 f6 h7 29 j4 40 40 l3 l3 pa4 i/o tt_a - spi1_nss, spi3_nss, usart2_ck, dcmi_hsync, sai1_fs_b, lptim2_out, eventout adc12_in9, dac1_out1 21 g6 j7 30 k4 41 41 k4 k4 pa5 i/o tt_a - tim2_ch1, tim2_etr, tim8_ch1n, spi1_sck, lptim2_etr, eventout adc12_in10, dac1_out2 table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 73/263 22 k9 k9 31 l4 42 42 m4 m4 pa6 i/o ft_la - tim1_bkin, tim3_ch1, tim8_bkin, dcmi_pixclk, spi1_miso, usart3_cts, lpuart1_cts, quadspi_bk1_io3, lcd_seg3, tim1_bkin_comp2, tim8_bkin_comp2, tim16_ch1, eventout opamp2_vinp, adc12_in11 ----m4--n4n4opamp2_vinmi tt-- - 23 j7 g6 32 j5 43 43 l4 l4 pa7 i/o ft_fla (1) tim1_ch1n, tim3_ch2, tim8_ch1n, i2c3_scl, spi1_mosi, quadspi_bk1_io2, lcd_seg4, tim17_ch1, eventout opamp2_vinm, adc12_in12 24 h6 k8 33 k5 44 44 h5 h5 pc4 i/o ft_la - usart3_tx, quadspi_bk2_io3, lcd_seg22, eventout comp1_inm, adc12_in13 25 k8 - 34 l5 45 45 j5 j5 pc5 i/o ft_la - usart3_rx, lcd_seg23, eventout comp1_inp, adc12_in14, wkup5 26 j6 h6 35 m5 46 46 k5 k5 pb0 i/o tt_la - tim1_ch2n, tim3_ch3, tim8_ch2n, spi1_nss, usart3_ck, quadspi_bk1_io1, lcd_seg5, comp1_out, sai1_extclk, eventout opamp2_vout, adc12_in15 27 k7 k7 36 m6 47 47 l5 l5 pb1 i/o ft_la - tim1_ch3n, tim3_ch4, tim8_ch3n, dfsdm1_datin0, usart3_rts_de, lpuart1_rts_de, quadspi_bk1_io0, lcd_seg6, lptim2_in1, eventout comp1_inm, adc12_in16 28 f5 j6 37 l6 48 48 n5 n5 pb2 i/o ft_la - rtc_out, lptim1_out, i2c3_smba, dfsdm1_ckin0, lcd_vlcd, eventout comp1_inp - - - - k6 49 49 m5 m5 pf11 i/o ft - dcmi_d12, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 74/263 docid029173 rev 2 - - - - j7 50 50 n6 n6 pf12 i/o ft - fmc_a6, eventout - -----5151-- vss s --- - -----5252a8a8 vdd s --- - - - - - k7 53 53 m6 m6 pf13 i/o ft - i2c4_smba, dfsdm1_datin6, fmc_a7, eventout - - - - - j8 54 54 l6 l6 pf14 i/o ft_fa - i2c4_scl, dfsdm1_ckin6, tsc_g8_io1, fmc_a8, eventout - - - - - j9 55 55 k6 k6 pf15 i/o ft_fa - i2c4_sda, tsc_g8_io2, fmc_a9, eventout - - - - - h9 56 56 j6 j6 pg0 i/o ft - tsc_g8_io3, fmc_a10, eventout - - - - - g9 57 57 h6 h6 pg1 i/o ft - tsc_g8_io4, fmc_a11, eventout - - k6k638m75858l7l7 pe7 i/o ft - tim1_etr, dfsdm1_datin2, fmc_d4, sai1_sd_b, eventout - - k5k539l75959k7k7 pe8 i/o ft - tim1_ch1n, dfsdm1_ckin2, fmc_d5, sai1_sck_b, eventout - - j5j540m86060j7 j7 pe9 i/o ft - tim1_ch1, dfsdm1_ckout, fmc_d6, sai1_fs_b, eventout - ----f66161m7m7 vss s --- - ----g66262n7n7 vdd s --- - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 75/263 - h5h541l86363h7h7 pe10 i/o ft - tim1_ch2n, dfsdm1_datin4, tsc_g5_io1, quadspi_clk, fmc_d7, sai1_mclk_b, eventout - - k4 k4 42 m9 64 64 n8 n8 pe11 i/o ft - tim1_ch2, dfsdm1_ckin4, tsc_g5_io2, quadspi_bk1_ncs, fmc_d8, eventout - - g5j443l96565m8m8 pe12 i/o ft - tim1_ch3n, spi1_nss, dfsdm1_datin5, tsc_g5_io3, quadspi_bk1_io0, fmc_d9, eventout - - g4 g5 44 m10 66 66 l8 l8 pe13 i/o ft - tim1_ch3, spi1_sck, dfsdm1_ckin5, tsc_g5_io4, quadspi_bk1_io1, fmc_d10, eventout - - j4 g4 45 m11 67 67 k8 k8 pe14 i/o ft - tim1_ch4, tim1_bkin2, tim1_bkin2_comp2, spi1_miso, quadspi_bk1_io2, fmc_d11, eventout - - h4 h4 46 m12 68 68 j8 j8 pe15 i/o ft - tim1_bkin, tim1_bkin_comp1, spi1_mosi, quadspi_bk1_io3, fmc_d12, eventout - 29 k3 k3 47 l10 69 69 n9 n9 pb10 i/o ft_fl - tim2_ch3, i2c4_scl, i2c2_scl, spi2_sck, dfsdm1_datin7, usart3_tx, lpuart1_rx, tsc_sync, quadspi_clk, lcd_seg10, comp1_out, sai1_sck_a, eventout - 30 j3 j3 48 l11 70 - h8 h8 pb11 i/o ft_fl - tim2_ch4, i2c4_sda, i2c2_sda, dfsdm1_ckin7, usart3_rx, lpuart1_tx, quadspi_bk1_ncs, lcd_seg11, comp2_out, eventout - --k1-- -70-m10 vdd12 s --- - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 76/263 docid029173 rev 2 - - - - - - - k9 k9 ph4 i/o ft_f - i2c2_scl, eventout - - - - - - - - l9 l9 ph5 i/o ft_f - i2c2_sda, dcmi_pixclk, eventout - - - - - - - - n10 n10 ph8 i/o ft_f - i2c3_sda, dcmi_hsync, eventout - - - - - - - - m9 m9 ph10 i/o ft - tim5_ch1, dcmi_d1, eventout - - - - - - - - m10 - ph11 i/o ft - tim5_ch2, dcmi_d2, eventout - ----- --m3m3 vss s --- - ----- --n3n3 vdd s --- - ----- --m11m11 vss s --- - 31 k2 k2 49 f12 71 71 l13 l13 vss s - - - - 32 k1 j2 50 g12 72 72 l12 l12 vdd s - - - - ----- --n11n11 vdd s --- - 33 j1 j1 51 l12 73 73 n12 n12 pb12 i/o ft_l - tim1_bkin, tim1_bkin_comp2, i2c2_smba, spi2_nss, dfsdm1_datin1, usart3_ck, lpuart1_rts_de, tsc_g1_io1, can2_rx, lcd_seg12, swpmi1_io, sai2_fs_a, tim15_bkin, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 77/263 34 j2 h2 52 k12 74 74 n13 n13 pb13 i/o ft_fl - tim1_ch1n, i2c2_scl, spi2_sck, dfsdm1_ckin1, usart3_cts, lpuart1_cts, tsc_g1_io2, can2_tx, lcd_seg13, swpmi1_tx, sai2_sck_a, tim15_ch1n, eventout - 35 h2 h1 53 k11 75 75 m13 m13 pb14 i/o ft_fl - tim1_ch2n, tim8_ch2n, i2c2_sda, spi2_miso, dfsdm1_datin2, usart3_rts_de, tsc_g1_io3, lcd_seg14, swpmi1_rx, sai2_mclk_a, tim15_ch1, eventout - 36 h1 h3 54 k10 76 76 m12 m12 pb15 i/o ft_l - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi, dfsdm1_ckin2, tsc_g1_io4, lcd_seg15, swpmi1_suspend, sai2_sd_a, tim15_ch2, eventout - - h3 g3 55 k9 77 77 l11 l11 pd8 i/o ft_l - usart3_tx, dcmi_hsync, lcd_seg28, fmc_d13, eventout - - g2 g2 56 k8 78 78 l10 l10 pd9 i/o ft_l - usart3_rx, dcmi_pixclk, lcd_seg29, fmc_d14, sai2_mclk_a, eventout - - g1 g1 57 j12 79 79 j13 j13 pd10 i/o ft_l - usart3_ck, tsc_g6_io1, lcd_seg30, fmc_d15, sai2_sck_a, eventout - - - - 58 j11 80 80 k12 k12 pd11 i/o ft_l - i2c4_smba, usart3_cts, tsc_g6_io2, lcd_seg31, fmc_a16, sai2_sd_a, lptim2_etr, eventout - - - - 59 j10 81 81 k11 k11 pd12 i/o ft_fl - tim4_ch1, i2c4_scl, usart3_rts_de, tsc_g6_io3, lcd_seg32, fmc_a17, sai2_fs_a, lptim2_in1, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 78/263 docid029173 rev 2 - - - 60 h12 82 82 k13 k13 pd13 i/o ft_fl - tim4_ch2, i2c4_sda, tsc_g6_io4, lcd_seg33, fmc_a18, lptim2_out, eventout - -----8383h12h12 vss s --- - - f1 f1 - - 84 84 h13 h13 vdd s - - - - - g3 f3 61 h11 85 85 k10 k10 pd14 i/o ft_l - tim4_ch3, lcd_seg34, fmc_d0, eventout - - f4 f2 62 h10 86 86 h11 h11 pd15 i/o ft_l - tim4_ch4, lcd_seg35, fmc_d1, eventout - ----g108787j12j12 pg2 i/oft_s- spi1_sck, fmc_a12, sai2_sck_b, eventout - ----f98888j11j11 pg3 i/oft_s- spi1_miso, fmc_a13, sai2_fs_b, eventout - ----f108989j10j10 pg4 i/oft_s- spi1_mosi, fmc_a14, sai2_mclk_b, eventout - ----e99090j9j9 pg5 i/oft_s- spi1_nss, lpuart1_cts, fmc_a15, sai2_sd_b, eventout - ----g49191g11g11 pg6 i/oft_s- i2c3_smba, lpuart1_rts_de, eventout - - - - - h4 92 92 h10 h10 pg7 i/o ft_fs - i2c3_scl, lpuart1_tx, fmc_int, sai1_mclk_a, eventout - - - - - j6 93 93 h9 h9 pg8 i/o ft_fs - i2c3_sda, lpuart1_rx, eventout - -----9494f13f13 vss s --- - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 79/263 -----9595f12f12 vddio2 s --- - 37 f2 f4 63 e12 96 96 f11 f11 pc6 i/o ft_l - tim3_ch1, tim8_ch1, dfsdm1_ckin3, tsc_g4_io1, dcmi_d0, lcd_seg24, sdmmc1_d6, sai2_mclk_a, eventout - 38 f3 e4 64 e11 97 97 g12 g12 pc7 i/o ft_l - tim3_ch2, tim8_ch2, dfsdm1_datin3, tsc_g4_io2, dcmi_d1, lcd_seg25, sdmmc1_d7, sai2_mclk_b, eventout - 39 e1 e1 65 e10 98 98 g10 g10 pc8 i/o ft_l - tim3_ch3, tim8_ch3, tsc_g4_io3, dcmi_d2, lcd_seg26, sdmmc1_d0, eventout - 40 e2 e2 66 d12 99 99 g9 g9 pc9 i/o ft_fl - tim8_bkin2, tim3_ch4, tim8_ch4, dcmi_d3, i2c3_sda, tsc_g4_io4, otg_fs_noe, lcd_seg27, sdmmc1_d1, sai2_extclk, tim8_bkin2_comp1, eventout - 41 e3 e3 67 d11 100 100 g8 g8 pa8 i/o ft_l - mco, tim1_ch1, usart1_ck, otg_fs_sof, lcd_com0, swpmi1_io, sai1_sck_a, lptim2_out, eventout - 42 d3 d3 68 d10 101 101 f10 f10 pa9 i/o ft_lu - tim1_ch2, spi2_sck, dcmi_d0, usart1_tx, lcd_com1, sai1_fs_a, tim15_bkin, eventout otg_fs_vbus 43 d2 d2 69 c12 102 102 f9 f9 pa10 i/o ft_lu - tim1_ch3, dcmi_d1, usart1_rx, otg_fs_id, lcd_com2, sai1_sd_a, tim17_bkin, eventout - 44 d1 d1 70 b12 103 103 e13 e13 pa11 i/o ft_u - tim1_ch4, tim1_bkin2, spi1_miso, usart1_cts, can1_rx, otg_fs_dm, tim1_bkin2_comp1, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 80/263 docid029173 rev 2 45 c1 c1 71 a12 104 104 d13 d13 pa12 i/o ft_u - tim1_etr, spi1_mosi, usart1_rts_de, can1_tx, otg_fs_dp, eventout - 46 c2 c2 72 a11 105 105 a11 a11 pa13 (jtms/swdio) i/o ft - jtms/swdio, ir_out, otg_fs_noe, swpmi1_tx, sai1_sd_b, eventout - 47 b1 b1 - - - - - - vss s - - - - 48 a1 a1 73 c11 106 106 e12 e12 vddusb s - - - - - - - 74 f11 107 107 c12 c12 vss s - - - - - - - 75 g11 108 108 c13 c13 vdd s - - - - - - - - - - - e11 e11 ph6 i/o ft - i2c2_smba, dcmi_d8, eventout - - - - - - - - d12 d12 ph7 i/o ft_f - i2c3_scl, dcmi_d9, eventout - - - - - - - - d11 d11 ph9 i/o ft - i2c3_smba, dcmi_d0, eventout - - - - - - - - b13 b13 ph12 i/o ft - tim5_ch3, dcmi_d3, eventout - - - - - - - - a13 a13 ph14 i/o ft - tim8_ch2n, dcmi_d4, eventout - - - - - - - - b12 b12 ph15 i/o ft - tim8_ch3n, dcmi_d11, eventout - - - - - - - - a12 a12 pi0 i/o ft - tim5_ch4, spi2_nss, dcmi_d13, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 81/263 - - - - - - - c11 c11 pi8 i/o ft - dcmi_d12, eventout - - - - - - - - b11 b11 pi1 i/o ft - spi2_sck, dcmi_d8, eventout - - - - - - - - b10 b10 pi2 i/o ft - tim8_ch4, spi2_miso, dcmi_d9, eventout - - - - - - - - c10 c10 pi3 i/o ft - tim8_etr, spi2_mosi, dcmi_d10, eventout - - - - - - - - d10 d10 pi4 i/o ft - tim8_bkin, dcmi_d5, eventout - - - - - - - - e10 e10 pi5 i/o ft - tim8_ch1, dcmi_vsync, eventout - - - - - - - - c9 c9 ph13 i/o ft - tim8_ch1n, can1_tx, eventout - - - - - - - - b9 b9 pi6 i/o ft - tim8_ch2, dcmi_d6, eventout - 49 b2 b2 76 a10 109 109 a10 a10 pa14 (jtck/swclk) i/o ft - jtck/swclk, lptim1_out, i2c1_smba, i2c4_smba, otg_fs_sof, swpmi1_rx, sai1_fs_b, eventout - 50 a2 a2 77 a9 110 110 a9 a9 pa15 (jtdi) i/o ft_l - jtdi, tim2_ch1, tim2_etr, usart2_rx, spi1_nss, spi3_nss, usart3_rts_de, uart4_rts_de, tsc_g3_io1, lcd_seg17, swpmi1_suspend, sai2_fs_b, eventout - 51 d4 c3 78 b11 111 111 d9 d9 pc10 i/o ft_l - traced1, spi3_sck, usart3_tx, uart4_tx, tsc_g3_io2, dcmi_d8, lcd_com4/lcd_seg28/lcd_seg40, sdmmc1_d2, sai2_sck_b, eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 82/263 docid029173 rev 2 52 c3 d4 79 c10 112 112 e9 e9 pc11 i/o ft_l - quadspi_bk2_ncs, spi3_miso, usart3_rx, uart4_rx, tsc_g3_io3, dcmi_d4, lcd_com5/lcd_seg29/lcd_seg41, sdmmc1_d3, sai2_mclk_b, eventout - 53 c4 c4 80 b10 113 113 f8 f8 pc12 i/o ft_l - traced3, spi3_mosi, usart3_ck, uart5_tx, tsc_g3_io4, dcmi_d9, lcd_com6/lcd_seg30/lcd_seg42, sdmmc1_ck, sai2_sd_b, eventout - - b3 b3 81 c9 114 114 b8 b8 pd0 i/o ft - spi2_nss, dfsdm1_datin7, can1_rx, fmc_d2, eventout - - a3 a3 82 b9 115 115 c8 c8 pd1 i/o ft - spi2_sck, dfsdm1_ckin7, can1_tx, fmc_d3, eventout - 54 e4 d5 83 c8 116 116 d8 d8 pd2 i/o ft_l - traced2, tim3_etr, usart3_rts_de, uart5_rx, tsc_sync, dcmi_d11, lcd_com7/lcd_seg31/lcd_seg43, sdmmc1_cmd, eventout - - - - 84 b8 117 117 e8 e8 pd3 i/o ft - spi2_sck, dcmi_d5, spi2_miso, dfsdm1_datin0, usart2_cts, quadspi_bk2_ncs, fmc_clk, eventout - - b4 c5 85 b7 118 118 c7 c7 pd4 i/o ft - spi2_mosi, dfsdm1_ckin0, usart2_rts_de, quadspi_bk2_io0, fmc_noe, eventout - - e5 b4 86 a6 119 119 d7 d7 pd5 i/o ft - usart2_tx, quadspi_bk2_io1, fmc_nwe, eventout - - - - - - 120 120 - - vss s - - - - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 83/263 - a4 a4 - - 121 121 - - vdd s - - - - - d5 b5 87 b6 122 122 e7 e7 pd6 i/o ft - dcmi_d10, quadspi_bk2_io1, dfsdm1_datin1, usart2_rx, quadspi_bk2_io2, fmc_nwait, sai1_sd_a, eventout - - c5 c6 88 a5 123 123 f7 f7 pd7 i/o ft - dfsdm1_ckin1, usart2_ck, quadspi_bk2_io3, fmc_ne1, eventout - - b5 d6 - d9 124 124 b7 b7 pg9 i/o ft_s - spi3_sck, usart1_tx, fmc_nce/fmc_ne2, sai2_sck_a, tim15_ch1n, eventout - - a5 a5 - d8 125 125 d6 d6 pg10 i/o ft_s - lptim1_in1, spi3_miso, usart1_rx, fmc_ne3, sai2_fs_a, tim15_ch1, eventout - - d6 e5 - g3 126 126 e6 e6 pg11 i/o ft_s - lptim1_in2, spi3_mosi, usart1_cts, sai2_mclk_a, tim15_ch2, eventout - - b6 b6 - d7 127 127 f6 f6 pg12 i/o ft_s - lptim1_etr, spi3_nss, usart1_rts_de, fmc_ne4, sai2_sd_a, eventout - - - - - c7 128 128 g7 g7 pg13 i/o ft_fs - i2c1_sda, usart1_ck, fmc_a24, eventout - - - - - c6 129 129 g6 g6 pg14 i/o ft_fs - i2c1_scl, fmc_a25, eventout - - - - - f7 130 130 a7 a7 vss s - - - - - a6 a6 - g7 131 131 b6 b6 vddio2 s - - - - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 84/263 docid029173 rev 2 - - - - k1 132 - c6 - pg15 i/o ft_s - lptim1_out, i2c1_smba, dcmi_d13, eventout comp2_inm 55 c6 f5 89 a8 133 132 a6 a6 pb3 (jtdo/traces wo) i/o ft_la - jtdo/traceswo, tim2_ch2, spi1_sck, spi3_sck, usart1_rts_de, otg_fs_crs_sync, lcd_seg7, sai1_sck_b, eventout comp2_inp 56 c7 e6 90 a7 134 133 a5 a5 pb4 (njtrst) i/o ft_fla - njtrst, tim3_ch1, i2c3_sda, spi1_miso, spi3_miso, usart1_cts, uart5_rts_de, tsc_g2_io1, dcmi_d12, lcd_seg8, sai1_mclk_b, tim17_bkin, eventout - 57 b7 c7 91 c5 135 134 b5 b5 pb5 i/o ft_la - lptim1_in1, tim3_ch2, can2_rx, i2c1_smba, spi1_mosi, spi3_mosi, usart1_ck, uart5_cts, tsc_g2_io2, dcmi_d10, lcd_seg9, comp2_out, sai1_sd_b, tim16_bkin, eventout - 58 a7 a7 92 b5 136 135 c5 c5 pb6 i/o ft_fa - lptim1_etr, tim4_ch1, tim8_bkin2, i2c1_scl, i2c4_scl, dfsdm1_datin5, usart1_tx, can2_tx, tsc_g2_io3, dcmi_d5, tim8_bkin2_comp2, sai1_fs_b, tim16_ch1n, eventout comp2_inp 59 d7 b7 93 b4 137 136 d5 d5 pb7 i/o ft_fla - lptim1_in2, tim4_ch2, tim8_bkin, i2c1_sda, i2c4_sda, dfsdm1_ckin5, usart1_rx, uart4_cts, tsc_g2_io4, dcmi_vsync, lcd_seg21, fmc_nl, tim8_bkin_comp1, tim17_ch1n, eventout comp2_inm, pvd_in 60 e6 d7 94 a4 138 137 e5 e5 ph3-boot0 i/o ft - eventout - table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
STM32L496XX pinouts and pin description docid029173 rev 2 85/263 61 b8 b8 95 a3 139 138 c4 c4 pb8 i/o ft_fl - tim4_ch3, i2c1_scl, dfsdm1_datin6, can1_rx, dcmi_d6, lcd_seg16, sdmmc1_d4, sai1_mclk_a, tim16_ch1, eventout - 62 a8 a8 96 b3 140 139 d4 d4 pb9 i/o ft_fl - ir_out, tim4_ch4, i2c1_sda, spi2_nss, dfsdm1_ckin6, can1_tx, dcmi_d7, lcd_com3, sdmmc1_d5, sai1_fs_a, tim17_ch1, eventout - ----- ---c6 vdd12 s --- - - - - 97 c3 141 140 a4 a4 pe0 i/o ft_l - tim4_etr, dcmi_d2, lcd_seg36, fmc_nbl0, tim16_ch1, eventout - - - - 98 a2 142 141 b4 b4 pe1 i/o ft_l - dcmi_d3, lcd_seg37, fmc_nbl1, tim17_ch1, eventout - - - a9 - - - 142 - - vdd12 s - - - - 63 a9 b9 99 d3 143 143 b3 b3 vss s - - - - 64 a10 a10 100 c4 144 144 a3 a3 vdd s - - - - ----- --c2c2 vss s --- - ----- --c1c1 vdd s --- - - - - - - - - a2 a2 ph2 i/o ft - quadspi_bk2_io0, eventout - 1. opampx_vinm pins are not available as additional functions on pins pa1 and pa7 on ufbga packages. on ufbga packages, use the opampx_vinm dedicated pins available on m3 and m4 balls. table 15. STM32L496XX pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 wlcsp100 wlcsp100_smps lqfp100 ufbga132 lqfp144 lqfp144_smps ufbga169 ufbga169_smps alternate functions additional functions
pinouts and pin description STM32L496XX 86/263 docid029173 rev 2 table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3 port a pa0 - tim2_ch1 tim5_ch1 tim8_etr - - - usart2_cts pa1 - tim2_ch2 tim5_ch2 - i2c1_smba spi1_sck - usart2_rts_ de pa2 - tim2_ch3 tim5_ch3 - - - - usart2_tx pa3 - tim2_ch4 tim5_ch4 - - - - usart2_rx pa4-----spi1_nssspi3_nssusart2_ck pa5 - tim2_ch1 tim2_etr tim8_ch1n - spi1_sck - - pa6 - tim1_bkin tim3_ch1 tim8_bkin dcmi_pixclk spi1_miso - usart3_cts pa7 - tim1_ch1n tim3_ch2 tim8_ch1n i2c3_scl spi1_mosi - - pa8 mco tim1_ch1 - - - - - usart1_ck pa9 - tim1_ch2 - spi2_sck i2c1_scl dcmi_d0 - usart1_tx pa10 - tim1_ch3 - - i2c1_sda dcmi_d1 - usart1_rx pa11 - tim1_ch4 tim1_bkin2 - - spi1_miso - usart1_cts pa12 - tim1_etr - - - spi1_mosi - usart1_rts_ de pa13 jtms/swdio ir_out - - - - - - pa14 jtck/swclk lptim1_out - - i2c1_smba i2c4_smba - - pa15 jtdi tim2_ch1 tim2_etr usart2_rx - spi1_nss spi3_nss usart3_rts_ de
STM32L496XX pinouts and pin description docid029173 rev 2 87/263 port b pb0 - tim1_ch2n tim3_ch3 tim8 _ch2n - spi1_nss - usart3_ck pb1 - tim1_ch3n tim3_ch4 tim8_ch3n - - dfsdm1_ datin0 usart3_rts_ de pb2 rtc_out lptim1_out - - i2c3_smba - dfsdm1_ckin0 - pb3 jtdo/ traceswo tim2_ch2 - - - spi1_sck spi3_sck usart1_rts_ de pb4 njtrst - tim3_ch1 - i2c3_sda spi1_miso spi3_miso usart1_cts pb5 - lptim1_in1 tim3_ch2 can2_rx i2c1_ smba spi1_mosi spi3_mosi usart1_ck pb6 - lptim1_etr tim4_ch1 tim8_bkin2 i2c1_scl i2c4_scl dfsdm1_ datin5 usart1_tx pb7 - lptim1_in2 tim4_ch2 tim8_bkin i2c1_ sda i2c4_sda dfsdm1_ckin5 usart1_rx pb8 - - tim4_ch3 - i2c1_scl - dfsdm1_ datin6 - pb9 - ir_out tim4_ch4 - i2c1_sd a spi2_nss dfsdm1_ckin6 - pb10 - tim2_ch3 - i2c4_scl i2c2_scl spi2_sck dfsdm1_ datin7 usart3_tx pb11 - tim2_ch4 - i2c4_sda i2c2_ sda - dfsdm1_ckin7 usart3_rx pb12 - tim1_bkin - tim1_bkin_ comp2 i2c2_smba spi2_nss dfsdm1_ datin1 usart3_ck pb13 - tim1_ch1n - - i2c2_scl spi2_sck dfsdm1_ckin1 usart3_cts pb14 - tim1_ch2n - tim8_ ch2n i2c2_sda spi2_miso dfsdm1_ datin2 usart3_rts_ de pb15 rtc_refin tim1_ ch3n - tim8_ch3n - spi2_mosi dfsdm1_ckin2 - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
pinouts and pin description STM32L496XX 88/263 docid029173 rev 2 port c pc0 - lptim1_in1 i2c4_scl - i2c3_scl - dfsdm1_ datin4 - pc1 traced0 lptim1_out i2c4_sda spi2_mosi i2c3_sda - dfsdm1_ckin4 - pc2 - lptim1_in2 - - - spi2_miso dfsdm1_ ckout - pc3 - lptim1_etr - - - spi2_mosi - - pc4------ -usart3_tx pc5------ -usart3_rx pc6 - - tim3_ch1 tim8_ch1 - - dfsdm1_ckin3 - pc7 - - tim3_ch2 tim8_ch2 - - dfsdm1_ datin3 - pc8 - - tim3_ch3 tim8_ch3 - - - - pc9 - tim8_bkin2 tim3_ch4 tim8_ch4 dcmi_d3 - i2c3_sda - pc10traced1-----spi3_sckusart3_tx pc11----- quadspi_bk 2_ncs spi3_miso usart3_rx pc12traced3-----spi3_mosiusart3_ck pc13------ - - pc14------ - - pc15------ - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
STM32L496XX pinouts and pin description docid029173 rev 2 89/263 port d pd0-----spi2_nss dfsdm1_ datin7 - pd1-----spi2_sckdfsdm1_ckin7- pd2 traced2 - tim3_etr - - - - usart3_rts_ de pd3 - - - spi2_sck dcmi_d5 spi2_miso dfsdm1_ datin0 usart2_cts pd4-----spi2_mosidfsdm1_ckin0 usart2_rts_ de pd5------ -usart2_tx pd6----dcmi_d10 quadspi_ bk2_io1 dfsdm1_ datin1 usart2_rx pd7------dfsdm1_ckin1usart2_ck pd8------ -usart3_tx pd9------ -usart3_rx pd10------ -usart3_ck pd11----i2c4_smba- -usart3_cts pd12 - - tim4_ch1 - i2c4_scl - - usart3_rts_ de pd13 - - tim4_ch2 - i2c4_sda - - - pd14--tim4_ch3--- - - pd15--tim4_ch4--- - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
pinouts and pin description STM32L496XX 90/263 docid029173 rev 2 port e pe0 - - tim4_etr - - - - - pe1------ - - pe2 traceck - tim3_etr - - - - - pe3 traced0 - tim3_ch1 - - - - - pe4 traced1 - tim3_ch2 - - - dfsdm1_ datin3 - pe5 traced2 - tim3_ch3 - - - dfsdm1_ckin3 - pe6 traced3 - tim3_ch4 - - - - - pe7 - tim1_etr - - - - dfsdm1_ datin2 - pe8 - tim1_ch1n - - - - dfsdm1_ckin2 - pe9 - tim1_ch1 - - - - dfsdm1_ ckout - pe10 - tim1_ch2n - - - - dfsdm1_ datin4 - pe11 - tim1_ch2 - - - - dfsdm1_ckin4 - pe12 - tim1_ch3n - - - spi1_nss dfsdm1_ datin5 - pe13 - tim1_ch3 - - - spi1_sck dfsdm1_ckin5 - pe14 - tim1_ch4 tim1_bkin2 tim1_bkin2_ comp2 -spi1_miso - - pe15 - tim1_bkin - tim1_bkin_ comp1 -spi1_mosi - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
STM32L496XX pinouts and pin description docid029173 rev 2 91/263 port f pf0----i2c2_sda- - - pf1----i2c2_scl- - - pf2----i2c2_smba- - - pf3------ - - pf4------ - - pf5------ - - pf6 - tim5_etr tim5_ch1 - - - - - pf7 - - tim5_ch2 - - - - - pf8 - - tim5_ch3 - - - - - pf9 - - tim5_ch4 - - - - - pf10 - - - quadspi_clk - - - - pf11------ - - pf12------ - - pf13----i2c4_smba- dfsdm1_ datin6 - pf14----i2c4_scl-dfsdm1_ckin6- pf15----i2c4_sda- - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
pinouts and pin description STM32L496XX 92/263 docid029173 rev 2 port g pg0------ - - pg1------ - - pg2-----spi1_sck- - pg3-----spi1_miso- - pg4-----spi1_mosi- - pg5-----spi1_nss- - pg6----i2c3_smba- - - pg7----i2c3_scl- - - pg8----i2c3_sda- - - pg9------spi3_sckusart1_tx pg10 - lptim1_in1 - - - - spi3_miso usart1_rx pg11 - lptim1_in2 - - - - spi3_mosi usart1_cts pg12 - lptim1_etr - - - - spi3_nss usart1_rts_ de pg13----i2c1_sda- -usart1_ck pg14----i2c1_scl- - - pg15 - lptim1_out - - i2c1_smba - - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
STM32L496XX pinouts and pin description docid029173 rev 2 93/263 port h ph0------ - - ph1------ - - ph2--- quadspi_ bk2_io0 -- - - ph3------ - - ph4----i2c2_scl- - - ph5----i2c2_sda- - - ph6----i2c2_smba- - - ph7----i2c3_scl- - - ph8----i2c3_sda- - - ph9----i2c3_smba- - - ph10--tim5_ch1--- - - ph11--tim5_ch2--- - - ph12--tim5_ch3--- - - ph13---tim8_ch1n-- - - ph14---tim8_ch2n-- - - ph15---tim8_ch3n-- - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
pinouts and pin description STM32L496XX 94/263 docid029173 rev 2 port i pi0 - - tim5_ch4 - - spi2_nss - - pi1-----spi2_sck- - pi2 - - - tim8_ch4 - spi2_miso - - pi3 - - - tim8_etr - spi2_mosi - - pi4 - - - tim8_bkin - - - - pi5---tim8_ch1-- - - pi6---tim8_ch2-- - - pi7---tim8_ch3-- - - pi8------ - - pi9------ - - pi10------ - - pi11------ - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/2/5/8/ lptim1 tim1/2/3/4/5 spi2/usart2/ can2/tim8/ quadspi i2c1/2/3/4/ dcmi spi1/2/dcmi/ quadspi spi3/i2c3/ dfsdm/ comp1/ quadspi usart1/2/3
STM32L496XX pinouts and pin description docid029173 rev 2 95/263 table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout port a pa0 uart4_tx - - - - sai1_extclk tim2_etr eventout pa1 uart4_rx - - lcd_seg0 - - tim15_ch1n eventout pa2 lpuart1_tx - quadspi_bk1_ncs lc d_seg1 - sai2_extclk t im15_ch1 eventout pa3 lpuart1_rx - quadspi_clk lcd_seg 2 - sai1_mclk_a tim15_ch2 eventout pa4 - - dcmi_hsync - - sai1_fs_b lptim2_out eventout pa5 - - - - - - lptim2_etr eventout pa6 lpuart1_ct s - quadspi_bk1 _io3 lcd_seg3 tim1_bkin_c omp2 tim8_bkin_c omp2 tim16_ch1 eventout pa7 - - quadspi_bk1_io2 lc d_seg4 - - tim17_ch1 eventout pa8 - - otg_fs_sof lcd_com0 swpmi1_i o sai1_sck_a lptim2_out eventout pa9 - - - lcd_com1 - sai1_fs_a tim15_bkin eventout pa10 - - otg_fs_id lcd_com2 - sai1_sd_a tim17_bkin eventout pa11 - can1_rx otg_fs_dm - tim1_bkin2_ comp1 - - eventout pa12 - can1_tx otg_fs_dp - - - - eventout pa13 - - otg_fs_noe - swpmi 1_tx sai1_sd_b - eventout pa14 - - otg_fs_sof - swpmi1_rx sai1_fs_b - eventout pa15 uart4_rts_ de tsc_g3_io1 - lcd_seg17 swpmi1_sus pend sai2_fs_b - eventout
pinouts and pin description STM32L496XX 96/263 docid029173 rev 2 port b pb0 - - quadspi_bk1_io1 lcd_seg5 c omp1_out sai1_extclk - eventout pb1 lpuart1_rt s_de - quadspi_bk1_io0 lcd_ seg6 - - lptim2_in1 eventout pb2 - - - lcd_vlcd - - - eventout pb3 - - otg_fs_crs_sync lcd_seg7 - sai1_sck_b - eventout pb4 uart5_rts_ de tsc_g2_io1 dcmi_d12 lcd_seg8 - sa i1_mclk_b tim17_bkin eventout pb5 uart5_cts tsc_g2_io2 dcmi_d10 lcd_seg9 c omp2_out sai1_sd_b tim16_bkin eventout pb6 can2_tx tsc_g2_io3 dcmi_d5 - tim8_bkin2_ comp2 sai1_fs_b tim16_ch1n eventout pb7 uart4_cts tsc_g2_io4 dcmi_vsync lcd_seg21 fmc_nl tim8_bkin_c omp1 tim17_ch1n eventout pb8 - can1_rx dcmi_d6 lcd_seg16 sdmmc 1_d4 sai1_mclk_a tim16_ch1 eventout pb9 - can1_tx dcmi_d7 lcd_com3 sdmmc 1_d5 sai1_fs_a tim17_ch1 eventout pb10 lpuart1_rx tsc_sync quadspi_clk l cd_seg10 comp1_out sai1_sck_a - eventout pb11 lpuart1_tx - quadspi_bk1_ncs lcd_seg11 comp2_out - - eventout pb12 lpuart1_rt s_de tsc_g1_io1 can2_rx lcd_seg12 swpmi1 _io sai2_fs_a tim15_bkin eventout pb13 lpuart1_ct s tsc_g1_io2 can2_tx lcd_seg13 swpmi 1_tx sai2_sck_a tim15_ch1n eventout pb14 - tsc_g1_io3 - lcd_seg14 swpmi1 _rx sai2_mclk_a tim15_ch1 eventout pb15 - tsc_g1_io4 - lcd_seg15 swpmi1_sus pend sai2_sd_a tim15_ch2 eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
STM32L496XX pinouts and pin description docid029173 rev 2 97/263 port c pc0 lpuart1_rx - - lcd_seg18 - - lptim2_in1 eventout pc1 lpuart1_tx - quadspi_bk2_io0 lcd_seg19 - sai1_sd_a - eventout pc2 - - quadspi_bk2_io1 lcd_seg20 - - - eventout pc3 - - quadspi_bk2_i o2 lcd_vlcd - sai1_sd_a lptim2_etr eventout pc4 - - quadspi_bk2_io3 lcd_seg22 - - - eventout pc5 - - - lcd_seg23 - - - eventout pc6 - tsc_g4_io1 dcmi_d0 lcd_seg24 sdmmc1_d6 sai2_mclk_a - eventout pc7 - tsc_g4_io2 dcmi_d1 lcd_seg25 sdmmc1_d7 sai2_mclk_b - eventout pc8 - tsc_g4_io3 dcmi_d2 lcd_seg26 sdmmc1_d0 - - eventout pc9 - tsc_g4_io4 otg_fs_noe l cd_seg27 sdmmc1_d1 sai2_extclk tim8_bkin2_c omp1 eventout pc10 uart4_tx tsc_g3_io2 dcmi_d8 lcd_com4/l cd_seg28/l cd_seg40 sdmmc1_d2 sai2_sck_b - eventout pc11 uart4_rx tsc_g3_io3 dcmi_d4 lcd_com5/l cd_seg29/l cd_seg41 sdmmc1_d3 sai2_mclk_b - eventout pc12 uart5_tx tsc_g3_io4 dcmi_d9 lcd_com6/l cd_seg30/l cd_seg42 sdmmc1_ck sai2_sd_b - eventout pc13 - - - - - - - eventout pc14 - - - - - - - eventout pc15 - - - - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
pinouts and pin description STM32L496XX 98/263 docid029173 rev 2 port d pd0 - can1_rx - - fmc_d2 - - eventout pd1 - can1_tx - - fmc_d3 - - eventout pd2 uart5_rx tsc_sync dcmi_d11 lcd_com7/l cd_seg31/l cd_seg43 sdmmc1_cm d - - eventout pd3 - - quadspi_bk2_ncs - fmc_clk - - eventout pd4 - - quadspi_bk2_io0 - fmc_noe - - eventout pd5 - - quadspi_bk2_i o1 - fmc_nwe - - eventout pd6 - - quadspi_bk2_io2 - fmc _nwait sai1_sd_a - eventout pd7 - - quadspi_bk2_io3 - fmc_ne1 - - eventout pd8 - - dcmi_hsync lcd_seg28 fmc_d13 - - eventout pd9 - - dcmi_pixclk lcd_seg29 fm c_d14 sai2_mclk_a - eventout pd10 - tsc_g6_io1 - lcd_seg30 fmc_d15 sai2_sck_a - eventout pd11 - tsc_g6_io2 - lcd_seg31 fmc_a1 6 sai2_sd_a lptim2_etr eventout pd12 - tsc_g6_io3 - lcd_seg32 fmc_a17 sai2_fs_a lptim2_in1 eventout pd13 - tsc_g6_io4 - lcd_seg33 fmc_a18 - lptim2_out eventout pd14 - - - lcd_seg34 fmc_d0 - - eventout pd15 - - - lcd_seg35 fmc_d1 - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
STM32L496XX pinouts and pin description docid029173 rev 2 99/263 port e pe0 - - dcmi_d2 lcd_seg36 fmc_nbl0 - tim16_ch1 eventout pe1 - - dcmi_d3 lcd_seg37 fmc_nbl1 - tim17_ch1 eventout pe2 - tsc_g7_io1 - lcd_seg38 fmc_a23 sai1_mclk_a - eventout pe3 - tsc_g7_io2 - lcd_seg39 fmc_a19 sai1_sd_b - eventout pe4 - tsc_g7_io3 dcmi_d4 - fmc_a20 sai1_fs_a - eventout pe5 - tsc_g7_io4 dcmi_d6 - fmc_a21 sai1_sck_a - eventout pe6 - - dcmi_d7 - fmc_a22 sai1_sd_a - eventout pe7 - - - - fmc_d4 sai1_sd_b - eventout pe8 - - - - fmc_d5 sai1_sck_b - eventout pe9 - - - - fmc_d6 sai1_fs_b - eventout pe10 - tsc_g5_io1 quadspi_clk - fmc_d7 sai1_mclk_b - eventout pe11 - tsc_g5_io2 quadspi_bk1_ncs - fmc_d8 - - eventout pe12 - tsc_g5_io3 quadspi_ bk1_io0 - fmc_d9 - - eventout pe13 - tsc_g5_io4 quadspi_bk1_io1 - fmc_d10 - - eventout pe14 - - quadspi_bk1_io2 - fmc_d11 - - eventout pe15 - - quadspi_bk1_io3 - fmc_d12 - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
pinouts and pin description STM32L496XX 100/263 docid029173 rev 2 port f pf0 - - - - fmc_a0 - - eventout pf1 - - - - fmc_a1 - - eventout pf2 - - - - fmc_a2 - - eventout pf3 - - - - fmc_a3 - - eventout pf4 - - - - fmc_a4 - - eventout pf5 - - - - fmc_a5 - - eventout pf6 - - quadspi_bk1_io3 - - sai1_sd_b - eventout pf7 - - quadspi_bk1_io2 - - sai1_mclk_b - eventout pf8 - - quadspi_bk1_io0 - - sai1_sck_b - eventout pf9 - - quadspi_bk1_io1 - - sai1_fs_b tim15_ch1 eventout pf10 - - dcmi_d11 - - - tim15_ch2 eventout pf11 - - dcmi_d12 - - - - eventout pf12 - - - - fmc_a6 - - eventout pf13 - - - - fmc_a7 - - eventout pf14 - tsc_g8_io1 - - fmc_a8 - - eventout pf15 - tsc_g8_io2 - - fmc_a9 - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
STM32L496XX pinouts and pin description docid029173 rev 2 101/263 port g pg0 - tsc_g8_io3 - - fmc_a10 - - eventout pg1 - tsc_g8_io4 - - fmc_a11 - - eventout pg2 - - - - fmc_a12 sai2_sck_b - eventout pg3 - - - - fmc_a13 sai2_fs_b - eventout pg4 - - - - fmc_a14 sai2_mclk_b - eventout pg5 lpuart1_ct s - - - fmc_a15 sai2_sd_b - eventout pg6 lpuart1_rt s_de - - - - - - eventout pg7 lpuart1_tx - - - fmc_int sai1_mclk_a - eventout pg8 lpuart1_rx - - - - - - eventout pg9 - - - - fmc_nce/fm c_ne2 sai2_sck_a tim15_ch1n eventout pg10 - - - - fmc_ne3 sai2_fs_a tim15_ch1 eventout pg11 - - - - - sai2_mclk_a tim15_ch2 eventout pg12 - - - - fmc_ne4 sai2_sd_a - eventout pg13 - - - - fmc_a24 - - eventout pg14 - - - - fmc_a25 - - eventout pg15 - - dcmi_d13 - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
pinouts and pin description STM32L496XX 102/263 docid029173 rev 2 port h ph0 - - - - - - - eventout ph1 - - - - - - - eventout ph2 - - - - - - - eventout ph3 - - - - - - - eventout ph4 - - - - - - - eventout ph5 - - dcmi_pixclk - - - - eventout ph6 - - dcmi_d8 - - - - eventout ph7 - - dcmi_d9 - - - - eventout ph8 - - dcmi_hsync - - - - eventout ph9 - - dcmi_d0 - - - - eventout ph10 - - dcmi_d1 - - - - eventout ph11 - - dcmi_d2 - - - - eventout ph12 - - dcmi_d3 - - - - eventout ph13 - can1_tx - - - - - eventout ph14 - - dcmi_d4 - - - - eventout ph15 - - dcmi_d11 - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
STM32L496XX pinouts and pin description docid029173 rev 2 103/263 port i pi0 - - dcmi_d13 - - - - eventout pi1 - - dcmi_d8 - - - - eventout pi2 - - dcmi_d9 - - - - eventout pi3 - - dcmi_d10 - - - - eventout pi4 - - dcmi_d5 - - - - eventout pi5 - - dcmi_vsync - - - - eventout pi6 - - dcmi_d6 - - - - eventout pi7 - - dcmi_d7 - - - - eventout pi8 - - dcmi_d12 - - - - eventout pi9 - can1_rx - - - - - eventout pi10 - - - - - - - eventout pi11 - - - - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4/5/ lpuart1/ can2 can1/tsc can2/ otg_fs/dcmi/ quadspi lcd sdmmc/ comp1/2/fm c/swpmi1 sai1/2 tim2/15/16/17/ lptim2 evenout
memory mapping STM32L496XX 104/263 docid029173 rev 2 5 memory mapping figure 15. STM32L496XX memory map 06y9 [)))))))) [( [& [$ [ [ [ [ [ &ruwh[?0 zlwk)38 ,qwhuqdo 3hulskhudov 3hulskhudov 65$0 &2'( 5hvhuyhg )0&dqg 48$'63, uhjlvwhuv [ 48$'63,)odvk edqn [ 65$0 273duhd 6\vwhpphpru\ )odvkphpru\ )odvkv\vwhpphpru\ ru65$0ghshqglqjrq %227frqiljxudwlrq $+% $+% $3% $3% [& [ [ [ [ [ [ [ [))))))) [)))) [))) [ [ [ [ 5hvhuyhg 5hvhuyhg 5hvhuyhg 5hvhuyhg 5hvhuyhg 5hvhuyhg [ [ 65$0 2swlrq%\whv 6\vwhpphpru\ 2swlrqv%\whv [)))) [))) [))) [))) [))) [))) [)))) 5hvhuyhg 5hvhuyhg 48$'63,uhjlvwhuv )0&uhjlvwhuv [%))))))) [$ [$ [$ 5hvhuyhg 5hvhuyhg 5hvhuyhg 5hvhuyhg [))))))) )0&edqn )0&edqn
docid029173 rev 2 105/263 STM32L496XX memory mapping 108 table 18. STM32L496XX memory map and peripheral register boundary addresses (1) bus boundary address size (bytes) peripheral ahb4 0xa000 1000 - 0xa000 13ff 1 kb quadspi ahb3 0xa000 0400 - 0xa000 0fff 3 kb reserved 0xa000 0000 - 0xa000 03ff 1 kb fmc - 0x5006 0c00 - 0x5fff ffff ~260 mb reserved ahb2 0x5006 0800 - 0x5006 0bff 1 kb rng 0x5005 0400 - 0x5005 ffff 62 kb reserved 0x5005 0000 - 0x5005 03ff 1 kb dcmi 0x5004 0400 - 0x5004 ffff 62 kb reserved 0x5004 0000 - 0x5004 03ff 1 kb adc 0x5000 0000 - 0x5003 ffff 16 kb otg_fs 0x4800 2400 - 0x4fff ffff ~127 mb reserved 0x4800 2000 - 0x4800 23ff 1 kb gpioi 0x4800 1c00 - 0x4800 1fff 1 kb gpioh 0x4800 1800 - 0x4800 1bff 1 kb gpiog 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb gpioe 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa - 0x4002 bc00 - 0x47ff ffff ~127 mb reserved ahb1 0x4002 b000 - 0x4002 bbff 3 kb dma2d 0x4002 4400 - 0x4002 afff 26 kb reserved 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 1 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash registers 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0800 - 0x4002 0fff 2 kb reserved 0x4002 0400 - 0x4002 07ff 1 kb dma2 0x4002 0000 - 0x4002 03ff 1 kb dma1
memory mapping STM32L496XX 106/263 docid029173 rev 2 apb2 0x4001 6400 - 0x4001 ffff 39 kb reserved 0x4001 6000 - 0x4001 63ff 1 kb dfsdm1 0x4001 5c00 - 0x4001 5fff 1 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb sai2 0x4001 5400 - 0x4001 57ff 1 kb sai1 0x4001 4c00 - 0x4001 53ff 2 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb tim8 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb sdmmc1 0x4001 2000 - 0x4001 27ff 2 kb reserved 0x4001 1c00 - 0x4001 1fff 1 kb firewall 0x4001 0800- 0x4001 1bff 5 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0200 - 0x4001 03ff 1 kb comp 0x4001 0030 - 0x4001 01ff vrefbuf 0x4001 0000 - 0x 4001 002f syscfg table 18. STM32L496XX memory map and peripheral register boundary addresses (1) (continued) bus boundary address size (bytes) peripheral
docid029173 rev 2 107/263 STM32L496XX memory mapping 108 apb1 0x4000 9800 - 0x4000 ffff 26 kb reserved 0x4000 9400 - 0x4000 97ff 1 kb lptim2 0x4000 8c00 - 0x4000 93ff 2 kb reserved 0x4000 8800 - 0x4000 8bff 1 kb swpmi1 0x4000 8400 - 0x4000 87ff 1 kb i2c4 0x4000 8000 - 0x4000 83ff 1 kb lpuart1 0x4000 7c00 - 0x4000 7fff 1 kb lptim1 0x4000 7800 - 0x4000 7bff 1 kb opamp 0x4000 7400 - 0x4000 77ff 1 kb dac 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6800 - 0x4000 6fff 1 kb reserved 0x4000 6800 - 0x4000 6bff 1 kb can2 0x4000 6400 - 0x4000 67ff 1 kb can1 0x4000 6000 - 0x4000 63ff 1 kb crs 0x4000 5c00- 0x4000 5fff 1 kb i2c3 0x4000 5800 - 0x4000 5bff 1 kb i2c2 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 5000 - 0x4000 53ff 1 kb uart5 0x4000 4c00 - 0x4000 4fff 1 kb uart4 table 18. STM32L496XX memory map and peripheral register boundary addresses (1) (continued) bus boundary address size (bytes) peripheral
memory mapping STM32L496XX 108/263 docid029173 rev 2 apb1 0x4000 4800 - 0x4000 4bff 1 kb usart3 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 4000 - 0x4000 43ff 1 kb reserved 0x4000 3c00 - 0x4000 3fff 1 kb spi3 0x4000 3800 - 0x4000 3bff 1 kb spi2 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb lcd 0x4000 1800 - 0x4000 23ff 3 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0c00- 0x4000 0fff 1 kb tim5 0x4000 0800 - 0x4000 0bff 1 kb tim4 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb tim2 1. the gray color is used for reserved boundary addresses. table 18. STM32L496XX memory map and peripheral register boundary addresses (1) (continued) bus boundary address size (bytes) peripheral
docid029173 rev 2 109/263 STM32L496XX electrical characteristics 236 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 16 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 17 . figure 16. pin loading conditi ons figure 17. pin input voltage 069 0&8slq & s) 069 0&8slq 9 ,1
electrical characteristics STM32L496XX 110/263 docid029173 rev 2 6.1.6 power supply scheme figure 18. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 9 '',2 9 '' 069 /hyhovkliwhu ,2 orjlf .huqhoorjlf &38'ljlwdo 0hprulhv %dfnxsflufxlwu\ /6(57& %dfnxsuhjlvwhuv ,1 287 5hjxodwru *3,2v 9 ,1 287 *3,2v q[q) [?) p[q) /hyhovkliwhu ,2 orjlf ?) p[9 '',2 p[9 66 q[9 66 q[9 '' 9 %$7 9 &25( 3rzhuvzlwfk 9 '',2 9 '',2 $'&v '$&v 23$03v &203v 95() 9 5() 9 5() 9 ''$ q) ?) 9 ''$ 9 66$ 069 9 '',2 9 '' /hyhovkliwhu ,2 orjlf <?voo}p] ~whu]p]?o ?du}?]? l?]?]??? ~>^uzdu l??p]???? /e khd zpo?}? *3,2v x??t?xs ,1 khd *3,2v q[q) [?) p[q) /hyhovkliwhu ,2 orjlf ?) p[9'',2 p[966 q[966 q[9'' 9%$7 9 &25( w}??]?z 9 '',2 9 '',2 $'&v '$&v 23$03v &203v 95() 9 5() 9 5() 9 ''$ v& ?) 9''$ 966$ 9 5() v& ?) 06y9 9 '',2 9 '' /hyhovkliwhu ,2 orjlf <?voo}p] ~whu]p]?o ?du}?]? l?]?]??? ~>^uzdu l??p]???? /e khd zpo?}? *3,2v x??t?xs ,1 khd *3,2v q[q) [?) p[q) /hyhovkliwhu ,2 orjlf ?) p[9'',2 p[966 q[966 q[9'' 9%$7 9 &25( w}??]?z 9 '',2 9 '',2 $'&v '$&v 23$03v &203v 95()%8) 9 5() 9 5() 9 ''$ v& ?) 9''$ 966$ 9 5() v& ?) x?tx??s [9''
docid029173 rev 2 111/263 STM32L496XX electrical characteristics 236 6.1.7 current consumption measurement figure 19. current consumption measurement scheme with and without external smps power supply the i dd_all parameters given in table 26 to table 48 represent the total mcu consumption including the current supplying v dd , v ddio2 , v dda , v ddusb and v bat . 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 19: voltage characteristics , table 20: current characteristics and table 21: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect de vice reliability. exposure to maximum rating conditions for extended periods may affect device reliability. device mission profile (application conditions) is compliant with jedec jesd47 qualificat ion standard, extended mission profiles are available on demand. 06y9 , ''b86% 9 ''86% , ''b9%$7 9 %$7 , '' 9 '' 9 '',2 , ''$ 9 ''$ , ''b86% 9 ''86% , ''b9%$7 9 %$7 , '' 9 '' 9 '',2 , ''$ 9 ''$ 9 '' 6036
electrical characteristics STM32L496XX 112/263 docid029173 rev 2 table 19. voltage characteristics (1) symbol ratings min max unit v ddx - v ss external main supply voltage (including v dd , v dda , v ddio2 , v ddusb , v lcd , v bat ) -0.3 4.0 v v dd12 - v ss external smps supply voltage range 1 -0.3 1.32 range 2 -0.3 v in (2) input voltage on ft_xxx pins v ss -0.3 min (v dd , v dda , v ddio2 , v ddusb , v lcd ) + 4.0 (3)(4) input voltage on tt_xx pins v ss -0.3 4.0 input voltage on boot0 pin v ss 9.0 input voltage on any other pins v ss -0.3 4.0 | ? v ddx | variations between different v ddx power pins of the same domain -50mv |v ssx -v ss | variations between all the different ground pins (5) -50mv 1. all main power (v dd , v dda , v ddio2 , v ddusb , v lcd , v bat ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. v in maximum must always be respected. refer to table 20: current characteristics for the maximum allowed injected current values. 3. this formula has to be applied only on the power supplies related to the io stru cture described in the pin definition table. 4. to sustain a voltage higher than 4 v the inter nal pull-up/pull-dow n resistors must be disabled. 5. include vref- pin. table 20. current characteristics symbol ratings max unit iv dd total current into sum of all v dd power lines (source) (1) (2) 150 ma iv ss total current out of sum of all v ss ground lines (sink) (1) 150 iv dd(pin) maximum current into each v dd power pin (source) (1)(2) 100 iv ss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io(pin) output current sunk by any i/o and control pin except ft_f 20 output current sunk by any ft_f pin 20 output current sourced by any i/o and control pin 20 i io(pin) total output current sunk by sum of all i/os and control pins (3) 100 total output current sourced by sum of all i/os and control pins (3) 100 i inj(pin) (4) injected current on ft_xxx, tt_xx, rst and b pins, except pa4, pa5 -5/+0 (5) injected current on pa4, pa5 -5/0 |i inj(pin) | total injected current (sum of all i/os and control pins) (6) 25 1. all main power (v dd , v dda , v ddio2 , v ddusb , v lcd , v bat ) and ground (v ss , v ssa ) pins must always be connected to the external power supplies, in the permitted range. 2. valid also for v dd12 on smps package
docid029173 rev 2 113/263 STM32L496XX electrical characteristics 236 6.3 operating conditions 6.3.1 general operating conditions 3. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 4. positive injection (when v in > v ddiox ) is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer also to table 19: voltage characteristics for the minimum allowed input voltage values. 6. when several inputs are submitted to a current injection, the maximum | i inj(pin) | is the absolute sum of the negative injected currents (instantaneous values). table 21. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 22. general operating conditions symbol parameter co nditions min max unit f hclk internal ahb clock frequency - 0 80 mhz f pclk1 internal apb1 clock frequency - 0 80 f pclk2 internal apb2 clock frequency - 0 80 v dd standard operating voltage - 1.71 (1) 3.6 v v dd12 standard operating voltage full frequency range 1.08 1.32 up to 26mhz 1.05 v ddio2 pg[15:2] i/os supply voltage at least one i/o in pg[15:2] used 1.08 3.6 v pg[15:2] not used 0 3.6 v dda analog supply voltage adc or comp used 1.62 3.6 v dac or opamp used 1.8 vrefbuf used 2.4 adc, dac, opamp, comp, vrefbuf not used 0
electrical characteristics STM32L496XX 114/263 docid029173 rev 2 v bat backup operating voltage - 1.55 3.6 v v ddusb usb supply voltage usb used 3.0 3.6 usb not used 0 3.6 v in i/o input voltage tt_xx i/o -0.3 v ddiox +0.3 boot0 0 9 all i/o except boot0 and tt_xx -0.3 min(min(v dd , v dda , v ddio2 , v ddusb , v lcd )+3.6 v, 5.5 v) (2)(3) p d power dissipation at t a = 85 c for suffix 6 (4) lqfp144 - - 625 mw lqfp100 - - 476 lqfp64 - - 444 ufbga169 - 385 ufbga132 - - 364 wlcsp100 - - 559 p d power dissipation at t a = 125 c for suffix 3 (4) lqfp144 - - 156 mw lqfp100 - - 119 lqfp64 - - 111 ufbga169 - 96 ufbga132 - - 91 wlcsp100 - - 140 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low-power dissipation (5) ?40 105 ambient temperature for the suffix 3 version maximum power dissipation ?40 125 low-power dissipation (5) ?40 130 t j junction temperature range suffix 6 version ?40 105 c suffix 3 version ?40 130 1. when reset is released func tionality is guaranteed down to v bor0 min. 2. this formula has to be applied only on t he power supplies related to the io struct ure described by the pin definition table. maximum i/o input voltage is the smallest value between min(v dd , v dda , v ddio2 , v ddusb , v lcd )+3.6 v and 5.5v. 3. for operation with voltage higher than min (v dd , v dda , v ddio2 , v ddusb , v lcd ) +0.3 v, the internal pull-up and pull-down resistors must be disabled. 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section 7.7: thermal characteristics ). 5. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.7: thermal characteristics ). table 22. general operating conditions (continued) symbol parameter co nditions min max unit
docid029173 rev 2 115/263 STM32L496XX electrical characteristics 236 6.3.2 operating conditions at power-up / power-down the parameters given in table 23 are derived from tests performed under the ambient temperature condition summarized in table 22 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 24 are derived from tests performed under the ambient temperature conditions summarized in table 22: general operating conditions . table 23. operating conditions at power-up / power-down (1) 1. at power up, the v dd12 voltage should not be forced externally symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 10 t vdda v dda rise time rate - 0 s/v v dda fall time rate 10 t vddusb v ddusb rise time rate - 0 s/v v ddusb fall time rate 10 t vddio2 v ddio2 rise time rate - 0 s/v v ddio2 fall time rate 10 table 24. embedded reset and power control block characteristics symbol parameter conditions (1) min typ max unit t rsttempo (2) reset temporization after bor0 is detected v dd rising - 250 400 s v bor0 (2) brown-out reset threshold 0 rising edge 1.62 1.66 1.7 v falling edge 1.6 1.64 1.69 v bor1 brown-out reset threshold 1 rising edge 2.06 2.1 2.14 v falling edge 1.96 2 2.04 v bor2 brown-out reset threshold 2 rising edge 2.26 2.31 2.35 v falling edge 2.16 2.20 2.24 v bor3 brown-out reset threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v bor4 brown-out reset threshold 4 rising edge 2.85 2.90 2.95 v falling edge 2.76 2.81 2.86 v pvd0 programmable voltage detector threshold 0 rising edge 2.1 2.15 2.19 v falling edge 2 2.05 2.1 v pvd1 pvd threshold 1 rising edge 2.26 2.31 2.36 v falling edge 2.15 2.20 2.25
electrical characteristics STM32L496XX 116/263 docid029173 rev 2 v pvd2 pvd threshold 2 rising edge 2.41 2.46 2.51 v falling edge 2.31 2.36 2.41 v pvd3 pvd threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v pvd4 pvd threshold 4 rising edge 2.69 2.74 2.79 v falling edge 2.59 2.64 2.69 v pvd5 pvd threshold 5 rising edge 2.85 2.91 2.96 v falling edge 2.75 2.81 2.86 v pvd6 pvd threshold 6 rising edge 2.92 2.98 3.04 v falling edge 2.84 2.90 2.96 v hyst_borh0 hysteresis voltage of borh0 hysteresis in continuous mode -20- mv hysteresis in other mode -30- v hyst_bor_pvd hysteresis voltage of borh (except borh0) and pvd --100-mv i dd (bor_pvd) (2) bor (3) (except bor0) and pvd consumption from v dd --1.11.6a v pvm3 v dda peripheral voltage monitoring rising edge 1.61 1.65 1.69 v falling edge 1.6 1.64 1.68 v pvm4 v dda peripheral voltage monitoring rising edge 1.78 1.82 1.86 v falling edge 1.77 1.81 1.85 v hyst_pvm3 pvm3 hysteresis - - 10 - mv v hyst_pvm4 pvm4 hysteresis - - 10 - mv i dd (pvm1/pvm2) (2) pvm1 and pvm2 consumption from v dd --0.2-a i dd (pvm3/pvm4) (2) pvm3 and pvm4 consumption from v dd --2-a 1. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. 2. guaranteed by design. 3. bor0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. table 24. embedded reset and power control block characteristics (continued) symbol parameter conditions (1) min typ max unit
docid029173 rev 2 117/263 STM32L496XX electrical characteristics 236 6.3.4 embedded voltage reference the parameters given in table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . table 25. embedded internal voltage reference symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +130 c 1.182 1.212 1.232 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -4 (2) --s t start_vrefint start time of reference voltage buffer when adc is enable --812 (2) s i dd (v refintbuf ) v refint buffer consumption from v dd when converted by adc - - 12.5 20 (2) a ? v refint internal reference voltage spread over the temperature range v dd = 3 v - 5 7.5 (2) mv t coeff average temperature coefficient ?40c < t a < +130c - 30 50 (2) ppm/c a coeff long term stability 1000 hours, t = 25c - 300 1000 (2) ppm v ddcoeff average voltage coefficient 3.0 v < v dd < 3.6 v - 250 1200 (2) ppm/v v refint_div1 1/4 reference voltage - 24 25 26 % v refint v refint_div2 1/2 reference voltage 49 50 51 v refint_div3 3/4 reference voltage 74 75 76 1. the shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design.
electrical characteristics STM32L496XX 118/263 docid029173 rev 2 figure 20. v refint versus temperature 06y9 9 ?& 0hdq 0lq 0d[
docid029173 rev 2 119/263 STM32L496XX electrical characteristics 236 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 19: current consumption measurement scheme with and without external smps power supply . typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted with the minimum wait states number, depending on the f hclk frequency (refer to the table ?number of wait states according to cpu clock (hclk) frequency? available in the rm0351 reference manual). ? when the peripherals are enabled f pclk = f hclk the parameters given in table 26 to table 49 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 22: general operating conditions .
electrical characteristics STM32L496XX 120/263 docid029173 rev 2 table 26. current consumption in run and low-power run modes, code with data processing running from flash, art enable (cache on prefetch off) symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.65 2.69 2.82 3.05 3.51 2.9 3.0 3.3 3.8 4.7 ma 16 mhz 1.68 1.72 1.85 2.07 2.53 1.9 2.0 2.2 2.7 3.7 8 mhz 0.91 0.94 1.07 1.29 1.74 1.0 1.1 1.4 1.8 2.8 4 mhz 0.52 0.55 0.68 0.9 1.35 0.6 0.7 0.9 1.4 2.4 2 mhz 0.33 0.36 0.48 0.7 1.15 0.4 0.5 0.7 1.2 2.2 1 mhz 0.23 0.26 0.38 0.6 1.06 0.3 0.4 0.6 1.1 2.0 100 khz 0.14 0.17 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 range 1 80 mhz 9.44 9.5 9.67 9.93 10.4 10.3 10.4 10.7 11.3 12.4 72 mhz 8.52 8.59 8.75 9.01 9.53 9.3 9.4 9.7 10.3 11.4 64 mhz 7.61 7.67 7.83 8.09 8.61 8.3 8.4 8.7 9.3 10.4 48 mhz 5.72 5.78 5.94 6.2 6.72 6.3 6.4 6.7 7.3 8.4 32 mhz 3.87 3.92 4.07 4.33 4.84 4.2 4.4 4.7 5.2 6.3 24 mhz 2.94 2.99 3.14 3.39 3.9 3.2 3.4 3.6 4.2 5.3 16 mhz 2.01 2.06 2.2 2.45 2.95 2.2 2.3 2.6 3.2 4.2 i dd_all (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable 2 mhz 274 307 444 678 1150 318 425 656 1167 2197 a 1 mhz 158 195 328 564 1040 195 309 558 1047 2084 400 khz 88.2 123 256 490 969 116 232 485 973 2012 100 khz 63 90.6 223 457 934 79 195 447 942 1975 1. guaranteed by characterization results, unless otherwise specified.
STM32L496XX electrical characteristics docid029173 rev 2 121/263 table 27. current consumption in run modes, co de with data processing running from flash, (art enable cache on prefetch off) and power supplied (by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit -f hclk 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable 80 mhz 3.39 3.42 3.48 3.57 3.74 ma 72 mhz 3.06 3.09 3.15 3.24 3.43 64 mhz 2.74 2.76 2.81 2.91 3.10 48 mhz 2.06 2.08 2.14 2.23 2.42 32 mhz 1.39 1.41 1.46 1.56 1.74 24 mhz 1.06 1.07 1.13 1.22 1.40 16 mhz 0.72 0.74 0.79 0.88 1.06 8 mhz 0.39 0.41 0.46 0.56 0.75 4 mhz 0.22 0.24 0.29 0.39 0.58 2 mhz 0.14 0.16 0.21 0.30 0.50 1 mhz 0.10 0.11 0.16 0.26 0.46 100 khz 0.06 0.07 0.13 0.22 0.42 1. all values are obtained by calculation ba sed on measurements done without smps and us ing following parameters: smps input = 3 .3 v, smps efficiency = 85%, v dd12 = 1.10 v
electrical characteristics STM32L496XX 122/263 docid029173 rev 2 table 28. current consumption in run and low-power run modes, code with data processing running from flash, art disable symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 3.1 3.14 3.28 3.51 3.98 3.5 3.6 3.8 4.3 5.3 ma 16 mhz 2.19 2.23 2.36 2.59 3.05 2.5 2.6 2.8 3.3 4.3 8 mhz 1.22 1.26 1.39 1.61 2.07 1.4 1.5 1.7 2.2 3.2 4 mhz 0.69 0.73 0.85 1.08 1.53 0.8 0.9 1.1 1.6 2.6 2 mhz 0.41 0.44 0.57 0.79 1.24 0.5 0.6 0.8 1.3 2.3 1 mhz 0.27 0.3 0.43 0.65 1.1 0.3 0.4 0.6 1.1 2.1 100 khz 0.14 0.18 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 range 1 80 mhz 10 10.1 10.3 10.5 11.1 11.1 11.2 11.6 12.2 13.31 72 mhz 9.02 9.1 9.29 9.59 10.1 10 10.1 10.5 11.0 12.2 64 mhz 8.94 9.02 9.2 9.48 10 9.9 10.1 10.4 11.0 12.1 48 mhz 7.51 7.59 7.77 8.05 8.59 8.4 8.6 8.9 9.5 10.6 32 mhz 5.38 5.45 5.62 5.88 6.41 6.0 6.2 6.5 7.0 8.2 24 mhz 4.07 4.12 4.28 4.54 5.06 4.5 4.7 5.0 5.5 6.6 16 mhz 2.86 2.92 3.07 3.33 3.84 3.2 3.3 3.6 4.2 5.3 i dd_all (lprun) supply current in low-power run f hclk = f msi all peripherals disable 2 mhz 378 412 549 782 1260 436 538 761 1287 2317 a 1 mhz 213 246 381 618 1100 255 367 609. 1105 2138 400 khz 101 144 277 514 989 141 256 507 995 2033 100 khz 62 95.8 228 463 939 85 201 454 947 1982 1. guaranteed by characterization results, unless otherwise specified.
STM32L496XX electrical characteristics docid029173 rev 2 123/263 table 29. current consumption in run modes, co de with data processing running from flash, art disable and power supplied by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ uni t -f hclk 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable 80 mhz 3.59 3.63 3.70 3.77 3.99 ma 72 mhz 3.24 3.27 3.34 3.45 3.63 64 mhz 3.21 3.24 3.31 3.41 3.59 48 mhz 2.70 2.73 2.79 2.89 3.09 32 mhz 1.93 1.96 2.02 2.11 2.30 24 mhz 1.46 1.48 1.54 1.63 1.82 16 mhz 1.03 1.05 1.10 1.20 1.38 8 mhz 0.53 0.54 0.60 0.69 0.89 4 mhz 0.30 0.31 0.37 0.47 0.66 2 mhz 0.18 0.19 0.25 0.34 0.53 1 mhz 0.12 0.13 0.19 0.28 0.47 100 khz 0.06 0.08 0.13 0.22 0.42 1. all values are obtained by calculation ba sed on measurements done without smps and us ing following parameters: smps input = 3 .3 v, smps efficiency = 85%, v dd12 = 1.10 v
electrical characteristics STM32L496XX 124/263 docid029173 rev 2 table 30. current consumption in run and low-power run modes, code with data processing running from sram1 symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.72 2.76 2.89 3.12 3.58 3.0 3.1 3.4 3.8 4.8 ma 16 mhz 1.73 1.76 1.89 2.12 2.58 1.9 2.0 2.3 2.7 3.7 8 mhz 0.93 0.96 1.09 1.31 1.77 1.0 1.1 1.42 1.8 2.8 4 mhz 0.53 0.57 0.69 0.91 1.36 0.6 0.7 0.9 1.4 2.4 2 mhz 0.33 0.36 0.49 0.71 1.16 0.4 0.5 0.7 1.2 2.2 1 mhz 0.23 0.26 0.39 0.61 1.06 0.2 0.4 0.6 1.1 2.1 100 khz 0.14 0.17 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 range 1 80 mhz 9.71 9.78 9.95 10.2 10.8 10.6 10.7 11.1 11.6 12.7 72 mhz 8.77 8.84 9 9.27 9.8 9.6 9.7 10.0 10.6 11.7 64 mhz7.827.898.058.328.84 8.5 8.7 9.0 9.5 10.6 48 mhz 5.87 5.93 6.1 6.36 6.88 6.4 6.6 6.9 7.4 8.5 32 mhz 3.97 4.03 4.18 4.44 4.95 4.4 4.5 4.8 5.3 6.4 24 mhz 3.02 3.07 3.22 3.47 3.99 3.3 3.5 3.7 4.3 5.4 16 mhz 2.07 2.11 2.26 2.51 3.02 2.3 2.4 2.7 3.2 4.3 i dd_all (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable flash in power-down 2 mhz 258 296 430 665 1140 295 402 634 1154 2180 a 1 mhz 136 180 314 550 1020 170 283 530 1034 2065 400 khz 78.5 109 241 475 951 90 206 458 958 1991 100 khz 37.4 78.1 208 440 918 53 171 429 925 1957 1. guaranteed by characterization resu lts, unless otherwise specified.
STM32L496XX electrical characteristics docid029173 rev 2 125/263 table 31. current consumption in run, code with data processing running from sram1 and power supplied by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit -f hclk 25 c 55 c 85 c 105 c 125 c i dd_all (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable 80 mhz 3.49 3.52 3.58 3.67 3.88 ma 72 mhz 3.15 3.18 3.24 3.33 3.52 64 mhz 2.81 2.84 2.89 2.99 3.18 48 mhz 2.11 2.13 2.19 2.29 2.47 32 mhz 1.43 1.45 1.50 1.60 1.78 24 mhz 1.09 1.10 1.16 1.25 1.43 16 mhz 0.74 0.76 0.81 0.90 1.09 8 mhz 0.40 0.41 0.47 0.57 0.76 4 mhz 0.23 0.25 0.30 0.39 0.59 2 mhz 0.14 0.16 0.21 0.31 0.50 1 mhz 0.10 0.11 0.17 0.26 0.46 100 khz 0.06 0.07 0.13 0.22 0.42 1. all values are obtained by calculati on based on measurements done without smps and using following parameters: smps input = 3 .3 v, smps efficiency = 85%, v dd12 = 1.10 v
electrical characteristics STM32L496XX 126/263 docid029173 rev 2 table 32. typical current consumption in run and low-power run modes, with different codes running from flash, art enable (cache on prefetch off) symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.65 ma 102 a/mhz coremark 2.97 114 dhrystone 2.1 3.1 119 fibonacci 2.9 112 while(1) 2.43 93 range 1 f hclk = 80 mhz reduced code (1) 9.44 ma 118 a/mhz coremark 10.6 133 dhrystone 2.1 10.9 136 fibonacci 10.3 129 while(1) 8.66 108 i dd_all (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 274 a 137 a/mhz coremark 307 154 dhrystone 2.1 308 154 fibonacci 273 137 while(1) 258 129 1. reduced code used for characterization results provided in table 26 , table 28 , table 30 . table 33. typical current consumption in run, with different codes running from flash, art enable (cache on prefetch off) and power supplied (by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable f hclk = 26 mhz reduced code (2) 1.14 ma 44 a/mhz coremark 1.28 49 dhrystone 2.1 1.34 51 fibonacci 1.25 48 while(1) 1.05 40 f hclk = 80 mhz reduced code (2) 3.39 42 coremark 3.81 48 dhrystone 2.1 3.92 49 fibonacci 3.70 46 while(1) 3.11 39 1. all values are obtained by calculation based on measur ements done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.10 v 2. reduced code used for characte rization results provided in table 26 , table 28 , table 30 .
docid029173 rev 2 127/263 STM32L496XX electrical characteristics 236 table 34. typical current consumption in run, with different codes running from flash, art enable (cache on prefetch off) and power supplied (by external smps (v dd12 = 1.05 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable f hclk = 26 mhz reduced code (2) 1.04 ma 40 a/mhz coremark 1.17 45 dhrystone 2.1 1.22 47 fibonacci 1.14 44 while(1) 0.96 37 1. all values are obtained by calculation based on measur ements done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.05 v 2. reduced code used for characte rization results provided in table 26 , table 28 , table 30 . table 35. typical current consumption in run and low-power run modes, with different codes running from flash, art disable symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 3.1 ma 119 a/mhz coremark 2.85 110 dhrystone 2.1 2.86 110 fibonacci 2.63 101 while(1) 2.42 93.1 range 1 f hclk = 80 mhz reduced code (1) 10 ma 125 a/mhz coremark 9.33 117 dhrystone 2.1 9.4 118 fibonacci 8.66 108 while(1) 8.61 108 i dd_all (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 378 a 189 a/mhz coremark 412 206 dhrystone 2.1 418 209 fibonacci 392 196 while(1) 266 133 1. reduced code used for characterization results provided in table 26 , table 28 , table 30 .
electrical characteristics STM32L496XX 128/263 docid029173 rev 2 table 36. typical current consumption in ru n modes, with different codesrunning from flash, art disable and power supplied by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable f hclk = 26 mhz reduced code (2) 1.34 ma 51 a/mhz coremark 1.23 47 dhrystone 2.1 1.23 47 fibonacci 1.13 44 while(1) 1.04 40 f hclk = 80 mhz reduced code (1) 3.59 45 coremark 3.35 42 dhrystone 2.1 3.38 42 fibonacci 3.11 39 while(1) 3.10 39 1. all values are obtained by calculation based on measurem ents done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.10 v 2. reduced code used for characterization results provided in table 26 , table 28 , table 30 . table 37. typical current consumption in ru n modes, with different codesrunning from flash, art disable and power supplied by external smps (v dd12 = 1.05 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals f hclk = 26 mhz reduced code (2) 1.22 ma 47 a/mhz coremark 1.12 43 dhrystone 2.1 1.12 43 fibonacci 1.03 40 while(1) 0.95 37 1. all values are obtained by calculation based on measurem ents done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.05 v 2. reduced code used for characterization results provided in table 26 , table 28 , table 30 .
docid029173 rev 2 129/263 STM32L496XX electrical characteristics 236 table 38. typical current consumption in run and low-power run modes, with different codes running from sram1 symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.72 ma 105 a/mhz coremark 2.72 105 dhrystone 2.1 2.65 102 fibonacci 2.47 95 while(1) 2.37 91 range 1 f hclk = 80 mhz reduced code (1) 9.71 ma 121 a/mhz coremark 9.7 121 dhrystone 2.1 9.48 119 fibonacci 8.79 110 while(1) 8.45 106 i dd_all (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 258 a 129 a/mhz coremark 268 134 dhrystone 2.1 240 120 fibonacci 230 115 while(1) 255 128 1. reduced code used for characterization results provided in table 26 , table 28 , table 30 . table 39. typical current consumption in run, with different codesrunning from sram1 and power supplied by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable f hclk = 26 mhz reduced code (2) 1.17 ma 45 a/mhz coremark 1.17 45 dhrystone 2.1 1.14 44 fibonacci 1.07 41 while(1) 1.02 39 f hclk = 80 mhz reduced code (1) 3.49 44 coremark 3.49 44 dhrystone 2.1 3.41 43 fibonacci 3.16 39 while(1) 3.04 38 1. all values are obtained by calculation based on measurem ents done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.10 v 2. reduced code used for characterization results provided in table 26 , table 28 , table 30 .
electrical characteristics STM32L496XX 130/263 docid029173 rev 2 table 40. typical current consumption in run, with different codesrunning from sram1 and power supplied by external smps (v dd12 = 1.05 v) symbol parameter conditions (1) typ unit typ unit - voltage scaling code 25 c 25 c i dd_all (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable f hclk = 26 mhz reduced code (2) 1.07 ma 41 a/mhz coremark 1.07 41 dhrystone 2.1 1.04 40 fibonacci 0.97 37 while(1) 0.93 36 1. all values are obtained by calculation based on measurem ents done without smps and using following parameters: smps input = 3.3 v, smps efficiency = 85%, v dd12 = 1.05 v 2. reduced code used for characterization results provided in table 26 , table 28 , table 30 .
STM32L496XX electrical characteristics docid029173 rev 2 131/263 table 41. current consumption in sleep and low-power sleep modes, flash on symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (sleep) supply current in sleep mode, f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 0.79 0.82 0.95 1.17 1.63 0.9 1.0 1.2 1.7 2.7 ma 16 mhz 0.54 0.57 0.7 0.92 1.38 0.6 0.7 1.0 1.4 2.4 8 mhz 0.33 0.37 0.49 0.71 1.17 0.4 0.5 0.7 1.2 2.2 4 mhz 0.23 0.26 0.39 0.61 1.06 0.3 0.4 0.6 1.1 2.1 2 mhz 0.18 0.21 0.34 0.56 1.01 0.2 0.3 0.5 1.0 1.0 1 mhz 0.16 0.19 0.31 0.53 0.99 0.2 0.3 0.5 1.0 1.0 100 khz 0.13 0.17 0.29 0.51 0.96 0.1 0.3 0.5 1.0 1.9 range 1 80 mhz 2.57 2.62 2.76 3.01 3.53 2.8 2.9 3.2 3.8 4.9 72 mhz 2.34 2.38 2.53 2.78 3.29 2.6 2.7 3.0 3.5 4.6 64 mhz 2.1 2.15 2.29 2.54 3.05 2.3 2.4 2.7 3.3 4.4 48 mhz 1.58 1.63 1.78 2.03 2.54 1.8 1.9 2.2 2.7 3.8 32 mhz 1.11 1.15 1.3 1.54 2.05 1.2 1.4 1.7 2.2 3.3 24 mhz 0.87 0.91 1.06 1.3 1.81 1.0 1.1 1.4 1.9 3.0 16 mhz 0.63 0.67 0.82 1.06 1.56 0.7 0.8 1.1 1.6 2.7 i dd_all (lpsleep) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 103 140 270 506 985 130 247 500 990 2025 a 1 mhz 74.2 111 245 476 955 100 215 467 963 1999 400 khz 60 89.8 224 457 937 79 194 444 941 1975 100 khz 53.7 84.1 216 448 928 70 185 434 933 1967 1. guaranteed by characterization re sults, unless otherwise specified.
electrical characteristics STM32L496XX 132/263 docid029173 rev 2 table 42. current consumption in sleep, flash on and power supplied by external smps (v dd12 = 1.10 v) symbol parameter conditions (1) typ unit -f hclk 25 c 55 c 85 c 105 c 125 c i dd_all (sleep) supply current in sleep mode, f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable 80 mhz 0.92 0.94 0.99 1.08 1.27 ma 72 mhz 0.84 0.86 0.91 1.00 1.18 64 mhz 0.75 0.77 0.82 0.91 1.10 48 mhz 0.57 0.59 0.64 0.73 0.91 32 mhz 0.40 0.41 0.47 0.55 0.74 24 mhz 0.31 0.33 0.38 0.47 0.65 16 mhz 0.23 0.24 0.29 0.38 0.56 8 mhz 0.14 0.16 0.21 0.31 0.50 4 mhz 0.10 0.11 0.17 0.26 0.46 2 mhz 0.08 0.09 0.15 0.24 0.44 1 mhz 0.07 0.08 0.13 0.23 0.43 100 khz 0.06 0.07 0.13 0.22 0.41 1. all values are obtained by calculation based on measurements done without smps and us ing following parameters: smps input = 3 .3 v, smps efficiency = 85%, v dd12 = 1.10 v
STM32L496XX electrical characteristics docid029173 rev 2 133/263 table 43. current consumption in low-pow er sleep modes, flash in power-down symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (lpsleep) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 92.7 124 258 487 968 105 224 474 969 2006 a 1 mhz 63.5 97.5 223 460 951 75 193 446 942 1975 400 khz 42.6 75.6 207 443 947 54 171 426 923 1955 100 khz 31.2 67.6 199 437 905 44 162 420 916 1947 1. guaranteed by characterization results, unless otherwise specified. table 44. current consumption in stop 2 mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (stop 2) supply current in stop 2 mode, rtc disabled lcd disabled 1.8 v 2.57 6.86 25.2 60.1 135 5.3 16.4 64 154.6 353 a 2.4 v 2.62 6.91 25.5 60.6 137 5.3 16.6 64.9 156.7 359 3 v 2.69 6.93 25.7 61.5 140 5.4 16.9 66.3 159.7 366 3.6 v 2.7 7.08 26.3 62.9 143 5.4 17.4 67.8 163.8 375 lcd enabled (2) clocked by lsi 1.8 v 2.92 7.19 25.3 59.5 135 5.3 16.6 64.8 155.6 355 2.4 v 2.99 7.3 25.6 60.3 136 5.5 16.8 65.9 157.9 360 3 v 3.04 7.41 26.1 61.7 140 5.9 17.3 67.1 160.8 367 3.6 v 3.31 7.7 26.8 63.2 143 6.2 17.9 69.1 165.0 376
electrical characteristics STM32L496XX 134/263 docid029173 rev 2 i dd_all (stop 2 with rtc) supply current in stop 2 mode, rtc enabled rtc clocked by lsi, lcd disabled 1.8 v 2.97 7.46 26.2 61.4 139 6.1 17.2 64.8 155.4 354 a 2.4 v 3.09 7.61 26.5 62.3 140 6.2 17.5 65.7 157.6 360 3 v 3.15 7.81 27 63.5 144 6.5 17.9 67.2 160.6 367 3.6 v 3.4 8.05 27.7 65.2 147 7.1 18.7 69.0 164.9 376 rtc clocked by lsi, lcd enabled (3) 1.8 v 2.98 7.31 25.5 60 135 5.5 16.8 65.1 155.8 355 2.4 v 3.10 7.46 25.8 60.7 137 5.8 17.1 66.3 158.2 360 3 v 3.23 7.63 26.4 62.1 141 6.2 17.5 67.6 161.4 367 3.6 v 3.47 7.95 27.1 63.6 144 6.58 18.3 69.5 165.5 376 rtc clocked by lse bypassed at 32768hz,lcd disabled 1.8 v 2.93 7.52 26.2 61.4 139 - - - - - 2.4 v 3.1 7.68 26.6 62.1 140 - - - - - 3 v 3.3 7.81 26.9 63.4 143 - - - - - 3.6 v 3.48 8.07 27.6 65.0 146 - - - - - rtc clocked by lse quartz (3) in low drive mode, lcd disabled 1.8 v 2.86 7.48 26.2 61.4 - - - - - - 2.4 v 3.01 7.56 26.5 62.2 - - - - - - 3 v 3.18 7.65 26.8 63.5 - - - - - - 3.6 v 3.31 7.94 27.5 65.1 - - - - - - table 44. current consumption in stop 2 mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c
STM32L496XX electrical characteristics docid029173 rev 2 135/263 i dd_all (wake up from stop2) supply current during wakeup from stop 2 mode wakeup clock is msi = 48 mhz, voltage range 1. see (4) . 3 v1.69--------- ma wakeup clock is msi = 4 mhz, voltage range 2. see (4) . 3 v1.35--------- wakeup clock is hsi16 = 16 mhz, voltage range 1. see (4) . 3 v 1.7 - - - - - - - - - 1. guaranteed by characterization re sults, unless otherwise specified. 2. lcd enabled with external voltage source. consumption from vlcd excluded. refer to lcd cont roller characteristics for i vlcd. 3. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 51: low-power mode wakeup timings . table 44. current consumption in stop 2 mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c
electrical characteristics STM32L496XX 136/263 docid029173 rev 2 table 45. current consumption in stop 1 mode symbol parameter conditions typ max (1) unit --v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (stop 1) supply current in stop 1 mode, rtc disabled - lcd disabled 1.8 v 11.2 30.7 107 243 523 25.4 79.6 287 651 1395 a 2.4 v 11.3 30.8 108 244 526 25.5 79.8 288 655 1403 3 v 11.6 31 108 245 530 25.9 80.5 290 659 1413 3.6 v 11.9 31.5 109 248 536 28.6 81.4 293 665 1428 - lcd enabled (2) clocked by lsi 1.8 v 11.7 29.7 102 234 504 27.1 81.1 288.5 653 1397 2.4 v 11.7 29.9 102 234 506 27.2 81.0 289 656 1405 3 v 12.1 29.9 103 234 508 27.4 81.6 291 660 1415 3.6 v 12.2 30.1 103 235 510 28.8 82.4 294 667 1429 i dd_all (stop 1 with rtc) supply current in stop 1 mode, rtc enabled rtc clocked by lsi lcd disabled 1.8 v 11.9 31.1 108 244 524 26.6 80.5 288 652 1396 a 2.4 v 12.1 31.4 109 245 528 26.7 80.9 289 656 1404 3 v 12.4 31.7 109 246 531 27.7 81.6 291 660 1415 3.6 v 12.6 32.3 110 249 537 28.9 82.8 295 667 1429 lcd enabled (2) 1.8 v 11.7 30.1 104 235 510 26.7 80.6 288 653 1397 2.4 v 11.8 30.2 104 238 511 26.7 81.1 290 657 1406 3 v 11.8 30.5 104 238 515 28.3 81.8 2912 661 1416 3.6 v 12.3 31 105 239 519 30.9 83.0 295 668 1430 rtc clocked by lse bypassed at 32768 hz lcd disabled 1.8 v 11.6 31.3 108 244 524 - - - - - 2.4 v 11.8 31.6 109 245 527 - - - - - 3 v 12.3 31.9 109 246 531 - - - - - 3.6 v 12.7 32.5 111 249 537 - - - - - rtc clocked by lse quartz (3) in low drive mode lcd disabled 1.8 v 11.5 31.1 108 244 - - - - - - 2.4 v 11.5 31.4 109 246 - - - - - - 3 v 12 31.7 109 247 - - - - - - 3.6 v 12.4 32.3 110 250 - - - - - -
STM32L496XX electrical characteristics docid029173 rev 2 137/263 i dd_all (wakeup from stop1) supply current during wakeup from stop 1 wakeup clock msi = 48 mhz, voltage range 1. see (4) . 3 v0.99-- - - --- - - ma wakeup clock msi = 4 mhz, voltage range 2. see (4) . 3 v1.1-- - - --- - - wakeup clock hsi16 = 16 mhz, voltage range 1. see (4) . 3 v0.95-- - - --- - - 1. guaranteed by characterization re sults, unless otherwise specified. 2. lcd enabled with external voltage source. consumption from vlcd excluded. refer to lcd cont roller characteristics for i vlcd. 3. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 51: low-power mode wakeup timings . table 45. current consumption in stop 1 mode (continued) symbol parameter conditions typ max (1) unit --v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c table 46. current consumption in stop 0 mode symbol parameter conditions typ max (1) unit v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (stop 0) supply current in stop 0 mode, rtc disabled 1.8 v 127 153 244 404 734 148 218 471 905 1795 a 2.4 v 129 155 247 407 737 151 221 474 910 1803 3 v 131 156 249 409 741 154 224 478 915 1813 3.6 v 133 158 251 412 744 157 228 482 921 1822 (2) 1. guaranteed by characterization resu lts, unless otherwise specified. 2. guaranteed by test in production.
electrical characteristics STM32L496XX 138/263 docid029173 rev 2 table 47. current consumption in standby mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (standby) supply current in standby mode (backup registers retained), rtc disabled no independent watchdog 1.8 v 108 299 1343 3822 10353 227 899 4159 13059 36572 na 2.4 v 118 348 1562 4447 12012 252 1009 4846 15026 41366 3 v 133 404 1777 5071 13589 318 1211 6082 17245 46714 3.6 v 171 501 2115 5898 15539 435 1508 7230 19850 52888 (2) with independent watchdog 1.8 v 296 - - - - - - - - - 2.4 v 349 - - - - - - - - - 3 v 411 - - - - - - - - - 3.6 v 506 - - - - - - - - - i dd_all (standby with rtc) supply current in standby mode (backup registers retained), rtc enabled rtc clocked by lsi, no independent watchdog 1.8 v 377 581 1700 4270 11100 763 1422 5182 13585 36564 na 2.4 v 461 700 2020 5030 12900 942 1704 5992 15473 41383 3 v 559 843 2390 5990 15500 1166 2032 6938 17889 46728 3.6 v 689 1050 2920 7130 18100 1454 2511 7754 20714 53018 rtc clocked by lsi, with independent watchdog 1.8 v 422 - - - - - - - - - 2.4 v 518 - - - - - - - - - 3 v 560 - - - - - - - - - 3.6 v 780 - - - - - - - - -
STM32L496XX electrical characteristics docid029173 rev 2 139/263 i dd_all (standby with rtc) supply current in standby mode (backup registers retained), rtc enabled rtc clocked by lse bypassed at 32768hz 1.8 v 308 504 1683 4193 10783 - - - - - na 2.4 v 400 633 1963 4957 12583 - - - - - 3 v 508 779 2319 5925 15130 - - - - - 3.6 v 661 1009 2825 7027 17540 - - - - - rtc clocked by lse quartz (3) in low drive mode 1.8 v 426 624 1679 4244 10884 - - - - - 2.4 v 521 751 1985 4952 12619 - - - - - 3 v 643 914 2371 5931 15121 - - - - - 3.6 v 819 1162 2914 7019 17551 - - - - - i dd_all (sram2) (4) supply current to be added in standby mode when sram2 is retained - 1.8 v 371 1111 4297 10153 22747 806 2640 10537 24695 54376 na 2.4 v 372 1112 4328 10154 22888 809 2661 10545 24767 54505 3 v 374 1116 4403 10429 23711 811 2683 10553 24840 54634 3.6 v 378 1149 4545 10702 24361 814 2704 10561 24913 54763 i dd_all (wakeup from standby) supply current during wakeup from standby mode wakeup clock is msi = 4 mhz. see (5) . 3 v 1.4 - - - - - - - - - ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. guaranteed by test in production. 3. based on characterization done with a 32.768 khz crystal (mc306-g- 06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. the supply current in standby with sram2 mode is: i dd_all (standby) + i dd_all (sram2). the supply current in standby with rtc with sram2 mode is: i i dd_all (standby + rtc) + i dd_all (sram2). 5. wakeup with code execution from flash. average val ue given for a typical wakeup time as specified in table 51: low-power mode wakeup timings . table 47. current consumption in standby mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c
electrical characteristics STM32L496XX 140/263 docid029173 rev 2 table 48. current consumption in shutdown mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd_all (shutdown) supply current in shutdown mode (backup registers retained) rtc disabled - 1.8 v 24 161 983 3020 8970 85 556 3314 10498 31391 na 2.4 v 31 193 1150 3530 10300 111 648 3844 11897 35017 3 v 44 242 1400 4260 12500 154 780 4447 13473 39297 3.6 v 76 338 1790 5220 14700 236 1009 5354 15679 44571 i dd_all (shutdown with rtc) supply current in shutdown mode (backup registers retained) rtc enabled rtc clocked by lse bypassed at 32768 hz 1.8 v 225 363 1190 3230 9180 - - - - - na 2.4 v 314 478 1440 3820 10700 - - - - - 3 v 421 621 1790 4660 12900 - - - - - 3.6 v 561 831 2280 5730 15300 - - - - - rtc clocked by lse quartz (2) in low drive mode 1.8 v 341 472 1303 3459 - - - - - - 2.4 v 435 586 1572 4041 - - - - - - 3 v 553 732 1982 5145 - - - - - - 3.6 v 716 948 2520 6325 - - - - - - i dd_all (wakeup from shutdown) supply current during wakeup from shutdown mode wakeup clock is msi = 4 mhz. see (3) . 3 v 0.6 - - - - - - - - - ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 51: low-power mode wakeup timings .
STM32L496XX electrical characteristics docid029173 rev 2 141/263 table 49. current consumption in vbat mode symbol parameter conditions typ max (1) unit -v bat 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i vdd_vbat (v bat ) backup domain supply current rtc disabled 1.8 v 2 18 110 329 908 - - - - - na 2.4 v 2 20 125 371 1016 - - - - - 3 v 3 25 154 546 1965 - - - - - 3.6 v 10 57 324 963 2688 - - - - - rtc enabled and clocked by lse bypassed at 32768 hz 1.8 v 198 216 312 535 - - - - - - 2.4 v 280 300 411 664 - - - - - - 3 v 375 402 544 943 - - - - - - 3.6 v 488 529 791 1459 - - - - - - rtc enabled and clocked by lse quartz (2) 1.8 v 320 347 448 856 1432 - - - - - 2.4 v 405 436 550 921 1567 - - - - - 3 v 512 545 686 1128 2529 - - - - - 3.6 v 648 705 976 1588 3293 - - - - - 1. guaranteed by characterization results, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors.
electrical characteristics STM32L496XX 142/263 docid029173 rev 2 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge n erate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 70: i/o static characteristics . for the output pins, any external pull-down or ext ernal load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os co nfigured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: an y floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 50: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switch es, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: i sw v ddiox f sw c = where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
docid029173 rev 2 143/263 STM32L496XX electrical characteristics 236 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 50 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? the given value is calculated by measuring the difference of the current consumptions: ? when the peripheral is clocked on ? when the peripheral is clocked off ? ambient operating temperature and supply voltage conditions summarized in table 19: voltage characteristics ? the power consumption of the digital part of the on-chip peripherals is given in table 50 . the power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. table 50. peripheral current consumption peripheral range 1 range 2 low-power run and sleep unit ahb bus matrix (1) 4.44 3.75 4.00 a/mhz adc independent clock domain 0.40 0.08 0.30 adc ahb clock domain 5.55 4.63 5.00 crc 0.48 0.42 0.50 dma1 2.00 1.60 2.00 dma2 1.76 1.50 1.50 dma2d 24.33 20.21 24.50 flash 8.50 7.10 8.00 fmc 7.58 6.29 7.00 gpioa (2) 1.59 1.25 1.50 gpiob (2) 1.56 1.25 1.50 gpioc (2) 1.58 1.29 1.50 gpiod (2) 1.40 1.17 1.40 gpioe (2) 1.36 1.13 1.40 gpiof (2) 1.70 1.40 1.50 gpiog (2) 1.80 1.50 1.80 gpioh (2) 1.50 1.30 1.50 gpioi (2) 1.18 0.96 1.00 dcmi 1.6 1.3 1.2 otg_fs independent clock domain 23.20 na na otg_fs ahb clock domain 14.30 na na quadspi 6.84 5.67 6.50
electrical characteristics STM32L496XX 144/263 docid029173 rev 2 ahb rng independent clock domain 2.20 na na a/mhz rng ahb clock domain 0.51 na na sram1 2.80 2.29 2.50 sram2 1.20 1.00 1.00 tsc 1.50 1.17 1.00 all ahb peripherals 121.00 79.10 87.20 apb1 ahb to apb1 bridge (3) 0.90 0.70 0.90 a/mhz can1 3.68 3.04 3.50 dac1 3.20 2.70 3.00 i2c1 independent clock domain 3.80 3.20 3.30 i2c1 apb clock domain 1.00 0.79 1.00 i2c2 independent clock domain 3.41 2.83 3.00 i2c2 apb clock domain 0.98 0.79 1.00 i2c3 independent clock domain 2.89 2.38 2.50 i2c3 apb clock domain 0.98 0.83 1.00 i2c4 independent clock domain 3.41 2.83 3.00 i2c4 apb clock domain 0.98 0.79 1.00 lcd 1.03 0.80 1.03 lpuart1 independent clock domain 2.40 2.00 2.20 lpuart1 apb clock domain 0.98 0.83 0.80 lptim1 independent clock domain 3.10 2.54 2.54 lptim1 apb clock domain 0.88 0.75 0.90 lptim2 independent clock domain 2.86 2.42 2.25 lptim2 apb clock domain 0.90 0.67 0.75 opamp 0.29 0.20 0.30 pwr 0.80 0.63 0.60 spi2 1.78 1.50 1.50 spi3 1.76 1.50 1.50 swpmi1 independent clock domain 2.10 1.50 2.00 swpmi1 apb clock domain 1.00 0.79 0.75 table 50. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit
docid029173 rev 2 145/263 STM32L496XX electrical characteristics 236 apb1 tim2 5.85 4.88 5.70 a/mhz tim3 5.20 4.25 5.00 tim4 4.50 3.67 4.20 tim5 5.60 4.58 5.10 tim6 0.85 0.70 0.90 tim7 0.86 0.71 0.90 usart2 independent clock domain 4.06 3.40 4.00 usart2 apb clock domain 1.38 1.17 1.40 usart3 independent clock domain 4.80 3.92 4.60 usart3 apb clock domain 1.80 1.50 1.80 uart4 independent clock domain 3.80 3.10 3.00 uart4 apb clock domain 1.30 1.13 1.30 uart5 independent clock domain 3.83 3.17 3.50 uart5 apb clock domain 1.60 1.25 1.50 wwdg 0.39 0.33 0.40 all apb1 on 84.20 74.96 82.70 apb2 ahb to apb2 bridge (4) 1.00 0.90 0.90 a/mhz dfsdm1 6.00 5.00 5.50 fw 0.28 0.30 0.30 sai1 independent clock domain 2.60 2.10 2.30 sai1 apb clock domain 2.09 1.80 2.00 sai2 independent clock domain 3.30 2.70 3.00 sai2 apb clock domain 2.50 2.00 2.50 sdmmc1 independent clock domain 4.20 3.90 4.20 sdmmc1 apb clock do main 2.10 1.80 2.00 spi1 1.71 1.42 1.50 syscfg/vrefbuf/comp 0.55 0.50 0.50 tim1 8.41 6.96 7.50 tim8 8.83 7.33 8.00 tim15 3.96 3.29 3.50 tim16 3.24 2.67 3.00 tim17 2.94 2.46 2.50 usart1 independent clock domain 5.20 4.29 5.50 usart1 apb clock domain 1.70 1.50 1.60 table 50. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit
electrical characteristics STM32L496XX 146/263 docid029173 rev 2 the consumption for the peripherals when using smps can be found using stm32cubemx pcc tool. 6.3.6 wakeup time from low-po wer modes and voltage scaling transition times the wakeup times given in table 51 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction. apb2 all apb2 on 55.40 41.33 46.00 a/mhz all 234.98 195.83 235.70 1. the busmatrix is automatically active w hen at least one master is on (cpu, dma). 2. the gpiox (x= a?i) dynamic current cons umption is approximately divided by a fact or two versus this table values when the gpio port is locked thanks to lckk and lcky bits in the gp iox_lckr register. in order to save the full gpiox current consumption, the gpiox clock should be disabled in the rcc when all port i/o s are used in alternate function or analog mode (clock is only required to read or write into gp io registers, and is not used in af or analog modes). 3. the ahb to apb1 bridge is automatically acti ve when at least one peripheral is on on the apb1. 4. the ahb to apb2 bridge is automatically acti ve when at least one peripheral is on on the apb2. table 50. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit table 51. low-power mode wakeup timings (1) symbol parameter conditions typ max unit t wusleep wakeup time from sleep mode to run mode -66 nb of cpu cycles t wulpsleep wakeup time from low- power sleep mode to low- power run mode wakeup in flash with flash in power-down during low-power sleep mode (sleep_pd=1 in flash_acr) and with clock msi = 2 mhz 79 t wustop0 wake up time from stop 0 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 7.0 11.6 s wakeup clock hsi16 = 16 mhz 6.2 10.7 range 2 wakeup clock msi = 24 mhz 7.3 11.7 wakeup clock hsi16 = 16 mhz 6.2 10.7 wakeup clock msi = 4 mhz 7.6 13.2 wake up time from stop 0 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 2.5 2.9 wakeup clock hsi16 = 16 mhz 2.7 2.9 range 2 wakeup clock msi = 24 mhz 3.2 3.6 wakeup clock hsi16 = 16 mhz 2.7 2.9 wakeup clock msi = 4 mhz 5.7 13.2
docid029173 rev 2 147/263 STM32L496XX electrical characteristics 236 t wustop1 wake up time from stop 1 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 8.4 9.4 s wakeup clock hsi16 = 16 mhz 7.8 8.4 range 2 wakeup clock msi = 24 mhz 8.7 9.6 wakeup clock hsi16 = 16 mhz 7.8 8.3 wakeup clock msi = 4 mhz 8.0 12.9 wake up time from stop 1 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 5.5 5.9 wakeup clock hsi16 = 16 mhz 6.6 7.0 range 2 wakeup clock msi = 24 mhz 6.1 6.5 wakeup clock hsi16 = 16 mhz 6.6 7.0 wakeup clock msi = 4 mhz 8.5 12.8 wake up time from stop 1 mode to low-power run mode in flash regulator in low-power mode (lpr=1 in pwr_cr1) wakeup clock msi = 2 mhz 13.8 20.0 wake up time from stop 1 mode to low-power run mode in sram1 11.8 22.0 t wustop2 wake up time from stop 2 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 8.9 9.8 s wakeup clock hsi16 = 16 mhz 8.3 9.2 range 2 wakeup clock msi = 24 mhz 9.3 10.2 wakeup clock hsi16 = 16 mhz 8.2 9.2 wakeup clock msi = 4 mhz 14.2 16.1 wake up time from stop 2 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 6.1 7.1 wakeup clock hsi16 = 16 mhz 7.2 8.1 range 2 wakeup clock msi = 24 mhz 6.8 7.8 wakeup clock hsi16 = 16 mhz 7.2 8.2 wakeup clock msi = 4 mhz 8.4 16.7 t wustby wakeup time from standby mode to run mode range 1 wakeup clock msi = 8 mhz 15.3 23.2 s wakeup clock msi = 4 mhz 21.3 30.5 t wustby sram2 wakeup time from standby with sram2 to run mode range 1 wakeup clock msi = 8 mhz 15.3 23.1 s wakeup clock msi = 4 mhz 21.3 30.6 t wushdn wakeup time from shutdown mode to run mode range 1 wakeup clock msi = 4 mhz 305.9 322.3 s 1. guaranteed by characterization results. table 51. low-power mode wakeup timings (1) (continued) symbol parameter conditions typ max unit
electrical characteristics STM32L496XX 148/263 docid029173 rev 2 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 21: high-speed external clock source ac timing diagram . table 52. regulator modes transition times (1) symbol parameter conditions typ max unit t wulprun wakeup time from low-power run mode to run mode (2) code run with msi 2 mhz 5 7 s t vost regulator transition time from range 2 to range 1 or range 1 to range 2 (3) code run with msi 24 mhz 20 40 1. guaranteed by characterization results. 2. time until reglpf flag is cleared in pwr_sr2. 3. time until vosf flag is cleared in pwr_sr2. table 53. wakeup time using usart/lpuart (1) symbol parameter conditions typ max unit t wuusart t wulpuart wakeup time needed to calculate the maximum usart/lpuart baudrate allowing to wakeup up from stop mode when usart/lpuart clock source is hsi stop mode 0 - 1.7 s stop mode 1/2 - 8.5 1. guaranteed by design. table 54. high-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f hse_ext user external clock source frequency voltage scaling range 1 -848 mhz voltage scaling range 2 -826 v hseh osc_in input pin high level voltage - 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage - v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time voltage scaling range 1 7- - ns voltage scaling range 2 18 - - 1. guaranteed by design.
docid029173 rev 2 149/263 STM32L496XX electrical characteristics 236 figure 21. high-speed external clock source ac timing diagram low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 22 . figure 22. low-speed external clock source ac timing diagram 069 9 +6(+ w i+6( 7 +6( w w u+6( 9 +6(/ w z+6(+ w z+6(/ table 55. low-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - - 32.768 1000 khz v lseh osc32_in input pin high level voltage - 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage - v ss -0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time - 250 - - ns 1. guaranteed by design. 069 9 /6(+ w i/6( 7 /6( w w u/6( 9 /6(/ w z/6(+ w z/6(/
electrical characteristics STM32L496XX 150/263 docid029173 rev 2 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 48 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 56 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-freque ncy applications, and selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . table 56. hse oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions (2) 2. resonator characteristics given by the crystal/ceramic resonator manufacturer. min typ max unit f osc_in oscillator frequency - 4 8 48 mhz r f feedback resistor - - 200 - k ? i dd(hse) hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time --5.5 ma v dd = 3 v, rm = 30 ? , cl = 10 pf@8 mhz -0.44- v dd = 3 v, rm = 45 ? , cl = 10 pf@8 mhz -0.45- v dd = 3 v, rm = 30 ? , cl = 5 pf@48 mhz -0.68- v dd = 3 v, rm = 30 ? , cl = 10 pf@48 mhz -0.94- v dd = 3 v, rm = 30 ? , cl = 20 pf@48 mhz -1.77- g m maximum critical crystal transconductance startup - - 1.5 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms
docid029173 rev 2 151/263 STM32L496XX electrical characteristics 236 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 23. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results obtained with typical external components specified in table 57 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 069 26&b,1 26&b287 5 ) %ldv frqwuroohg jdlq i +6( 5 (;7 0+] uhvrqdwru 5hvrqdwruzlwklqwhjudwhg fdsdflwruv & / & / table 57. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions (2) min typ max unit i dd(lse) lse current consumption lsedrv[1:0] = 00 low drive capability -250- na lsedrv[1:0] = 01 medium low drive capability -315- lsedrv[1:0] = 10 medium high drive capability -500- lsedrv[1:0] = 11 high drive capability -630- gm critmax maximum critical crystal gm lsedrv[1:0] = 00 low drive capability --0.5 a/v lsedrv[1:0] = 01 medium low drive capability - - 0.75 lsedrv[1:0] = 10 medium high drive capability --1.7 lsedrv[1:0] = 11 high drive capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s
electrical characteristics STM32L496XX 152/263 docid029173 rev 2 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 24. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 1. guaranteed by design. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is en abled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 069 26&b,1 26&b287 'ulyh surjudppdeoh dpsolilhu i /6( n+] uhvrqdwru 5hvrqdwruzlwklqwhjudwhg fdsdflwruv & / & /
docid029173 rev 2 153/263 STM32L496XX electrical characteristics 236 6.3.8 internal clock source characteristics the parameters given in table 58 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi16) rc oscillator table 58. hsi16 oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi16 hsi16 frequency v dd =3.0 v, t a =30 c 15.88 - 16.08 mhz trim hsi16 user trimming step trimming code is not a multiple of 64 0.2 0.3 0.4 % trimming code is a multiple of 64 -4 -6 -8 ducy(hsi16) (2) duty cycle - 45 - 55 % ? te m p (hsi16) hsi16 oscillator frequency drift over temperature t a = 0 to 85 c -1 - 1 % t a = -40 to 125 c -2 - 1.5 % ? vdd (hsi16) hsi16 oscillator frequency drift over v dd v dd =1.62 v to 3.6 v -0.1 - 0.05 % t su (hsi16) (2) hsi16 oscillator start-up time --0.81.2 s t stab (hsi16) (2) hsi16 oscillator stabilization time --35 s i dd (hsi16) (2) hsi16 oscillator power consumption - - 155 190 a 1. guaranteed by characterization results. 2. guaranteed by design.
electrical characteristics STM32L496XX 154/263 docid029173 rev 2 figure 25. hsi16 frequency versus temperature 06y9 0+] ?& 0hdq plq pd[
docid029173 rev 2 155/263 STM32L496XX electrical characteristics 236 multi-speed internal (msi) rc oscillator table 59. msi oscillator characteristics (1) symbol parameter conditions min typ max unit f msi msi frequency after factory calibration, done at v dd =3 v and t a =30 c msi mode range 0 98.7 100 101.3 khz range 1 197.4 200 202.6 range 2 394.8 400 405.2 range 3 7896 800 810.4 range 4 0.987 1 1.013 mhz range 5 1.974 2 2.026 range 6 3.948 4 4.052 range 7 7.896 8 8.104 range 8 15.79 16 16.21 range 9 23.69 24 24.31 range 10 31.58 32 32.42 range 11 47.38 48 48.62 pll mode xtal= 32.768 khz range 0 - 98.304 - khz range 1 - 196.608 - range 2 - 393.216 - range 3 - 786.432 - range 4 - 1.016 - mhz range 5 - 1.999 - range 6 - 3.998 - range 7 - 7.995 - range 8 - 15.991 - range 9 - 23.986 - range 10 - 32.014 - range 11 - 48.005 - ? temp (msi) (2) msi oscillator frequency drift over temperature msi mode t a = -0 to 85 c -3.5 - 3 % t a = -40 to 125 c -8 - 6
electrical characteristics STM32L496XX 156/263 docid029173 rev 2 ? vdd (msi) (2) msi oscillator frequency drift over v dd (reference is 3 v) msi mode range 0 to 3 v dd =1.62 v to 3.6 v -1.2 - 0.5 % v dd =2.4 v to 3.6 v -0.5 - range 4 to 7 v dd =1.62 v to 3.6 v -2.5 - 0.7 v dd =2.4 v to 3.6 v -0.8 - range 8 to 11 v dd =1.62 v to 3.6 v -5 - 1 v dd =2.4 v to 3.6 v -1.6 - ? f sampling (msi) (2)(4) frequency variation in sampling mode (3) msi mode t a = -40 to 85 c - 1 2 % t a = -40 to 125 c - 2 4 cc jitter(msi) (4) rms cycle-to- cycle jitter pll mode range 11 - - 60 - ps p jitter(msi) (4) rms period jitter pll mode range 11 - - 50 - ps t su (msi) (4) msi oscillator start-up time range 0 - - 10 20 us range 1 - - 5 10 range 2 - - 4 8 range 3 - - 3 7 range 4 to 7 - - 3 6 range 8 to 11 - - 2.5 6 t stab (msi) (4) msi oscillator stabilization time pll mode range 11 10 % of final frequency --0.250.5 ms 5 % of final frequency --0.51.25 1 % of final frequency ---2.5 table 59. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 157/263 STM32L496XX electrical characteristics 236 figure 26. typical current consumption versus msi frequency i dd (msi) (4) msi oscillator power consumption msi and pll mode range 0 - - 0.6 1 a range 1 - - 0.8 1.2 range 2 - - 1.2 1.7 range 3 - - 1.9 2.5 range 4 - - 4.7 6 range 5 - - 6.5 9 range 6 - - 11 15 range 7 - - 18.5 25 range 8 - - 62 80 range 9 - - 85 110 range 10 - - 110 130 range 11 - - 155 190 1. guaranteed by characterization results. 2. this is a deviation for an individual pa rt once the initial frequency has been measured. 3. sampling mode means low-power run/low-power sl eep modes with temperature sensor disable. 4. guaranteed by design. table 59. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics STM32L496XX 158/263 docid029173 rev 2 high-speed internal 48 mhz (hsi48) rc oscillator table 60. hsi48 oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi48 hsi48 frequency v dd =3.0v, t a =30c - 48 - mhz trim hsi48 user trimming step - - 0.11 (2) 0.18 (2) % user trim coverage hsi48 user trimming coverage 32 steps 3 (3) 3.5 (3) -% ducy(hsi48) duty cycle - 45 (2) -55 (2) % acc hsi48_rel accuracy of the hsi48 oscillator over temperature (factory calibrated) v dd = 3.0 v to 3.6 v, t a = ?15 to 85 c --3 (3) % v dd = 1.65 v to 3.6 v, t a = ?40 to 125 c --4.5 (3) d vdd (hsi48) hsi48 oscillator frequency drift with v dd v dd = 3 v to 3.6 v - 0.025 (3) 0.05 (3) % v dd = 1.65 v to 3.6 v - 0.05 (3) 0.1 (3) t su (hsi48) hsi48 oscillator start-up time - - 2.5 (2) 6 (2) s i dd (hsi48) hsi48 oscillator power consumption --340 (2) 380 (2) a n t jitter next transition jitter accumulated jitter on 28 cycles (4) --+/-0.15 (2) -ns p t jitter paired transition jitter accumulated jitter on 56 cycles (4) --+/-0.25 (2) -ns 1. v dd = 3 v, t a = ?40 to 125c unless otherwise specified. 2. guaranteed by design. 3. guaranteed by characterization results. 4. jitter measurement are performed without clock source activated in parallel.
docid029173 rev 2 159/263 STM32L496XX electrical characteristics 236 figure 27. hsi48 frequency versus temperature low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 62 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 22: general operating conditions . 06y9 $yj plq pd[ ?& table 61. lsi oscillator characteristics (1) symbol parameter conditions min typ max unit f lsi lsi frequency v dd = 3.0 v, t a = 30 c 31.04 - 32.96 khz v dd = 1.62 to 3.6 v, t a = -40 to 125 c 29.5 - 34 t su (lsi) (2) lsi oscillator start- up time --80130 s t stab (lsi) (2) lsi oscillator stabilization time 5% of final frequency - 125 180 s i dd (lsi) (2) lsi oscillator power consumption --110180na 1. guaranteed by characterization results. 2. guaranteed by design. table 62. pll, pllsai1, pllsai2 characteristics (1) symbol parameter conditions min typ max unit f pll_in pll input clock (2) -4-16mhz pll input clock duty cycle - 45 - 55 %
electrical characteristics STM32L496XX 160/263 docid029173 rev 2 6.3.10 flash memory characteristics f pll_p_out pll multiplier output clock p voltage scaling range 1 2.0645 - 80 mhz voltage scaling range 2 2.0645 - 26 f pll_q_out pll multiplier output clock q voltage scaling range 1 8 - 80 mhz voltage scaling range 2 8 - 26 f pll_r_out pll multiplier output clock r voltage scaling range 1 8 - 80 mhz voltage scaling range 2 8 - 26 f vco_out pll vco output voltage scaling range 1 64 - 344 mhz voltage scaling range 2 64 - 128 t lock pll lock time - - 15 40 s jitter rms cycle-to-cycle jitter system clock 80 mhz -40- ps rms period jitter - 30 - i dd (pll) pll power consumption on v dd (1) vco freq = 64 mhz - 150 200 a vco freq = 96 mhz - 200 260 vco freq = 192 mhz - 300 380 vco freq = 344 mhz - 520 650 1. guaranteed by design. 2. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between the 3 plls. table 62. pll, pllsai1, pllsai2 characteristics (1) (continued) symbol parameter conditions min typ max unit table 63. flash memory characteristics (1) symbol parameter conditions typ max unit t prog 64-bit programming time - 81.69 90.76 s t prog_row one row (32 double word) programming time normal programming 2.61 2.90 ms fast programming 1.91 2.12 t prog_page one page (2 kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 t erase page (2 kb) erase time - 22.02 24.47 t prog_bank one bank (512 kbyte) programming time normal programming 5.35 5.95 s fast programming 3.91 4.35 t me mass erase time (one or two banks) - 22.13 24.59 ms
docid029173 rev 2 161/263 STM32L496XX electrical characteristics 236 i dd average consumption from v dd write mode 3.4 - ma erase mode 3.4 - maximum current (peak) write mode 7 (for 2 s) - erase mode 7 (for 41 s) - 1. guaranteed by design. table 64. flash memory endurance and data retention symbol parameter conditions min (1) 1. guaranteed by characterization results. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 15 1 kcycle (2) at t a = 125 c 7 10 kcycles (2) at t a = 55 c 30 10 kcycles (2) at t a = 85 c 15 10 kcycles (2) at t a = 105 c 10 table 63. flash memory characteristics (1) (continued) symbol parameter conditions typ max unit
electrical characteristics STM32L496XX 162/263 docid029173 rev 2 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 65 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 65. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-4 5a
docid029173 rev 2 163/263 STM32L496XX electrical characteristics 236 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. table 66. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8 mhz / 80 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp144 package compliant with iec 61967-2 0.1 mhz to 30 mhz 3 dbv 30 mhz to 130 mhz -2 130 mhz to 1 ghz 0 1 ghz to 2 ghz 8 emi level 1.5 - table 67. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/esda/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 c3 250
electrical characteristics STM32L496XX 164/263 docid029173 rev 2 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 69 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 68. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a (1) 1. negative injection is limited to -30 ma for pf0, pf1, pg6, pg7, pg8, pg12, pg13, pg14. table 69. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj (1) 1. guaranteed by characterization. injected current on all pins except pa4, pa5, pb0, pf12, pf13, opamp1_v1nm, opamp2_v1nm -5 na ma injected current on pins pb0, pf12, pf13 0 na injected current on opamp1_v1nm, opamp2_v1nm 0 0 injected current on pa4, pa5 pins -5 0
docid029173 rev 2 165/263 STM32L496XX electrical characteristics 236 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 70 are derived from tests performed under the conditions summarized in table 22: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 70. i/o static characteristics symbol parameter conditions min typ max unit v il (1) i/o input low level voltage except boot0 1.62 v electrical characteristics STM32L496XX 166/263 docid029173 rev 2 i lkg ft_xx input leakage current (3) v in max(v ddxxx ) (4) --100 na max(v ddxxx ) v in max(v ddxxx )+1 v (4)(5) --650 (3)(6) max(v ddxxx )+1 v < vin 5.5 v (3)(5) - - 200 (6) ft_lu, ft_u and pc3 io v in max(v ddxxx ) (4) --150 max(v ddxxx ) v in max(v ddxxx )+1 v (4) - - 2500 (3)(7) max(v ddxxx )+1 v < vin 5.5 v (4)(5)(7) - - 250 (7) tt_xx input leakage current v in max(v ddxxx ) (6) --150 max(v ddxxx ) v in < 3.6 v (6) - - 2000 (3) opampx_vinm (x=1,2) dedicated input leakage current (ufbga132 only) --- (8) r pu weak pull-up equivalent resistor (9) v in = v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (9) v in = v ddiox 25 40 55 k ? c io i/o pin capacitance - - 5 - pf 1. refer to figure 28: i/o input characteristics . 2. tested in production. 3. guaranteed by design. 4. max(v ddxxx ) is the maximum value of all the i/o supplies. refer to table: legend/abbreviations used in the pinout table. 5. all tx_xx io except ft_lu, ft_u and pc3. 6. this value represents the pad leakage of the io itself. the total product pad leakage is provided by this formula: i to ta l _ i l e a k _ m a x = 10 a + [number of ios where v in is applied on the pad] ? i lkg (max). 7. to sustain a voltage higher than min(v dd , v dda ) +0.3 v, the internal pull-up and pull-down resistors must be disabled. 8. refer to i bias in table 85: opamp characteristics for the values of the opamp dedicated input leakage current. 9. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 70. i/o static characteristics (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 167/263 STM32L496XX electrical characteristics 236 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 28 for standard i/os, and in figure 28 for 5 v tolerant i/os. figure 28. i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 19: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximu m consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 19: voltage characteristics ). 06y9 7hvwh glqsurgxfwlrq&026uhtxluhphqw9lk plq [9 ' ',2 [ %dvhgrqvlpxodwl rq9l kplq [9 '',2[ iru9 ' ',2[ ru [9 '', 2[ i r u9 '', 2[ ! %dvhgrqvlpx odwlrq9 lop d[ [9 '',2[ iru 9 '',2[ ru[9 '' ,2[ iru 9 '',2 [ ! 7hvwhglqsurgx fwlrq&026uht xluhphqw9lop d [ [9gg 77/uhtxluhphqw9lkplq 9 77/uhtxluhphqw9lopd[ 9
electrical characteristics STM32L496XX 168/263 docid029173 rev 2 output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . all i/os are cmos- and ttl -compliant (ft or tt unless otherwise specified). input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 29 and table 72 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . table 71. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox -0.4 - v ol (3) output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v oh (3) output high level voltage for an i/o pin v ddiox -1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 4 ma v ddiox 1.62 v -0.45 v oh (3) output high level voltage for an i/o pin v ddiox -0.45 - v ol (3) output low level voltage for an i/o pin |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.35 ? v ddiox v oh (3) output high level voltage for an i/o pin 0.65 ? v ddiox - v olfm+ (3) output low level voltage for an ft i/o pin in fm+ mode (ft i/o with "f" option) |i io | = 20 ma v ddiox 2.7 v -0.4 |i io | = 10 ma v ddiox 1.62 v -0.4 |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.4 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 19: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. guaranteed by design.
docid029173 rev 2 169/263 STM32L496XX electrical characteristics 236 table 72. i/o ac characteristics (1)(2) speed symbol parameter conditions min max unit 00 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 5 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 1 c=50 pf, 1.08 v v ddiox 1.62 v - 0.1 c=10 pf, 2.7 v v ddiox 3.6 v - 10 c=10 pf, 1.62 v v ddiox 2.7 v - 1.5 c=10 pf, 1.08 v v ddiox 1.62 v - 0.1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 25 ns c=50 pf, 1.62 v v ddiox 2.7 v - 52 c=50 pf, 1.08 v v ddiox 1.62 v - 140 c=10 pf, 2.7 v v ddiox 3.6 v - 17 c=10 pf, 1.62 v v ddiox 2.7 v - 37 c=10 pf, 1.08 v v ddiox 1.62 v - 110 01 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 25 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 10 c=50 pf, 1.08 v v ddiox 1.62 v - 1 c=10 pf, 2.7 v v ddiox 3.6 v - 50 c=10 pf, 1.62 v v ddiox 2.7 v - 15 c=10 pf, 1.08 v v ddiox 1.62 v - 1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 9 ns c=50 pf, 1.62 v v ddiox 2.7 v - 16 c=50 pf, 1.08 v v ddiox 1.62 v - 40 c=10 pf, 2.7 v v ddiox 3.6 v - 4.5 c=10 pf, 1.62 v v ddiox 2.7 v - 9 c=10 pf, 1.08 v v ddiox 1.62 v - 21
electrical characteristics STM32L496XX 170/263 docid029173 rev 2 10 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 50 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 25 c=50 pf, 1.08 v v ddiox 1.62 v - 5 c=10 pf, 2.7 v v ddiox 3.6 v - 100 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 37.5 c=10 pf, 1.08 v v ddiox 1.62 v - 5 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 5.8 ns c=50 pf, 1.62 v v ddiox 2.7 v - 11 c=50 pf, 1.08 v v ddiox 1.62 v - 28 c=10 pf, 2.7 v v ddiox 3.6 v - 2.5 c=10 pf, 1.62 v v ddiox 2.7 v - 5 c=10 pf, 1.08 v v ddiox 1.62 v - 12 11 fmax maximum frequency c=30 pf, 2.7 v v ddiox 3.6 v - 120 (3) mhz c=30 pf, 1.62 v v ddiox 2.7 v - 50 c=30 pf, 1.08 v v ddiox 1.62 v - 10 c=10 pf, 2.7 v v ddiox 3.6 v - 180 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 75 c=10 pf, 1.08 v v ddiox 1.62 v - 10 tr/tf output rise and fall time c=30 pf, 2.7 v v ddiox 3.6 v - 3.3 ns c=30 pf, 1.62 v v ddiox 2.7 v - 6 c=30 pf, 1.08 v v ddiox 1.62 v - 16 fm+ fmax maximum frequency c=50 pf, 1.6 v v ddiox 3.6 v -1mhz tf output fall time (4) -5ns 1. the i/o speed is configured using the ospeedry[1:0] bits. the fm+ mode is configured in the syscfg_cfgr1 register. refer to the rm0351 reference manual for a descr iption of gpio port configuration register. 2. guaranteed by design. 3. this value represents the i/o capability but t he maximum system frequency is limited to 80 mhz. 4. the fall time is defined between 70% and 30% of the output waveform accordingly to i 2 c specification. table 72. i/o ac characteristics (1)(2) (continued) speed symbol parameter conditions min max unit
docid029173 rev 2 171/263 STM32L496XX electrical characteristics 236 figure 29. i/o ac characteristics definition (1) 1. refer to table 72: i/o ac characteristics . 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . 069 7 0d[lpxpiuhtxhqf\lvdfklhyhgliww?7dqgliwkhg xw\f\fohlv zkhqordghge\wkhvshflilhgfdsdflwdqfh u i u,2rxw w i,2rxw w table 73. nrst pin characteristics (1) symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage ---0.3 ? v ddiox v v ih(nrst) nrst input high level voltage -0.7 ? v ddiox -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse ---70ns v nf(nrst) nrst input not filtered pulse 1.71 v v dd 3.6 v 350 - - ns 1. guaranteed by design. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order) .
electrical characteristics STM32L496XX 172/263 docid029173 rev 2 figure 30. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 73: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 3. the external capacitor on nrst must be placed as close as pos sible to the device. 6.3.16 analog switches booster 069 5 38 9 '' ,qwhuqdouhvhw ([whuqdo uhvhwflufxlw 1567 )lowhu ?) table 74. analog switches booster characteristics (1) 1. guaranteed by design. symbol parameter min typ max unit v dd supply voltage 1.62 - 3.6 v t su(boost) booster startup time - - 240 s i dd(boost) booster consumption for 1.62 v v dd 2.0 v --250 a booster consumption for 2.0 v v dd 2.7 v --500 booster consumption for 2.7 v v dd 3 .6 v --900
docid029173 rev 2 173/263 STM32L496XX electrical characteristics 236 6.3.17 analog-to-digital converter characteristics unless otherwise specified, the parameters given in table 75 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 22: general operating conditions . note: it is recommended to perform a calibration after each power-up. table 75. adc characteristics (1) (2) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v ref+ positive reference voltage v dda 2 v 2 - v dda v v dda < 2 v v dda v v ref- negative reference voltage -v ssa v f adc adc clock frequency range 1 - - 80 mhz range 2 - - 26 f s sampling rate for fast channels resolution = 12 bits - - 5.33 msps resolution = 10 bits - - 6.15 resolution = 8 bits - - 7.27 resolution = 6 bits - - 8.88 sampling rate for slow channels resolution = 12 bits - - 4.21 resolution = 10 bits - - 4.71 resolution = 8 bits - - 5.33 resolution = 6 bits - - 6.15 f trig external trigger frequency f adc = 80 mhz resolution = 12 bits - - 5.33 mhz resolution = 12 bits - - 15 1/f adc v ain (3) conversion voltage range(2) -0-v ref+ v r ain external input impedance - - - 50 k ? c adc internal sample and hold capacitor --5-pf t stab power-up time - 1 conversion cycle t cal calibration time f adc = 80 mhz 1.45 s -1161/f adc t latr trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2.0 ckmode = 10 - - 2.25 ckmode = 11 - - 2.125
electrical characteristics STM32L496XX 174/263 docid029173 rev 2 the maximum value of r ain can be found in table 76: maximum adc rain . t latrinj trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3.0 ckmode = 10 - - 3.25 ckmode = 11 - - 3.125 t s sampling time f adc = 80 mhz 0.03125 - 8.00625 s - 2.5 - 640.5 1/f adc t adcvreg_stup adc voltage regulator start-up time ---20 s t conv total conversion time (including sampling time) f adc = 80 mhz resolution = 12 bits 0.1875 - 8.1625 s resolution = 12 bits ts + 12.5 cycles for successive approximation = 15 to 653 1/f adc i dda (adc) adc consumption from the v dda supply fs = 5 msps - 730 830 a fs = 1 msps - 160 220 fs = 10 ksps - 16 50 i ddv_s (adc) adc consumption from the v ref+ single ended mode fs = 5 msps - 130 160 a fs = 1 msps - 30 40 fs = 10 ksps - 0.6 2 i ddv_d (adc) adc consumption from the v ref+ differential mode fs = 5 msps - 260 310 a fs = 1 msps - 60 70 fs = 10 ksps - 1.3 3 1. guaranteed by design 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pinouts and pin description for further details. table 75. adc characteristics (1) (2) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 175/263 STM32L496XX electrical characteristics 236 table 76. maximum adc rain (1)(2) resolution sampling cycle @80 mhz sampling time [ns] @80 mhz rain max ( ? ) fast channels (3) slow channels (4) 12 bits 2.5 31.25 100 n/a 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 10 bits 2.5 31.25 120 n/a 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 5600 4700 247.5 3093.75 12000 10000 640.5 8006.75 47000 39000 8 bits 2.5 31.25 180 n/a 6.5 81.25 470 270 12.5 156.25 1000 680 24.5 306.25 1800 1500 47.5 593.75 2700 2200 92.5 1156.25 6800 5600 247.5 3093.75 15000 12000 640.5 8006.75 50000 50000 6 bits 2.5 31.25 220 n/a 6.5 81.25 560 330 12.5 156.25 1200 1000 24.5 306.25 2700 2200 47.5 593.75 3900 3300 92.5 1156.25 8200 6800 247.5 3093.75 18000 15000 640.5 8006.75 50000 50000 1. guaranteed by design.
electrical characteristics STM32L496XX 176/263 docid029173 rev 2 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. fast channels are: pc0, pc1, pc2, pc3, pa0. 4. slow channels are: all adc i nputs except the fast channels.
docid029173 rev 2 177/263 STM32L496XX electrical characteristics 236 table 77. adc accuracy - limited test conditions 1 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = vref+ = 3 v, ta = 25 c single ended fast channel (max speed) - 4 5 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 3.5 4.5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 1 2.5 slow channel (max speed) - 1 2.5 differential fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 eg gain error single ended fast channel (max speed) - 2.5 4.5 slow channel (max speed) - 2.5 4.5 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 differential fast channel (max speed) - 1 2 slow channel (max speed) - 1 2 enob effective number of bits single ended fast channel (max speed) 10.4 10.5 - bits slow channel (max speed) 10.4 10.5 - differential fast channel (max speed) 10.8 10.9 - slow channel (max speed) 10.8 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 64.4 65 - db slow channel (max speed) 64.4 65 - differential fast channel (max speed) 66.8 67.4 - slow channel (max speed) 66.8 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - differential fast channel (max speed) 67 68 - slow channel (max speed) 67 68 -
electrical characteristics STM32L496XX 178/263 docid029173 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = v ref+ = 3 v, ta = 25 c single ended fast channel (max speed) - -74 -73 db slow channel (max speed) - -74 -73 differential fast channel (max speed) - -79 -76 slow channel (max speed) - -79 -76 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 77. adc accuracy - limited test conditions 1 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit
docid029173 rev 2 179/263 STM32L496XX electrical characteristics 236 table 78. adc accuracy - limited test conditions 2 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - 4 6.5 lsb slow channel (max speed) - 4 6.5 differential fast channel (max speed) - 3.5 5.5 slow channel (max speed) - 3.5 5.5 eo offset error single ended fast channel (max speed) - 1 4.5 slow channel (max speed) - 1 5 differential fast channel (max speed) - 1.5 3 slow channel (max speed) - 1.5 3 eg gain error single ended fast channel (max speed) - 2.5 6 slow channel (max speed) - 2.5 6 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 3.5 slow channel (max speed) - 1.5 3.5 differential fast channel (max speed) - 1 3 slow channel (max speed) - 1 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.5 - bits slow channel (max speed) 10 10.5 - differential fast channel (max speed) 10.7 10.9 - slow channel (max speed) 10.7 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 65 - db slow channel (max speed) 62 65 - differential fast channel (max speed) 66 67.4 - slow channel (max speed) 66 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 64 66 - slow channel (max speed) 64 66 - differential fast channel (max speed) 66.5 68 - slow channel (max speed) 66.5 68 -
electrical characteristics STM32L496XX 180/263 docid029173 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - -74 -65 db slow channel (max speed) - -74 -67 differential fast channel (max speed) - -79 -70 slow channel (max speed) - -79 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 78. adc accuracy - limited test conditions 2 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit
docid029173 rev 2 181/263 STM32L496XX electrical characteristics 236 table 79. adc accuracy - limited test conditions 3 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - 5.5 7.5 lsb slow channel (max speed) - 4.5 6.5 differential fast channel (max speed) - 4.5 7.5 slow channel (max speed) - 4.5 5.5 eo offset error single ended fast channel (max speed) - 2 5 slow channel (max speed) - 2.5 5 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2.5 3 eg gain error single ended fast channel (max speed) - 4.5 7 slow channel (max speed) - 3.5 6 differential fast channel (max speed) - 3.5 4 slow channel (max speed) - 3.5 5 ed differential linearity error single ended fast channel (max speed) - 1.2 1.5 slow channel (max speed) - 1.2 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 3 3.5 slow channel (max speed) - 2.5 3.5 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.4 - bits slow channel (max speed) 10 10.4 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 64 - db slow channel (max speed) 62 64 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 63 65 - slow channel (max speed) 63 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 -
electrical characteristics STM32L496XX 182/263 docid029173 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - -69 -67 db slow channel (max speed) - -71 -67 differential fast channel (max speed) - -72 -71 slow channel (max speed) - -72 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 79. adc accuracy - limited test conditions 3 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit
docid029173 rev 2 183/263 STM32L496XX electrical characteristics 236 table 80. adc accuracy - limited test conditions 4 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - 5 5.4 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 4 5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 2 4 slow channel (max speed) - 2 4 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2 3.5 eg gain error single ended fast channel (max speed) - 4 4.5 slow channel (max speed) - 4 4.5 differential fast channel (max speed) - 3 4 slow channel (max speed) - 3 4 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 2.5 3 slow channel (max speed) - 2.5 3 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10.2 10.5 - bits slow channel (max speed) 10.2 10.5 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 63 65 - db slow channel (max speed) 63 65 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 64 65 - slow channel (max speed) 64 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 -
electrical characteristics STM32L496XX 184/263 docid029173 rev 2 thd to ta l harmonic distortion adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - -71 -69 db slow channel (max speed) - -71 -69 differential fast channel (max speed) - -73 -72 slow channel (max speed) - -73 -72 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 80. adc accuracy - limited test conditions 4 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit
docid029173 rev 2 185/263 STM32L496XX electrical characteristics 236 figure 31. adc accuracy characteristics figure 32. typical connecti on diagram using the adc 1. refer to table 75: adc characteristics for the values of r ain and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (refer to table 70: i/o static characteristics for the value of the pad capacitance). a high c parasitic value will downgrade conversion a ccuracy. to remedy this, f adc should be reduced. 3. refer to table 70: i/o static characteristics for the values of i lkg . general pcb design guidelines power supply decoupling should be performed as shown in figure 18: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 7 7rwdo8qdmxvwhg(uurupd[lpxpghyldwlrq ehwzhhqwkhdfwxdodqglghdowudqvihufxuyhv ( 2 2iivhw(uurupd[lpxpghyldwlrq ehwzhhqwkhiluvwdfwxdowudqvlwlrqdqgwkhiluvw lghdorqh ( * *dlq(uurughyldwlrqehwzhhqwkhodvw lghdowudqvlwlrqdqgwkhodvwdfwxdorqh ( ' 'liihuhqwldo/lqhdulw\(uurupd[lpxp ghyldwlrqehwzhhqdfwxdovwhsvdqgwkhlghdorqhv ( / ,qwhjudo/lqhdulw\(uurupd[lpxpghyldwlrq ehwzhhqdq\dfwxdowudqvlwlrqdqgwkhhqgsrlqw fruuhodwlrqolqh ([dpsohridqdfwxdowudqvihufxuyh 7khlghdowudqvihufxuyh (qgsrlqwfruuhodwlrqolqh 9 ''$ 9 66$ ( 2 ( 7 ( / ( * ( ' /6% ,'($/ 069 069 6dpsohdqgkrog$'&frqyhuwhu elw frqyhuwhu & sdudvlwlf , onj 9 7 & $'& 9 ''$ 5 $,1 9 $,1 9 7 $,1[ 5 $'&
electrical characteristics STM32L496XX 186/263 docid029173 rev 2 6.3.18 digital-to-analog converter characteristics table 81. dac characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage for dac on dac output buffer off, dac_out pin not connected (internal connection only) 1.71 - 3.6 v other modes 1.80 - v ref+ positive reference voltage dac output buffer off, dac_out pin not connected (internal connection only) 1.71 - v dda other modes 1.80 - v ref- negative reference voltage - v ssa r l resistive load dac output buffer on connected to v ssa 5- - k ? connected to v dda 25 - - r o output impedance dac output buffer off 9.6 11.7 13.8 k ? r bon output impedance sample and hold mode, output buffer on v dd = 2.7 v - - 2 k ? v dd = 2.0 v - - 3.5 r boff output impedance sample and hold mode, output buffer off v dd = 2.7 v - - 16.5 k ? v dd = 2.0 v - - 18.0 c l capacitive load dac output buffer on - - 50 pf c sh sample and hold mode - 0.1 1 f v dac_out voltage on dac_out output dac output buffer on 0.2 - v ref+ ? 0.2 v dac output buffer off 0 - v ref+ t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when dac_out reaches final value 0.5lsb, 1 lsb, 2 lsb, 4 lsb, 8 lsb) normal mode dac output buffer on cl 50 pf, rl 5 k ? 0.5 lsb - 1.7 3 s 1 lsb - 1.6 2.9 2 lsb - 1.55 2.85 4 lsb - 1.48 2.8 8 lsb - 1.4 2.75 normal mode dac output buffer off, 1lsb, cl = 10 pf -2 2.5 t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) until final value 1 lsb normal mode dac output buffer on cl 50 pf, rl 5 k ? -4.2 7.5 s normal mode dac output buffer off, cl 10 pf -2 5 psrr v dda supply rejection ratio normal mode dac output buffer on cl 50 pf, rl = 5 k ? , dc --80 -28db
docid029173 rev 2 187/263 STM32L496XX electrical characteristics 236 t w_to_w minimal time between two consecutive writes into the dac_dorx register to guarantee a correct dac_out for a small variation of the input code (1 lsb) dac_mcr:modex[2:0] = 000 or 001 dac_mcr:modex[2:0] = 010 or 011 cl 50 pf, rl 5 k ? cl 10 pf 1 1.4 --s t samp sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when dacout reaches final value 1lsb) dac_out pin connected dac output buffer on, c sh = 100 nf -0.7 3.5 ms dac output buffer off, c sh = 100 nf -10.5 18 dac_out pin not connected (internal connection only) dac output buffer off -2 3.5s i leak output leakage current sample and hold mode, dac_out pin connected -- - (3) na ci int internal sample and hold capacitor - 5.2 7 8.8 pf t trim middle code offset trim time dac output buffer on 50 - - s v offset middle code offset for 1 trim code step v ref+ = 3.6 v - 1500 - v v ref+ = 1.8 v - 750 - i dda (dac) dac consumption from v dda dac output buffer on no load, middle code (0x800) - 315 500 a no load, worst code (0xf1c) - 450 670 dac output buffer off no load, middle code (0x800) -- 0.2 sample and hold mode, c sh = 100 nf - 315 ? to n / ( to n +toff) (4) 670 ? to n / ( to n +toff) (4) table 81. dac characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics STM32L496XX 188/263 docid029173 rev 2 figure 33. 12-bit buffered / non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. i ddv (dac) dac consumption from v ref+ dac output buffer on no load, middle code (0x800) - 185 240 a no load, worst code (0xf1c) - 340 400 dac output buffer off no load, middle code (0x800) - 155 205 sample and hold mode, buffer on, c sh = 100 nf, worst case - 185 ? to n / ( to n +toff) (4) 400 ? to n / ( to n +toff) (4) sample and hold mode, buffer off, c sh = 100 nf, worst case - 155 ? to n / ( to n +toff) (4) 205 ? to n / ( to n +toff) (4) 1. guaranteed by design. 2. in buffered mode, the output can overshoot above the final value for low input code (starting from min value). 3. refer to table 70: i/o static characteristics . 4. ton is the refresh phase duration. toff is the hold phase duration. refer to rm0351 reference manual for more details. table 81. dac characteristics (1) (continued) symbol parameter conditions min typ max unit %xiihu elw gljlwdowr dqdorj frqyhuwhu %xiihuhgqrqexiihuhg'$& '$&[b287 5 /2$' & /2$' dlg
docid029173 rev 2 189/263 STM32L496XX electrical characteristics 236 . table 82. dac accuracy (1) symbol parameter conditions min typ max unit dnl differential non linearity (2) dac output buffer on - - 2 lsb dac output buffer off - - 2 - monotonicity 10 bits guaranteed inl integral non linearity (3) dac output buffer on cl 50 pf, rl 5 k ? --4 dac output buffer off cl 50 pf, no rl --4 offset offset error at code 0x800 (3) dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 12 v ref+ = 1.8 v - - 25 dac output buffer off cl 50 pf, no rl --8 offset1 offset error at code 0x001 (4) dac output buffer off cl 50 pf, no rl --5 offsetcal offset error at code 0x800 after calibration dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 5 v ref+ = 1.8 v - - 7 gain gain error (5) dac output buffer on cl 50 pf, rl 5 k ? --0.5 % dac output buffer off cl 50 pf, no rl --0.5 tue to ta l unadjusted error dac output buffer on cl 50 pf, rl 5 k ? --30 lsb dac output buffer off cl 50 pf, no rl --12 tuecal to ta l unadjusted error after calibration dac output buffer on cl 50 pf, rl 5 k ? --23lsb snr signal-to-noise ratio dac output buffer on cl 50 pf, rl 5 k ? 1 khz, bw 500 khz -71.2- db dac output buffer off cl 50 pf, no rl, 1 khz bw 500 khz -71.6- thd total harmonic distortion dac output buffer on cl 50 pf, rl 5 k ? , 1 khz --78- db dac output buffer off cl 50 pf, no rl, 1 khz --79-
electrical characteristics STM32L496XX 190/263 docid029173 rev 2 sinad signal-to-noise and distortion ratio dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -70.4- db dac output buffer off cl 50 pf, no rl, 1 khz -71- enob effective number of bits dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -11.4- bits dac output buffer off cl 50 pf, no rl, 1 khz -11.5- 1. guaranteed by design. 2. difference between two consecutive codes - 1 lsb. 3. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. 4. difference between the value measured at code (0x001) and the ideal value. 5. difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xfff when buffer is off, and from code giving 0.2 v and (v ref+ ? 0.2) v when buffer is on. table 82. dac accuracy (1) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 191/263 STM32L496XX electrical characteristics 236 6.3.19 voltage reference buffer characteristics table 83. vrefbuf characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage normal mode v rs = 0 2.4 - 3.6 v v rs = 1 2.8 - 3.6 degraded mode (2) v rs = 0 1.65 - 2.4 v rs = 1 1.65 - 2.8 v refbuf_ out voltage reference output normal mode v rs = 0 2.046 (3) 2.048 2.049 (3) v rs = 1 2.498 (3) 2.5 2.502 (3) degraded mode (2) v rs = 0 v dda -150 mv - v dda v rs = 1 v dda -150 mv - v dda trim trim step resolution ---0.050.1% cl load capacitor - - 0.5 1 1.5 f esr equivalent serial resistor of cload ----2 ? i load static load current ----4ma i line_reg line regulation 2.8 v v dda 3.6 v i load = 500 a - 200 1000 ppm/v i load = 4 ma - 100 500 i load_reg load regulation 500 a i load 4 ma normal mode - 50 500 ppm/ma t coeff temperature coefficient -40 c < tj < +125 c - - t coeff_ vrefint + 50 ppm/ c 0 c < tj < +50 c - - t coeff_ vrefint + 50 psrr power supply rejection dc 40 60 - db 100 khz 25 40 - t start start-up time cl = 0.5 f (4) - 300 350 s cl = 1.1 f (4) - 500 650 cl = 1.5 f (4) - 650 800 i inrush control of maximum dc current drive on vrefbuf_ out during start-up phase (5) ---8-ma
electrical characteristics STM32L496XX 192/263 docid029173 rev 2 i dda (vref buf) vrefbuf consumption from v dda i load = 0 a - 16 25 a i load = 500 a - 18 30 i load = 4 ma - 35 50 1. guaranteed by design, unl ess otherwise specified. 2. in degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (v dda - drop voltage). 3. guaranteed by test in production. 4. the capacitive load must include a 100 nf capacitor in order to cut-off the high frequency noise. 5. to correctly control the vrefbuf inrush current during start-up phase and scaling change, the v dda voltage should be in the range [2.4 v to 3.6 v] and [2.8 v to 3.6 v] respectively for v rs = 0 and v rs = 1. table 83. vrefbuf characteristics (1) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 193/263 STM32L496XX electrical characteristics 236 6.3.20 comparator characteristics table 84. comp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v in comparator input voltage range -0-v dda v bg (2) scaler input voltage - v refint v sc scaler offset voltage - - 5 10 mv i dda (scaler) scaler static consumption from v dda brg_en=0 (bridge disable) - 200 300 na brg_en=1 (bridge enable) - 0.8 1 a t start_scaler scaler startup time - - 100 200 s t start comparator startup time to reach propagation delay specification high-speed mode v dda 2.7 v - - 5 s v dda < 2.7 v - - 7 medium mode v dda 2.7 v - - 15 v dda < 2.7 v - - 25 ultra-low-power mode - - 80 t d (3) propagation delay for 200 mv step with 100 mv overdrive high-speed mode v dda 2.7 v - 55 80 ns v dda < 2.7 v - 65 100 medium mode v dda 2.7 v - 0.55 0.9 s v dda < 2.7 v - 0.65 1 ultra-low-power mode - 5 12 v offset comparator offset error full common mode range --520mv v hys comparator hysteresis no hysteresis - 0 - mv low hysteresis - 8 - medium hysteresis - 15 - high hysteresis - 27 -
electrical characteristics STM32L496XX 194/263 docid029173 rev 2 6.3.21 operational ampl ifiers characteristics i dda (comp) comparator consumption from v dda ultra-low- power mode static - 400 600 na with 50 khz 100 mv overdrive square signal -1200- medium mode static - 5 7 a with 50 khz 100 mv overdrive square signal -6- high-speed mode static - 70 100 with 50 khz 100 mv overdrive square signal -75- i bias comparator input bias current ---- (4) na 1. guaranteed by design, unless otherwise specified. 2. refer to table 25: embedded internal voltage reference . 3. guaranteed by characterization results. 4. mostly i/o leakage when used in analog mode. refer to i lkg parameter in table 70: i/o static characteristics . table 84. comp characteristics (1) (continued) symbol parameter conditions min typ max unit table 85. opamp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage -1.8-3.6v cmir common mode input range -0-v dda v vi offset input offset voltage 25 c, no load on output. - - 1.5 mv all voltage/temp. - - 3 ? vi offset input offset voltage drift normal mode - 5 - v/c low-power mode - 10 - trimoffsetp trimlpoffsetp offset trim step at low common input voltage (0.1 ? v dda ) --0.81.1 mv trimoffsetn trimlpoffsetn offset trim step at high common input voltage (0.9 ? v dda ) --11.35
docid029173 rev 2 195/263 STM32L496XX electrical characteristics 236 i load drive current normal mode v dda 2 v - - 500 a low-power mode - - 100 i load_pga drive current in pga mode normal mode v dda 2 v - - 450 low-power mode - - 50 r load resistive load (connected to vssa or to vdda) normal mode v dda < 2 v 4- - k ? low-power mode 20 - - r load_pga resistive load in pga mode (connected to vssa or to v dda ) normal mode v dda < 2 v 4.5 - - low-power mode 40 - - c load capacitive load - - - 50 pf cmrr common mode rejection ratio normal mode - -85 - db low-power mode - -90 - psrr power supply rejection ratio normal mode c load 50 pf, r load 4 k ? dc 70 85 - db low-power mode c load 50 pf, r load 20 k ? dc 72 90 - gbw gain bandwidth product normal mode v dda 2.4 v (opa_range = 1) 550 1600 2200 khz low-power mode 100 420 600 normal mode v dda < 2.4 v (opa_range = 0) 250 700 950 low-power mode 40 180 280 sr (2) slew rate (from 10 and 90% of output voltage) normal mode v dda 2.4 v -700- v/ms low-power mode - 180 - normal mode v dda < 2.4 v -300- low-power mode - 80 - ao open loop gain normal mode 55 110 - db low-power mode 45 110 - v ohsat (2) high saturation voltage normal mode i load = max or r load = min input at v dda . v dda - 100 -- mv low-power mode v dda - 50 -- v olsat (2) low saturation voltage normal mode i load = max or r load = min input at 0. - - 100 low-power mode - - 50 m phase margin normal mode - 74 - low-power mode - 66 - table 85. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics STM32L496XX 196/263 docid029173 rev 2 gm gain margin normal mode - 13 - db low-power mode - 20 - t wakeup wake up time from off state. normal mode c load 50 pf, r load 4 k ? follower configuration -510 s low-power mode c load 50 pf, r load 20 k ? follower configuration -1030 i bias opamp input bias current general purpose input (all packages except ufbga132 and ufbga169 only) -- (3) na dedicated input (ufbga132 and ufbga169 only) t j 75 c - - 1 t j 85 c - - 3 t j 105 c - - 8 t j 125 c - - 15 pga gain (2) non inverting gain value - -2- - -4- -8- -16- r network r2/r1 internal resistance values in pga mode (4) pga gain = 2 - 80/80 - k ? /k ? pga gain = 4 - 120/ 40 - pga gain = 8 - 140/ 20 - pga gain = 16 - 150/ 10 - delta r resistance variation (r1 or r2) --15-15% pga gain error pga gain error - -1 - 1 % pga bw pga bandwidth for different non inverting gain gain = 2 - - gbw/ 2 - mhz gain = 4 - - gbw/ 4 - gain = 8 - - gbw/ 8 - gain = 16 - - gbw/ 16 - table 85. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 197/263 STM32L496XX electrical characteristics 236 en voltage noise density normal mode at 1 khz, output loaded with 4 k ? -500- nv/ hz low-power mode at 1 khz, output loaded with 20 k ? -600- normal mode at 10 khz, output loaded with 4 k ? -180- low-power mode at 10 khz, output loaded with 20 k ? -290- i dda (opamp) (2) opamp consumption from v dda normal mode no load, quiescent mode - 120 260 a low-power mode - 45 100 1. guaranteed by design, unless otherwise specified. 2. guaranteed by characterization results. 3. mostly i/o leakage, when used in analog mode. refer to i lkg parameter in table 70: i/o static characteristics . 4. r2 is the internal resistance between opamp output and opam p inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 table 85. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics STM32L496XX 198/263 docid029173 rev 2 6.3.22 temperature sensor characteristics 6.3.23 v bat monitoring characteristics table 86. ts characteristics symbol parameter min typ max unit t l (1) v ts linearity with temperature - 1 2 c avg_slope (2) average slope 2.3 2.5 2.7 mv/c v 30 voltage at 30c (5 c) (3) 0.742 0.76 0.785 v t start (ts_buf) (1) sensor buffer start-up time in continuous mode (4) -815s t start (1) start-up time when entering in continuous mode (4) -70120s t s_temp (1) adc sampling time when reading the temperature 5 - - s i dd (ts) (1) temperature sensor consumption from v dd , when selected by adc -4.77 a 1. guaranteed by design. 2. guaranteed by characterization results. 3. measured at v dda = 3.0 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte. refer to table 8: temperature sensor calibration values . 4. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. table 87. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -39-k ? qratio on v bat measurement - 3 - - er (1) 1. guaranteed by design. error on q -10 - 10 % t s_vbat (1) adc sampling time when reading the vbat 12 - - s table 88. v bat charging characteristics symbol parameter conditions min typ max unit r bc battery charging resistor vbrs = 0 - 5 - k ? vbrs = 1 - 1.5 -
docid029173 rev 2 199/263 STM32L496XX electrical characteristics 236 6.3.24 lcd controller characteristics the devices embed a built-in step-up converter to provide a constant lcd reference voltage independently from the v dd voltage. an external capacitor c ext must be connected to the vlcd pin to decouple this converter. table 89. lcd controller characteristics (1) symbol parameter conditions min typ max unit v lcd lcd external voltage - - 3.6 v v lcd0 lcd internal reference voltage 0 - 2.62 - v lcd1 lcd internal reference voltage 1 - 2.76 - v lcd2 lcd internal reference voltage 2 - 2.89 - v lcd3 lcd internal reference voltage 3 - 3.04 - v lcd4 lcd internal reference voltage 4 - 3.19 - v lcd5 lcd internal reference voltage 5 - 3.32 - v lcd6 lcd internal reference voltage 6 - 3.46 - v lcd7 lcd internal reference voltage 7 - 3.62 - c ext v lcd external capacitance buffer off (bufen=0 is lcd_cr register) 0.2 - 2 f buffer on (bufen=1 is lcd_cr register) 1-2 i lcd (2) supply current from v dd at v dd = 2.2 v buffer off (bufen=0 is lcd_cr register) -3- a supply current from v dd at v dd = 3.0 v buffer off (bufen=0 is lcd_cr register) -1.5- i vlcd supply current from v lcd (v lcd = 3 v) buffer off (buffen = 0, pon = 0) -0.5- a buffer on (buffen = 1, 1/2 bias) -0.6- buffer on (buffen = 1, 1/3 bias) -0.8- buffer on (buffen = 1, 1/4 bias) -1- r hn total high resistor value for low drive resistive network - 5.5 - m ? r ln total low resistor value for hig h drive resistive network - 240 - k ?
electrical characteristics STM32L496XX 200/263 docid029173 rev 2 6.3.25 dfsdm characteristics unless otherwise specified, the parameters given in table 90 for dfsdm are derived from tests performed under the ambient temperature, f apb2 frequency and v dd supply voltage conditions su mmarized in table 22: general operating conditions . ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? vdd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (dfsdm1_ckin y, dfsdm1_datiny, dfsdm1_ckout for dfsdm). v 44 segment/common highest level voltage - v lcd - v v 34 segment/common 3/4 level voltage - 3/4 v lcd - v 23 segment/common 2/3 level voltage - 2/3 v lcd - v 12 segment/common 1/2 level voltage - 1/2 v lcd - v 13 segment/common 1/3 level voltage - 1/3 v lcd - v 14 segment/common 1/4 level voltage - 1/4 v lcd - v 0 segment/common lowest level voltage - 0 - 1. guaranteed by design. 2. lcd enabled with 3 v internal step-up active, 1/8 duty, 1/4 bi as, division ratio= 64, all pi xels active, no lcd connected. table 89. lcd controller characteristics (1) (continued) symbol parameter conditions min typ max unit table 90. dfsdm characteristics (1) symbol parameter conditions min typ max unit f dfsdmclk dfsdm clock - - - f sysclk mhz f ckin (1/t ckin ) input clock frequency spi mode (sitp[1:0] = 01) - - 20 (f dfsdmclk /4) f ckout output clock frequency ---20mhz ducy ckout output clock frequency duty cycle -455055%
docid029173 rev 2 201/263 STM32L496XX electrical characteristics 236 t wh(ckin) t wl(ckin) input clock high and low time spi mode (sitp[1:0] = 01), external clock mode (spicksel[1:0] = 0) t ckin /2-0.5 t ckin /2 - ns t su data input setup time spi mode (sitp[1:0]=01), external clock mode (spicksel[1:0] = 0) 2- - t h data input hold time spi mode (sitp[1:0]=01), external clock mode (spicksel[1:0] = 0) 0- - t manchester manchester data period (recovered clock period) manchester mode (sitp[1:0] = 10 or 11), internal clock mode (spicksel[1:0] 0) (ckout div+1) ? t dfsdmclk - (2 ? ckoutdiv) ? t dfsdmclk 1. data based on characterization re sults, not tested in production. table 90. dfsdm characteristics (1) (continued) symbol parameter conditions min typ max unit
electrical characteristics STM32L496XX 202/263 docid029173 rev 2 figure 16: dfsdm timing diagram 6.3.26 timer characteristics the parameters given in the followi ng tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 06y9 63,&.6(/ 63,&.6(/ 63,&.6(/ ')6'0b&.287 w vx w zo w zk w u w i w k w vx w k 6,73 6,73 ')6'0b'$7$,1\ ')6'0b &.,1,1\ 63,&.6(/ w vx w k w vx w k 6,73 6,73 ')6'0b'$7$,1\ 6,73 6,73 5hfryhuhgforfn 5hfryhuhggdwd ')6'0b'$7$,1\ 0dqfkhvwhuwlplqj 63,wlplqj63,&.6(/ 63,wlplqj63,&.6(/ w zo w zk w u w i
docid029173 rev 2 203/263 STM32L496XX electrical characteristics 236 table 91. timx (1) characteristics 1. timx , is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17. symbol parameter conditions min max unit t res(tim) timer resolution time -1-t timxclk f timxclk = 80 mhz 12.5 - ns f ext timer external clock frequency on ch1 to ch4 -0f timxclk /2 mhz f timxclk = 80 mhz 0 40 mhz res tim timer resolution timx (except tim2 and tim5) -16 bit tim2 and tim5 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 80 mhz 0.0125 819.2 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 80 mhz - 53.68 s table 92. iwdg min/max timeout period at 32 khz (lsi) (1) 1. the exact timings still depend on the phasing of the apb in terface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 table 93. wwdg min/max timeout value at 80 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0512 3.2768 ms 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144
electrical characteristics STM32L496XX 204/263 docid029173 rev 2 6.3.27 communication interfaces characteristics i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to rm0351 reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still pr esent. only ft_f i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 94. i2c analog filter characteristics (1) 1. guaranteed by design. symbol paramete rminmaxunit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns
docid029173 rev 2 205/263 STM32L496XX electrical characteristics 236 spi characteristics unless otherwise specified, the parameters given in table 95 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 22: general operating conditions . ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 95. spi characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode receiver/full duplex 2.7 v < v dd < 3.6 v voltage range 1 -- 40 mhz master mode receiver/full duplex 1.71 v < v dd < 3.6 v voltage range 1 16 master mode transmitter 1.71 v < v dd < 3.6 v voltage range 1 40 slave mode receiver 1.71 v < v dd < 3.6 v voltage range 1 40 slave mode transmitter/full duplex 2.7 v < v dd < 3.6 v voltage range 1 31 (2) slave mode transmitter/full duplex 1.71 v < v dd < 3.6 v voltage range 1 18.5 (2) voltage range 2 13 1.08 v < v ddio2 < 1.32 v (3) 8 t su(nss) nss setup time slave mode, spi prescaler = 2 4 ? t pclk --ns t h(nss) nss hold time slave mode, spi prescaler = 2 2 ? t pclk --ns t w(sckh) t w(sckl) sck high and low time master mode t pclk -2 t pclk t pclk +2 ns t su(mi) data input setup time master mode 1 - - ns t su(si) slave mode 1.5 - - t h(mi) data input hold time master mode 5 - - ns t h(si) slave mode 1.5 - - t a(so) data output access time slave mode 9 - 34 ns t dis(so) data output disable time slave mode 9 - 16 ns
electrical characteristics STM32L496XX 206/263 docid029173 rev 2 figure 34. spi timing diagram - slave mode and cpha = 0 t v(so) data output valid time slave mode 2.7 v < v dd < 3.6 v voltage range 1 -1315.5 ns slave mode 1.71 v < v dd < 3.6 v voltage range 1 -1326.5 slave mode 1.71 v < v dd < 3.6 v voltage range 2 -1330 - slave mode 1.08 v < v ddio2 < 1.32 v (3) -2660 t v(mo) master mode - 4.5 6 t h(so) data output hold time slave mode 1.71 v < v dd < 3.6 v 7 - - t h(mo) master mode 0 - - 1. guaranteed by characterization results. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value can be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50 %. 3. spi mapped on port g. table 95. spi characteristics (1) (continued) symbol parameter conditions min typ max unit 06y9 166lqsxw &3+$ &32/ 6&.lqsxw &3+$ &32/ 0,62rxwsxw 026,lqsxw w vx6, w k6, w z6&./ w z6&.+ w f6&. w u6&. w k166 w glv62 w vx166 w d62 w y62 1h[welwv,1 /dvwelw287 )luvwelw,1 )luvwelw287 1h[welwv287 w k62 w i6&. /dvwelw,1
docid029173 rev 2 207/263 STM32L496XX electrical characteristics 236 figure 35. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . figure 36. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 06y9 166lqsxw &3+$ &32/ 6&.lqsxw &3+$ &32/ 0,62rxwsxw 026,lqsxw w vx6, w k6, w z6&./ w z6&.+ w vx166 w f6&. w d62 w y62 )luvwelw287 1h[welwv287 1h[welwv,1 /dvwelw287 w k62 w u6&. w i6&. w k166 w glv62 )luvwelw,1 /dvwelw,1 dlf 6&.2xwsxw &3+$ 026, 287387 0,62 ,13 87 &3+$ /6%287 /6%,1 &32/ &32/ % , 7287 166lqsxw w f6&. w z6&.+ w z6&./ w u6&. w i6&. w k0, +ljk 6&.2xwsxw &3+$ &3+$ &32/ &32/ w vx0, w y02 w k02 06%,1 %,7,1 06%287
electrical characteristics STM32L496XX 208/263 docid029173 rev 2 quad spi characteristics unless otherwise specified, the parameters given in table 96 and table 97 for quad spi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage condit ions summarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 15 or 20 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics. table 96. quad spi characteristics in sdr mode (1) symbol parameter conditions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 v < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 1.71 v < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 2.7 v < v dd < 3.6 v, c load = 15 pf voltage range 1 --60 1.71 v < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc=0 t (ck) /2 - t (ck) /2+1 ns t w(ckl) t (ck) /2-1 - t (ck) /2 t s(in) data input setup time voltage range 1 1.5 - - voltage range 2 3.5 - - t h(in) data input hold time voltage range 1 4 - - voltage range 2 6.5 - - t v(out) data output valid time voltage range 1 - 1 1.5 voltage range 2 - 3 5 t h(out) data output hold time voltage range 1 0 - - voltage range 2 0 - - 1. guaranteed by characterization results.
docid029173 rev 2 209/263 STM32L496XX electrical characteristics 236 table 97. quadspi characteristics in ddr mode (1) symbol parameter condit ions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 v < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 2 v < v dd < 3.6 v, c load = 20 pf voltage range 1 --48 1.71 v < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 1.71 v < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc= 1 t (ck) /2 - t (ck) /2+1 ns t w(ckl) t (ck) /2-1 - t (ck) /2 t sf(in) ;t sr(in) data input setup time voltage range 1 and 2 3.5 - - t hf(in) ; t hr(in) data input hold time 6.5 - - t vr(out) data output valid time on rise edge voltage range 1 dhhc = 0 - 4.5 5.5 dhhc = 1 t (ck) /2+1 t (ck) /2+1.5 voltage range 2 9.5 14 t vf(out) data output valid time on falling edge voltage range 1 dhhc = 0 - 56 dhhc = 1 t (ck) /2+1 t (ck) /2+1.5 voltage range 2 15 18 t hr(out) data output hold time on rise edge voltage range 1 dhhc = 0 4 - - dhhc = 1 t (ck) /2+0.5 - - voltage range 2 8 - - t hf(out) data output hold time on falling edge voltage range 1 dhhc = 0 3.5 - - dhhc = 1 t (ck) /2+0.5 - - voltage range 2 13 - 1. guaranteed by characterization results.
electrical characteristics STM32L496XX 210/263 docid029173 rev 2 figure 37. quad spi timing diagram - sdr mode figure 38. quad spi ti ming diagram - ddr mode 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w v,1 w k,1 w y287 w k287 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w vi,1 w ki,1 w yi287 w ku287 ' ' ' ' ' ' w yu287 w ki287 w vu,1 w ku,1
docid029173 rev 2 211/263 STM32L496XX electrical characteristics 236 sai characteristics unless otherwise specified, the parameters given in table 98 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage condi- tions summarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (ck,sd,fs). table 98. sai characteristics (1) symbol parameter conditions min max unit f mclk sai main clock output - - 50 mhz f ck sai clock frequency (2) master transmitter 2.7 v v dd 3.6 v voltage range 1 -21.5 mhz master transmitter 1.71 v v dd 3.6 v voltage range 1 -13.5 master receiver voltage range 1 -25 slave transmitter 2.7 v v dd 3.6 v voltage range 1 -20 slave transmitter 1.71 v v dd 3.6 v voltage range 1 -13.5 slave receiver voltage range 1 -25 voltage range 2 - 13 1.08 v v dd 1.32 v - 7 t v(fs) fs valid time master mode 2.7 v v dd 3.6 v -22 ns master mode 1.71 v v dd 3.6 v -40 t h(fs) fs hold time master mode 10 - ns t su(fs) fs setup time slave mode 1 - ns t h(fs) fs hold time slave mode 2 - ns t su(sd_a_mr) data input setup time master receiver 1 - ns t su(sd_b_sr) slave receiver 1 - t h(sd_a_mr) data input hold time master receiver 5 - ns t h(sd_b_sr) slave receiver 2 -
electrical characteristics STM32L496XX 212/263 docid029173 rev 2 figure 39. sai master timing waveforms t v(sd_b_st) data output valid time slave transmitter (after enable edge) 2.7 v v dd 3.6 v -25 ns slave transmitter (after enable edge) 1.71 v v dd 3.6 v -36 slave transmitter (after enable edge) 1.8 v < v dd <1.32 v -68 t h(sd_b_st) data output hold time slave transmitter (after enable edge) 10 - ns t v(sd_a_mt) data output valid time master transmitter (after enable edge) 2.7 v v dd 3.6 v -23 ns master transmitter (after enable edge) 1.71 v v dd 3.6 v -35 master transmitter (after enable edge) 1.08 v v dd 1.32 v -70 t h(sd_a_mt) data output hold time master tr ansmitter (after enable edge) 10 - ns 1. guaranteed by characterization results. 2. apb clock frequency must be at least twice sai clock frequency. table 98. sai characteristics (1) (continued) symbol parameter conditions min max unit -36 3!)?3#+?8 3!)?&3?8 output f 3#+ 3!)?3$?8 transmit t v&3 3lotn 3!)?3$?8 receive t h&3 3lotn t v3$?-4 t h3$?-4 3lotn t su3$?-2 t h3$?-2
docid029173 rev 2 213/263 STM32L496XX electrical characteristics 236 figure 40. sai slave timing waveforms sdmmc characteristics unless otherwise specified, the parameters given in table 99 for sdio are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output characteristics. table 99. sd / mmc dynamic characteristics, v dd =2.7 v to 3.6 v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 4/3 - t w(ckl) clock low time f pp = 50 mhz 8 10 - ns t w(ckh) clock high time f pp = 50 mhz 8 10 - ns cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs f pp = 50 mhz 2.5 - - ns t ih input hold time hs f pp = 50 mhz 2.5 - - ns cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs f pp = 50 mhz - 12 13 ns t oh output hold time hs f pp = 50 mhz 10 - - ns cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd f pp = 25 mhz 3.5 - - ns t ihd input hold time sd f pp = 25 mhz 3.5 - - ns -36 3!)?3#+?8 3!)?&3?8 input 3!)?3$?8 transmit t su&3 3lotn 3!)?3$?8 receive t w#+(?8 t h&3 3lotn t v3$?34 t h3$?34 3lotn t su3$?32 t w#+,?8 t h3$?32 f 3#+
electrical characteristics STM32L496XX 214/263 docid029173 rev 2 figure 41. sdio high-speed mode cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd f pp = 25 mhz - 3 5 ns t ohd output hold default time sd f pp = 25 mhz 0 - - ns 1. guaranteed by characterization results. table 100. emmc dynamic characteristics, v dd = 1.71 v to 1.9 v (1)(2) 1. guaranteed by characterization results. 2. c load = 20pf. symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/f pclk2 frequency ratio - - - 4/3 - t w(ckl) clock low time f pp = 50 mhz 8 10 - ns t w(ckh) clock high time f pp = 50 mhz 8 10 - ns cmd, d inputs (reference d to ck) in emmc mode t isu input setup time hs f pp = 50 mhz 2.5 - - ns t ih input hold time hs f pp = 50 mhz 2.5 - - ns cmd, d outputs (referenced to ck) in emmc mode t ov output valid time hs f pp = 50 mhz - 13.5 16.5 ns t oh output hold time hs f pp = 50 mhz 9 - - ns table 99. sd / mmc dynamic characteristics, v dd =2.7 v to 3.6 v (1) (continued) symbol parameter conditions min typ max unit t 7#+( #+ $#-$ output $#-$ input t # t 7#+, t /6 t /( t )35 t )( t f t r ai
docid029173 rev 2 215/263 STM32L496XX electrical characteristics 236 figure 42. sd default mode usb characteristics the STM32L496XX usb interface is fully complia nt with the usb specification version 2.0 and is usb-if certified (for full-speed device operation). can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 101. usb electri cal characteristics symbol parameter conditions min typ max unit v ddusb usb transceiver operating voltage 3.0 (1) 1. the STM32L496XX usb functionality is ensured down to 2.7 v but not the full usb electrical characteristics which are degraded in the 2.7-to-3.0 v voltage range. -3.6v r pui embedded usb_dp pull-up value during idle 900 1250 1600 ? r pur embedded usb_dp pull-up value during reception 1400 2300 3200 z drv (2) 2. guaranteed by design. output driver impedance (3) 3. no external termination series resistors are r equired on usb_dp (d+) and usb_dm (d-); the matching impedance is already included in the embedded driver. driving high and low 28 36 44 ? ai #+ $#-$ output t /6$ t /($
electrical characteristics STM32L496XX 216/263 docid029173 rev 2 6.3.28 fsmc characteristics unless otherwise specified, the parameters given in table 102 to table 115 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage cond itions summarized in table 22 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output characteristics. asynchronous waveforms and timings figure 43 through figure 46 represent asynchronous waveforms and table 102 through table 109 provide the corresponding timings. the results shown in these tables are obtained with the follo wing fmc configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode, datasetuptime = 0x5) ? busturnaroundduration = 0x0 in all timing tables, the thclk is the hclk clock period.
docid029173 rev 2 217/263 STM32L496XX electrical characteristics 236 figure 43. asynchronous non-multiplexed sram/psram/nor read waveforms $ata &-#?.% &-#?.",;= &-#?$;= t v",?.% t h$ata?.% &-#?./% !ddress &-#?!;= t v!?.% &-#?.7% t su$ata?.% t w.% -36 w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics STM32L496XX 218/263 docid029173 rev 2 table 102. asynchronous non-multiplexed sram/psram/nor read timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 2t hclk -1 2t hclk +1 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 0.5 t w(noe) fmc_noe low time 2t hclk -1 2t hclk +1 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 0.5 t h(a_noe) address hold time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - t su(data_ne) data to fmc_nex high setup time t hclk -1 - t su(data_noe) data to fmc_noex high setup time t hclk -1 - t h(data_noe) data hold time after fmc_noe high 0 - t h(data_ne) data hold time after fmc_nex high 0 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk +1 table 103. asynchronous non-multiplexed sram/psram/nor read-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 7t hclk -1 7t hclk +1 ns t w(noe) fmc_nwe low time 5t hclk -1 5t hclk +1 t w(nwait) fmc_nwait low time t hclk -0.5 - t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
docid029173 rev 2 219/263 STM32L496XX electrical characteristics 236 figure 44. asynchronous non-multiplexed sram/psram/nor write waveforms table 104. asynchronous non-multiplexe d sram/psram/nor write timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk -1 3t hclk +1 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk -1 t hclk +1 t w(nwe) fmc_nwe low time t hclk -1.5 t hclk + 0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk - t v(a_ne) fmc_nex low to fmc_a valid - 0 t h(a_nwe) address hold time after fmc_nwe high t hclk -0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk -0.5 - t v(data_ne) data to fmc_nex low to data valid - t hclk +3 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk +1 .", $ata &-#?.%x &-#?.",;= &-#?$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#?!;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% th!?.7% t h",?.7% t v$ata?.% t w.% -36 &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics STM32L496XX 220/263 docid029173 rev 2 figure 45. asynchronous multiplexed psram/nor read waveforms table 105. asynchronous non-multiplexed sram/psram/nor write-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk -1 8t hclk +1 ns t w(nwe) fmc_nwe low time 6t hclk -1.5 6t hclk +0.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk -1 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +2 - .", $ata &-#? .",;= &-#? !$;= t v",?.% t h$ata?.% !ddress &-#? !;= t v!?.% &-#?.7% t v!?.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t su$ata?.% t h!$?.!$6 &-#? .% &-#?./% t w.% t w./% t v./%?.% t h.%?./% t h!?./% t h",?./% t su$ata?./% t h$ata?./% &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid029173 rev 2 221/263 STM32L496XX electrical characteristics 236 table 106. asynchronous multiplexed psram/nor read timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk -1 3t hclk +1 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk 2t hclk +0.5 t w(noe) fmc_noe low time t hclk - 1 t hclk +1 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 0.5 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 0.5 t w(nadv) fmc_nadv low time t hclk - 0.5 t hclk +1 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high t hclk + 0.5 - t h(a_noe) address hold time after fmc_noe high t hclk - 0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t su(data_ne) data to fmc_nex high setup time t hclk -1 - t su(data_noe) data to fmc_noe high setup time t hclk -1 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - table 107. asynchronous multiplexed psram/nor read-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk + 1 8t hclk + 1 ns t w(noe) fmc_nwe low time 5t hclk - 1.5 5t hclk + 0.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +0.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
electrical characteristics STM32L496XX 222/263 docid029173 rev 2 figure 46. asynchronous multip lexed psram/nor write waveforms table 108. asynchronous multip lexed psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk -1 4t hclk +1 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk -1 t hclk +1 t w(nwe) fmc_nwe low time 2xt hclk -0.5 2xt hclk + 0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk -0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 0 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 0.5 t w(nadv) fmc_nadv low time t hclk t hclk +1 t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high t hclk + 0.5 - t h(a_nwe) address hold time after fmc_nwe high t hclk + 0.5 - t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk - 0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t v(data_nadv) fmc_nadv high to data valid - t hclk +3 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - .", $ata &-#? .%x &-#? .",;= &-#? !$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#? !;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% t h!?.7% t h",?.7% t v!?.% t w.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t v$ata?.!$6 t h!$?.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid029173 rev 2 223/263 STM32L496XX electrical characteristics 236 synchronous waveforms and timings figure 47 through figure 50 represent synchronous waveforms and table 110 through table 113 provide the corresponding timings. the results shown in these tables are obtained with the following fmc configuration: ? burstaccessmode = fmc_ burstaccessmode_enable ? memorytype = fmc_memorytype_cram ? writeburst = fmc_writeburst_enable ? clkdivision = 1 ? datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period. 1. cl = 30 pf. 2. guaranteed by characterization results. table 109. asynchronous multiple xed psram/nor write-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk - 1 9t hclk + 1 ns t w(nwe) fmc_nwe low time 7t hclk - 0.5 7t hclk + 0.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk + 2 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk - 1 -
electrical characteristics STM32L496XX 224/263 docid029173 rev 2 figure 47. synchronous multiplexed nor/psram read timings &-#?#,+ &-#?.%x &-#?.!$6 &-#?!;= &-#?./% &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, td#,+( .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( td#,+( !)6 t d#,+, ./%, td#,+( ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36
docid029173 rev 2 225/263 STM32L496XX electrical characteristics 236 table 110. synchronous multipl exed nor/psram read timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk -0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 1 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 4.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 1.5 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk +0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 1 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 3.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 -
electrical characteristics STM32L496XX 226/263 docid029173 rev 2 figure 48. synchronous multiplexed psram write timings 06y9 )0&b&/. )0&b1([ )0&b1$'9 )0&b$>@ )0&b1:( )0&b$'>@ $'>@ ' ' )0&b1:$,7 :$,7&)* e :$,732/e w z&/. w z&/. 'dwdodwhqf\ %867851 w g&/./1([/ w g&/.+1([+ w g&/./1$'9/ w g&/./$9 w g&/./1$'9+ w g&/.+$,9 w g&/.+1:(+ w g&/./1:(/ w g&/.+1%/+ w g&/./$'9 w g&/./$',9 w g&/./'dwd w vx1:$,79&/.+ w k&/.+1:$,79 w g&/./'dwd )0&b1%/
docid029173 rev 2 227/263 STM32L496XX electrical characteristics 236 table 111. synchronous multiplexed psram write timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk - 0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk + 0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 1 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 4.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 1.5 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk + 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 3.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low - 2 t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk + 0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 -
electrical characteristics STM32L496XX 228/263 docid029173 rev 2 figure 49. synchronous non-multiplexed nor/psram read timings table 112. synchronous non-multiplexed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk - 0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 4 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 1.5 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk -0.5 - t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 1 - t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 3.5 - &-#?#,+ &-#?.%x &-#?!;= &-#?./% &-#?$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency t d#,+, .%x, t d#,+( .%x( t d#,+, !6 t d#,+( !)6 t d#,+, ./%, t d#,+( ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36 &-#?.!$6 t d#,+, .!$6, t d#,+, .!$6(
docid029173 rev 2 229/263 STM32L496XX electrical characteristics 236 figure 50. synchronous non-multi plexed psram write timings t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - ns t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 - 1. cl = 30 pf. 2. guaranteed by characterization results. table 112. synchronous non-multiplexed nor/psram read timings (1)(2) (continued) symbol parameter min max unit 06y9 )0&b&/. )0&b1([ )0&b$>@ )0&b1:( )0&b'>@ ' ' )0&b1:$,7 :$,7&)* e:$,732/e w z&/. w z&/. 'dwdodwhqf\ w g&/./1([/ w g&/.+1([+ w g&/./$9 w g&/.+$,9 w g&/.+1:(+ w g&/./1:(/ w g&/./'dwd w vx1:$,79&/.+ w k&/.+1:$,79 )0&b1$'9 w g&/./1$'9/ w g&/./1$'9+ w g&/./'dwd )0&b1%/ w g&/.+1%/+
electrical characteristics STM32L496XX 230/263 docid029173 rev 2 nand controller waveforms and timings figure 51 through figure 54 represent synchronous waveforms, and table 114 and table 115 provide the corresponding timings. the results shown in these tables are obtained with the following fmc configuration: ? com.fmc_setuptime = 0x01 ? com.fmc_waitsetuptime = 0x03 ? com.fmc_holdsetuptime = 0x02 ? com.fmc_hizsetuptime = 0x01 ? att.fmc_setuptime = 0x01 ? att.fmc_waitsetuptime = 0x03 ? att.fmc_holdsetuptime = 0x02 ? att.fmc_hizsetuptime = 0x01 ? bank = fmc_bank_nand ? memorydatawidth = fmc_memorydatawidth_16b ? ecc = fmc_ecc_enable ? eccpagesize = fmc_eccpagesize_512bytes ? tclrsetuptime = 0 ? tarsetuptime = 0 in all timing tables, the t hclk is the hclk clock period. table 113. synchronous non-mul tiplexed psram write timings (1)(2) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk -0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 4 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 1.5 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk +1 - t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 3 t d(clkl-nbll) fmc_clk low to fmc_nbl low 1.5 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk +0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 - 1. cl = 30 pf. 2. guaranteed by characterization results.
docid029173 rev 2 231/263 STM32L496XX electrical characteristics 236 figure 51. nand controller waveforms for read access figure 52. nand controller waveforms for write access figure 53. nand controller waveforms for common memory read access 06y9 )0&b1:( )0&b12(15( )0&b'>@ w vx'12( w k12(' $/()0&b$ &/()0&b$ )0&b1&([ w g1&(12( w k12($/( 06y9 w k1:(' w y1:(' )0&b1:( )0&b12(15( )0&b'>@ $/()0&b$ &/()0&b$ )0&b1&([ w g1&(1:( w k1:($/( 06y9 )0&b1:( )0&b12( )0&b'>@ w z12( w vx'12( w k12(' $/()0&b$ &/()0&b$ )0&b1&([ w g1&(12( w k12($/(
electrical characteristics STM32L496XX 232/263 docid029173 rev 2 figure 54. nand controller wavefo rms for common memory write access 6.3.29 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 116 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage table 114. switching characteristics for nand flash read cycles (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(n0e) fmc_noe low width 4t hclk -0.5 4t hclk +0.5 ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high 12 - t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 0 - t d(nce-noe) fmc_nce valid before fmc_noe low - 3t hclk +1 t h(noe-ale) fmc_noe high to fmc_ale invalid 4t hclk -2 - table 115. switching characteri stics for nand fl ash write cycles (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(nwe) fmc_nwe low width 4t hclk -0.5 4t hclk +0.5 ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid 5 - t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 2t hclk -1 - t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5t hclk -1 - t d(nce_nwe) fmc_nce valid before fmc_nwe low - 3t hclk +1 t h(nwe-ale) fmc_nwe high to fmc_ale invalid 2t hclk -2 - 06y9 w z1:( w k1:(' w y1:(' )0&b1:( )0&b12( )0&b'>@ w g'1:( $/()0&b$ &/()0&b$ )0&b1&([ w g1&(1:( w k12($/(
docid029173 rev 2 233/263 STM32L496XX electrical characteristics 236 summarized in table 21 , with the following configuration: ? dcmi_pixclk polarity: falling ? dcmi_vsync and dcmi_hsync polarity: high ? data format: 14 bits ? capacitive load c=30pf figure 55. dcmi timing diagram table 116. dcmi characteristics (1) 1. data based on characterization results, not tested in production. symbol paramete rminmaxunit frequency ratio dcmi_pixclk/f hclk -0.4 dcmi_pixclk pixel clock input - 32 mhz d pixel pixel clock input duty cycle 30 70 % t su(data) data input setup time 4 - ns t h(data) data hold time 5 - t su(hsync) , t su(vsync) dcmi_hsync/dcmi_vsync input setup time 3- t h(hsync) , t h(vsync) dcmi_hsync/dcmi_vsync input hold time 3 - 069 '&0,b3,;&/. w vx96<1& w vx+6<1& '&0,b+6<1& '&0,b96<1& '$7$>@ '&0,b3,;&/. w k+6<1& w k+6<1& w vx'$7$ w k'$7$
electrical characteristics STM32L496XX 234/263 docid029173 rev 2 6.3.30 swpmi characteristics the single wire protocol master interf ace (swpmi) and the associated swpmi_io transceiver are compliant with the etsi ts 102 613 technical specification. 6.3.31 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 118 for the sdio/mmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 22 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output characteristics. figure 56. sdio high-speed mode table 117. swpmi electrical characteristics symbol parameter conditions min typ max unit t swpstart swpmi regulator startup time swp class b 2.7 v v dd 3,3v - - 300 s t swpbit swp bit duration v core voltage range 1 500 - - ns v core voltage range 2 620 - - t 7#+( #+ $#-$ output $#-$ input t # t 7#+, t /6 t /( t )35 t )( t f t r ai
docid029173 rev 2 235/263 STM32L496XX electrical characteristics 236 figure 57. sd default mode ai #+ $#-$ output t /6$ t /($ table 118. sd / mmc dynamic characteristics, v dd =2.7 v to 3.6 v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode 0 50 mhz - sdio_ck/fpclk2 frequency ratio - - 4/3 - t w(ckl) clock low time fpp =50 mhz 8 10 - ns t w(ckh) clock high time fpp =50 mhz 8 10 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp =50 mhz 2.5 - - ns t ih input hold time hs fpp =50 mhz 2.5 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp =50 mhz - 12 13 ns t oh output hold time hs fpp =50 mhz 10 - - cmd, d inputs (referenced to ck) in sd default mode tisud input setup time sd fpp =25 mhz 3.5 - - ns tihd input hold time sd fpp =25 mhz 3 - - cmd, d outputs (referenced to ck) in sd default mode tovd output valid default time sd fpp =25 mhz - 3 5 ns tohd output hold default time sd fpp =25 mhz 0 - - 1. guaranteed by characterization results. table 119. sd / mmc dynamic characteristics, v dd =1.71 v to 1.9 v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 4/3 - t w(ckl) clock low time f pp = 50 mhz 8 10 - ns t w(ckh) clock high time f pp = 50 mhz 8 10 - ns
electrical characteristics STM32L496XX 236/263 docid029173 rev 2 cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs f pp = 50 mhz 2.5 - - ns t ih input hold time hs f pp = 50 mhz 2.5 - - ns cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs f pp = 50 mhz - 13.5 16.5 ns t oh output hold time hs f pp = 50 mhz 9 - - ns cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd f pp = 50 mhz 2 - - ns t ihd input hold time sd f pp = 50 mhz 4.5 - - ns cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd f pp = 50 mhz - 4.5 5 ns t ohd output hold default time sd f pp = 50 mhz 0 - - ns 1. guaranteed by characterization results. table 119. sd / mmc dyna mic characteristics, v dd =1.71 v to 1.9 v (1) (continued) symbol parameter conditions min typ max unit
docid029173 rev 2 237/263 STM32L496XX package information 260 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 ufbga169 package information figure 58. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 120. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.1 10 0.0020 0.0031 0.0043 a2 0.400 0.450 0.50 0 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.37 0 0.0106 0.0126 0.0146 $<9b0(b9 6hdwlqjsodqh $ $ $ h ) ) h 1 $ %277209,(: ( ' 7239,(: ?eedoov < ; < hhh ? 0 iii ? 0 = = ; $edoo lghqwlilhu $edoo lqgh[duhd e ' ( $ $ = = ggg 6,'(9,(:
package information STM32L496XX 238/263 docid029173 rev 2 figure 59. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array recommend ed footprint note: non-solder mask defined (nsmd) pads are recommended. note: 4 to 6 mils solder paste screen printing process. b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - f 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 121. ufbga169 recommended p cb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 mm dpad 0.27 mm dsm 0.35 mm typ. (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter. table 120. ufbga169 - 169-ball, 7 x 7 mm, 0. 50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 069 'vp 'sdg
docid029173 rev 2 239/263 STM32L496XX package information 260 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 60. ufbga169 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 3urgxfwlghqwlilfdwlrq 670/ $*, :: < $ 'dwhfrgh 3lqlghqwlilhu
package information STM32L496XX 240/263 docid029173 rev 2 figure 61. ufbga169, external smps device, marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 3urgxfwlghqwlilfdwlrq 670/ $*,3 :: < % 'dwhfrgh 3lqlghqwlilhu
docid029173 rev 2 241/263 STM32L496XX package information 260 7.2 lqfp144 package information figure 62. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 1. drawing is not to scale. h ,'(17,),&$7,21 3,1 *$8*(3/$1( pp 6($7,1* 3/$1( ' ' ' ( ( ( . fff & & $b0(b9 $ $ $ / / f e $
package information STM32L496XX 242/263 docid029173 rev 2 table 122. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.6890 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031
docid029173 rev 2 243/263 STM32L496XX package information 260 figure 63. lqfp144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. dlh
package information STM32L496XX 244/263 docid029173 rev 2 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 64. lqfp144 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. figure 65. lqfp144, external smps device, marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 'dwhfrgh 3lqlghqwlilhu 670/=*7 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh <:: 2swlrqdojdwhpdun % 06y9 'dwhfrgh 3lqlghqwlilhu 670/=*73 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh <:: 2swlrqdojdwhpdun %
docid029173 rev 2 245/263 STM32L496XX package information 260 7.3 ufbga132 package information figure 66. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package outline 1. drawing is not to scale. table 123. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 0.600 - - 0.0236 a1 - - 0.110 - - 0.0043 a2 - 0.450 - - 0.0177 - a3 - 0.130 - - 0.0051 0.0094 a4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 d 6.850 7.000 7.150 0.2697 0.2756 0.2815 d1 - 5.500 - - 0.2165 - e 6.850 7.000 7.150 0.2697 0.2756 0.2815 e1 - 5.500 - - 0.2165 - 8)%*$b$*b0(b9 6($7,1* 3/$1( $ $ h = = ' $ hhh & $ % iii ?eedoov ? ? 0 0 0 ( 7239,(: %277209,(: h $ $ & $ % $edoolghqwlilhu e ' ( ggg & $
package information STM32L496XX 246/263 docid029173 rev 2 figure 67. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package recommended footprint e - 0.500 - - 0.0197 - z - 0.750 - - 0.0295 - ddd - 0.080 - - 0.0031 - eee - 0.150 - - 0.0059 - fff - 0.050 - - 0.0020 - 1. values in inches are converted from mm and rounded to 4 decimal digits. table 124. ufbga132 recommended p cb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 mm dpad 0.280 mm dsm 0.370 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.280 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.100 mm ball diameter 0.280 mm table 123. ufbga132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 8)%*$b$*b)3b9 'sdg 'vp
docid029173 rev 2 247/263 STM32L496XX package information 260 device marking the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 68. ufbga132 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh %doo$lqghqwlilhu 670/ 4*, <zz $
package information STM32L496XX 248/263 docid029173 rev 2 7.4 lqfp100 package information figure 69. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. table 125. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0. 6220 0.6299 0.6378 d1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0. 6220 0.6299 0.6378 e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).'0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b !
docid029173 rev 2 249/263 STM32L496XX package information 260 figure 70. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. e1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 125. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
package information STM32L496XX 250/263 docid029173 rev 2 figure 71. lqfp100 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu 670/ 9&7$ 2swlrqdojdwhpdun <zz
docid029173 rev 2 251/263 STM32L496XX package information 260 7.5 wlcsp100 package information figure 72.wlcsp100l ? 4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. 2. dimension is measured at the maximum bum p diameter parallel to primary datum z. 3. primary datum z and seating plane are defined by the spherical crowns of the bump. 4. bump position designation per jesd 95-1, spp-010. $ . $'b0(b9 $25,(17$7,21 5()(5(1&( %277209,(: %8036,'( 6,'(9,(: 7239,(: :$)(5%$&.6,'( '(7$,/$ '(7$,/$ h h ' h ( * ) h ' ( ; ddd %803 hhh = 6($7,1* 3/$1( = = =;< e; $
package information STM32L496XX 252/263 docid029173 rev 2 figure 73. wlcsp100l ? 100l, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale package recommended footprint table 126. wlcsp100l ?4.618 x 4.142 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0. 0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - ? b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.008 7 0.0098 0.0110 d 4.583 4.618 4.653 0. 1804 0.1818 0.1832 e 4.107 4.142 4.177 0. 1617 0.1631 0.1644 e - 0.400 - - 0.0157 - e1 - 3.600 - - 0.1417 - e2 - 3.600 - - 0.1417 - f - 0.509 - - 0.0200 - g - 0.271 - - 0.0107 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - :/&63/b$4b)3b9 'sdg 'vp
docid029173 rev 2 253/263 STM32L496XX package information 260 figure 74. wlcsp100l marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 127. wlcsp100l recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 mm dpad 0.225 mm dsm 0.290 mm stencil thickness 0.1 mm 06y9 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu 6//< <zz $ h
package information STM32L496XX 254/263 docid029173 rev 2 figure 75. wlcsp100, external smps de vice, marking (package top view) 06y9 3urgxfwlghqwlilfdwlrq 'dwhfrgh 3lq lqghqwlilhu /9*3 <zz % h
docid029173 rev 2 255/263 STM32L496XX package information 260 7.6 lqfp64 package information figure 76. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 128. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - :b0(b9 $ $ $ 6($7,1*3/$1( fff & e & f $ / / . ,'(17,),&$7,21 3,1 ' ' ' h ( ( ( *$8*(3/$1( pp
package information STM32L496XX 256/263 docid029173 rev 2 figure 77. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 128. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max aic
docid029173 rev 2 257/263 STM32L496XX package information 260 figure 78. lqfp64 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 06y9 'dwhfrgh 3lqlghqwlilhu 670/ 5&7 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh $ < ::
package information STM32L496XX 258/263 docid029173 rev 2 7.7 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of all i ddxxx and v ddxxx , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v ddiox ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.7.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.7.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm32l4 96xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature ra nge will be best suited to the application. table 129. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient ufbga169 - 7 7 mm 52 c/w thermal resistance junction-ambient lqfp144 - 20 20 mm 32 thermal resistance junction-ambient ufbga132 - 7 7 mm 55 thermal resistance junction-ambient wlcsp100 35.8 thermal resistance junction-ambient lqfp100 - 14 14mm 42 thermal resistance junction-ambient lqfp64 45
docid029173 rev 2 259/263 STM32L496XX package information 260 the following examples show how to calculat e the temperature range needed for a given application. example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 129 t jmax is calculated as follows: ? for lqfp100, 42 c/w t jmax = 82 c + (42 c/w 447 mw) = 82 c + 18.774 c = 100.774 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see section 8: part numbering . in this case, parts must be ordered at least with the temperature range suffix 6 (see part numbering). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 3). suffix 6: t amax = t jmax - (42c/w 447 mw) = 105-18.774 = 86.226 c suffix 3: t amax = t jmax - (42c/w 447 mw) = 130-18.774 = 111.226 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 129 t jmax is calculated as follows: ? for lqfp100, 42 c/w t jmax = 100 c + (42 c/w 134 mw) = 100 c + 5.628 c = 105.628 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c).
package information STM32L496XX 260/263 docid029173 rev 2 in this case, parts must be ordered at leas t with the temperature range suffix 3 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts.
docid029173 rev 2 261/263 STM32L496XX part numbering 262 8 part numbering table 130. STM32L496XX ordering information scheme example: stm32 l 496 v g t 6 p tr device family stm32 = arm ? based 32-bit microcontroller product type l = ultra-low-power device subfamily 496: STM32L496XX pin count r = 64 pins v = 100 pins q = 132 pins z = 144 pins a = 169 pins flash memory size g = 1 mb of flash memory e = 512 kbyte of flash memory package t = lqfp ecopack ? 2 i = ufbga ecopack ? 2 y = csp ecopack ? 2 temperature range 6 = industrial temperature range, -40 to 85 c (105 c junction) 3 = industrial temperature range, -40 to 125 c (130 c junction) option blank = standard production with integrated ldo p = dedicated pinout supporting external smps packing tr = tape and reel xxx = programmed parts
revision history STM32L496XX 262/263 docid029173 rev 2 9 revision history table 131. document revision history date revision changes 22-feb-2017 1 initial release. 02-may-2017 2 updated: ? features in cover page, section 2: description , section 6.1.7: current consumption measurement , section 6.3.17: analog-to-digital converter characteristics , section 7.7: thermal characteristics , section 7.7.2: selectin g the product temperature range ? table 2: STM32L496XX family device features and peripheral counts , table 22: general operating conditions , table 44: current consumption in stop 2 mode , table 45: current consumption in stop 1 mode , table 47: current consumption in standby mode , table 48: current consumption in shutdown mode , table 51: low-power mode wakeup timings , table 61: lsi oscillator characteristics , table 81: dac characteristics , table 130: STM32L496XX ordering information scheme ? note 1. on figure 32
docid029173 rev 2 263/263 STM32L496XX 263 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved

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