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| this is information on a product in full production. march 2016 docid027692 rev 2 1/193 stm32l475xx ultra-low-power arm ? cortex ? -m4 32-bit mcu+fpu, 100dmips, up to 1mb flash, 128 kb sr am, usb otg fs, analog, audio datasheet - production data features ? ultra-low-power with flexpowercontrol ? 1.71 v to 3.6 v power supply ? -40 c to 85/105/125 c temperature range ? 300 na in v bat mode: supply for rtc and 32x32-bit backup registers ? 30 na shutdown mode (5 wakeup pins) ? 120 na standby mode (5 wakeup pins) ? 420 na standby mode with rtc ? 1.1 a stop 2 mode, 1.4 a stop 2 with rtc ? 100 a/mhz run mode ? batch acquisition mode (bam) ? 4 s wakeup from stop mode ? brown out reset (bor) in all modes except shutdown ? interconnect matrix ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0- wait-state execution from flash memory, frequency up to 80 mhz, mpu, 100dmips/1.25dmips/mhz (dhrystone 2.1), and dsp instructions ? clock sources ? 4 to 48 mhz crystal oscillator ? 32 khz crystal oscillator for rtc (lse) ? internal 16 mhz factory-trimmed rc (1%) ? internal low-power 32 khz rc (5%) ? internal multispeed 100 khz to 48 mhz oscillator, auto-trimmed by lse (better than 0.25 % accuracy) ? 3 plls for system clock, usb, audio, adc ? rtc with hw calendar, alarms and calibration ? up to 21 capacitive sensing channels: support touchkey, linear and ro tary touch sensors ? 16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in stop mode), 2x watchdogs, systick timer ? up to 114 fast i/os, most 5 v-tolerant, up to 14 i/os with independent supply down to 1.08 v ? memories ? up to 1 mb flash, 2 banks read-while- write, proprietary code readout protection ? up to 128 kb of sram including 32 kb with hardware parity check ? external memory interface for static memories supporting sram, psram and nor memories ? quad spi memory interface ? 4x digital filters for sigma delta modulator ? rich analog peripherals (independent supply) ? 3 12-bit adc 5 msps, up to 16-bit with hardware oversampling, 200 a/msps ? 2x 12-bit dac, low-power sample and hold ? 2x operational amplifiers with built-in pga ? 2x ultra-low-power comparators ? 18x communication interfaces ? usb otg 2.0 full-speed, lpm and bcd ? 2x sais (serial audio interface) ?3x i2c fm+(1 mbi t/s), smbus/pmbus ? 6x usarts (iso 7816, lin, irda, modem) ? 3x spis (4x spis with the quad spi) ? can (2.0b active) and sdmmc interface ? swpmi single wire pr otocol master i/f ? 14-channel dma controller ? true random number generator ? crc calculation unit, 96-bit unique id ? development support: serial wire debug (swd), jtag, embedded trace macrocell? table 1. device summary reference part number stm32l475xx stm32l475rg, stm32l475vg, STM32L475RE, stm32l475ve, stm32l475rc, stm32l475vc lqfp100 (14 x 14) lqfp64 (10 x 10) www.st.com
contents stm32l475xx 2/193 docid027692 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 arm ? cortex ? -m4 core with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 15 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 18 3.9 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9.5 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9.6 vbat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.11 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.12 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.13 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.14 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.14.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 35 3.14.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 35 3.15 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.15.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.15.2 internal voltage reference (vrefint) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.15.3 vbat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.16 digital to analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 docid027692 rev 2 3/193 stm32l475xx contents 5 3.17 voltage reference buffer (vrefbuf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18 comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.19 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.21 digital filter for sigma-delta modulators (dfsdm) . . . . . . . . . . . . . . . . . . 40 3.22 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.23 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.23.1 advanced-control timer (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.23.2 general-purpose timers (tim2, tim3, tim4, tim5, tim15, tim16, tim17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.23.3 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.4 low-power timer (lptim1 and lptim2) . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.5 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.6 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.23.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.24 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 44 3.25 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.26 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 46 3.27 low-power universal asynchronous rece iver transmitter (lpuart) . . . . 47 3.28 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.29 serial audio interfaces (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.30 single wire protocol master interface (swpmi) . . . . . . . . . . . . . . . . . . . . 49 3.31 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.32 secure digital input/output and multimediacards interface (sdmmc) . . . 50 3.33 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 50 3.34 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 51 3.35 quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.36 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.36.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.36.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 contents stm32l475xx 4/193 docid027692 rev 2 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 85 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 85 6.3.4 embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.6 wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.16 analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.3.17 analog-to-digital converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 134 6.3.18 digital-to-analog converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 147 6.3.19 voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.21 operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.3.24 dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.25 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 docid027692 rev 2 5/193 stm32l475xx contents 5 6.3.26 communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 161 6.3.27 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.1 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 188 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 list of tables stm32l475xx 6/193 docid027692 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32l475xx family device features and periphera l counts . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 16 table 4. stm32l475 modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 table 5. functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. stm32l475xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. dma implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 11. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. stm32l475xx usart/uart/lpuart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. sai implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 14. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. stm32l475xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) . . . . . . . . . . . . . . . . . . . . . 65 table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) . . . . . . . . . . . . . . . . . . . . . 70 table 18. stm32l475xx memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 19. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 20. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 21. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 22. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 23. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 24. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 25. embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 table 26. current consumption in run and lo w-power run modes, code with data processing running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . . 90 table 27. current consumption in run and low-power run modes, code with data processing running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 28. current consumption in run and lo w-power run modes, code with data processing running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 29. typical current consumption in run a nd low-power run modes, with different codes running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . . 93 table 30. typical current consumption in run a nd low-power run modes, with different codes running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 31. typical current consumption in run a nd low-power run modes, with different codes running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 32. current consumption in sleep and low-power sleep modes, flash on . . . . . . . . . . . . . . 95 table 33. current consumption in low-power sleep modes, flash in power-down . . . . . . . . . . . . . . 96 table 34. current consumption in stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 35. current consumption in stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 36. current consumption in stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 37. current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 38. current consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 39. current consumption in vbat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 40. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 41. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 docid027692 rev 2 7/193 stm32l475xx list of tables 8 table 42. regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 43. wakeup time using usart/lpuart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 44. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 45. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 46. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 47. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 48. hsi16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 49. msi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 50. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 51. pll, pllsai1, pllsai2 characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 52. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 53. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 54. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 55. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 56. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 table 57. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 58. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 59. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 60. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 61. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 62. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 63. analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 64. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 65. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 66. adc accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 67. adc accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 68. adc accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 69. adc accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 70. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 71. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 72. vrefbuf characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 73. comp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 74. opamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 75. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 76. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 77. v bat charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 78. dfsdm characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 79. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 80. iwdg min/max timeout period at 32 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 81. wwdg min/max timeout value at 80 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 82. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 83. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 84. quad spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 85. quadspi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 86. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 87. sd / mmc dynamic characteristics, vdd=2.7 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 88. emmc dynamic characteristics, vdd = 1.71 v to 1.9 v . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 89. usb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 90. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 91. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 175 table 92. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 93. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 177 list of tables stm32l475xx 8/193 docid027692 rev 2 table 94. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 95. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 96. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 98. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 99. stm32l475xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 100. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 docid027692 rev 2 9/193 stm32l475xx list of figures 9 list of figures figure 1. stm32l475xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4. voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 5. stm32l475vx lqfp100 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 6. stm32l475rx lqfp64 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 7. stm32l475 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 12. vrefint versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 13. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 14. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 15. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 figure 16. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 17. hsi16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 18. typical current consumption versus msi frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 19. i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 20. i/o ac characteristics definition (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 21. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 22. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 23. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 24. 12-bit buffered / non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 25. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 26. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 27. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 64 figure 28. quad spi timing diagram - sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 29. quad spi timing diagram - ddr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 30. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 31. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 32. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 33. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 34. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 174 figure 35. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 176 figure 36. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 37. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 38. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 182 figure 39. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 40. lqfp100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 41. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 185 figure 42. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 43. lqfp64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 44. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 introduction stm32l475xx 10/193 docid027692 rev 2 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32l475xx microcontrollers. this document should be read in conjun ction with the stm32l4x5 reference manual (rm0395). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from the www.arm.com website. docid027692 rev 2 11/193 stm32l475xx description 53 2 description the stm32l475xx devices are the ultra-low- power microcontrollers based on the high- performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 80 mhz. the cortex-m4 core features a floating point un it (fpu) single precision which supports all arm single-precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protec tion unit (mpu) which enhances application security. the stm32l475xx devices embed high-speed memories (flash memory up to 1 mbyte, up to 128 kbyte of sram), a flexible external memory controller (fsmc) for static memories (for devices with 100 pins package), a quad spi flash memories interface (available on all packages) and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. the stm32l475xx devices embed several pr otection mechanisms for embedded flash memory and sram: readout protection, writ e protection, proprietary code readout protection and firewall. the devices offer up to three fast 12-bit adcs (5 msps), two comparators, two operational amplifiers, two dac channels, an internal vo ltage reference buffer, a low-power rtc, two general-purpose 32-bit timer, two 16-bit pw m timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. the devices support four digital filters for external sigma delta modulators (dfsdm). in addition, up to 21 capacitive sensing channels are available. they also feature standard and advanced communication interfaces. ? three i2cs ? three spis ? three usarts, two uarts and one low-power uart. ? two sais (serial audio interfaces) ? one sdmmc ? one can ? one usb otg full-speed ? one swpmi (single wire protocol master interface) the stm32l475xx operates in the -40 to +85 c (+105 c junction), -40 to +105 c (+125 c junction) and -40 to +125 c (+130 c junction) temperature ranges from a 1.71 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low- power applications. some independent power supplies are supported: analog independent supply input for adc, dac, opamps and comparators, 3.3 v dedicated supply input for usb and up to 14 i/os can be supplied independently down to 1.08v . a vbat input allows to backup the rtc and backup registers. the stm32l475xx family offers two packages from 64-pin to 100-pin packages. description stm32l475xx 12/193 docid027692 rev 2 table 2. stm32l475xx family device features and peripheral counts peripheral stm32l475vx stm32l475rx flash memory 256kb 512kb 1mb 256kb 512kb 1mb sram 128 kb external memory controller for static memories yes (1) no quad spi yes timers advanced control 2 (16-bit) general purpose 5 (16-bit) 2 (32-bit) basic 2 (16-bit) low -power 2 (16-bit) systick timer 1 watchdog timers (independent, window) 2 comm. interfaces spi 3 i 2 c3 usart uart lpuart 3 2 1 sai 2 can 1 usb otg fs yes sdmmc yes swpmi yes digital filters for sigma-delta modulators yes (4 filters) number of channels 8 rtc yes tamper pins 3 2 random generator yes gpios wakeup pins nb of i/os down to 1.08 v 82 5 0 51 4 0 capacitive sensing number of channels 21 12 12-bit adcs number of channels 3 16 3 16 12-bit dac channels 2 internal voltage reference buffer yes no analog comparator 2 operational amplifiers 2 max. cpu frequency 80 mhz operating voltage 1.71 to 3.6 v operating temperature ambient operating temperature: -40 to 85 c / -40 to 105 c / -40 to 125 c junction temperature: -40 to 105 c / -40 to 125 c / -40 to 130 c packages lqfp100 lqfp64 docid027692 rev 2 13/193 stm32l475xx description 53 1. for the lqfp100 package, only fmc bank1 is av ailable. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. description stm32l475xx 14/193 docid027692 rev 2 figure 1. stm32l475xx block diagram note: af: alternate function on i/o pins. 0 6 y 9 ) o d v k x s w r 0 % * 3 , 2 3 2 5 7 $ $ + % $ 3 % ( ; 7 , 7 : . 8 3 $ ) 3 $ > @ 7 , 0 3 : 0 f r p s o f k d q q h o v 7 , 0 b & + > @ 1 f k d q q h o v 7 , 0 b & + > @ ( 7 5 % . , 1 % . , 1 d v $ ) 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) $ 3 % 0 + ] $ 3 % 0 + ] 2 8 7 , 7 ) : : ' * 5 7 & b 7 6 2 6 & b , 1 2 6 & b 2 8 7 v p f d u g l u ' $ e 6 ' , 2 0 0 & ' > @ & 0 ' & . d v $ ) 9 % $ 7 w r 9 - 7 $ * 6 : $ 5 0 & r u w h [ 0 0 + ] ) 3 8 1 9 , & ( 7 0 0 3 8 ' 0 $ $ 5 7 $ & & ( / & $ & + ( ) , ) 2 # 9 ' ' $ % 2 5 6 x s s o \ v x s h u y l v l r q 3 9 ' 3 9 0 , q w u h v h w ; 7 $ / n + ] 0 $ 1 $ * 7 5 7 & ) & / . 6 w d q g e \ l q w h u i d f h , : ' * # 9 % $ 7 # 9 ' ' # 9 ' ' $ : 8 5 h v h w f o r f n f r q w u r o 3 & / . [ 9 r o w d j h u h j x o d w r u w r 9 9 ' ' 3 r z h u p d q d j h p h q w # 9 ' ' 5 7 & b 7 $ 0 3 [ % d f n x s u h j l v w h u $ + % e x v p d w u l [ 7 , 0 f k d q q h o v f r p s o f k d q q h o % . , 1 d v $ ) ' $ & ' $ & 7 , 0 7 , 0 ' % 8 6 $ 3 % 0 + ] p d [ 6 5 $ 0 . % 6 5 $ 0 . % , % 8 6 6 % 8 6 ' 0 $ 3 % > @ 3 & > @ 3 ' > @ 3 ( > @ 3 + > @ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' * 3 , 2 3 2 5 7 ( * 3 , 2 3 2 5 7 + 7 , 0 3 : 0 e e 7 , 0 e 7 , 0 e f r p s o f k d q q h o v 7 , 0 b & + > @ 1 f k d q q h o v 7 , 0 b & + > @ ( 7 5 % . , 1 % . , 1 d v $ ) f k d q q h o f r p s o f k d q q h o % . , 1 d v $ ) f k d q q h o f r p s o f k d q q h o % . , 1 d v $ ) 2 8 7 e e $ + % $ 3 % 2 6 & b , 1 2 6 & b 2 8 7 + & / . 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e f k d q q h o v 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) v p f d u g l u ' $ 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) v p f d u g l u ' $ 5 ; 7 ; & 7 6 5 7 6 d v $ ) 8 $ 5 7 5 ; 7 ; & 7 6 5 7 6 d v $ ) 8 $ 5 7 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 3 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 3 , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 0 % 8 6 ) , ) 2 7 ; 5 ; d v $ ) e [ & $ 1 9 2 8 7 9 , 1 0 9 , 1 3 2 s $ p s 2 s $ p s # 9 ' ' $ 9 2 8 7 9 , 1 0 9 , 1 3 / 3 8 $ 5 7 5 ; 7 ; & 7 6 5 7 6 d v $ ) 6 : 3 0 , , 2 5 ; 7 ; 6 8 6 3 ( 1 ' d v $ ) / 3 7 , 0 , 1 , 1 2 8 7 ( 7 5 d v $ ) / 3 7 , 0 , 1 2 8 7 ( 7 5 d v $ ) 5 1 * ) o h [ l e o h v w d w l f p h p r u \ f r q w u r o o h u ) 6 0 & 6 5 $ 0 3 6 5 $ 0 1 2 5 ) o d v k 1 $ 1 ' ) o d v k & / . 1 ( 1 / 1 % / > @ $ > @ ' > @ 1 2 ( 1 : ( 1 : $ , 7 d v $ ) 4 x d g 6 3 , p h p r u \ l q w h u i d f h % . b , 2 > @ & / . 1 & 6 , 7 ) $ ' & $ ' & docid027692 rev 2 15/193 stm32l475xx functional overview 53 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc processor features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32l475xx family is compatible with all arm tools and software. figure 1 shows the general block diagram of the stm32l475xx family devices. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 processors. it balances the in herent performance advantage of the arm ? cortex ? -m4 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor near 100 dmips performance at 80mhz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 80 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. functional overview stm32l475xx 16/193 docid027692 rev 2 3.4 embedded flash memory stm32l475xx devices feature up to 1 mbyte of embedded flash memory available for storing programs and data. the flash memory is divided into two banks allowing read- while-write operations. this feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. the dual bank boot is also supported. each bank contains 256 pages of 2 kbyte. flexible protections can be configured thanks to option bytes: ? readout protection (rdp) to protect the wh ole memory. three levels are available: ? level 0: no readout protection ? level 1: memory readout protection: th e flash memory cannot be read from or written to if either debug features are co nnected, boot in ram or bootloader is selected ? level 2: chip readout protection: debug features (cortex-m4 jtag and serial wire), boot in ram and bootloader sele ction are disabled (jtag fuse). this selection is irreversible. ? write protection (wrp): the protected ar ea is protected against erasing and programming. two areas per bank can be selected, with 2-kbyte granularity. ? proprietary code readout protection (pcro p): a part of the flash memory can be protected against read and write from third pa rties. the protected area is execute-only: it can only be reached by the stm32 cpu, as an instruction co de, while all other accesses (dma, debug and cpu data read, wr ite and erase) are strictly prohibited. one area per bank can be selected, with 64-b it granularity. an additional option bit (pcrop_rdp) allows to select if the pcro p area is erased or not when the rdp protection is changed from level 1 to level 0. table 3. access status versus readout protection level and execution modes area protection level user execution debug, boot from ram or boot from system memory (loader) read write erase read write erase main memory 1 yes yes yes no no no 2 yes yes yes n/a n/a n/a system memory 1 yes no no yes no no 2 yes no no n/a n/a n/a option bytes 1 yes yes yes yes yes yes 2 yes no no n/a n/a n/a backup registers 1yesyesn/a (1) 1. erased when rdp change from level 1 to level 0. no no n/a (1) 2 yes yes n/a n/a n/a n/a sram2 1 yes yes yes (1) no no no (1) 2 yes yes yes n/a n/a n/a docid027692 rev 2 17/193 stm32l475xx functional overview 53 the whole non-volatile memory embeds the error correction code (ecc) feature supporting: ? single error detection and correction ? double error detection. ? the address of the ecc fail can be read in the ecc register 3.5 embedded sram stm32l475xx devices feature up to 128 kbyte of embedded sram. this sram is split into two blocks: ? 96 kbyte mapped at address 0x2000 0000 (sram1) ? 32 kbyte located at address 0x1000 0000 with hardware parity check (sram2). this block is accessed through the icode/dcode buses for maximum performance. these 32 kbyte sram can also be retained in standby mode. the sram2 can be write-protec ted with 1 kbyte granularity. the memory can be accessed in read/writ e at cpu clock speed with 0 wait states. 3.6 firewall the device embeds a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. each illegal access generates a reset which kills immediat ely the detected intrusion. the firewall main features are the following: ? three segments can be protected and de fined thanks to the firewall registers: ? code segment (located in flash or sram 1 if defined as ex ecutable protected area) ? non-volatile data segment (located in flash) ? volatile data segment (located in sram1) ? the start address and the length of each segments are configurable: ? code segment: up to 1024 kbyte with granularity of 256 bytes ? non-volatile data segment: up to 1024 kbyte with granularity of 256 bytes ? volatile data segment: up to 96 kbyte with a granularity of 64 bytes ? specific mechanism implemented to open th e firewall to get access to the protected areas (call gate entry sequence) ? volatile data segment can be shared or not with the non-protected code ? volatile data segment can be executed or not depending on the firewall configuration the flash readout protection must be set to le vel 2 in order to reach the expected level of protection. functional overview stm32l475xx 18/193 docid027692 rev 2 3.7 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart, i2c, spi, can and usb otg fs in device mode through dfu (device firmware upgrade). 3.8 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.9 power supply management 3.9.1 power supply schemes ? v dd = 1.71 to 3.6 v: external power supply for i/os (v ddio1 ), the internal regulator and the system analog such as reset, power mana gement and internal clocks. it is provided externally through v dd pins. ? v dda = 1.62 v (adcs/comps) / 1.8 (dacs/opamps ) to 3.6 v: external analog power supply for adcs, dacs, opamps, comparators and voltage reference buffer. the v dda voltage level is independent from the v dd voltage. ? v ddusb = 3.0 to 3.6 v: external independent power supply for usb transceivers. the v ddusb voltage level is independent from the v dd voltage. ? v bat = 1.55 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. note: when the functions supplied by v dda or v ddusb are not used, these supplies should preferably be shorted to v dd . note: if these supplies are tied to ground, the i/os supplied by these power supplies are not 5 v tolerant (refer to table 19: voltage characteristics ). note: v ddiox is the i/os general purpos e digital functions supply. v ddiox represents v ddio1 , with v ddio1 = v dd . docid027692 rev 2 19/193 stm32l475xx functional overview 53 figure 2. power supply overview 3.9.2 power supply supervisor the device has an integrated ultra-low-power brown-out reset (bor) active in all modes except shutdown and ensuring proper operation after power-on and during power down. the device remains in reset mode when the monitored supply voltage v dd is below a specified threshold, without the need for an external reset circuit. the lowest bor level is 1.71 v at power on, and other higher thresholds can be selected through option bytes.the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and co mpares it to the vpvd threshold. an interrupt can be generated when v dd drops below the vpvd th reshold and/or when v dd is higher than the vpvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. in addition, the devices embeds a peripheral voltage monitor which compares the independent supply voltages v dda , v ddusb with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 0 6 y 9 % d f n x s g r p d l q 6 w d q g e \ f l u f x l w u \ : d n h x s o r j l f , : ' * 9 r o w d j h u h j x o d w r u & r u h 6 5 $ 0 6 5 $ 0 ' l j l w d o s h u l s k h u d o v / r z y r o w d j h g h w h f w r u / 6 ( f u \ v w d o . r v f % . 3 u h j l v w h u v 5 & & % ' & 5 u h j l v w h u 5 7 & , 2 u l q j 9 & 2 5 ( g r p d l q 7 h p s v h q v r u 5 h v h w e o r f n [ 3 / / + 6 , 0 6 , + 6 , ) o d v k p h p r u \ 9 ' ' , 2 9 ' ' g r p d l q 9 & 2 5 ( 9 6 6 9 ' ' 9 % $ 7 9 ' ' $ g r p d l q [ ' $ f r q y h u w h u v [ $ ' f r q y h u w h u v [ f r p s d u d w r u v [ r s h u d w l r q d o d p s o l i l h u 9 r o w d j h u h i h u h q f h e x i i h u 8 6 % w u d q v f h l y h u v 9 ' ' 8 6 % 9 ' ' $ 9 6 6 $ 9 6 6 functional overview stm32l475xx 20/193 docid027692 rev 2 3.9.3 voltage regulator two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (mr) and the low-power regulator (lpr). ? the mr is used in the run and sleep modes and in the stop 0 mode. ? the lpr is used in low-power run, low-power sleep, stop 1 and stop 2 modes. it is also used to supply the 32 kbyte sram2 in standby with ram2 retention. ? both regulators are in power-down in standby and shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the ultralow-power stm32l475xx supports dynam ic voltage scaling to optimize its power consumption in run mode. the voltage from the main regulator that supplies the logic (vcore) can be adjusted according to the system?s maximum operating frequency. there are two power consumption ranges: ? range 1 with the cpu running at up to 80 mhz. ? range 2 with a maximum cpu frequency of 26 mhz. all peripheral clocks are also limited to 26 mhz. the vcore can be supplied by the low-power r egulator, the main regulator being switched off. the system is then in low-power run mode. ? low-power run mode with the cpu running at up to 2 mhz. peripherals with independent clock can be clocked by hsi16. 3.9.4 low-power modes the ultra-low-power stm32l475xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources: stm32l475xx functional overview docid027692 rev 2 21/193 table 4. stm32l475 modes overview mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time run range 1 yes on (4) on any all n/a 112 a/mhz n/a range2 all except otg_fs, rng 100 a/mhz lprun lpr yes on (4) on any except pll all except otg_fs, rng n/a 136 a/mhz to range 1: 4 s to range 2: 64 s sleep range 1 no on (4) on (5) any all any interrupt or event 37 a/mhz 6 cycles range 2 all except otg_fs, rng 35 a/mhz 6 cycles lpsleep lpr no on (4) on (5) any except pll all except otg_fs, rng any interrupt or event 40 a/mhz 6 cycles stop 0 range 1 no off on lse lsi bor, pvd, pvm rtc,iwdg compx (x=1,2) dacx (x=1,2) opampx (x=1,2) usartx (x=1...5) (6) lpuart1 (6) i2cx (x=1...3) (7) lptimx (x=1,2) *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc,iwdg compx (x=1..2) usartx (x=1...5) (6) lpuart1 (6) i2cx (x=1...3) (7) lptimx (x=1,2) otg_fs (8) swpmi1 (9) 108 a 0.7 s in sram 4.5 s in flash range 2 functional overview stm32l475xx 22/193 docid027692 rev 2 stop 1 lpr no off on lse lsi bor, pvd, pvm rtc,iwdg compx (x=1,2) dacx (x=1,2) opampx (x=1,2) usartx (x=1...5) (6) lpuart1 (6) i2cx (x=1...3) (7) lptimx (x=1,2) *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc,iwdg compx (x=1..2) usartx (x=1...5) (6) lpuart1 (6) i2cx (x=1...3) (7) lptimx (x=1,2) otg_fs (8) swpmi1 (9) 6.6 a w/o rtc 6.9 a w rtc 4 s in sram 6 s in flash stop 2 lpr no off on lse lsi bor, pvd, pvm rtc,iwdg compx (x=1..2) i2c3 (7) lpuart1 (6) lptim1 *** all other peripherals are frozen. reset pin, all i/os bor, pvd, pvm rtc,iwdg compx (x=1..2) i2c3 (7) lpuart1 (6) lptim1 1.1 a w/o rtc 1.4 a w/rtc 5 s in sram 7 s in flash table 4. stm32l475 modes overview (continued) mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time stm32l475xx functional overview docid027692 rev 2 23/193 standby lpr powered off off sram2 on lse lsi bor, rtc, iwdg *** all other peripherals are powered off. *** i/o configuration can be floating, pull-up or pull-down reset pin 5 i/os (wkupx) (10) bor, rtc, iwdg 0.35 a w/o rtc 0.65 a w/ rtc 14 s off powered off 0.12 a w/o rtc 0.42 a w/ rtc shutdown off powered off off powered off lse rtc *** all other peripherals are powered off. *** i/o configuration can be floating, pull-up or pull-down (11) reset pin 5 i/os (wkupx) (10) rtc 0.03 a w/o rtc 0.33 a w/ rtc 256 s 1. lpr means main regulator is off and low-power regulator is on. 2. all peripherals can be active or cl ock gated to save power consumption. 3. typical current at v dd = 1.8 v, 25c. consumptions values provided running from sram , flash memory off, 80 mhz in range 1, 26 mhz in range 2, 2 mhz i n lprun/lpsleep. 4. the flash memory can be put in power-down and its clock can be gated off when executing from sram. 5. the sram1 and sram2 clocks can be gated on or off independently. 6. u(s)art and lpuart reception is functional in stop mode, an d generates a wakeup interrupt on start, address match or received frame event. 7. i2c address detection is functional in stop mode, and generates a wakeup interrupt in case of address match. 8. otg_fs wakeup by resume from susp end and attach detection protocol event. 9. swpmi1 wakeup by resume from suspend. 10. the i/os with wakeup from standby/shutdown capability are: pa0, pc13, pe6, pa2, pc5. 11. i/os can be configured with internal pul l-up, pull-down or floating in shutdown mode but the configuration is lost when exit ing the shutdown mode. table 4. stm32l475 modes overview (continued) mode regulator (1) cpu flash sram clocks dma & peripherals (2) wakeup source consumption (3) wakeup time functional overview stm32l475xx 24/193 docid027692 rev 2 by default, the microcontroller is in run mode af ter a system or a power reset. it is up to the user to select one of the low-power modes described below: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? low-power run mode this mode is achieved with vcore supplied by the low-power regu lator to minimize the regulator's operating current. the code ca n be executed from sram or from flash, and the cpu frequency is limited to 2 mhz. the peripherals with independent clock can be clocked by hsi16. ? low-power sleep mode this mode is entered from the low-power run mode. only the cpu clock is stopped. when wakeup is triggered by an event or an interrupt, the system reverts to the low- power run mode. ? stop 0, stop 1 and stop 2 modes stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the vcore domain are stopped, the pll, the msi rc, the hsi16 rc and the hse crystal oscilla tors are disabled. the lse or lsi is still running. the rtc can remain active (stop mode with rtc, stop mode without rtc). some peripherals with wakeup capability can enable the hsi16 rc during stop mode to detect their wakeup condition. three stop modes are available: stop 0, stop 1 and stop 2 modes. in stop 2 mode, most of the vcore domain is put in a lower leakage mode. stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than stop 2. in stop 0 mode, the main regulator remains on, allowing a very fast wakeup time but with much higher consumption. the system clock when exiting from stop 0, stop1 or stop2 modes can be either msi up to 48 mhz or hsi16, depending on software configuration. ? standby mode the standby mode is used to achieve t he lowest power consumption with bor. the internal regulator is switched off so that the vcore domain is powered off. the pll, the msi rc, the hsi16 rc and the hse crystal oscillators are also switched off. the rtc can remain active (standby mo de with rtc, standby mode without rtc). the brown-out reset (bor) always remains active in standby mode. the state of each i/o during standby mode can be selected by software: i/o with internal pull-up, internal pull-down or floating. after entering standby mode, sram1 and register contents are lost except for registers in the backup domain and standby circuitry. optionally, sram2 can be retained in docid027692 rev 2 25/193 stm32l475xx functional overview 53 standby mode, supplied by the low-power regulator (standby with ram2 retention mode). the device exits standby mode when an external reset (nrst pin), an iwdg reset, wkup pin event (configurable rising or fallin g edge), or an rtc event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on lse (css on lse). the system clock after wakeup is msi up to 8 mhz. ? shutdown mode the shutdown mode allows to achieve the lowest power consumption. the internal regulator is switched off so that the vc ore domain is powered off. the pll, the hsi16, the msi, the lsi and the hse oscillators are also switched off. the rtc can remain active (shutdown mode with rtc, shutdown mode without rtc). the bor is not available in shutdown mode . no power voltage monitoring is possible in this mode, therefore the switch to backup domain is not supported. sram1, sram2 and register contents are lost except for registers in the backup domain. the device exits shutdown mode when an external reset (nrst pin), a wkup pin event (configurable rising or falling edge), or an rtc ev ent occurs (alarm, periodic wakeup, timestamp, tamper). the system clock after wakeup is msi at 4 mhz. functional overview stm32l475xx 26/193 docid027692 rev 2 table 5. functionalities depending on the working mode (1) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability cpu y - y - - -- -- -- -- flash memory (up to 1 mb) o (2) o (2) o (2) o (2) - -- -- -- -- sram1 (up to 96 kb) yy (3) yy (3) y -y -- -- -- sram2 (32 kb) y y (3) yy (3) y -y -o (4) -- -- fsmc oooo- -- -- -- -- quad spi o o o o - -- -- -- -- backup registers y y y y y -y -y -y -y brown-out reset (bor) yyyyy yy yy y- -- programmable voltage detector (pvd) ooooo oo o- -- -- peripheral voltage monitor (pvmx; x=1,2,3,4) ooooo oo o- -- -- dma oooo- -- -- -- -- high speed internal (hsi16) oooo (5) - (5) -- -- -- high speed external (hse) oooo- -- -- -- -- low speed internal (lsi) ooooo -o -o -- -- low speed external (lse) ooooo -o -o -o -o multi-speed internal (msi) oooo- -- -- -- -- clock security system (css) oooo- -- -- -- -- clock security system on lse ooooo oo oo o- -- rtc / auto wakeup o o o o o oo oo oo oo number of rtc tamper pins 33333 o3 o3 o3 o3 docid027692 rev 2 27/193 stm32l475xx functional overview 53 usb otg fs o (8) o (8) --- o- -- -- -- usartx (x=1,2,3,4,5) ooooo (6) o (6) - -- -- -- low-power uart (lpuart) ooooo (6) o (6) o (6) o (6) - -- -- i2cx (x=1,2) o o o o o (7) o (7) - -- -- -- i2c3 ooooo (7) o (7) o (7) o (7) - -- -- spix (x=1,2,3) o o o o - -- -- -- -- can oooo- -- -- -- -- sdmmc1 oooo- -- -- -- -- swpmi1 o o o o - o- -- -- -- saix (x=1,2) o o o o - -- -- -- -- dfsdm oooo- -- -- -- -- adcx (x=1,2,3) o o o o - -- -- -- -- dacx (x=1,2) o o o o o -- -- -- -- vrefbuf o o o o o -- -- -- -- opampx (x=1,2) o o o o o -- -- -- -- compx (x=1,2) ooooo oo o- -- -- temperature sensor o o o o - -- -- -- -- timers (timx) o o o o - -- -- -- -- low-power timer 1 (lptim1) ooooo oo o- -- -- low-power timer 2 (lptim2) ooooo o- -- -- -- independent watchdog (iwdg) ooooo oo oo o- -- window watchdog (wwdg) oooo- -- -- -- -- systick timer o o o o - -- -- -- -- touch sensing controller (tsc) oooo- -- -- -- -- random number generator (rng) o (8) o (8) --- -- -- -- -- table 5. functionalities depending on the working mode (1) (continued) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability functional overview stm32l475xx 28/193 docid027692 rev 2 3.9.5 reset mode in order to improve the consumption under reset, the i/os state under and after reset is ?analog state? (the i/o schmitt trigger is disabl e). in addition, the internal reset pull-up is deactivated when the reset source is internal. 3.9.6 vbat operation the vbat pin allows to power the device vbat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. the vbat pin supplies the rtc with lse and the backup registers. three anti- tamper detection pins are available in vbat mode. vbat operation is automatically activated when v dd is not present. an internal vbat battery charging circuit is embedded and can be activated when v dd is present. note: when the microcontroller is supplied from vba t, external interrupts and rtc alarm/events do not exit it from vbat operation. crc calculation unit oooo- -- -- -- -- gpios ooooo oo o (9) 5 pins (10) (11) 5 pins (10) - 1. legend: y = yes (enable). o = optional (disable by default. can be enabled by software). - = not available. 2. the flash can be configured in power-down m ode. by default, it is not in power-down mode. 3. the sram clock can be gated on or off. 4. sram2 content is preserved when the bit rrs is set in pwr_cr3 register. 5. some peripherals with wakeup from stop capability can r equest hsi16 to be enabled. in this case, hsi16 is woken up by the peripheral, and only feeds the peripheral which requested it. hsi16 is automatically put of f when the peripheral does not need it anymore. 6. uart and lpuart reception is functional in stop mode, and generates a wakeup interrupt on start, address match or received frame event. 7. i2c address detection is functional in stop mode, and generates a wakeup interrupt in case of address match. 8. voltage scaling range 1 only. 9. i/os can be configured with internal pul l-up, pull-down or floating in standby mode. 10. the i/os with wakeup from standby/shutdown capability are: pa0, pc13, pe6, pa2, pc5. 11. i/os can be configured with internal pul l-up, pull-down or floating in shutdown mode but the configuration is lost when exiting the shutdown mode. table 5. functionalities depending on the working mode (1) (continued) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown vbat - wakeup capability - wakeup capability - wakeup capability - wakeup capability docid027692 rev 2 29/193 stm32l475xx functional overview 53 3.10 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. depending on peripherals, these interconnecti ons can operate in run, sleep, low-power run and sleep, stop 0, stop 1 and stop 2 modes. table 6. stm32l475xx peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2 timx timx timers synchronization or chaining y y y y - - adcx dacx dfsdm conversion triggers y y y y - - dma memory to memory transfer trigger y y y y - - compx comparator output blanking y y y y - - compx tim1, 8 tim2, 3 timer input channel, trigger, break from analog signals comparison yyyy - - lptimerx low-power timer triggered by analog signals comparison yyyyy y (1) adcx tim1, 8 timer triggered by analog watchdog y y y y - - rtc tim16 timer input channel from rtc events y y y y - - lptimerx low-power timer triggered by rtc alarms or tampers yyyyy y (1) all clocks sources (internal and external) tim2 tim15, 16, 17 clock source used as input channel for rc measurement and trimming yyyy - - usb tim2 timer triggered by usb sof y y - - - - css cpu (hard fault) ram (parity error) flash memory (ecc error) compx pvd dfsdm (analog watchdog, short circuit detection) tim1,8 tim15,16,17 timer break y y y y - - functional overview stm32l475xx 30/193 docid027692 rev 2 gpio timx external trigger y y y y - - lptimerx external trigger y y y y y y (1) adcx dacx dfsdm conversion external trigger y y y y - - 1. lptim1 only. table 6. stm32l475xx peripherals interconnect matrix (continued) interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2 docid027692 rev 2 31/193 stm32l475xx functional overview 53 3.11 clocks and startup the clock controller (see figure 3 ) distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robust ness. it features: ? clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source: four different clock sources can be used to drive the master clock sysclk: ? 4-48 mhz high-speed external crystal or ceramic resonator (hse) , that can supply a pll. the hse can also be configured in bypass mode for an external clock. ? 16 mhz high-speed internal rc oscillator (h si16), trimmable by software, that can supply a pll ? multispeed internal rc oscillator (msi), tr immable by software, able to generate 12 frequencies from 100 khz to 48 mhz. when a 32.768 khz clock source is available in the system (lse), the msi fr equency can be automatically trimmed by hardware to reach better than 0.25% accuracy. in this mode the msi can feed the usb device, saving the need of an exte rnal high-speed crystal (hse). the msi can supply a pll. ? system pll which can be fed by hse, hsi16 or msi, with a maximum frequency at 80 mhz. ? auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: ? 32.768 khz low-speed external crystal (lse), supporting four drive capability modes. the lse can also be configured in bypass mode for an external clock. ? 32 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock accura cy is 5% accuracy. ? peripheral clock sources: several peripherals (usb, sdmmc, rng, sai, usarts, i2cs, lptimers, adc, swpmi) have their ow n independent clock whatever the system clock. three plls, each having three i ndependent outputs allowing the highest flexibility, can generate independent cl ocks for the adc, the usb/sdmmc/rng and the two sais. ? startup clock: after reset, the microcontroller restar ts by default with an internal 4 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master clock is automatically switched to hsi16 and a software functional overview stm32l475xx 32/193 docid027692 rev 2 interrupt is generated if enabled. lse failure can also be detected and generated an interrupt. ? clock-out capability: ? mco: microcontroller clock output: it outputs one of the internal clocks for external use by the application ? lsco: low speed clock output: it outputs lsi or lse in all low-power modes (except vbat). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the ma ximum frequency of the ahb and the apb domains is 80 mhz. docid027692 rev 2 33/193 stm32l475xx functional overview 53 figure 3. clock tree 0 6 y 9 6 < 6 & / . 0 & 2 / 6 & 2 3 / / 6 $ , b ( ; 7 & / . 0 + ] f o r f n w r 8 6 % 5 1 * 6 ' 0 0 & w r $ ' & w r , : ' * w r 5 7 & w r 3 : 5 + & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ ) & / . & r u w h [ i u h h u x q q l q j f o r f n w r & r u w h [ v \ v w h p w l p h u w r $ 3 % s h u l s k h u d o v w r $ 3 % s h u l s k h u d o v 3 & / . 3 & / . w r 6 $ , w r 6 $ , / 6 ( + 6 , 6 < 6 & / . w r 8 6 $ 5 7 [ ; w r / 3 8 $ 5 7 w r , & [ [ w r / 3 7 , 0 [ [ 6 $ , b ( ; 7 & / . w r 6 : 3 0 , w r 7 , 0 [ [ 2 6 & b 2 8 7 2 6 & b , 1 0 6 , + 6 , + 6 ( + 6 , / 6 , / 6 ( + 6 ( 6 < 6 & / . + 6 ( 0 6 , + 6 , 0 6 , 6 < 6 & / . / 6 ( 2 6 & n + ] $ + % 3 5 ( 6 & $ 3 % 3 5 ( 6 & [ r u [ + 6 , 6 < 6 & / . / 6 , / 6 ( + 6 , + 6 , $ 3 % 3 5 ( 6 & w r 7 , 0 [ [ [ r u [ w r 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 4 5 3 / / 6 $ , 3 4 5 3 / / 6 $ , 3 4 5 0 0 6 , 5 & n + ] 0 + ] + 6 , 5 & 0 + ] + 6 ( 2 6 & 0 + ] & o r f n g h w h f w r u 2 6 & b 2 8 7 2 6 & b , 1 : / 6 , 5 & n + ] & o r f n v r x u f h f r q w u r o 3 / / 6 $ , & / . 3 / / 8 6 % & / . 3 / / & / . 3 / / 6 $ , & / . 3 / / 8 6 % & / . 3 / / $ ' & & / . 3 / / 6 $ , & / . 3 / / $ ' & & / . functional overview stm32l475xx 34/193 docid027692 rev 2 3.12 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. fast i/o toggling can be achieved thanks to their mapping on the ahb2 bus. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.13 direct memory a ccess controller (dma) the device embeds 2 dmas. refer to table 7: dma implementation for the features implementation. direct memory access (dma) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. data can be quickly moved by dma without any cpu actions. this keeps cpu resources free for other operations. the two dma controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. each has an arbiter for handling the priority between dma requests. the dma supports: ? 14 independently configurable channels (requests) ? each channel is connected to dedicated hardware dma requests, software trigger is also supported on each channel. this configuration is done by software. ? priorities between requests from channels of one dma are software programmable (4 levels consisting of very high, high, medi um, low) or hardware in case of equality (request 1 has priority over request 2, etc.) ? independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. source/destination addresses must be aligned on the data size. ? support for circular buffer management ? 3 event flags (dma half transfer, dma transfer complete and dma transfer error) logically ored together in a single interrupt request for each channel ? memory-to-memory transfer ? peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers ? access to flash, sram, apb and ahb pe ripherals as source and destination ? programmable number of data to be transferred: up to 65536. table 7. dma implementation dma features dma1 dma2 number of regular channels 7 7 docid027692 rev 2 35/193 stm32l475xx functional overview 53 3.14 interrupts and events 3.14.1 nested vectored inte rrupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 36 edge det ector lines used to generate interrupt/event requests and wake-up the system from stop mode. each external line can be independently configur ed to select the trigger event (rising edge, fa lling edge, both) and can be masked independently a pending register main tains the status of the interrupt requests. the internal lines are connected to peripherals with wakeup fr om stop mode capability. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 114 gpios can be connected to the 16 external interrupt lines. functional overview stm32l475xx 36/193 docid027692 rev 2 3.15 analog to digital converter (adc) the device embeds 3 successive approximati on analog-to-digital converters with the following features: ? 12-bit native resolution , with built-in calibration ? 5.33 msps maximum conversion rate with full resolution ? down to 18.75 ns sampling time ? increased conversion rate for lower resolution (up to 8.88 msps for 6-bit resolution) ? up to 16 external channels, some of them shared between adc1 and adc2, or adc1, adc2 and adc3. ? 5 internal channels: internal reference voltage, temperature sensor, vbat/3, dac1 and dac2 outputs. ? one external reference pin is available on some package, allowing the input voltage range to be independent from the power supply ? single-ended and differential mode inputs ? low-power design ? capable of low-current operation at lo w conversion rate (consumption decreases linearly with speed) ? dual clock domain architecture: adc speed independent from cpu frequency ? highly versatile digital interface ? single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions ? handles two adc converters for du al mode operation (simultaneous or interleaved sampling modes) ? each adc support multiple trigger inputs for synchronization with on-chip timers and external signals ? results stored into 3 data register or in ram with dma controller support ? data pre-processing: left/right alignment and per channel offset compensation ? built-in oversampling unit for enhanced snr ? channel-wise programmable sampling time ? three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers ? hardware assistant to prepare the context of the injected channels to allow fast context switching 3.15.1 temperature sensor the temperature sensor (ts) generates a voltage v ts that varies linearly with temperature. the temperature sensor is internally conn ected to the adc1_in17 and adc3_in17 input channels which is used to convert the sens or output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. docid027692 rev 2 37/193 stm32l475xx functional overview 53 to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.15.2 internal voltage reference (v refint ) the internal voltage reference (vrefint) provides a stable (bandgap) voltage output for the adc and comparators. vrefint is inte rnally connected to the adc1_in0 input channel. the precise voltage of vrefint is individually measured for each part by st during production test and stored in the system memory area. it is a ccessible in read-only mode. 3.15.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in18 or adc3_in18. as the v bat voltage may be higher than vdda, and thus outside the adc input range, the vbat pin is internally connected to a bridge divider by 3. as a c onsequence, the converted digital value is one third the v bat voltage. 3.16 digital to analog converter (dac) two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inve rting configuration. this digital interface supp orts the following features: ? up to two dac output channels ? 8-bit or 12-bit output mode ? buffer offset calibration (factory and user trimming) ? left or right data alignment in 12-bit mode ? synchronized update capability table 8. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75a8 - 0x1fff 75a9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75ca - 0x1fff 75cb table 9. internal voltage reference calibration values calibration value name description memory address vrefint raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75aa - 0x1fff 75ab functional overview stm32l475xx 38/193 docid027692 rev 2 ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? sample and hold low-power mode, with internal or external capacitor the dac channels are triggered through the ti mer update outputs that are also connected to different dma channels. 3.17 voltage referenc e buffer (vrefbuf) the stm32l475xx devices embed an voltage reference buffer which can be used as voltage reference for adcs, dacs and also as voltage reference for external components through the vref+ pin. the internal voltage reference buffer supports two voltages: ? 2.048 v ? 2.5 v an external voltage reference can be provided through the vref+ pin when the internal voltage reference buffer is off. the vref+ pin is double-bonded with vdda on some packages. in these packages the internal voltage reference buffer is not available. figure 4. voltage reference buffer 3.18 comparators (comp) the stm32l475xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hyster esis and speed (low speed for low-power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output channels ? internal reference voltage or submultiple (1/4, 1/2, 3/4). 0 6 y 9 9 5 ( ) % 8 ) / r z i u h t x h q f \ f x w r i i f d s d f l w r u ' $ & $ ' & % d q g j d s 9 ' ' $ q ) 9 5 ( ) docid027692 rev 2 39/193 stm32l475xx functional overview 53 all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.19 operational amplifier (opamp) the stm32l475xx embeds two operational amplifiers with external or internal follower routing and pga capability. the operational amplifier features: ? low input bias current ? low offset voltage ? low-power mode ? rail-to-rail input 3.20 touch sensing controller (tsc) the touch sensing controller provides a simple solution for adding capacitive sensing functionality to any a pplication. capacitive sensing technology is able to detect finger presence near an electrode which is protecte d from direct touch by a dielectric (glass, plastic, ...). the capacitive va riation introduced by the finger (or any conductive object) is measured using a proven implementation base d on a surface charge transfer acquisition principle. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. the main features of the touch sensing controller are the following: ? proven and robust surface charge transfer acquisition principle ? supports up to 21 capacitive sensing channels ? up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time ? spread spectrum feature to improve system robustness in noisy environments ? full hardware management of the charge transfer acquisition sequence ? programmable charge transfer frequency ? programmable sampling capacitor i/o pin ? programmable channel i/o pin ? programmable max count value to avoid long acquisition when a channel is faulty ? dedicated end of acquisiti on and max count er ror flags with inte rrupt capability ? one sampling capacitor for up to 3 capaciti ve sensing channels to reduce the system components ? compatible with proximity, touchkey, linear and rotary touch sensor implementation ? designed to operate with stmtouch touch sensing firmware library note: the number of capacitive sensing channels is dependent on the size of the packages and subject to i/ o availability. functional overview stm32l475xx 40/193 docid027692 rev 2 3.21 digital filter for sigma- delta modulators (dfsdm) the device embeds one dfsdm with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. the dfsdm peripheral is dedicated to interface the external ? modulators to microcontroller and then to perform digital f iltering of the received data streams (which represent analog value on ? modulators inputs). dfsdm can also interface pdm (pulse density modulation) microphones and perform pdm to pcm conversion and filtering in hardware. dfsdm features optio nal parallel data stream inputs from microcontrollers memory (through dma/cpu transfers into dfsdm). dfsdm transceivers support several serial interface formats (to support various ? modulators). dfsdm digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final adc resolution. the dfsdm peripheral supports: ? 8 multiplexed input digital serial channels: ? configurable spi interface to connect various sd modulator(s) ? configurable manchester coded 1 wire interface support ? pdm (pulse density modulation) microphone input support ? maximum input clock frequency up to 20 mhz (10 mhz for manchester coding) ? clock output for sd modulator(s): 0..20 mhz ? alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): ? internal sources: device memory data streams (dma) ? 4 digital filter modules with adjustable digital signal processing: ?sinc x filter: filter order/type (1..5), oversampling ratio (up to 1..1024) ? integrator: oversampling ratio (1..256) ? up to 24-bit output data resolution, signed output data format ? automatic data offset correction (offset stored in register by user) ? continuous or single conversion ? start-of-conversion triggered by: ? software trigger ? internal timers ? external events ? start-of-conversion synchronously wit h first digital filter module (dfsdm0) ? analog watchdog feature: ? low value and high value data threshold registers ? dedicated configurable sincx digital filter (order = 1..3, oversampling ratio = 1..32) ? input from final output data or from selected input digital serial channels ? continuous monitoring independently from standard conversion ? short circuit detector to detect saturated analog input values (bottom and top range): ? up to 8-bit counter to detect 1..256 cons ecutive 0?s or 1?s on serial data stream ? monitoring continuously each input serial channel ? break signal generation on analog watchdog ev ent or on short circuit detector event docid027692 rev 2 41/193 stm32l475xx functional overview 53 ? extremes detector: ? storage of minimum and maximum values of final conversion data ? refreshed by software ? dma capability to read th e final conversion data ? interrupts: end of conversion, overrun, ana log watchdog, short circuit, input serial channel clock absence ? ?regular? or ?injected? conversions: ? ?regular? conversions can be requested at any time or even in continuous mode without having any impact on the timing of ?injected? conversions ? ?injected? conversions for precise timi ng and with high conversion priority 3.22 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 3.23 timers and watchdogs the stm32l475xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers , two watchdog timers and a systick timer. the table below compares the features of t he advanced control, gener al purpose and basic timers. table 10. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 3 general- purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no functional overview stm32l475xx 42/193 docid027692 rev 2 3.23.1 advanced-control timer (tim1, tim8) the advanced-control timer can each be se en as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead- times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose timx timers (described in section 3.23.2 ) using the same architecture, so th e advanced-control timers can work together with the timx timers via the time r link feature for synchronization or event chaining. 3.23.2 general-purpose timers (tim2, tim3, tim4, tim5 , tim15, tim16, tim17) there are up to seven synchronizable general-purpose timers embedded in the stm32l475xx (see table 10 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2, tim3, tim4 and tim5 they are full-featured general-purpose timers: ? tim2 and tim5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and tim4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. these timers feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. they can work to gether, or with the other general-purpose timers via the timer link feature fo r synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 they are general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. docid027692 rev 2 43/193 stm32l475xx functional overview 53 3.23.3 basic timers (tim6 and tim7) the basic timers are mainly used for dac tri gger generation. they can also be used as generic 16-bit timebases. 3.23.4 low-power timer (lptim1 and lptim2) the devices embed two low-power timers. these timers have an independent clock and are running in stop mode if they are clocked by lse, lsi or an external cl ock. they are able to wakeup the system from stop mode. lptim1 is active in stop 0, stop 1 and stop 2 modes. lptim2 is active in stop 0 and stop 1 mode. this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous/ one shot mode ? selectable software/ hardware input trigger ? selectable clock source ? internal clock sources: l se, lsi, hsi16 or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by pulse counter application). ? programmable digital glitch filter ? encoder mode (lptim1 only) 3.23.5 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc (lsi) and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.23.6 system window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. functional overview stm32l475xx 44/193 docid027692 rev 2 3.23.7 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.24 real-time clock (rtc ) and backup registers the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap ye ar), 30, and 31 days of the month. ? two programmable alarms. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to vbat mode. ? 17-bit auto-reload wakeup timer (wut) for periodic events with programmable resolution and period. the rtc and the 32 backup registers are supplied through a switch that takes power either from the v dd supply when present or from the vbat pin. the backup registers are 32-bit registers used to store 128 bytes of user application data when vdd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby or shutdown mode. the rtc clock sources can be: ? a 32.768 khz external crystal (lse) ? an external resonator or oscillator (lse) ? the internal low power rc oscillator (l si, with typical frequency of 32 khz) ? the high-speed external clock (hse) divided by 32. the rtc is functional in vbat m ode and in all low-power modes when it is clocked by the lse. when clocked by the lsi, the rtc is not functional in vbat mode, but is functional in all low-power modes except shutdown mode. all rtc events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes. docid027692 rev 2 45/193 stm32l475xx functional overview 53 3.25 inter-integrated ci rcuit interface (i2c) the device embeds 3 i2c. refer to table 11: i2c implementation for the features implementation. the i 2 c bus interface handles communications bet ween the microcontroller and the serial i 2 c bus. it co ntrols all i 2 c bus-specific sequencing, protocol, arbitration and timing. the i2c peripheral supports: ? i 2 c-bus specification and user manual re v. 5 compatibility: ? slave and master modes , multimaster capability ? standard-mode (sm), with a bitrate up to 100 kbit/s ? fast-mode (fm), with a bitrate up to 400 kbit/s ? fast-mode plus (fm+), with a bitrate up to 1 mbit/s and 20 ma output drive i/os ? 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses ? programmable setup and hold times ? optional clock stretching ? system management bus (smbus) spec ification rev 2.0 compatibility: ? hardware pec (packet error checking) generation and verification with ack control ? address resolution protocol (arp) support ? smbus alert ? power system management protocol (pmbus tm ) specification rev 1.1 compatibility ? independent clock: a choice of independent clock sources allowing the i2c communication speed to be independent from the pclk reprogramming. refer to figure 3: clock tree . ? wakeup from stop mode on address match ? programmable analog and digital noise filters ? 1-byte buffer with dma capability table 11. i2c implementation i2c features (1) 1. x: supported i2c1 i2c2 i2c3 standard-mode (up to 100 kbit/s) x x x fast-mode (up to 400 kbit/s) x x x fast-mode plus with 20ma output drive i/os (up to 1 mbit/s) x x x programmable analog and digital noise filters x x x smbus/pmbus hardware support x x x independent clock x x x wakeup from stop 0 / stop 1 mode on address match x x x wakeup from stop 2 mode on address match - - x functional overview stm32l475xx 46/193 docid027692 rev 2 3.26 universal synchronous/asynch ronous receiver transmitter (usart) the stm32l475xx devices have three embedded universal synchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4, uart5). these interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. they pr ovide hardware m anagement of the cts and rts signals, and rs485 driver enable. they are able to communicate at speeds of up to 10mbit/s. usart1, usart2 and usart3 also provide smart card mode (iso 7816 compliant) and spi-like communication capability. all usart have a clock domain independent from the cpu clock, allowing the usartx (x=1,2,3,4,5) to wake up the mcu from stop mode using baudrates up to 200 kbaud.the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame all usart interfaces can be served by the dma controller. table 12. stm32l475xx us art/uart/lpuart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 lpuart1 hardware flow control for modem xxxxx x continuous communication using dma xxxxx x multiprocessor communication xxxxx x synchronous mode x x x - - - smartcard mode x x x - - - single-wire half-dupl ex communication xxxxx x irda sir endec block xxxxx - lin mode xxxxx - dual clock domain xxxxx x wakeup from stop 0 / stop 1 modes xxxxx x wakeup from stop 2 mode ----- x receiver timeout interrupt xxxxx - modbus communication xxxxx - auto baud rate detection x (4 modes) - driver enable xxxxx x lpuart/usart data length 7, 8 and 9 bits 1. x = supported. docid027692 rev 2 47/193 stm32l475xx functional overview 53 3.27 low-power universal asynchr onous receiver transmitter (lpuart) the device embeds one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock, and can wakeup the system from stop mode using baudrates up to 220 kbaud. the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller. functional overview stm32l475xx 48/193 docid027692 rev 2 3.28 serial peripheral interface (spi) three spi interfaces allow communication up to 40 mbits/s in master and up to 24 mbits/s slave modes, in half-duplex, full-duplex and simplex modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. the spi interfaces support nss pulse mode, ti mode and hardware crc calculation. all spi interfaces can be served by the dma controller. 3.29 serial audio interfaces (sai) the device embeds 2 sai. refer to table 13: sai implementation for the features implementation. the sai bus interface handles communications between the microcontroller and the serial audio protocol. the sai peripheral supports: ? two independent audio sub-blocks which can be transmitters or receivers with their respective fifo. ? 8-word integrated fifos for each audio sub-block. ? synchronous or asynchronous mode between the audio sub-blocks. ? master or slave configuration inde pendent for both audio sub-blocks. ? clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. ? data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. ? peripheral with large configurability and flexib ility allowing to target as example the following audio protocol: i2s, lsb or msb-ju stified, pcm/dsp, td m, ac?97 and spdif out. ? up to 16 slots available with configurable size and with th e possibility to select which ones are active in the audio frame. ? number of bits by frame may be configurable. ? frame synchronization active level conf igurable (offset, bit length, level). ? first active bit position in the slot is configurable. ? lsb first or msb first for data transfer. ? mute mode. ? stereo/mono audio frame capability. ? communication clock strobing edge configurable (sck). ? error flags with associated interrupts if enabled respectively. ? overrun and underrun detection. ? anticipated frame synchronization signal detection in slave mode. ? late frame synchronization signal detection in slave mode. ? codec not ready for the ac?97 mode in reception. ? interruption sources when enabled: ?errors. ? fifo requests. ? dma interface with 2 dedicated channels to handle access to the dedicated integrated fifo of each sai audio sub-block. docid027692 rev 2 49/193 stm32l475xx functional overview 53 3.30 single wire protocol master interface (swpmi) the single wire protocol master interface (swp mi) is the master interface corresponding to the contactless frontend (clf) defined in the et si ts 102 613 technical specification. the main features are: ? full-duplex communication mode ? automatic swp bus state management (active, suspend, resume) ? configurable bitrate up to 2 mbit/s ? automatic sof, eof and crc handling swpmi can be served by the dma controller. 3.31 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. the can peripheral supports: ? supports can protocol version 2.0 a, b active ? bit rates up to 1 mbit/s table 13. sai implementation sai features (1) 1. x: supported sai1 sai2 i2s, lsb or msb-justified, pcm/dsp, tdm, ac?97 x x mute mode x x stereo/mono audio frame capability. x x 16 slots x x data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit x x fifo size x (8 word) x (8 word) spdif x x functional overview stm32l475xx 50/193 docid027692 rev 2 ? transmission ? three transmit mailboxes ? configurable transmit priority ? reception ? two receive fifos with three stages ? 14 scalable filter banks ? identifier list feature ? configurable fifo overrun ? time-triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? time stamp sent in last two data bytes ? management ? maskable interrupts ? software-efficient mailbox mapping at a unique address space 3.32 secure digital input/output and multimediacards interface (sdmmc) the card host interface (sdmmc) provides an interface between th e apb peripheral bus and multimediacards (mmcs), sd memory cards and sdio cards. the sdmmc features include the following: ? full compliance with multimediacard system specification version 4.2. card support for three different databus modes: 1-bit (default), 4-bit and 8-bit ? full compatibility with previous versions of multimed iacards (forward compatibility) ? full compliance with sd memory card specifications version 2.0 ? full compliance with sd i/o card specification version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit ? data transfer up to 48 mhz for the 8 bit mode ? data write and read with dma capability 3.33 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg c ontroller requires a dedicated 48 mhz clock that can be provided by the internal mult ispeed oscillator (msi) automati cally trimmed by 32.768 khz external oscillator (lse).this allows to use the usb device without external high speed crystal (hse). docid027692 rev 2 51/193 stm32l475xx functional overview 53 the major features are: ? combined rx and tx fifo size of 1.25 kb with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 1 bidirectional control endpoint + 5 in endpoints + 5 out endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? software configurable to otg 1.3 and otg 2.0 modes of operation ? otg 2.0 supports adp (att ach detection protocol) ? usb 2.0 lpm (link power management) support ? battery charging specific ation revision 1.2 support ? internal fs otg phy support for otg/host modes, a power switch is needed in case bus-powered devices are connected. 3.34 flexible static me mory controller (fsmc) flexible static memory contro ller (fsmc) is also named flex ible memory controller (fmc). the main features of the fmc controller are the following: ? interface with static-memory mapped devices in multiplexed mode including: ? static random access memory (sram) ? nor flash memory ? psram ? 8-,16- bit data bus width ? write fifo ? the maximum fmc_clk frequency for synchronous accesses is hclk/2. lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.35 quad spi memory interface (quadspi) the quad spi is a specialized communication in terface targeting single, dual or quad spi flash memories. it can operate in any of the three following modes: ? indirect mode: all the operations are performed using the quadspi registers ? status polling mode: the exter nal flash status register is periodically read and an interrupt can be generated in case of flag setting ? memory-mapped mode: the external flash is memory mapped and is seen by the system as if it were an internal memory functional overview stm32l475xx 52/193 docid027692 rev 2 the quad spi interface supports: ? three functional modes: indirect , status-polling, and memory-mapped ? sdr and ddr support ? fully programmable opcode for both indirect and memory mapped mode ? fully programmable frame format for both indirect and memory mapped mode ? each of the 5 following phases can be conf igured independently (enable, length, single/dual/quad communication) ? instruction phase ? address phase ? alternate bytes phase ? dummy cycles phase ? data phase ? integrated fifo for reception and transmission ? 8, 16, and 32-bit data accesses are allowed ? dma channel for indirect mode operations ? programmable masking for external flash flag management ? timeout management ? interrupt generation on fifo threshold, tim eout, status match, operation complete, and access error docid027692 rev 2 53/193 stm32l475xx functional overview 53 3.36 development support 3.36.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.36.2 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32l475xx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. real-time instruction and data flow activity be recorded and then formatted for display on the host computer th at runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. pinouts and pin description stm32l475xx 54/193 docid027692 rev 2 4 pinouts and pin description figure 5. stm32l475vx lqfp100 pinout (1) 1. the above figure shows the package top view. figure 6. stm32l475rx lqfp64 pinout (1) 1. the above figure shows the package top view. 0 6 9 > y & w 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 ( 3 & 3 & 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % 9 6 6 9 ' ' 9 % $ 7 3 ( 3 ( 3 ( 3 ( 3 ( 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 6 6 9 ' ' 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 5 ( ) 9 ' ' $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 9 ' ' 8 6 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 ' 3 $ 3 $ 3 & 3 & 3 & 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 % % 2 2 7 3 % 3 % 3 ( 3 ( 9 6 6 9 ' ' 0 6 9 > y & we 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 % $ 7 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' 8 6 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 3 $ 3 & 3 & 3 & 3 ' 3 % 3 % 3 % 3 % 3 % % 2 2 7 3 % 3 % 9 6 6 9 ' ' docid027692 rev 2 55/193 stm32l475xx pinouts and pin description 79 table 14. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below th e pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tt 3.6 v tolerant i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor option for tt or ft i/os _f (1) i/o, fm+ capable _u (2) i/o, with usb function supplied by v ddusb _a (3) i/o, with analog switch function supplied by v dda notes unless otherwise specified by a note, all i/os are set as analog inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers 1. the related i/o structures in table 15 are: ft_f, ft_fa, ft_f, ft_fa. 2. the related i/o structures in table 15 are: ft_u. 3. the related i/o structures in table 15 are: ft_a, ft_fa, tt_a. table 15. stm32l475xx pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions - 1 pe2 i/o ft - traceck, tim3_etr, tsc_g7_io1, fmc_a23, sai1_mclk_a, eventout - - 2 pe3 i/o ft - traced0, tim3_ch1, tsc_g7_io2, fmc_a19, sai1_sd_b, eventout - - 3 pe4 i/o ft - traced1, tim3_ch2, dfsdm_datin3, tsc_g7_io3, fmc_a20, sai1_fs_a, eventout - pinouts and pin description stm32l475xx 56/193 docid027692 rev 2 - 4 pe5 i/o ft - traced2, tim3_ch3, dfsdm_ckin3, tsc_g7_io4, fmc_a21, sai1_sck_a, eventout - - 5 pe6 i/o ft - traced3, tim3_ch4, fmc_a22, sai1_sd_a, eventout rtc_tamp3/ wkup3 1 6 vbat s - - - - 2 7 pc13 i/o ft (1) (2) eventout rtc_tamp1/ rtc_ts/ rtc_out/ wkup2 38 pc14- osc32_in (pc14) i/o ft (1) (2) eventout osc32_in 49 pc15- osc32_out (pc15) i/o ft (1) (2) eventout osc32_out -10 vss s - - - - -11 vdd s - - - - 512 ph0-osc_in (ph0) i/o ft - eventout osc_in 613 ph1-osc_out (ph1) i/o ft - eventout osc_out 7 14 nrst i/o rst - - - 8 15 pc0 i/o ft_fa - lptim1_in1, i2c3_scl, dfsdm_datin4, lpuart1_rx, lptim2_in1, eventout adc123_in1 9 16 pc1 i/o ft_fa - lptim1_out, i2c3_sda, dfsdm_ckin4, lpuart1_tx, eventout adc123_in2 10 17 pc2 i/o ft_a - lptim1_in2, spi2_miso, dfsdm_ckout, eventout adc123_in3 11 18 pc3 i/o ft_a - lptim1_etr, spi2_mosi, sai1_sd_a, lptim2_etr, eventout adc123_in4 -19 vssa s - - - - -20 vref- s - - - - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions docid027692 rev 2 57/193 stm32l475xx pinouts and pin description 79 12 - vssa/vref- - - - - - - 21 vref+ s - - - vrefbuf_out -22 vdda s - - - - 13 - vdda/vref+ s - - - - 14 23 pa0 i/o ft_a - tim2_ch1, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, sai1_extclk, tim2_etr, eventout opamp1_vinp, adc12_in5, rtc_tamp2/wkup1 15 24 pa1 i/o ft_a - tim2_ch2, tim5_ch2, usart2_rts_de, uart4_rx, tim15_ch1n, eventout opamp1_vinm, adc12_in6 16 25 pa2 i/o ft_a - tim2_ch3, tim5_ch3, usart2_tx, sai2_extclk, tim15_ch1, eventout adc12_in7, wkup4/lsco 17 26 pa3 i/o tt - tim2_ch4, tim5_ch4, usart2_rx, tim15_ch2, eventout opamp1_ vout, adc12_in8 18 27 vss s - - - - 19 28 vdd s - - - - 20 29 pa4 i/o tt_a - spi1_nss, spi3_nss, usart2_ck, sai1_fs_b, lptim2_out, eventout adc12_in9, dac1_out1 21 30 pa5 i/o tt_a - tim2_ch1, tim2_etr, tim8_ch1n, spi1_sck, lptim2_etr, eventout adc12_in10, dac1_out2 22 31 pa6 i/o ft_a - tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, usart3_cts, quadspi_bk1_io3, tim1_bkin_comp2, tim8_bkin_comp2, tim16_ch1, eventout opamp2_vinp, adc12_in11 23 32 pa7 i/o ft_a - tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi, quadspi_bk1_io2, tim17_ch1, eventout opamp2_vinm, adc12_in12 24 33 pc4 i/o ft_a - usart3_tx, even tout comp1_inm, adc12_in13 25 34 pc5 i/o ft_a - usart3_rx, eventout comp1_inp, adc12_in14, wkup5 table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions pinouts and pin description stm32l475xx 58/193 docid027692 rev 2 26 35 pb0 i/o tt_a - tim1_ch2n, tim3_ch3, tim8_ch2n, usart3_ck, quadspi_bk1_io1, comp1_out, eventout opamp2_ vout, adc12_in15 27 36 pb1 i/o ft_a - tim1_ch3n, tim3_ch4, tim8_ch3n, dfsdm_datin0, usart3_rts_de, quadspi_bk1_io0, lptim2_in1, eventout comp1_inm, adc12_in16 28 37 pb2 i/o ft_a - rtc_out, lptim1_out, i2c3_smba, dfsdm_ckin0, eventout comp1_inp - 38 pe7 i/o ft - tim1_etr, dfsdm_datin2, fmc_d4, sai1_sd_b, eventout - - 39 pe8 i/o ft - tim1_ch1n, dfsdm_ckin2, fmc_d5, sai1_sck_b, eventout - - 40 pe9 i/o ft - tim1_ch1, dfsdm_ckout, fmc_d6, sai1_fs_b, eventout - - 41 pe10 i/o ft - tim1_ch2n, dfsdm_datin4, tsc_g5_io1, fmc_d7, quadspi_clk, sai1_mclk_b, eventout - - 42 pe11 i/o ft - tim1_ch2, dfsdm_ckin4, tsc_g5_io2, quadspi_ncs, fmc_d8, eventout - - 43 pe12 i/o ft - tim1_ch3n, spi1_nss, dfsdm_datin5, tsc_g5_io3, quadspi_bk1_io0, fmc_d9, eventout - - 44 pe13 i/o ft - tim1_ch3, spi1_sck, dfsdm_ckin5, tsc_g5_io4, quadspi_bk1_io1, fmc_d10, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions docid027692 rev 2 59/193 stm32l475xx pinouts and pin description 79 - 45 pe14 i/o ft - tim1_ch4, tim1_bkin2, tim1_bkin2_comp2, spi1_miso, quadspi_bk1_io2, fmc_d11, eventout - - 46 pe15 i/o ft - tim1_bkin, tim1_bkin_comp1, spi1_mosi, quadspi_bk1_io3, fmc_d12, eventout - 29 47 pb10 i/o ft_f - tim2_ch3, i2c2_scl, spi2_sck, dfsdm_datin7, usart3_tx, lpuart1_rx, quadspi_clk, comp1_out, sai1_sck_a, eventout - 30 48 pb11 i/o ft_f - tim2_ch4, i2c2_sda, dfsdm_ckin7, usart3_rx, lpuart1_tx, quadspi_ncs, comp2_out, eventout - 31 49 vss s - - - - 32 50 vdd s - - - - 33 51 pb12 i/o ft - tim1_bkin, tim1_bkin_comp2, i2c2_smba, spi2_nss, dfsdm_datin1, usart3_ck, lpuart1_rts_de, tsc_g1_io1, swpmi1_io, sai2_fs_a, tim15_bkin, eventout - 34 52 pb13 i/o ft_f - tim1_ch1n, i2c2_scl, spi2_sck, dfsdm_ckin1, usart3_cts, lpuart1_cts, tsc_g1_io2, swpmi1_tx, sai2_sck_a, tim15_ch1n, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions pinouts and pin description stm32l475xx 60/193 docid027692 rev 2 35 53 pb14 i/o ft_f - tim1_ch2n, tim8_ch2n, i2c2_sda, spi2_miso, dfsdm_datin2, usart3_rts_de, tsc_g1_io3, swpmi1_rx, sai2_mclk_a, tim15_ch1, eventout - 36 54 pb15 i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi, dfsdm_ckin2, tsc_g1_io4, swpmi1_suspend, sai2_sd_a, tim15_ch2, eventout - - 55 pd8 i/o ft - usart3_tx, fmc_d13, eventout - - 56 pd9 i/o ft - usart3_rx, fmc_d14, sai2_mclk_a, eventout - - 57 pd10 i/o ft - usart3_ck, tsc_g6_io1, fmc_d15, sai2_sck_a, eventout - - 58 pd11 i/o ft - usart3_cts, tsc_g6_io2, fmc_a16, sai2_sd_a, lptim2_etr, eventout - - 59 pd12 i/o ft - tim4_ch1, usart3_rts_de, tsc_g6_io3, fmc_a17, sai2_fs_a, lptim2_in1, eventout - - 60 pd13 i/o ft - tim4_ch2, tsc_g6_io4, fmc_a18, lptim2_out, eventout - - 61 pd14 i/o ft - tim4_ch3, fmc_d0, eventout - - 62 pd15 i/o ft - tim4_ch4, fmc_d1, eventout - 37 63 pc6 i/o ft - tim3_ch1, tim8_ch1, dfsdm_ckin3, tsc_g4_io1, sdmmc1_d6, sai2_mclk_a, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions docid027692 rev 2 61/193 stm32l475xx pinouts and pin description 79 38 64 pc7 i/o ft - tim3_ch2, tim8_ch2, dfsdm_datin3, tsc_g4_io2, sdmmc1_d7, sai2_mclk_b, eventout - 39 65 pc8 i/o ft - tim3_ch3, tim8_ch3, tsc_g4_io3, sdmmc1_d0, eventout - 40 66 pc9 i/o ft - tim8_bkin2, tim3_ch4, tim8_ch4, tsc_g4_io4, otg_fs_noe, sdmmc1_d1, sai2_extclk, tim8_bkin2_comp1, eventout - 41 67 pa8 i/o ft - mco, tim1_ch1, usart1_ck, otg_fs_sof, lptim2_out, eventout - 42 68 pa9 i/o ft_u - tim1_ch2, usart1_tx, tim15_bkin, eventout otg_fs_vbus 43 69 pa10 i/o ft_u - tim1_ch3, usart1_rx, otg_fs_id, tim17_bkin, eventout - 44 70 pa11 i/o ft_u - tim1_ch4, tim1_bkin2, usart1_cts, can1_rx, otg_fs_dm, tim1_bkin2_comp1, eventout - 45 71 pa12 i/o ft_u - tim1_etr, usart1_rts_de, can1_tx, otg_fs_dp, eventout - 46 72 pa13 (jtms-swdio) i/o ft (3) jtms-swdio, ir_out, otg_fs_noe, eventout - 47 - vss s - - - - 48 73 vddusb s - - - - -74 vss s - - - - -75 vdd s - - - - 49 76 pa14 (jtck-swclk) i/o ft (3) jtck-swclk, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions pinouts and pin description stm32l475xx 62/193 docid027692 rev 2 50 77 pa15 (jtdi) i/o ft (3) jtdi, tim2_ch1, tim2_etr, spi1_nss, spi3_nss, uart4_rts_de, tsc_g3_io1, sai2_fs_b, eventout - 51 78 pc10 i/o ft - spi3_sck, usart3_tx, uart4_tx, tsc_g3_io2, sdmmc1_d2, sai2_sck_b, eventout - 52 79 pc11 i/o ft - spi3_miso, usart3_rx, uart4_rx, tsc_g3_io3, sdmmc1_d3, sai2_mclk_b, eventout - 53 80 pc12 i/o ft - spi3_mosi, usart3_ck, uart5_tx, tsc_g3_io4, sdmmc1_ck, sai2_sd_b, eventout - - 81 pd0 i/o ft - spi2_nss, dfsdm_datin7, can1_rx, fmc_d2, eventout - - 82 pd1 i/o ft - spi2_sck, dfsdm_ckin7, can1_tx, fmc_d3, eventout - 54 83 pd2 i/o ft - tim3_etr, usart3_rts_de, uart5_rx, tsc_sync, sdmmc1_cmd, eventout - - 84 pd3 i/o ft - spi2_miso, dfsdm_datin0, usart2_cts, fmc_clk, eventout - - 85 pd4 i/o ft - spi2_mosi, dfsdm_ckin0, usart2_rts_de, fmc_noe, eventout - - 86 pd5 i/o ft - usart2_tx, fmc_nwe, eventout - - 87 pd6 i/o ft - dfsdm_datin1, usart2_rx, fmc_nwait, sai1_sd_a, eventout - - 88 pd7 i/o ft - dfsdm_ckin1, usart2_ck, fmc_ne1, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions docid027692 rev 2 63/193 stm32l475xx pinouts and pin description 79 55 89 pb3 (jtdo- traceswo) i/o ft_a (3) jtdo-traceswo, tim2_ch2, spi1_sck, spi3_sck, usart1_rts_de, sai1_sck_b, eventout comp2_inm 56 90 pb4 (njtrst) i/o ft_a (3) njtrst, tim3_ch1, spi1_miso, spi3_miso, usart1_cts, uart5_rts_de, tsc_g2_io1, sai1_mclk_b, tim17_bkin, eventout comp2_inp 57 91 pb5 i/o ft_a - lptim1_in1, tim3_ch2, i2c1_smba, spi1_mosi, spi3_mosi, usart1_ck, uart5_cts, tsc_g2_io2, comp2_out, sai1_sd_b, tim16_bkin, eventout - 58 92 pb6 i/o ft_fa - lptim1_etr, tim4_ch1, tim8_bkin2, i2c1_scl, dfsdm_datin5, usart1_tx, tsc_g2_io3, tim8_bkin2_comp2, sai1_fs_b, tim16_ch1n, eventout comp2_inp 59 93 pb7 i/o ft_fa - lptim1_in2, tim4_ch2, tim8_bkin, i2c1_sda, dfsdm_ckin5, usart1_rx, uart4_cts, tsc_g2_io4, fmc_nl, tim8_bkin_comp1, tim17_ch1n, eventout comp2_inm, pvd_in 60 94 boot0 i - - - - 61 95 pb8 i/o ft_f - tim4_ch3, i2c1_scl, dfsdm_datin6, can1_rx, sdmmc1_d4, sai1_mclk_a, tim16_ch1, eventout - 62 96 pb9 i/o ft_f - ir_out, tim4_ch4, i2c1_sda, spi2_nss, dfsdm_ckin6, can1_tx, sdmmc1_d5, sai1_fs_a, tim17_ch1, eventout - - 97 pe0 i/o ft - tim4_etr, fmc_nbl0, tim16_ch1, eventout - table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions pinouts and pin description stm32l475xx 64/193 docid027692 rev 2 - 98 pe1 i/o ft - fmc_nbl1, tim17_ch1, eventout - 63 99 vss s - - - - 64 100 vdd s - - - - 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led). 2. after a backup domain power-up, pc13, pc14 and pc15 operat e as gpios. their function then depends on the content of the rtc registers which are not reset by the system reset. fo r details on how to manage these gpios, refer to the backup domain and rtc register descriptions in the rm0395 reference manual. 3. after reset, these pins are configured as jtag/sw debug alternate functions, and the internal pull-up on pa15, pa13, pb4 pins and the internal pull-down on pa14 pin are activated. table 15. stm32l475xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp100 alternate functions additional functions stm32l475xx pinouts and pin description docid027692 rev 2 65/193 table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ tim5/tim8/ lptim1 tim1/tim2/ tim3/tim4/ tim5 tim8 i2c1/i2c2/i2c3 spi1/spi2 spi3/dfsdm usart1/ usart2/ usart3 port a pa0 - tim2_ch1 tim5_ch1 tim8_etr - - - usart2_cts pa1 - tim2_ch2 tim5_ch2 - - - - usart2_rts_ de pa2 - tim2_ch3 tim5_ch3 - - - - usart2_tx pa3 - tim2_ch4 tim5_ch4 - - - - usart2_rx pa4-----spi1_nssspi3_nssusart2_ck pa5 - tim2_ch1 tim2_etr tim8_ch1n - spi1_sck - - pa6 - tim1_bkin tim3_ch1 tim8_bkin - spi1_miso - usart3_cts pa7 - tim1_ch1n tim3_ch2 tim8_ch1n - spi1_mosi - - pa8mcotim1_ch1---- -usart1_ck pa9-tim1_ch2---- -usart1_tx pa10-tim1_ch3---- -usart1_rx pa11 - tim1_ch4 tim1_bkin2 - - - - usart1_cts pa12-tim1_etr---- - usart1_rts_ de pa13 jtms-swdio ir_out - - - - - - pa14jtck-swclk----- - - pa15 jtdi tim2_ch1 tim2_e tr - - spi1_nss spi3_nss - pinouts and pin description stm32l475xx 66/193 docid027692 rev 2 port b pb0 - tim1_ch2n tim3_ch3 tim8_ch2n - - - usart3_ck pb1 - tim1_ch3n tim3_ch4 tim8_ch3n - - dfsdm_datin0 usart3_rts_ de pb2 rtc_out lptim1_out - - i2c3_smba - dfsdm_ckin0 - pb3 jtdo- traceswo tim2_ch2 - - - spi1_sck spi3_sck usart1_rts_ de pb4 njtrst - tim3_ch1 - - spi1_miso spi3_miso usart1_cts pb5 - lptim1_in1 tim3_ch2 - i2c1_smba spi1_mosi spi3_mosi usart1_ck pb6 - lptim1_etr tim4_ch1 tim8_bkin2 i2c1_scl - dfsdm_datin5 usart1_tx pb7 - lptim1_in2 tim4_ch2 tim8_bkin i 2c1_sda - dfsdm_ckin5 usart1_rx pb8 - - tim4_ch3 - i2c1_scl - dfsdm_datin6 - pb9 - ir_out tim4_ch4 - i2c1_sd a spi2_nss dfsdm_ckin6 - pb10 - tim2_ch3 - - i2c2_scl spi2_sck dfsdm_datin7 usart3_tx pb11 - tim2_ch4 - - i2c2_sda - dfsdm_ckin7 usart3_rx pb12 - tim1_bkin - tim1_bkin_ comp2 i2c2_smba spi2_nss dfsdm_datin1 usart3_ck pb13 - tim1_ch1n - - i2c2_scl spi2_ sck dfsdm_ckin1 usart3_cts pb14 - tim1_ch2n - tim8_ch2n i2c2_sda spi2_miso dfsdm_datin2 usart3_rts_ de pb15 rtc_refin tim1_ch3n - tim8_ch3n - spi2_mosi dfsdm_ckin2 - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ tim5/tim8/ lptim1 tim1/tim2/ tim3/tim4/ tim5 tim8 i2c1/i2c2/i2c3 spi1/spi2 spi3/dfsdm usart1/ usart2/ usart3 stm32l475xx pinouts and pin description docid027692 rev 2 67/193 port c pc0 - lptim1_in1 - - i2c3_scl - dfsdm_datin4 - pc1 - lptim1_out - - i2c3_sda - dfsdm_ckin4 - pc2 - lptim1_in2 - - - spi2_miso dfsdm_ckout - pc3 - lptim1_etr - - - spi2_mosi - - pc4------ -usart3_tx pc5------ -usart3_rx pc6 - - tim3_ch1 tim8_ch1 - - dfsdm_ckin3 - pc7 - - tim3_ch2 tim8_ch2 - - dfsdm_datin3 - pc8 - - tim3_ch3 tim8_ch3 - - - - pc9 - tim8_bkin2 tim3_ch4 tim8_ch4 - - - - pc10------spi3_sckusart3_tx pc11------spi3_misousart3_rx pc12------spi3_mosiusart3_ck pc13------ - - pc14------ - - pc15------ - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ tim5/tim8/ lptim1 tim1/tim2/ tim3/tim4/ tim5 tim8 i2c1/i2c2/i2c3 spi1/spi2 spi3/dfsdm usart1/ usart2/ usart3 pinouts and pin description stm32l475xx 68/193 docid027692 rev 2 port d pd0-----spi2_nssdfsdm_datin7- pd1-----spi2_sckdfsdm_ckin7- pd2 - - tim3_etr - - - - usart3_rts_ de pd3-----spi2_misodfsdm_datin0usart2_cts pd4-----spi2_mosidfsdm_ckin0 usart2_rts_ de pd5------ -usart2_tx pd6------dfsdm_datin1usart2_rx pd7------dfsdm_ckin1usart2_ck pd8------ -usart3_tx pd9------ -usart3_rx pd10------ -usart3_ck pd11------ -usart3_cts pd12 - - tim4_ch1 - - - - usart3_rts_ de pd13 - - tim4_ch2 - - - - - pd14 - - tim4_ch3 - - - - - pd15 - - tim4_ch4 - - - - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ tim5/tim8/ lptim1 tim1/tim2/ tim3/tim4/ tim5 tim8 i2c1/i2c2/i2c3 spi1/spi2 spi3/dfsdm usart1/ usart2/ usart3 stm32l475xx pinouts and pin description docid027692 rev 2 69/193 port e pe0--tim4_etr--- - - pe1------ - - pe2 traceck - tim3_etr - - - - - pe3 traced0 - tim3_ch1 - - - - - pe4 traced1 - tim3_ch2 - - - dfsdm_datin3 - pe5 traced2 - tim3_ch3 - - - dfsdm_ckin3 - pe6 traced3 - tim3_ch4 - - - - - pe7-tim1_etr----dfsdm_datin2- pe8-tim1_ch1n----dfsdm_ckin2- pe9-tim1_ch1----dfsdm_ckout- pe10-tim1_ch2n----dfsdm_datin4- pe11-tim1_ch2----dfsdm_ckin4- pe12 - tim1_ch3n - - - spi1_nss dfsdm_datin5 - pe13 - tim1_ch3 - - - spi1_sck dfsdm_ckin5 - pe14 - tim1_ch4 tim1_bkin2 tim1_bkin2_ comp2 - spi1_miso - - pe15 - tim1_bkin - tim1_bkin_ comp1 - spi1_mosi - - port h ph0------ - - ph1------ - - table 16. alternate function af0 to af7 (for af8 to af15 see table 17 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ tim5/tim8/ lptim1 tim1/tim2/ tim3/tim4/ tim5 tim8 i2c1/i2c2/i2c3 spi1/spi2 spi3/dfsdm usart1/ usart2/ usart3 pinouts and pin description stm32l475xx 70/193 docid027692 rev 2 table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) port af8 af9 af10 af11 af12 af13 af14 af15 uart4, uart5, lpuart1 can1, tsc otg_fs, quadspi - sdmmc1, comp1, comp2, fmc, swpmi1 sai1, sai2 tim2, tim15, tim16, tim17, lptim2 eventout port a pa0 uart4_tx - - - - sai1_extclk tim2_etr eventout pa1 uart4_rx - - - - - tim15_ch1n eventout pa2 - - - - - sai2_extclk tim15_ch1 eventout pa3 - - - - - - tim15_ch2 eventout pa4 - - - - - sai1_fs_b lptim2_out eventout pa5 - - - - - - lptim2_etr eventout pa6 - - quadspi_bk1_io3 - tim1_bkin_ comp2 tim8_bkin_ comp2 tim16_ch1 eventout pa7 - - quadspi_bk1_io2 - - - tim17_ch1 eventout pa8 - - otg_fs_sof - - - lptim2_out eventout pa9 - - - - - - tim15_bkin eventout pa10 - - otg_fs_id - - - tim17_bkin eventout pa11 - can1_rx otg_fs_dm - tim1_bkin2_ comp1 - - eventout pa12 - can1_tx otg_fs_dp - - - - eventout pa13 - - otg_fs_noe - - - - eventout pa14 - - - - - - - eventout pa15 uart4_rts _de tsc_g3_io1 - - - sai2_fs_b - eventout stm32l475xx pinouts and pin description docid027692 rev 2 71/193 port b pb0 - - quadspi_bk1_io1 - comp1_out - - eventout pb1 - - quadspi_bk1_io0 - - - lptim2_in1 eventout pb2 - - - - - - - eventout pb3 - - - - - sai1_sck_b - eventout pb4 uart5_rts _de tsc_g2_io1 - - - sai1_mclk_ b tim17_bkin eventout pb5 uart5_cts tsc_g2_io2 - - comp2_out sai1_sd_b tim16_bkin eventout pb6 - tsc_g2_io3 - - tim8_bkin2_ comp2 sai1_fs_b tim16_ch1n eventout pb7 uart4_cts tsc_g2_io4 - - fmc_nl tim8_bkin_ comp1 tim17_ch1n eventout pb8 - can1_rx - - sdmmc1_d4 sai1_mclk_ a tim16_ch1 eventout pb9 - can1_tx - - sdmmc1_d5 sai1_fs_a tim17_ch1 eventout pb10 lpuart1_ rx - quadspi_clk - comp1_out sai1_sck_a - eventout pb11 lpuart1_tx - quadspi_ncs - comp2_out - - eventout pb12 lpuart1_ rts_de tsc_g1_io1 - - swpmi1_io sai 2_fs_a tim15_bkin eventout pb13 lpuart1_ cts tsc_g1_io2 - - swpmi1_tx sai 2_sck_a tim15_ch1n eventout pb14 - tsc_g1_io3 - - swpmi1_rx sai2_mclk_ a tim15_ch1 eventout pb15 - tsc_g1_io4 - - swpmi1_suspend sai2_sd_a tim15_ch2 eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4, uart5, lpuart1 can1, tsc otg_fs, quadspi - sdmmc1, comp1, comp2, fmc, swpmi1 sai1, sai2 tim2, tim15, tim16, tim17, lptim2 eventout pinouts and pin description stm32l475xx 72/193 docid027692 rev 2 port c pc0 lpuart1_ rx - - - - - lptim2_in1 eventout pc1 lpuart1_tx - - - - - - eventout pc2 - - - - - - - eventout pc3 - - - - - sai1_sd_a lptim2_etr eventout pc4 - - - - - - - eventout pc5 - - - - - - - eventout pc6 - tsc_g4_io1 - - sdmmc1_d6 sai2_mclk_ a - eventout pc7 - tsc_g4_io2 - - sdmmc1_d7 sai2_mclk_ b - eventout pc8 - tsc_g4_io3 - - sdmmc1_d0 - - eventout pc9 - tsc_g4_io4 otg_fs_n oe - sdmmc1_d1 sai2_extclk tim8_bkin2_ comp1 eventout pc10 uart4_tx tsc_g3_io2 - - s dmmc1_d2 sai2_sck_b - eventout pc11 uart4_rx tsc_g3_io3 - - sdmmc1_d3 sai2_mclk_ b - eventout pc12 uart5_tx tsc_g3_io4 - - s dmmc1_ck sai2_sd_b - eventout pc13 - - - - - - - eventout pc14 - - - - - - - eventout pc15 - - - - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4, uart5, lpuart1 can1, tsc otg_fs, quadspi - sdmmc1, comp1, comp2, fmc, swpmi1 sai1, sai2 tim2, tim15, tim16, tim17, lptim2 eventout stm32l475xx pinouts and pin description docid027692 rev 2 73/193 port d pd0 - can1_rx - - fmc_d2 - - eventout pd1 - can1_tx - - fmc_d3 - - eventout pd2 uart5_rx tsc_sync - - sdmmc1_cmd - - eventout pd3 - - - - fmc_clk - - eventout pd4 - - - - fmc_noe - - eventout pd5 - - - - fmc_nwe - - eventout pd6 - - - - fmc_nwait sai1_sd_a - eventout pd7 - - - - fmc_ne1 - - eventout pd8 - - - - fmc_d13 - - eventout pd9 - - - - fmc_d14 sai2_mclk_ a - eventout pd10 - tsc_g6_io1 - - fmc_d15 sai2_sck_a - eventout pd11 - tsc_g6_io2 - - fmc_a16 sai2_sd_a lptim2_etr eventout pd12 - tsc_g6_io3 - - fmc_a17 sai2_fs_a lptim2_in1 eventout pd13 - tsc_g6_io4 - - fmc_a 18 - lptim2_out eventout pd14 - - - - fmc_d0 - - eventout pd15 - - - - fmc_d1 - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4, uart5, lpuart1 can1, tsc otg_fs, quadspi - sdmmc1, comp1, comp2, fmc, swpmi1 sai1, sai2 tim2, tim15, tim16, tim17, lptim2 eventout pinouts and pin description stm32l475xx 74/193 docid027692 rev 2 port e pe0 - - - - fmc_nbl0 - tim16_ch1 eventout pe1 - - - - fmc_nbl1 - tim17_ch1 eventout pe2 - tsc_g7_io1 - - fmc_a23 sai1_mclk_ a - eventout pe3 - tsc_g7_io2 - - fmc_a19 sai1_sd_b - eventout pe4 - tsc_g7_io3 - - fmc_a20 sai1_fs_a - eventout pe5 - tsc_g7_io4 - - fmc_a21 sai1_sck_a - eventout pe6 - - - - fmc_a22 sai1_sd_a - eventout pe7 - - - - fmc_d4 sai1_sd_b - eventout pe8 - - - - fmc_d5 sai1_sck_b - eventout pe9 - - - - fmc_d6 sai1_fs_b - eventout pe10 - tsc_g5_io1 quadspi_clk - fmc_d7 sai1_mclk_ b - eventout pe11 - tsc_g5_io2 quadspi _ncs - fmc_d8 - - eventout pe12 - tsc_g5_io3 quadspi_bk1_io0 - fmc_d9 - - eventout pe13 - tsc_g5_io4 quadspi_bk1_io1 - fmc_d10 - - eventout pe14 - - quadspi_bk1_io2 - fmc_d11 - - eventout pe15 - - quadspi_bk1_io3 - fmc_d12 - - eventout port h ph0 - - - - - - - eventout ph1 - - - - - - - eventout table 17. alternate function af8 to af15 (for af0 to af7 see table 16 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 uart4, uart5, lpuart1 can1, tsc otg_fs, quadspi - sdmmc1, comp1, comp2, fmc, swpmi1 sai1, sai2 tim2, tim15, tim16, tim17, lptim2 eventout docid027692 rev 2 75/193 stm32l475xx memory mapping 79 5 memory mapping figure 7. stm32l475 memory map 0 6 9 [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ ? 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 7 3 d u h d 6 \ v w h p p h p r u \ ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ & [ [ [ [ [ [ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) [ [ [ [ 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g [ [ 6 5 $ 0 ) 0 & d q g 4 8 $ ' 6 3 , u h j l v w h u v ) 0 & e d q n ) 0 & e d q n e d q n 2 s w l r q % \ w h v 6 \ v w h p p h p r u \ 2 s w l r q v % \ w h v [ ) ) ) ) [ ) ) ) [ ) ) ) [ ) ) ) [ ) ) ) [ ) ) ) [ ) ) ) ) 5 h v h u y h g 5 h v h u y h g 4 8 $ ' 6 3 , u h j l v w h u v ) 0 & u h j l v w h u v [ % ) ) ) ) ) ) ) [ $ [ $ [ $ 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g [ ) ) ) ) ) ) ) [ 4 8 $ ' 6 3 , ) o d v k e d q n memory mapping stm32l475xx 76/193 docid027692 rev 2 table 18. stm32l475xx memory map and peripheral register boundary addresses (1) bus boundary address size (bytes) peripheral ahb3 0xa000 1000 - 0xa000 13ff 1 kb quadspi 0xa000 0000 - 0xa000 0fff 4 kb fmc ahb2 0x5006 0800 - 0x5006 0bff 1 kb rng 0x5004 0400 - 0x5006 07ff 129 kb reserved 0x5004 0000 - 0x5004 03ff 1 kb adc 0x5000 0000 - 0x5003 ffff 16 kb otg_fs 0x4800 2000 - 0x4fff ffff ~127 mb reserved 0x4800 1c00 - 0x4800 1fff 1 kb gpioh 0x4800 1800 - 0x4800 1bff 1 kb gpiog 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb gpioe 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa - 0x4002 4400 - 0x47ff ffff ~127 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 1 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash registers 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0800 - 0x4002 0fff 2 kb reserved 0x4002 0400 - 0x4002 07ff 1 kb dma2 0x4002 0000 - 0x4002 03ff 1 kb dma1 docid027692 rev 2 77/193 stm32l475xx memory mapping 79 apb2 0x4001 6400 - 0x4001 ffff 39 kb reserved 0x4001 6000 - 0x4000 63ff 1 kb dfsdm 0x4001 5c00 - 0x4000 5fff 1 kb reserved 0x4001 5800 - 0x4000 5bff 1 kb sai2 0x4001 5400 - 0x4000 57ff 1 kb sai1 0x4001 4c00 - 0x4000 53ff 2 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 apb2 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb tim8 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb sdmmc1 0x4001 2000 - 0x4001 27ff 2 kb reserved 0x4001 1c00 - 0x4001 1fff 1 kb firewall 0x4001 0800- 0x4001 1bff 5 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0200 - 0x4001 03ff 1 kb comp 0x4001 0030 - 0x4001 01ff vrefbuf 0x4001 0000 - 0x 4001 002f syscfg table 18. stm32l475xx memory map and peripheral register boundary addresses (continued) (1) bus boundary address size (bytes) peripheral memory mapping stm32l475xx 78/193 docid027692 rev 2 apb1 0x4000 9800 - 0x4000 ffff 26 kb reserved 0x4000 9400 - 0x4000 97ff 1 kb lptim2 0x4000 8c00 - 0x4000 93ff 2 kb reserved 0x4000 8800 - 0x4000 8bff 1 kb swpmi1 0x4000 8400 - 0x4000 87ff 1 kb reserved 0x4000 8000 - 0x4000 83ff 1 kb lpuart1 0x4000 7c00 - 0x4000 7fff 1 kb lptim1 0x4000 7800 - 0x4000 7bff 1 kb opamp 0x4000 7400 - 0x4000 77ff 1 kb dac 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6800 - 0x4000 6fff 1 kb reserved 0x4000 6400 - 0x4000 67ff 1 kb can1 0x4000 6000 - 0x4000 63ff 1 kb reserved 0x4000 5c00- 0x4000 5fff 1 kb i2c3 0x4000 5800 - 0x4000 5bff 1 kb i2c2 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 5000 - 0x4000 53ff 1 kb uart5 0x4000 4c00 - 0x4000 4fff 1 kb uart4 0x4000 4800 - 0x4000 4bff 1 kb usart3 0x4000 4400 - 0x4000 47ff 1 kb usart2 table 18. stm32l475xx memory map and peripheral register boundary addresses (continued) (1) bus boundary address size (bytes) peripheral docid027692 rev 2 79/193 stm32l475xx memory mapping 79 apb1 0x4000 4000 - 0x4000 43ff 1 kb reserved 0x4000 3c00 - 0x4000 3fff 1 kb spi3 0x4000 3800 - 0x4000 3bff 1 kb spi2 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 1800 - 0x4000 27ff 4 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0c00- 0x4000 0fff 1 kb tim5 0x4000 0800 - 0x4000 0bff 1 kb tim4 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb tim2 1. the gray color is used for reserved boundary addresses. table 18. stm32l475xx memory map and peripheral register boundary addresses (continued) (1) bus boundary address size (bytes) peripheral electrical characteristics stm32l475xx 80/193 docid027692 rev 2 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading conditions figure 9. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid027692 rev 2 81/193 stm32l475xx electrical characteristics 181 6.1.6 power supply scheme figure 10. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 y 9 $ ' & v ' $ & v 2 3 $ 0 3 v & 2 0 3 v 9 5 ( ) % 8 ) 9 5 ( ) 9 5 ( ) 9 ' ' $ v & ? ) 9 ' ' $ 9 6 6 $ 9 5 ( ) v & ? ) 9 ' ' / h y h o v k l i w h u , 2 o r j l f < ?v o o}p] ~ w hu ]p]?o ? d u}?] ? l? ]?]??? ~ > ^ u z d u l? ? p]?? ?? / e k h d z po?}? * 3 , 2 v x?? t ?x s q [ q ) [ ? ) q [ 9 6 6 q [ 9 ' ' 9 % $ 7 9 & 2 5 ( w} ? ?]?z 9 ' ' , 2 electrical characteristics stm32l475xx 82/193 docid027692 rev 2 6.1.7 current consumption measurement figure 11. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 19: voltage characteristics , table 20: current characteristics and table 21: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. 0 6 y 9 , ' ' b 8 6 % 9 ' ' 8 6 % , ' ' b 9 % $ 7 9 % $ 7 , ' ' 9 ' ' , ' ' $ 9 ' ' $ table 19. voltage characteristics (1) symbol ratings min max unit v ddx - v ss external main supply voltage (including v dd , v dda , v ddusb , v bat ) -0.3 4.0 v v in (2) input voltage on ft_xxx pins v ss -0.3 min (v dd , v dda , v ddusb ) + 4.0 (3)(4) v input voltage on tt_xx pins v ss -0.3 4.0 input voltage on boot0 pin v ss 9.0 input voltage on any other pins v ss -0.3 4.0 | ? v ddx | variations between different v ddx power pins of the same domain -50mv |v ssx -v ss | variations between all the different ground pins (5) -50mv docid027692 rev 2 83/193 stm32l475xx electrical characteristics 181 1. all main power (v dd , v dda , v ddusb , v bat ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. v in maximum must always be respected. refer to table 20: current characteristics for the maximum allowed injected current values. 3. this formula has to be applied only on the power supplies related to the io struct ure described in the pin definition table. 4. to sustain a voltage higher than 4 v the internal pull-up/pull-down resistors must be disabled. 5. include vref- pin. table 20. current characteristics symbol ratings max unit iv dd total current into sum of all v dd power lines (source) (1) 150 ma iv ss total current out of sum of all v ss ground lines (sink) (1) 150 iv dd(pin) maximum current into each v dd power pin (source) (1) 100 iv ss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io(pin) output current sunk by any i/o and control pin except ft_f 20 output current sunk by any ft_f pin 20 output current sourced by any i/o and control pin 20 i io(pin) total output current sunk by sum of all i/os and control pins (2) 100 total output current sourced by sum of all i/os and control pins (2) 100 i inj(pin) (3) injected current on ft_xxx, tt_xx, rst and b pins, except pa4, pa5 -5/+0 (4) injected current on pa4, pa5 -5/0 |i inj(pin) | total injected current (sum of all i/os and control pins) (5) 25 1. all main power (v dd , v dda , v ddusb , v bat ) and ground (v ss , v ssa ) pins must always be connected to the external power supplies, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 3. positive injection (when v in > v ddiox ) is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer also to table 19: voltage characteristics for the minimum allowed input voltage values. 5. when several inputs are submitted to a current injection, the maximum | i inj(pin) | is the absolute sum of the negative injected currents (instantaneous values). table 21. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c electrical characteristics stm32l475xx 84/193 docid027692 rev 2 6.3 operating conditions 6.3.1 general operating conditions table 22. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 80 mhz f pclk1 internal apb1 clock frequency - 0 80 f pclk2 internal apb2 clock frequency - 0 80 v dd standard operating voltage - 1.71 (1) 3.6 v v dda analog supply voltage adc or comp used 1.62 3.6 v dac or opamp used 1.8 vrefbuf used 2.4 adc, dac, opamp, comp, vrefbuf not used 0 v bat backup operating voltage - 1.55 3.6 v v ddusb usb supply voltage usb used 3.0 3.6 v usb not used 0 3.6 v in i/o input voltage tt_xx i/o -0.3 v ddiox +0.3 v boot0 0 9 all i/o except boot0 and tt_xx -0.3 min(min(v dd , v dda , v ddusb )+3.6 v, 5.5 v) (2)(3) p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (4) lqfp100 - - 476 mw lqfp64 - - 444 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low-power dissipation (5) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 low-power dissipation (5) ?40 125 ambient temperature for the suffix 3 version maximum power dissipation ?40 125 low-power dissipation (5) ?40 130 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 suffix 3 version ?40 130 1. when reset is released functi onality is guaranteed down to v bor0 min. 2. this formula has to be applied only on the power supplies related to the io structur e described by the pin definition table. maximum i/o input voltage is the smallest value between min(v dd , v dda , v ddusb )+3.6 v and 5.5v. 3. for operation with voltage higher than min (v dd , v dda , v ddusb ) +0.3 v, the internal pull-up and pull-down resistors must be disabled. docid027692 rev 2 85/193 stm32l475xx electrical characteristics 181 6.3.2 operating conditions at power-up / power-down the parameters given in table 23 are derived from tests performed under the ambient temperature condition summarized in table 22 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 24 are derived from tests performed under the ambient temperature conditions summarized in table 22: general operating conditions . 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section 7.3: thermal characteristics ). 5. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.3: thermal characteristics ). table 23. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 10 t vdda v dda rise time rate - 0 s/v v dda fall time rate 10 t vddusb v ddusb rise time rate - 0 s/v v ddusb fall time rate 10 table 24. embedded reset and power control block characteristics symbol parameter conditions (1) min typ max unit t rsttempo (2) reset temporization after bor0 is detected v dd rising - 250 400 s v bor0 (2) brown-out reset threshold 0 rising edge 1.62 1.66 1.7 v falling edge 1.6 1.64 1.69 v bor1 brown-out reset threshold 1 rising edge 2.06 2.1 2.14 v falling edge 1.96 2 2.04 v bor2 brown-out reset threshold 2 rising edge 2.26 2.31 2.35 v falling edge 2.16 2.20 2.24 v bor3 brown-out reset threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v bor4 brown-out reset threshold 4 rising edge 2.85 2.90 2.95 v falling edge 2.76 2.81 2.86 v pvd0 programmable voltage detector threshold 0 rising edge 2.1 2.15 2.19 v falling edge 2 2.05 2.1 v pvd1 pvd threshold 1 rising edge 2.26 2.31 2.36 v falling edge 2.15 2.20 2.25 electrical characteristics stm32l475xx 86/193 docid027692 rev 2 v pvd2 pvd threshold 2 rising edge 2.41 2.46 2.51 v falling edge 2.31 2.36 2.41 v pvd3 pvd threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v pvd4 pvd threshold 4 rising edge 2.69 2.74 2.79 v falling edge 2.59 2.64 2.69 v pvd5 pvd threshold 5 rising edge 2.85 2.91 2.96 v falling edge 2.75 2.81 2.86 v pvd6 pvd threshold 6 rising edge 2.92 2.98 3.04 v falling edge 2.84 2.90 2.96 v hyst_borh0 hysteresis voltage of borh0 hysteresis in continuous mode -20- mv hysteresis in other mode -30- v hyst_bor_pvd hysteresis voltage of borh (except borh0) and pvd --100-mv i dd (bor_pvd) (2) bor (3) (except bor0) and pvd consumption from v dd --1.11.6a v pvm1 v ddusb peripheral voltage monitoring - 1.18 1.22 1.26 v v pvm3 v dda peripheral voltage monitoring rising edge 1.61 1.65 1.69 v falling edge 1.6 1.64 1.68 v pvm4 v dda peripheral voltage monitoring rising edge 1.78 1.82 1.86 v falling edge 1.77 1.81 1.85 v hyst_pvm3 pvm3 hysteresis - - 10 - mv v hyst_pvm4 pvm4 hysteresis - - 10 - mv i dd (pvm1/pvm2) (2) pvm1 and pvm2 consumption from v dd --0.2-a i dd (pvm3/pvm4) (2) pvm3 and pvm4 consumption from v dd --2-a 1. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. 2. guaranteed by design. 3. bor0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. table 24. embedded reset and power control block characteristics (continued) symbol parameter conditions (1) min typ max unit docid027692 rev 2 87/193 stm32l475xx electrical characteristics 181 6.3.4 embedded voltage reference the parameters given in table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . table 25. embedded internal voltage reference symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +130 c 1.182 1.212 1.232 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -4 (2) -- s t start_vrefint start time of reference voltage buffer when adc is enable --812 (2) s i dd (v refintbuf ) v refint buffer consumption from v dd when converted by adc - - 12.5 20 (2) a ? v refint internal reference voltage spread over the temperature range v dd = 3 v - 5 7.5 (2) mv t coeff average temperature coefficient ?40c < t a < +130c - 30 50 (2) ppm/c a coeff long term stability 1000 hours, t = 25c - - tbd (2) ppm v ddcoeff average voltage coefficient 3.0 v < v dd < 3.6 v - 250 1200 (2) ppm/v v refint_div1 1/4 reference voltage - 24 25 26 % v refint v refint_div2 1/2 reference voltage 49 50 51 v refint_div3 3/4 reference voltage 74 75 76 1. the shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design. electrical characteristics stm32l475xx 88/193 docid027692 rev 2 figure 12. v refint versus temperature 0 6 y 9 9 ? & 0 h d q 0 l q 0 d [ docid027692 rev 2 89/193 stm32l475xx electrical characteristics 181 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted with the minimum wait states number, depending on the f hclk frequency (refer to the table ?number of wait states according to cpu clock (hclk) frequency? available in the rm0395 reference manual). ? when the peripherals are enabled f pclk = f hclk the parameters given in table 26 to table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . electrical characteristics stm32l475xx 90/193 docid027692 rev 2 table 26. current consumption in run and low-power run modes, code with data processing running from flash, art enable (cache on prefetch off) symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.88 2.93 3.05 3.23 3.58 3.20 3.37 3.51 3.93 4.76 ma 16 mhz 1.83 1.87 1.98 2.16 2.49 2.01 2.16 2.30 2.72 3.34 8 mhz 0.98 1.02 1.12 1.29 1.62 1.10 1.17 1.31 1.73 2.56 4 mhz 0.55 0.59 0.69 0.85 1.18 0.61 0.70 0.89 1.24 1.95 2 mhz 0.34 0.37 0.47 0.64 0.96 0.37 0.46 0.64 0.98 1.71 1 mhz 0.23 0.26 0.36 0.53 0.85 0.27 0.33 0.50 0.86 1.57 100 khz 0.14 0.17 0.27 0.43 0.75 0.17 0.21 0.38 0.74 1.44 range 1 80 mhz 10.2 10.3 10.5 10.7 1 1.1 11.22 11.8 12.1 12.5 13.3 72 mhz 9.24 9.31 9.47 9.69 10.1 10.16 10.7 11.0 11.4 12.2 64 mhz 8.25 8.32 8.46 8.68 9.09 9.08 9.6 9.9 10.3 11.1 48 mhz 6.28 6.35 6.5 6.72 7.11 6.91 7.3 7.6 8.0 8.8 32 mhz 4.24 4.30 4.44 4.65 5.04 4.66 4.97 5.26 5.67 6.51 24 mhz 3.21 3.27 3.4 3.61 3.98 3.53 3.76 4.05 4.46 5.30 16 mhz 2.19 2.24 2.36 2.56 2.94 2.41 2.66 2.95 3.16 3.99 i dd (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable 2 mhz 272 303 413 592 958 330 393 579 954 1704 a 1 mhz 154 184 293 473 835 195 265 457 822 1572 400 khz 78 108 217 396 758 110 180 380 755 1505 100 khz 42 73 182 360 723 75 138 331 706 1456 1. guaranteed by characterization re sults, unless otherwise specified. stm32l475xx electrical characteristics docid027692 rev 2 91/193 table 27. current consumption in run and low-power run modes, code with data processing running from flash, art disable symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 3.15 3.19 3.31 3.50 3.85 3.47 3.70 3.84 4.26 4.88 ma 16 mhz 2.24 2.28 2.39 2.57 2.90 2.46 2.60 2.74 3.16 3.78 8 mhz 1.26 1.29 1.40 1.57 1.89 1.40 1.50 1.64 2.06 2.68 4 mhz 0.71 0.75 0.85 1.02 1.34 0.79 0.88 1.06 1.38 2.21 2 mhz 0.42 0.45 0.55 0.72 1.04 0.46 0.55 0.73 1.09 1.88 1 mhz 0.27 0.30 0.40 0.57 0.89 0.30 0.38 0.57 0.90 1.61 100 khz 0.14 0.17 0.27 0.43 0.75 0.17 0.22 0.40 0.74 1.44 range 1 80 mhz 10.0 10.1 10.3 10.6 11. 0 11.00 11.35 11.64 12.26 13.10 72 mhz 9.06 9.13 9.28 9.51 9.92 9.97 10.36 10.65 11.06 11.69 64 mhz 8.96 9.04 9.22 9.48 9.92 9.86 10.25 10.54 10.95 11.79 48 mhz 7.64 7.72 7.91 8.17 8.62 8.40 8.76 8.90 9.52 10.36 32 mhz 5.49 5.57 5.74 5.98 6.40 6.04 6.40 6.69 7.10 7.94 24 mhz 4.16 4.22 4.36 4.57 4.96 4.60 4.86 5.15 5.56 6.19 16 mhz 2.93 2.99 3.13 3.35 3.75 3.22 3.43 3.72 4.13 4.97 i dd (lprun) supply current in low-power run f hclk = f msi all peripherals disable 2 mhz 358 392 503 683 1050 435 501 694 1069 1819 a 1 mhz 197 230 340 519 880 245 312 512 887 1637 400 khz 97 126 235 414 778 130 202 402 777 1527 100 khz 47 77 186 365 726 85 147 347 711 1472 1. guaranteed by characterization re sults, unless otherwise specified. electrical characteristics stm32l475xx 92/193 docid027692 rev 2 table 28. current consumption in run and low-power run modes, code with data processing running from sram1 symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.88 2.94 3.05 3.23 3.58 3.18 3.26 3.40 4.02 4.65 ma 16 mhz 1.83 1.87 1.98 2.15 2.50 2.01 2.16 2.30 2.72 3.34 8 mhz 0.97 1.00 1.11 1.27 1.62 1.07 1.16 1.32 1.73 2.36 4 mhz 0.54 0.57 0.67 0.84 1.18 0.59 0.69 0.88 1.23 1.96 2 mhz 0.33 0.36 0.46 0.62 0.96 0.37 0.45 0.63 0.98 1.70 1 mhz 0.22 0.25 0.35 0.51 0.85 0.25 0.33 0.50 0.86 1.57 100 khz 0.12 0.15 0.25 0.41 0.75 0.15 0.21 0.39 0.74 1.45 range 1 80 mhz 10.2 10.3 10.5 10.7 11.1 11.22 11.57 11.86 12.07 13.11 72 mhz 9.25 9.31 9.46 9.68 10.1 10.18 10.41 10.55 10.76 11.80 64 mhz 8.25 8.31 8.46 8.67 9.08 9.08 9.37 9.66 9.87 10.91 48 mhz 6.26 6.33 6.48 6.69 7.11 6.89 7.11 7.25 7.67 8.50 32 mhz 4.22 4.28 4.42 4.63 5.03 4.64 4.86 5.15 5.56 6.19 24 mhz 3.20 3.25 3.38 3.59 3.99 3.52 3.70 3.84 4.26 5.09 16 mhz 2.18 2.22 2.35 2.55 2.94 2.40 2.55 2.84 3.25 4.09 i dd (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable flash in power-down 2 mhz 242 275 384 562 924 300 380 573 927 1677 a 1 mhz 130 162 269 445 809 180 243 435 810 1560 400 khz 61 90 197 374 734 95 160 353 728 1478 100 khz 26 56 163 339 702 55 122 314 679 1429 1. guaranteed by characterization re sults, unless otherwise specified. docid027692 rev 2 93/193 stm32l475xx electrical characteristics 181 table 29. typical current consumption in run and low-power run modes, with different codes running from flash, art enable (cache on prefetch off) symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.9 ma 111 a/mhz coremark 3.1 118 dhrystone 2.1 3.1 119 fibonacci 2.9 112 while(1) 2.8 108 range 1 f hclk = 80 mhz reduced code (1) 10.2 ma 127 a/mhz coremark 10.9 136 dhrystone 2.1 11.0 137 fibonacci 10.5 131 while(1) 9.9 124 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 272 a 136 a/mhz coremark 291 145 dhrystone 2.1 302 151 fibonacci 269 135 while(1) 269 135 1. reduced code used for characterization results provided in table 26 , table 27 , table 28 . electrical characteristics stm32l475xx 94/193 docid027692 rev 2 table 30. typical current consumption in run and low-power run modes, with different codes running from flash, art disable symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 3.1 ma 119 a/mhz coremark 2.9 111 dhrystone 2.1 2.8 111 fibonacci 2.7 104 while(1) 2.6 100 range 1 f hclk = 80 mhz reduced code (1) 10.0 ma 125 a/mhz coremark 9.4 117 dhrystone 2.1 9.1 114 fibonacci 9.0 112 while(1) 9.3 116 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 358 a 179 a/mhz coremark 392 196 dhrystone 2.1 390 195 fibonacci 385 192 while(1) 385 192 1. reduced code used for characterization results provided in table 26 , table 27 , table 28 . table 31. typical current consumption in run and low-power run modes, with different codes running from sram1 symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.9 ma 111 a/mhz coremark 2.9 111 dhrystone 2.1 2.9 111 fibonacci 2.6 100 while(1) 2.6 100 range 1 f hclk = 80 mhz reduced code (1) 10.2 ma 127 a/mhz coremark 10.4 130 dhrystone 2.1 10.3 129 fibonacci 9.6 120 while(1) 9.3 116 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 242 a 121 a/mhz coremark 242 121 dhrystone 2.1 242 121 fibonacci 225 112 while(1) 242 121 1. reduced code used for characterization results provided in table 26 , table 27 , table 28 . stm32l475xx electrical characteristics docid027692 rev 2 95/193 table 32. current consumption in sleep and low-power sleep modes, flash on symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (sleep) supply current in sleep mode, f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 0.92 0.96 1.07 1.25 1.59 1.012 1.14 1.36 1.77 2.40 ma 16 mhz 0.61 0.65 0.75 0.92 1.27 0.69 0.78 0.97 1.32 2.04 8 mhz 0.36 0.40 0.50 0.66 1.01 0.42 0.50 0.68 1.03 1.75 4 mhz 0.24 0.27 0.37 0.53 0.87 0.28 0.36 0.54 0.89 1.60 2 mhz 0.18 0.20 0.30 0.47 0.81 0.215 0.29 0.46 0.82 1.53 1 mhz 0.15 0.17 0.27 0.43 0.77 0.18 0.25 0.44 0.78 1.49 100 khz 0.12 0.14 0.24 0.41 0 .74 0.15 0.21 0.39 0.74 1.44 range 1 80 mhz 2.96 3.00 3.13 3.33 3.73 3.26 3.43 3.72 4.13 4.97 72 mhz 2.69 2.73 2.85 3.05 3.45 2.96 3.21 3.50 3.71 4.54 64 mhz 2.41 2.45 2.58 2.77 3.17 2.65 2.88 3.17 3.58 4.21 48 mhz 1.88 1.93 2.07 2.27 2.67 2.10 2.27 2.41 2.83 3.66 32 mhz 1.30 1.35 1.48 1.68 2.08 1.43 1.56 1.85 2.26 3.10 24 mhz 1.01 1.05 1.17 1.37 1.76 1.11 1.23 1.52 1.93 2.77 16 mhz 0.71 0.75 0.87 1.07 1.45 0.80 0.90 1.19 1.60 2.44 i dd (lpsleep) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 96 126 233 412 775 130 202 402 777 1527 a 1 mhz 65 94 202 381 742 95 166 358 733 1483 400 khz 43 73 181 359 718 75 138 331 706 1456 100 khz 33 63 171 348 708 65 128 322 691 1441 1. guaranteed by characterization re sults, unless otherwise specified. electrical characteristics stm32l475xx 96/193 docid027692 rev 2 table 33. current consumption in low-pow er sleep modes, flash in power-down symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (lpsleep ) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 81 110 217 395 754 115 182 375 750 1500 a 1 mhz 50 78 185 362 720 80 149 342 717 1456 400 khz 28 57 163 340 698 60 122 314 689 1429 100 khz 18 47 155 332 686 50 114 313 688 1438 1. guaranteed by characterization re sults, unless otherwise specified. table 34. current consumption in stop 2 mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 2) supply current in stop 2 mode, rtc disabled - 1.8 v 1.14 3.77 14.7 34.7 77 2.7 9 37 87 193 a 2.4 v 1.15 3.86 15 35.5 79.1 2.7 10 38 89 198 3 v 1.18 3.97 15.4 36.4 81.3 2.8 10 39 91 203 3.6 v 1.26 4.11 16 38 85.1 3.0 10 40 95 (2) 213 i dd (stop 2 with rtc) supply current in stop 2 mode, rtc enabled rtc clocked by lsi 1.8 v 1.42 4.04 15 34.9 77.2 3.1 10 38 87 193 a 2.4 v 1.5 4.22 15.4 35.7 79.2 3.2 11 39 89 198 3 v 1.64 4.37 15.8 36.7 81.4 3.4 11 40 92 204 3.6 v 1.79 4.65 16.6 38.4 85.4 3.6 12 42 96 214 rtc clocked by lse bypassed at 32768 hz 1.8 v 1.5 4.13 15.2 35.3 77.6 3.2 10 38 88 194 2.4 v 1.63 4.33 15.6 36 79.6 3.4 11 39 90 199 3 v 1.79 4.55 16.1 37 81.8 3.6 11 40 93 205 3.6 v 2.04 4.9 16.8 38.7 85.6 3.9 12 42 97 214 rtc clocked by lse quartz (3) in low drive mode 1.8 v 1.43 3.99 14.7 35 - 3.2 10 37 88 - 2.4 v 1.54 4.11 15 35.8 - 3.3 10 38 90 - 3 v 1.67 4.29 15.5 36.7 - 3.4 11 39 92 - 3.6 v 1.87 4.57 16.2 38.3 - 3.7 11 41 96 - stm32l475xx electrical characteristics docid027692 rev 2 97/193 i dd (wakeup from stop2) supply current during wakeup from stop 2 mode wakeup clock is msi = 48 mhz, voltage range 1. see (4) . 3 v 1.9 - - - - -ma wakeup clock is msi = 4 mhz, voltage range 2. see (4) . 3 v 2.24 - - - - wakeup clock is hsi16 = 16 mhz, voltage range 1. see (4) . 3 v 2.1 - - - - 1. guaranteed based on test during charac terization, unless otherwise specified. 2. guaranteed by test in production. 3. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 41: low-power mode wakeup timings . table 34. current consumption in stop 2 mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c electrical characteristics stm32l475xx 98/193 docid027692 rev 2 table 35. current consumption in stop 1 mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 1) supply current in stop 1 mode, rtc disabled - 1.8 v 6.59 24.7 92.7 208 437 16 62 232 520 1093 a 2.4 v 6.65 24.8 92.9 209 439 17 62 232 523 1098 3 v 6.65 24.9 93.3 210 442 17 62 233 525 1105 3.6 v 6.70 25.1 93.8 212 447 17 63 235 530 1118 i dd (stop 1 with rtc) supply current in stop 1 mode, rtc enabled rtc clocked by lsi 1.8 v 6.88 25.0 93.1 209 439 17 63 233 523 1098 a 2.4 v 7.02 25.2 93.7 210 441 18 63 234 525 1103 3 v 7.12 25.4 94.2 212 444 18 64 236 530 1110 3.6 v 7.25 25.7 95.2 214 449 18 64 238 535 1123 rtc clocked by lse bypassed, at 32768 hz 1.8 v 6.91 25.2 93.4 210 440 17 63 234 525 1100 2.4 v 7.04 25.3 94.2 211 443 18 63 236 528 1108 3 v 7.19 25.7 95.0 212 446 18 64 238 530 1115 3.6 v 7.97 26.0 96.1 215 451 20 65 240 538 1128 rtc clocked by lse quartz (2) in low drive mode 1.8 v 6.85 25.0 93.0 208.3 - 17 63 233 521 - 2.4 v 6.94 25.1 93.2 209.3 - 17 63 233 523 - 3 v 7.10 25.2 93.6 210.3 - 18 63 234 526 - 3.6 v 7.34 25.4 94.1 212.3 - 18 64 235 531 - i dd (wakeup from stop1) supply current during wakeup from stop 1 wakeup clock msi = 48 mhz, voltage range 1, see (3) . 3 v 1.47 - - - - -ma wakeup clock msi = 4 mhz, voltage range 2, see (3) . 3 v 1.7 - - - - wakeup clock hsi16 = 16 mhz, voltage range 1, see (3) . 3 v 1.62 - - - - 1. guaranteed based on test during charac terization, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 41: low-power mode wakeup timings . stm32l475xx electrical characteristics docid027692 rev 2 99/193 table 36. current consumption in stop 0 mode symbol parameter conditions typ max (1) 1. guaranteed by characterization re sults, unless otherwise specified. unit v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 0) supply current in stop 0 mode, rtc disabled 1.8 v 108 132 217 356 631 153 213 426 773 1461 a 2.4 v 110 134 219 358 634 158 218 431 778 1468 3 v 111 135 220 360 637 161 221 433 783 1476 3.6 v 113 137 222 363 642 166 226 438 791 (2) 2. guaranteed by test in production. 1488 electrical characteristics stm32l475xx 100/193 docid027692 rev 2 table 37. current consumption in standby mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (standby) supply current in standby mode (backup registers retained), rtc disabled no independent watchdog 1.8 v 114 355 1540 4146 10735 176 888 3850 10365 26838 na 2.4 v 138 407 1795 4828 12451 223 1018 4488 12070 31128 3 v 150 486 2074 5589 14291 263 1215 5185 13973 35728 3.6 v 198 618 2608 6928 17499 383 1545 6520 17320 (2) 43748 with independent watchdog 1.8 v 317 - - - - - - - - - 2.4 v 391 - - - - - - - - - 3 v 438 - - - - - - - - - 3.6 v 566 - - - - - - - - - i dd (standby with rtc) supply current in standby mode (backup registers retained), rtc enabled rtc clocked by lsi, no independent watchdog 1.8 v 377 621 1873 4564 11318 491 1207 4250 10867 27537 na 2.4 v 464 756 2210 5348 13166 614 1436 4986 12694 31986 3 v 572 913 2599 6219 15197 770 1727 5815 14729 36815 3.6 v 722 1144 3253 7724 18696 1012 2176 7294 18275 45184 rtc clocked by lsi, with independent watchdog 1.8 v 456 - - - - - - - - - 2.4 v 557 - - - - - - - - - 3 v 663 - - - - - - - - - 3.6 v 885 - - - - - - - - - rtc clocked by lse bypassed at 32768hz 1.8 v 289 527 1747 4402 11009 - - - - - na 2.4 v 396 671 2108 5202 12869 - - - - - 3 v 528 853 2531 6095 14915 - - - - - 3.6 v 710 1111 3115 7470 18221 - - - - - rtc clocked by lse quartz (3) in low drive mode 1.8 v 416 640 1862 4479 11908 - - - - - 2.4 v 514 796 2193 5236 13689 - - - - - 3 v 652 961 2589 6103 15598 - - - - - 3.6 v 821 1226 3235 7551 17947 - - - - - stm32l475xx electrical characteristics docid027692 rev 2 101/193 i dd (sram2) (4) supply current to be added in standby mode when sram2 is retained - 1.8 v 235 641 2293 5192 11213 588 1603 5733 12980 28033 na 2.4 v 237 645 2303 5213 11246 593 1613 5758 13033 28115 3 v 236 647 2306 5221 11333 593 1618 5765 13053 28333 3.6 v 235 646 2308 5200 11327 595 1620 5770 13075 28350 i dd (wakeup from standby) supply current during wakeup from standby mode wakeup clock is msi = 4 mhz. see (5) . 3 v 1.7 - - - - - ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. guaranteed by test in production. 3. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. the supply current in standby with sram2 mode is: i dd (standby) + i dd (sram2). the supply current in standby with rtc with sram2 mode is: i dd (standby + rtc) + i dd (sram2). 5. wakeup with code execution from flash. average val ue given for a typical wak eup time as specified in table 41: low-power mode wakeup timings . table 37. current consumption in standby mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c table 38. current consumption in shutdown mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (shutdown) supply current in shutdown mode (backup registers retained) rtc disabled - 1.8 v 29.8 194 1110 3250 9093 75 485 2775 8125 22733 na 2.4 v 44.3 237 1310 3798 10473 111 593 3275 9495 26183 3 v 64.1 293 1554 4461 12082 160 733 3885 11153 30205 3.6 v 112 420 2041 5689 15186 280 1050 5103 14223 37965 electrical characteristics stm32l475xx 102/193 docid027692 rev 2 i dd (shutdown with rtc) supply current in shutdown mode (backup registers retained) rtc enabled rtc clocked by lse bypassed at 32768 hz 1.8 v 210 378 1299 3437 9357 - - - - - na 2.4 v 303 499 1577 4056 10825 - - - - - 3 v 422 655 1925 4820 12569 - - - - - 3.6 v 584 888 2511 6158 15706 - - - - - rtc clocked by lse quartz (2) in low drive mode 1.8 v 329 499 1408 3460 - - - - - - 2.4 v 431 634 1688 4064 - - - - - - 3 v 554 791 2025 4795 - - - - - - 3.6 v 729 1040 2619 6129 - - - - - - i dd (wakeup from shutdown) supply current during wakeup from shutdown mode wakeup clock is msi = 4 mhz. see (3) . 3 v 0.6 - - - - - - - - - ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 41: low-power mode wakeup timings . table 38. current consumption in shutdown mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c stm32l475xx electrical characteristics docid027692 rev 2 103/193 table 39. current consumption in vbat mode symbol parameter conditions typ max (1) unit -v bat 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (vbat) backup domain supply current rtc disabled 1.8 v 4 29 196 587 1663 10.8 73 490 1468 4158 na 2.4 v 5.27 36 226 673 1884 13.2 90 565 1683 4710 3 v 6 42 264 775 2147 15.5 106 660 1938 5368 3.6 v 10 58 323 919 2488 25.8 144 808 2298 6220 rtc enabled and clocked by lse bypassed at 32768 hz 1.8 v 183 201 367 729 - - - - - - 2.4 v 268 295 486 901 - - - - - - 3 v 376 412 602 1075 - - - - - - 3.6 v 508 558 752 1299 - - - - - - rtc enabled and clocked by lse quartz (2) 1.8 v 302 344 521 915 1978 - - - - - 2.4 v 388 436 639 1091 2289 - - - - - 3 v 494 549 784 1301 2656 - - - - - 3.6 v 630 692 971 1571 3115 - - - - - 1. guaranteed by characterization re sults, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. electrical characteristics stm32l475xx 104/193 docid027692 rev 2 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 59: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 40: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v ddiox f sw c = docid027692 rev 2 105/193 stm32l475xx electrical characteristics 181 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 40 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? the given value is calculated by measuring the difference of the current consumptions: ? when the peripheral is clocked on ? when the peripheral is clocked off ? ambient operating temperature and supply voltage conditions summarized in table 19: voltage characteristics ? the power consumption of the digital part of the on-chip peripherals is given in table 40 . the power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. table 40. peripheral current consumption peripheral range 1 range 2 low-power run and sleep unit ahb bus matrix (1) 4.5 3.7 4.1 a/mhz adc independent clock domain 0.4 0.1 0.2 adc ahb clock domain 5.5 4.7 5.5 crc 0.4 0.2 0.3 dma1 1.4 1.3 1.4 dma2 1.5 1.3 1.4 flash 6.2 5.2 5.8 fmc 8.9 7.5 8.4 gpioa (2) 4.8 3.8 4.4 gpiob (2) 4.8 4.0 4.6 gpioc (2) 4.5 3.8 4.3 gpiod (2) 4.6 3.9 4.4 gpioe (2) 5.2 4.5 4.9 gpiof (2) 5.9 4.9 5.7 gpiog (2) 4.3 3.8 4.2 gpioh (2) 0.7 0.6 0.8 otg_fs independent clock domain 23.2 na na otg_fs ahb clock domain 16.4 na na quadspi 7.8 6.7 7.3 rng independent clock domain 2.2 na na rng ahb clock domain 0.6 na na sram1 0.9 0.8 0.9 electrical characteristics stm32l475xx 106/193 docid027692 rev 2 ahb sram2 1.6 1.4 1.6 a/mhz tsc 1.8 1.4 1.6 all ahb peripherals 118.5 77.3 87.6 apb1 ahb to apb1 bridge (3) 0.9 0.7 0.9 a/mhz can1 4.6 4.0 4.4 dac1 2.4 1.9 2.2 i2c1 independent clock domain 3.7 3.1 3.2 i2c1 apb clock domain 1.3 1.1 1.5 i2c2 independent clock domain 3.7 3.0 3.2 i2c2 apb clock domain 1.4 1.1 1.5 i2c3 independent clock domain 2.9 2.3 2.5 i2c3 apb clock domain 0.9 0.9 1.1 lpuart1 independent clock domain 2.1 1.6 2.0 lpuart1 apb clock domain 0.6 0.6 0.6 lptim1 independent clock domain 3.3 2.6 2.9 lptim1 apb clock domain 0.9 0.8 1.0 lptim2 independent clock domain 3.1 2.7 2.9 lptim2 apb clock domain 0.8 0.6 0.7 opamp 0.4 0.4 0.3 pwr 0.5 0.5 0.4 spi2 1.8 1.6 1.6 spi3 2.1 1.7 1.8 swpmi1 independent clock domain 2.3 1.8 2.2 swpmi1 apb clock domain 1.1 1.1 1.0 tim2 6.8 5.7 6.3 tim3 5.4 4.6 5.0 tim4 5.2 4.4 4.9 tim5 6.5 5.5 6.1 tim6 1.1 1.0 1.0 tim7 1.1 0.9 1.0 table 40. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit docid027692 rev 2 107/193 stm32l475xx electrical characteristics 181 apb1 usart2 independent clock domain 4.1 3.6 3.8 a/mhz usart2 apb clock domain 1.4 1.1 1.5 usart3 independent clock domain 4.7 4.1 4.2 usart3 apb clock domain 1.5 1.3 1.7 uart4 independent clock domain 3.9 3.2 3.5 uart4 apb clock domain 1.5 1.3 1.6 uart5 independent clock domain 3.9 3.2 3.5 uart5 apb clock domain 1.3 1.2 1.4 wwdg 0.5 0.5 0.5 all apb1 on 84.2 70.7 80.2 apb2 ahb to apb2 bridge (4) 1.0 0.9 0.9 dfsdm 5.6 4.6 5.3 fw 0.7 0.5 0.7 sai1 independent clock domain 2.6 2.1 2.3 sai1 apb clock domain 2.1 1.8 2.0 sai2 independent clock domain 3.3 2.7 3.0 sai2 apb clock domain 2.4 2.1 2.2 sdmmc1 independent clock domain 4.7 3.9 4.2 sdmmc1 apb clock domain 2.5 1.9 2.1 spi1 2.0 1.6 1.9 syscfg/vrefbuf/comp 0.6 0.4 0.5 tim1 8.3 6.9 7.9 tim8 8.6 7.1 8.1 tim15 4.1 3.4 3.9 tim16 3.0 2.5 2.9 tim17 3.0 2.4 2.9 usart1 independent clock domain 4.9 4.0 4.4 usart1 apb clock domain 1.5 1.3 1.7 all apb2 on 56.8 43.3 48.2 all 256.8 189.6 215.5 table 40. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit electrical characteristics stm32l475xx 108/193 docid027692 rev 2 6.3.6 wakeup time from low-po wer modes and voltage scaling transition times the wakeup times given in table 41 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction. 1. the busmatrix is automatica lly active when at least one master is on (cpu, dma). 2. the gpiox (x= a?h) dynamic current cons umption is approximately divided by a fact or two versus this table values when the gpio port is locked thanks to lckk and lcky bits in the gpio x_lckr register. in order to save the full gpiox current consumption, the gpiox clock should be disabled in the rcc when all port i/os ar e used in alternate function or analog mode (clock is only required to read or write into gp io registers, and is not used in af or analog modes). 3. the ahb to apb1 bridge is automatically active when at least one peripheral is on on the apb1. 4. the ahb to apb2 bridge is automatically active when at least one peripheral is on on the apb2. table 41. low-power mode wakeup timings (1) symbol parameter conditions typ max unit t wusleep wakeup time from sleep mode to run mode -66 nb of cpu cycles t wulpsleep wakeup time from low- power sleep mode to low- power run mode wakeup in flash with flash in power-down during low-power sleep mode (sleep_pd=1 in flash_acr) and with clock msi = 2 mhz 69.3 t wustop0 wake up time from stop 0 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 5.6 10.9 s wakeup clock hsi16 = 16 mhz 4.7 10.4 range 2 wakeup clock msi = 24 mhz 5.7 11.1 wakeup clock hsi16 = 16 mhz 4.5 10.5 wakeup clock msi = 4 mhz 6.6 14.2 wake up time from stop 0 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 0.7 2.05 wakeup clock hsi16 = 16 mhz 1.7 2.8 range 2 wakeup clock msi = 24 mhz 0.8 2.72 wakeup clock hsi16 = 16 mhz 1.7 2.8 wakeup clock msi = 4 mhz 2.4 11.32 docid027692 rev 2 109/193 stm32l475xx electrical characteristics 181 t wustop1 wake up time from stop 1 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 6.2 10.2 s wakeup clock hsi16 = 16 mhz 6.3 8.99 range 2 wakeup clock msi = 24 mhz 6.3 10.46 wakeup clock hsi16 = 16 mhz 6.3 8.87 wakeup clock msi = 4 mhz 8.0 13.23 wake up time from stop 1 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 4.5 5.78 wakeup clock hsi16 = 16 mhz 5.5 7.1 range 2 wakeup clock msi = 24 mhz 5.0 6.5 wakeup clock hsi16 = 16 mhz 5.5 7.1 wakeup clock msi = 4 mhz 8.2 13.5 wake up time from stop 1 mode to low-power run mode in flash regulator in low-power mode (lpr=1 in pwr_cr1) wakeup clock msi = 2 mhz 12.7 20 wake up time from stop 1 mode to low-power run mode in sram1 10.7 21.5 t wustop2 wake up time from stop 2 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 8.0 9.4 s wakeup clock hsi16 = 16 mhz 7.3 9.3 range 2 wakeup clock msi = 24 mhz 8.2 9.9 wakeup clock hsi16 = 16 mhz 7.3 9.3 wakeup clock msi = 4 mhz 10.6 15.8 wake up time from stop 2 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 5.1 6.7 wakeup clock hsi16 = 16 mhz 5.7 8 range 2 wakeup clock msi = 24 mhz 5.5 6.65 wakeup clock hsi16 = 16 mhz 5.7 7.53 wakeup clock msi = 4 mhz 8.2 16.6 t wustby wakeup time from standby mode to run mode range 1 wakeup clock msi = 8 mhz 14.3 20.8 s wakeup clock msi = 4 mhz 20.1 35.5 t wustby sram2 wakeup time from standby with sram2 to run mode range 1 wakeup clock msi = 8 mhz 14.3 24.3 s wakeup clock msi = 4 mhz 20.1 38.5 t wushdn wakeup time from shutdown mode to run mode range 1 wakeup clock msi = 4 mhz 256 330.6 s 1. guaranteed by characterization results. table 41. low-power mode wakeup timings (1) (continued) symbol parameter conditions typ max unit electrical characteristics stm32l475xx 110/193 docid027692 rev 2 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 13: high-speed external clock source ac timing diagram . table 42. regulator modes transition times (1) symbol parameter conditions typ max unit t wulprun wakeup time from low-power run mode to run mode (2) code run with msi 2 mhz 5 7 s t vost regulator transition time from range 2 to range 1 or range 1 to range 2 (3) code run with msi 24 mhz 20 40 1. guaranteed by characterization results. 2. time until reglpf flag is cleared in pwr_sr2. 3. time until vosf flag is cleared in pwr_sr2. table 43. wakeup time using usart/lpuart (1) symbol parameter conditions typ max unit t wuusart t wulpuart wakeup time needed to calculate the maximum usart/lpuart baudrate allowing to wakeup up from stop mode stop mode 0 - 1.7 s stop mode 1/2 - 8.5 1. guaranteed by design. table 44. high-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f hse_ext user external clock source frequency voltage scaling range 1 -848 mhz voltage scaling range 2 -826 v hseh osc_in input pin high level voltage - 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage - v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time voltage scaling range 1 7- - ns voltage scaling range 2 18 - - 1. guaranteed by design. docid027692 rev 2 111/193 stm32l475xx electrical characteristics 181 figure 13. high-speed external clock source ac timing diagram low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 14 . figure 14. low-speed external clock source ac timing diagram 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / table 45. low-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - - 32.768 1000 khz v lseh osc32_in input pin high level voltage - 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage - v ss -0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time - 250 - - ns 1. guaranteed by design. 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics stm32l475xx 112/193 docid027692 rev 2 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 48 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 46 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 15 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . table 46. hse oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions (2) 2. resonator characteristics given by the crystal/ceramic resonator manufacturer. min typ max unit f osc_in oscillator frequency - 4 8 48 mhz r f feedback resistor - - 200 - k ? i dd(hse) hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time --5.5 ma v dd = 3 v, rm = 30 ? , cl = 10 pf@8 mhz -0.44- v dd = 3 v, rm = 45 ? , cl = 10 pf@8 mhz -0.45- v dd = 3 v, rm = 30 ? , cl = 5 pf@48 mhz -0.68- v dd = 3 v, rm = 30 ? , cl = 10 pf@48 mhz -0.94- v dd = 3 v, rm = 30 ? , cl = 20 pf@48 mhz -1.77- g m maximum critical crystal transconductance startup - - 1.5 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms docid027692 rev 2 113/193 stm32l475xx electrical characteristics 181 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 15. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results obtained with typical external components specified in table 47 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / table 47. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions (2) min typ max unit i dd(lse) lse current consumption lsedrv[1:0] = 00 low drive capability -250- na lsedrv[1:0] = 01 medium low drive capability -315- lsedrv[1:0] = 10 medium high drive capability -500- lsedrv[1:0] = 11 high drive capability -630- gm critmax maximum critical crystal gm lsedrv[1:0] = 00 low drive capability --0.5 a/v lsedrv[1:0] = 01 medium low drive capability - - 0.75 lsedrv[1:0] = 10 medium high drive capability --1.7 lsedrv[1:0] = 11 high drive capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s electrical characteristics stm32l475xx 114/193 docid027692 rev 2 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 16. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 1. guaranteed by design. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is en abled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid027692 rev 2 115/193 stm32l475xx electrical characteristics 181 6.3.8 internal clock source characteristics the parameters given in table 48 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi16) rc oscillator table 48. hsi16 oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi16 hsi16 frequency v dd =3.0 v, t a =30 c 15.88 - 16.08 mhz trim hsi16 user trimming step trimming code is not a multiple of 64 0.2 0.3 0.4 % trimming code is a multiple of 64 -4 -6 -8 ducy(hsi16) (2) duty cycle - 45 - 55 % ? te m p (hsi16) hsi16 oscillator frequency drift over temperature t a = 0 to 85 c -1 - 1 % t a = -40 to 125 c -2 - 1.5 % ? vdd (hsi16) hsi16 oscillator frequency drift over v dd v dd =1.62 v to 3.6 v -0.1 - 0.05 % t su (hsi16) (2) hsi16 oscillator start-up time --0.81.2 s t stab (hsi16) (2) hsi16 oscillator stabilization time --35 s i dd (hsi16) (2) hsi16 oscillator power consumption - - 155 190 a 1. guaranteed by characterization results. 2. guaranteed by design. electrical characteristics stm32l475xx 116/193 docid027692 rev 2 figure 17. hsi16 frequency versus temperature 0 6 y 9 0 + ] ? & 0 h d q p l q p d [ docid027692 rev 2 117/193 stm32l475xx electrical characteristics 181 multi-speed internal (msi) rc oscillator table 49. msi oscillator characteristics (1) symbol parameter conditions min typ max unit f msi msi frequency after factory calibration, done at v dd =3 v and t a =30 c msi mode range 0 99 100 101 khz range 1 198 200 202 range 2 396 400 404 range 3 792 800 808 range 4 0.99 1 1.01 mhz range 5 1.98 2 2.02 range 6 3.96 4 4.04 range 7 7.92 8 8.08 range 8 15.8 16 16.16 range 9 23.8 24 24.4 range 10 31.7 32 32.32 range 11 47.5 48 48.48 pll mode xtal= 32.768 khz range 0 - 98.304 - khz range 1 - 196.608 - range 2 - 393.216 - range 3 - 786.432 - range 4 - 1.016 - mhz range 5 - 1.999 - range 6 - 3.998 - range 7 - 7.995 - range 8 - 15.991 - range 9 - 23.986 - range 10 - 32.014 - range 11 - 48.005 - ? temp (msi) (2) msi oscillator frequency drift over temperature msi mode t a = -0 to 85 c -3.5 - 3 % t a = -40 to 125 c -8 - 6 electrical characteristics stm32l475xx 118/193 docid027692 rev 2 ? vdd (msi) (2) msi oscillator frequency drift over v dd (reference is 3 v) msi mode range 0 to 3 v dd =1.62 v to 3.6 v -1.2 - 0.5 % v dd =2.4 v to 3.6 v -0.5 - range 4 to 7 v dd =1.62 v to 3.6 v -2.5 - 0.7 v dd =2.4 v to 3.6 v -0.8 - range 8 to 11 v dd =1.62 v to 3.6 v -5 - 1 v dd =2.4 v to 3.6 v -1.6 - ? f sampling (msi) (2)(6) frequency variation in sampling mode (3) msi mode t a = -40 to 85 c - 1 2 % t a = -40 to 125 c - 2 4 p_usb jitter(msi) (6) period jitter for usb clock (4) pll mode range 11 for next transition ---3.458 ns for paired transition ---3.916 mt_usb jitter(msi) (6) medium term jitter for usb clock (5) pll mode range 11 for next transition --- 2 ns for paired transition --- 1 cc jitter(msi) (6) rms cycle-to- cycle jitter pll mode range 11 - - 60 - ps p jitter(msi) (6) rms period jitter pll mode range 11 - - 50 - ps t su (msi) (6) msi oscillator start-up time range 0 - - 10 20 us range 1 - - 5 10 range 2 - - 4 8 range 3 - - 3 7 range 4 to 7 - - 3 6 range 8 to 11 - - 2.5 6 t stab (msi) (6) msi oscillator stabilization time pll mode range 11 10 % of final frequency - - 0.25 0.5 ms 5 % of final frequency --0.51.25 1 % of final frequency ---2.5 table 49. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit docid027692 rev 2 119/193 stm32l475xx electrical characteristics 181 i dd (msi) (6) msi oscillator power consumption msi and pll mode range 0 - - 0.6 1 a range 1 - - 0.8 1.2 range 2 - - 1.2 1.7 range 3 - - 1.9 2.5 range 4 - - 4.7 6 range 5 - - 6.5 9 range 6 - - 11 15 range 7 - - 18.5 25 range 8 - - 62 80 range 9 - - 85 110 range 10 - - 110 130 range 11 - - 155 190 1. guaranteed by characterization results. 2. this is a deviation for an individual part once the init ial frequency has been measured. 3. sampling mode means low-power run/low-power sleep modes with temper ature sensor disable. 4. average period of msi @48 mhz is compared to a real 48 mh z clock over 28 cycles. it includes frequenc y tolerance + jitter of msi @48 mhz clock. 5. only accumulated jitter of msi @48 mhz is extracted over 28 cycles. for next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of th e msi @48 mhz, for 1000 captures over 28 cycles. for paired transitions: min. and max. jitte r of 2 consecutive frame of 56 cycles of the msi @48 mhz, for 1000 captures over 56 cycles. 6. guaranteed by design. table 49. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l475xx 120/193 docid027692 rev 2 figure 18. typical current consumption versus msi frequency low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 51 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 22: general operating conditions . table 50. lsi oscillator characteristics (1) symbol parameter conditions min typ max unit f lsi lsi frequency v dd = 3.0 v, t a = 30 c 31.04 - 32.96 khz v dd = 1.62 to 3.6 v, ta = -40 to 125 c 29.5 - 34 t su (lsi) (2) lsi oscillator start- up time --80130 s t stab (lsi) (2) lsi oscillator stabilization time 5% of final frequency - 125 180 s i dd (lsi) (2) lsi oscillator power consumption --110180na 1. guaranteed by characterization results. 2. guaranteed by design. docid027692 rev 2 121/193 stm32l475xx electrical characteristics 181 table 51. pll, pllsai1, pllsai2 characteristics (1) symbol parameter conditions min typ max unit f pll_in pll input clock (2) -4-16mhz pll input clock duty cycle - 45 - 55 % f pll_p_out pll multiplier output clock p voltage scaling range 1 2.0645 - 80 mhz voltage scaling range 2 2.0645 - 26 f pll_q_out pll multiplier output clock q voltage scaling range 1 8 - 80 mhz voltage scaling range 2 8 - 26 f pll_r_out pll multiplier output clock r voltage scaling range 1 8 - 80 mhz voltage scaling range 2 8 - 26 f vco_out pll vco output voltage scaling range 1 64 - 344 mhz voltage scaling range 2 64 - 128 t lock pll lock time - - 15 40 s jitter rms cycle-to-cycle jitter system clock 80 mhz -40- ps rms period jitter - 30 - i dd (pll) pll power consumption on v dd (1) vco freq = 64 mhz - 150 200 a vco freq = 96 mhz - 200 260 vco freq = 192 mhz - 300 380 vco freq = 344 mhz - 520 650 1. guaranteed by design. 2. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between the 3 plls. electrical characteristics stm32l475xx 122/193 docid027692 rev 2 6.3.10 flash memory characteristics table 52. flash memory characteristics (1) 1. guaranteed by design. symbol parameter conditions typ max unit t prog 64-bit programming time - 81.69 90.76 s t prog_row one row (32 double word) programming time normal programming 2.61 2.90 ms fast programming 1.91 2.12 t prog_page one page (2 kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 t erase page (2 kb) erase time - 22.02 24.47 t prog_bank one bank (512 kbyte) programming time normal programming 5.35 5.95 s fast programming 3.91 4.35 t me mass erase time (one or two banks) - 22.13 24.59 ms i dd average consumption from v dd write mode 3.4 - ma erase mode 3.4 - maximum current (peak) write mode 7 (for 2 s) - erase mode 7 (for 41 s) - table 53. flash memory endurance and data retention symbol parameter conditions min (1) 1. guaranteed by characterization results. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 15 1 kcycle (2) at t a = 125 c 7 10 kcycles (2) at t a = 55 c 30 10 kcycles (2) at t a = 85 c 15 10 kcycles (2) at t a = 105 c 10 docid027692 rev 2 123/193 stm32l475xx electrical characteristics 181 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 54 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 54. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-4 4a electrical characteristics stm32l475xx 124/193 docid027692 rev 2 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. table 55. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit max vs. [f hse = 8 mhz / f hclk = 80 mhz] s emi peak level v dd = 3.6 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 mhz to 30 mhz -2 dbv 30 mhz to 130 mhz -9 130 mhz to 1 ghz 6 emi level 3.5 - table 56. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/esda/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 c3 250 docid027692 rev 2 125/193 stm32l475xx electrical characteristics 181 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functiona l failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 58 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 57. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 58. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin -0 na (1) 1. na: not applicable ma injected current on pins except pa4, pa5, boot0 -5 na (1) injected current on pa4, pa5 pins -5 0 electrical characteristics stm32l475xx 126/193 docid027692 rev 2 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 59 are derived from tests performed under the conditions summarized in table 22: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 59. i/o static characteristics symbol parameter conditions min typ max unit v il (1) i/o input low level voltage except boot0 1.62 v electrical characteristics stm32l475xx 128/193 docid027692 rev 2 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 19 for standard i/os, and in figure 19 for 5 v tolerant i/os. figure 19. i/o input characteristics output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 19: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximu m consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 19: voltage characteristics ). 0 6 y 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 l k p l q [ 9 ' ' , 2 [ % d v h g r q v l p x o d w l r q 9 l k p l q [ 9 ' ' , 2 [ i r u 9 ' ' , 2 [ r u [ 9 ' ' , 2 [ i r u 9 ' ' , 2 [ ! % d v h g r q v l p x o d w l r q 9 l o p d [ [ 9 ' ' , 2 [ i r u 9 ' ' , 2 [ r u [ 9 ' ' , 2 [ i r u 9 ' ' , 2 [ ! 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 l o p d [ [ 9 g g 7 7 / u h t x l u h p h q w 9 l k p l q 9 7 7 / u h t x l u h p h q w 9 l o p d [ 9 docid027692 rev 2 129/193 stm32l475xx electrical characteristics 181 output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . all i/os are cmos- and ttl -compliant (ft or tt unless otherwise specified). input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 20 and table 61 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . table 60. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox -0.4 - v ol (3) output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v oh (3) output high level voltage for an i/o pin v ddiox -1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 4 ma v ddiox 1.62 v -0.45 v oh (3) output high level voltage for an i/o pin v ddiox -0.45 - v ol (3) output low level voltage for an i/o pin |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.35 ? v ddiox v oh (3) output high level voltage for an i/o pin 0.65 ? v ddiox - v olfm+ (3) output low level voltage for an ft i/o pin in fm+ mode (ft i/o with "f" option) |i io | = 20 ma v ddiox 2.7 v -0.4 |i io | = 10 ma v ddiox 1.62 v -0.4 |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.4 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 19: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. guaranteed by design. electrical characteristics stm32l475xx 130/193 docid027692 rev 2 table 61. i/o ac characteristics (1)(2) speed symbol parameter conditions min max unit 00 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 5 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 1 c=50 pf, 1.08 v v ddiox 1.62 v - 0.1 c=10 pf, 2.7 v v ddiox 3.6 v - 10 c=10 pf, 1.62 v v ddiox 2.7 v - 1.5 c=10 pf, 1.08 v v ddiox 1.62 v - 0.1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 25 ns c=50 pf, 1.62 v v ddiox 2.7 v - 52 c=50 pf, 1.08 v v ddiox 1.62 v - 140 c=10 pf, 2.7 v v ddiox 3.6 v - 17 c=10 pf, 1.62 v v ddiox 2.7 v - 37 c=10 pf, 1.08 v v ddiox 1.62 v - 110 01 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 25 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 10 c=50 pf, 1.08 v v ddiox 1.62 v - 1 c=10 pf, 2.7 v v ddiox 3.6 v - 50 c=10 pf, 1.62 v v ddiox 2.7 v - 15 c=10 pf, 1.08 v v ddiox 1.62 v - 1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 9 ns c=50 pf, 1.62 v v ddiox 2.7 v - 16 c=50 pf, 1.08 v v ddiox 1.62 v - 40 c=10 pf, 2.7 v v ddiox 3.6 v - 4.5 c=10 pf, 1.62 v v ddiox 2.7 v - 9 c=10 pf, 1.08 v v ddiox 1.62 v - 21 docid027692 rev 2 131/193 stm32l475xx electrical characteristics 181 10 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 50 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 25 c=50 pf, 1.08 v v ddiox 1.62 v - 5 c=10 pf, 2.7 v v ddiox 3.6 v - 100 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 37.5 c=10 pf, 1.08 v v ddiox 1.62 v - 5 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 5.8 ns c=50 pf, 1.62 v v ddiox 2.7 v - 11 c=50 pf, 1.08 v v ddiox 1.62 v - 28 c=10 pf, 2.7 v v ddiox 3.6 v - 2.5 c=10 pf, 1.62 v v ddiox 2.7 v - 5 c=10 pf, 1.08 v v ddiox 1.62 v - 12 11 fmax maximum frequency c=30 pf, 2.7 v v ddiox 3.6 v - 120 (3) mhz c=30 pf, 1.62 v v ddiox 2.7 v - 50 c=30 pf, 1.08 v v ddiox 1.62 v - 10 c=10 pf, 2.7 v v ddiox 3.6 v - 180 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 75 c=10 pf, 1.08 v v ddiox 1.62 v - 10 tr/tf output rise and fall time c=30 pf, 2.7 v v ddiox 3.6 v - 3.3 ns c=30 pf, 1.62 v v ddiox 2.7 v - 6 c=30 pf, 1.08 v v ddiox 1.62 v - 16 fm+ fmax maximum frequency c=50 pf, 1.6 v v ddiox 3.6 v -1mhz tf output fall time (4) -5ns 1. the i/o speed is configured using the ospeedry[1:0] bits. the fm+ mode is configured in the syscfg_cfgr1 register. refer to the rm0395 reference manual for a descr iption of gpio port configuration register. 2. guaranteed by design. 3. this value represents the i/o capability but t he maximum system frequency is limited to 80 mhz. 4. the fall time is defined between 70% and 30% of the output waveform accordingly to i 2 c specification. table 61. i/o ac characteristics (1)(2) (continued) speed symbol parameter conditions min max unit electrical characteristics stm32l475xx 132/193 docid027692 rev 2 figure 20. i/o ac characteristics definition (1) 1. refer to table 61: i/o ac characteristics . 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 22: general operating conditions . 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ w k h v s h f l i l h g f d s d f l w d q f h u i u , 2 r x w w i , 2 r x w w table 62. nrst pin characteristics (1) symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage ---0.3 ? v ddiox v v ih(nrst) nrst input high level voltage -0.7 ? v ddiox -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse ---70ns v nf(nrst) nrst input not filtered pulse 1.71 v v dd 3.6 v 350 - - ns 1. guaranteed by design. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order) . docid027692 rev 2 133/193 stm32l475xx electrical characteristics 181 figure 21. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 62: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 analog switches booster 5 3 8 9 ' ' 0 6 9 , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 63. analog switches booster characteristics (1) 1. guaranteed by design. symbol parameter min typ max unit v dd supply voltage 1.62 - 3.6 v v boost boost supply 2.7 - 4 t su(boost) booster startup time - - 240 s i dd(boost) booster consumption for 1.62 v v dd 2.0 v --250 a booster consumption for 2.0 v v dd 2.7 v --500 booster consumption for 2.7 v v dd 3 .6 v --900 electrical characteristics stm32l475xx 134/193 docid027692 rev 2 6.3.17 analog-to-digital converter characteristics unless otherwise specified, the parameters given in table 64 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 22: general operating conditions . note: it is recommended to perform a calibration after each power-up. table 64. adc characteristics (1) (2) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v ref+ positive reference voltage v dda 2 v 2 - v dda v v dda < 2 v v dda v v ref- negative reference voltage -v ssa v f adc adc clock frequency range 1 - - 80 mhz range 2 - - 26 f s sampling rate for fast channels resolution = 12 bits - - 5.33 msps resolution = 10 bits - - 6.15 resolution = 8 bits - - 7.27 resolution = 6 bits - - 8.88 sampling rate for slow channels resolution = 12 bits - - 4.21 resolution = 10 bits - - 4.71 resolution = 8 bits - - 5.33 resolution = 6 bits - - 6.15 f trig external trigger frequency f adc = 80 mhz resolution = 12 bits - - 5.33 mhz resolution = 12 bits - - 15 1/f adc v ain (3) conversion voltage range(2) -0-v ref+ v r ain external input impedance - - - 50 k ? c adc internal sample and hold capacitor --5-pf t stab power-up time - 1 conversion cycle t cal calibration time f adc = 80 mhz 1.45 s -1161/f adc t latr trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2.0 ckmode = 10 - - 2.25 ckmode = 11 - - 2.125 docid027692 rev 2 135/193 stm32l475xx electrical characteristics 181 t latrinj trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3.0 ckmode = 10 - - 3.25 ckmode = 11 - - 3.125 t s sampling time f adc = 80 mhz 0.03125 - 8.00625 s - 2.5 - 640.5 1/f adc t adcvreg_stup adc voltage regulator start-up time ---20 s t conv total conversion time (including sampling time) f adc = 80 mhz resolution = 12 bits 0.1875 - 8.1625 s resolution = 12 bits ts + 12.5 cycles for successive approximation = 15 to 653 1/f adc i dda (adc) adc consumption from the v dda supply fs = 5 msps - 730 830 a fs = 1 msps - 160 220 fs = 10 ksps - 16 50 i ddv_s (adc) adc consumption from the v ref+ single ended mode fs = 5 msps - 130 160 a fs = 1 msps - 30 40 fs = 10 ksps - 0.6 2 i ddv_d (adc) adc consumption from the v ref+ differential mode fs = 5 msps - 260 310 a fs = 1 msps - 60 70 fs = 10 ksps - 1.3 3 1. guaranteed by design 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pinouts and pin description for further details. table 64. adc characteristics (1) (2) (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l475xx 136/193 docid027692 rev 2 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < table 65. maximum adc rain (1)(2) resolution sampling cycle @80 mhz sampling time [ns] @80 mhz rain max ( ? ) fast channels (3) slow channels (4) 12 bits 2.5 31.25 100 n/a 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 10 bits 2.5 31.25 120 n/a 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 5600 4700 247.5 3093.75 12000 10000 640.5 8006.75 47000 39000 8 bits 2.5 31.25 180 n/a 6.5 81.25 470 270 12.5 156.25 1000 680 24.5 306.25 1800 1500 47.5 593.75 2700 2200 92.5 1156.25 6800 5600 247.5 3093.75 15000 12000 640.5 8006.75 50000 50000 docid027692 rev 2 137/193 stm32l475xx electrical characteristics 181 6 bits 2.5 31.25 220 n/a 6.5 81.25 560 330 12.5 156.25 1200 1000 24.5 306.25 2700 2200 47.5 593.75 3900 3300 92.5 1156.25 8200 6800 247.5 3093.75 18000 15000 640.5 8006.75 50000 50000 1. guaranteed by design. 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. fast channels are: pc0, pc1, pc2, pc3, pa0, pa1. 4. slow channels are: all adc i nputs except the fast channels. table 65. maximum adc rain (1)(2) (continued) resolution sampling cycle @80 mhz sampling time [ns] @80 mhz rain max ( ? ) fast channels (3) slow channels (4) electrical characteristics stm32l475xx 138/193 docid027692 rev 2 table 66. adc accuracy - limited test conditions 1 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = vref+ = 3 v, ta = 25 c single ended fast channel (max speed) - 4 5 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 3.5 4.5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 1 2.5 slow channel (max speed) - 1 2.5 differential fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 eg gain error single ended fast channel (max speed) - 2.5 4.5 slow channel (max speed) - 2.5 4.5 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 differential fast channel (max speed) - 1 2 slow channel (max speed) - 1 2 enob effective number of bits single ended fast channel (max speed) 10.4 10.5 - bits slow channel (max speed) 10.4 10.5 - differential fast channel (max speed) 10.8 10.9 - slow channel (max speed) 10.8 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 64.4 65 - db slow channel (max speed) 64.4 65 - differential fast channel (max speed) 66.8 67.4 - slow channel (max speed) 66.8 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - differential fast channel (max speed) 67 68 - slow channel (max speed) 67 68 - docid027692 rev 2 139/193 stm32l475xx electrical characteristics 181 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = v ref+ = 3 v, ta = 25 c single ended fast channel (max speed) - -74 -73 db slow channel (max speed) - -74 -73 differential fast channel (max speed) - -79 -76 slow channel (max speed) - -79 -76 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 66. adc accuracy - limited test conditions 1 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit electrical characteristics stm32l475xx 140/193 docid027692 rev 2 table 67. adc accuracy - limited test conditions 2 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - 4 6.5 lsb slow channel (max speed) - 4 6.5 differential fast channel (max speed) - 3.5 5.5 slow channel (max speed) - 3.5 5.5 eo offset error single ended fast channel (max speed) - 1 4.5 slow channel (max speed) - 1 5 differential fast channel (max speed) - 1.5 3 slow channel (max speed) - 1.5 3 eg gain error single ended fast channel (max speed) - 2.5 6 slow channel (max speed) - 2.5 6 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 3.5 slow channel (max speed) - 1.5 3.5 differential fast channel (max speed) - 1 3 slow channel (max speed) - 1 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.5 - bits slow channel (max speed) 10 10.5 - differential fast channel (max speed) 10.7 10.9 - slow channel (max speed) 10.7 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 65 - db slow channel (max speed) 62 65 - differential fast channel (max speed) 66 67.4 - slow channel (max speed) 66 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 64 66 - slow channel (max speed) 64 66 - differential fast channel (max speed) 66.5 68 - slow channel (max speed) 66.5 68 - docid027692 rev 2 141/193 stm32l475xx electrical characteristics 181 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - -74 -65 db slow channel (max speed) - -74 -67 differential fast channel (max speed) - -79 -70 slow channel (max speed) - -79 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 67. adc accuracy - limited test conditions 2 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit electrical characteristics stm32l475xx 142/193 docid027692 rev 2 table 68. adc accuracy - limited test conditions 3 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - 5.5 7.5 lsb slow channel (max speed) - 4.5 6.5 differential fast channel (max speed) - 4.5 7.5 slow channel (max speed) - 4.5 5.5 eo offset error single ended fast channel (max speed) - 2 5 slow channel (max speed) - 2.5 5 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2.5 3 eg gain error single ended fast channel (max speed) - 4.5 7 slow channel (max speed) - 3.5 6 differential fast channel (max speed) - 3.5 4 slow channel (max speed) - 3.5 5 ed differential linearity error single ended fast channel (max speed) - 1.2 1.5 slow channel (max speed) - 1.2 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 3 3.5 slow channel (max speed) - 2.5 3.5 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.4 - bits slow channel (max speed) 10 10.4 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 64 - db slow channel (max speed) 62 64 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 63 65 - slow channel (max speed) 63 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 - docid027692 rev 2 143/193 stm32l475xx electrical characteristics 181 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - -69 -67 db slow channel (max speed) - -71 -67 differential fast channel (max speed) - -72 -71 slow channel (max speed) - -72 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 68. adc accuracy - limited test conditions 3 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit electrical characteristics stm32l475xx 144/193 docid027692 rev 2 table 69. adc accuracy - limited test conditions 4 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - 5 5.4 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 4 5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 2 4 slow channel (max speed) - 2 4 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2 3.5 eg gain error single ended fast channel (max speed) - 4 4.5 slow channel (max speed) - 4 4.5 differential fast channel (max speed) - 3 4 slow channel (max speed) - 3 4 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 2.5 3 slow channel (max speed) - 2.5 3 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10.2 10.5 - bits slow channel (max speed) 10.2 10.5 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 63 65 - db slow channel (max speed) 63 65 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 64 65 - slow channel (max speed) 64 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 - docid027692 rev 2 145/193 stm32l475xx electrical characteristics 181 thd to ta l harmonic distortion adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - -71 -69 db slow channel (max speed) - -71 -69 differential fast channel (max speed) - -73 -72 slow channel (max speed) - -73 -72 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 69. adc accuracy - limited test conditions 4 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit electrical characteristics stm32l475xx 146/193 docid027692 rev 2 figure 22. adc accuracy characteristics figure 23. typical connecti on diagram using the adc 1. refer to table 64: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (refer to table 59: i/o static characteristics for the value of the pad capacitance). a high c parasitic value will downgrade conversion a ccuracy. to remedy this, f adc should be reduced. 3. refer to table 59: i/o static characteristics for the values of i lkg . general pcb design guidelines power supply decoupling should be performed as shown in figure 10: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 7 7 r w d o 8 q d m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h v ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h 9 ' ' $ 9 6 6 $ ( 2 ( 7 ( / ( * ( ' / 6 % , ' ( $ / 0 6 9 0 6 9 6 d p s o h d q g k r o g $ ' & f r q y h u w h u e l w f r q y h u w h u & s d u d v l w l f , o n j 9 7 & $ ' & 9 ' ' $ 5 $ , 1 9 $ , 1 9 7 $ , 1 [ 5 $ ' & docid027692 rev 2 147/193 stm32l475xx electrical characteristics 181 6.3.18 digital-to-analog converter characteristics table 70. dac characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage for dac on - 1.8 - 3.6 v v ref+ positive reference voltage - 1.8 - v dda v ref- negative reference voltage -v ssa r l resistive load dac output buffer on connected to v ssa 5- - k ? connected to v dda 25 - - r o output impedance dac output buffer off 9.6 11.7 13.8 k ? r bon output impedance sample and hold mode, output buffer on v dd = 2.7 v - - 2 k ? v dd = 2.0 v - - 3.5 r boff output impedance sample and hold mode, output buffer off v dd = 2.7 v - - 16.5 k ? v dd = 2.0 v - - 18.0 c l capacitive load dac output buffer on - - 50 pf c sh sample and hold mode - 0.1 1 f v dac_out voltage on dac_out output dac output buffer on 0.2 - v ref+ ? 0.2 v dac output buffer off 0 - v ref+ t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when dac_out reaches final value 0.5lsb, 1 lsb, 2 lsb, 4 lsb, 8 lsb) normal mode dac output buffer on cl 50 pf, rl 5 k ? 0.5 lsb - 1.7 3 s 1 lsb - 1.6 2.9 2 lsb - 1.55 2.85 4 lsb - 1.48 2.8 8 lsb - 1.4 2.75 normal mode dac output buffer off, 1lsb, cl = 10 pf -22.5 t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) until final value 1 lsb normal mode dac output buffer on cl 50 pf, rl 5 k ? -4.27.5 s normal mode dac output buffer off, cl 10 pf -2 5 psrr v dda supply rejection ratio normal mode dac output buffer on cl 50 pf, rl = 5 k ? , dc --80-28db electrical characteristics stm32l475xx 148/193 docid027692 rev 2 t samp sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when dacout reaches final value 1lsb) dac_out pin connected dac output buffer on, c sh = 100 nf -0.73.5 ms dac output buffer off, c sh = 100 nf -10.5 18 dac_out pin not connected (internal connection only) dac output buffer off -23.5s i leak output leakage current sample and hold mode, dac_out pin connected -- - (3) na ci int internal sample and hold capacitor - 5.2 7 8.8 pf t trim middle code offset trim time dac output buffer on 50 - - s v offset middle code offset for 1 trim code step v ref+ = 3.6 v - 1500 - v v ref+ = 1.8 v - 750 - i dda (dac) dac consumption from v dda dac output buffer on no load, middle code (0x800) - 315 500 a no load, worst code (0xf1c) - 450 670 dac output buffer off no load, middle code (0x800) --0.2 sample and hold mode, c sh = 100 nf - 315 ? ton/(ton +toff) (4) 670 ? ton/(ton +toff) (4) i ddv (dac) dac consumption from v ref+ dac output buffer on no load, middle code (0x800) - 185 240 a no load, worst code (0xf1c) - 340 400 dac output buffer off no load, middle code (0x800) - 155 205 sample and hold mode, buffer on, c sh = 100 nf, worst case - 185 ? ton/(ton +toff) (4) 400 ? ton/(ton +toff) (4) sample and hold mode, buffer off, c sh = 100 nf, worst case - 155 ? ton/(ton +toff) (4) 205 ? ton/(ton +toff) (4) 1. guaranteed by design. 2. in buffered mode, the output can overshoot above the final value for low input code (starting from min value). table 70. dac characteristics (1) (continued) symbol parameter conditions min typ max unit docid027692 rev 2 149/193 stm32l475xx electrical characteristics 181 figure 24. 12-bit buffered / non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. . 3. refer to table 59: i/o static characteristics . 4. ton is the refresh phase duration. toff is the hold phase duration. refer to rm0395 reference manual for more details. % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' d l g table 71. dac accuracy (1) symbol parameter conditions min typ max unit dnl differential non linearity (2) dac output buffer on - - 2 lsb dac output buffer off - - 2 - monotonicity 10 bits guaranteed inl integral non linearity (3) dac output buffer on cl 50 pf, rl 5 k ? --4 dac output buffer off cl 50 pf, no rl --4 offset offset error at code 0x800 (3) dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 12 v ref+ = 1.8 v - - 25 dac output buffer off cl 50 pf, no rl --8 offset1 offset error at code 0x001 (4) dac output buffer off cl 50 pf, no rl --5 offsetcal offset error at code 0x800 after calibration dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 5 v ref+ = 1.8 v - - 7 electrical characteristics stm32l475xx 150/193 docid027692 rev 2 gain gain error (5) dac output buffer on cl 50 pf, rl 5 k ? --0.5 % dac output buffer off cl 50 pf, no rl --0.5 tue to ta l unadjusted error dac output buffer on cl 50 pf, rl 5 k ? --30 lsb dac output buffer off cl 50 pf, no rl --12 tuecal to ta l unadjusted error after calibration dac output buffer on cl 50 pf, rl 5 k ? --23lsb snr signal-to-noise ratio dac output buffer on cl 50 pf, rl 5 k ? 1 khz, bw 500 khz -71.2- db dac output buffer off cl 50 pf, no rl, 1 khz bw 500 khz -71.6- thd total harmonic distortion dac output buffer on cl 50 pf, rl 5 k ? , 1 khz --78- db dac output buffer off cl 50 pf, no rl, 1 khz --79- sinad signal-to-noise and distortion ratio dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -70.4- db dac output buffer off cl 50 pf, no rl, 1 khz -71- enob effective number of bits dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -11.4- bits dac output buffer off cl 50 pf, no rl, 1 khz -11.5- 1. guaranteed by design. 2. difference between two consecutive codes - 1 lsb. 3. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. 4. difference between the value measured at code (0x001) and the ideal value. 5. difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xfff when buffer is off, and from code giving 0.2 v and (v ref+ ? 0.2) v when buffer is on. table 71. dac accuracy (1) (continued) symbol parameter conditions min typ max unit docid027692 rev 2 151/193 stm32l475xx electrical characteristics 181 6.3.19 voltage reference buffer characteristics table 72. vrefbuf characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage normal mode v rs = 0 2.4 - 3.6 v v rs = 1 2.8 - 3.6 degraded mode (2) v rs = 0 1.65 - 2.4 v rs = 1 1.65 - 2.8 v refbuf_ out voltage reference output normal mode v rs = 0 2.046 (3) 2.048 2.049 (3) v rs = 1 2.498 (3) 2.5 2.502 (3) degraded mode (2) v rs = 0 v dda -150 mv - v dda v rs = 1 v dda -150 mv - v dda trim trim step resolution ---0.050.1% cl load capacitor - - 0.5 1 1.5 f esr equivalent serial resistor of cload ----2 ? i load static load current ----4ma i line_reg line regulation 2.8 v v dda 3.6 v i load = 500 a - 200 1000 ppm/v i load = 4 ma - 100 500 i load_reg load regulation 500 a i load 4 ma normal mode - 50 500 ppm/ma t coeff temperature coefficient -40 c < tj < +125 c - - t coeff_ vrefint + 50 ppm/ c 0 c < tj < +50 c - - t coeff_ vrefint + 50 psrr power supply rejection dc 40 60 - db 100 khz 25 40 - t start start-up time cl = 0.5 f (4) - 300 350 s cl = 1.1 f (4) - 500 650 cl = 1.5 f (4) - 650 800 i inrush control of maximum dc current drive on vrefbuf_ out during start-up phase (5) ---8-ma electrical characteristics stm32l475xx 152/193 docid027692 rev 2 i dda (vref buf) vrefbuf consumption from v dda i load = 0 a - 16 25 a i load = 500 a - 18 30 i load = 4 ma - 35 50 1. guaranteed by design, unl ess otherwise specified. 2. in degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (v dda - drop voltage). 3. guaranteed by test in production. 4. the capacitive load must include a 100 nf capacitor in order to cut-off the high frequency noise. 5. to correctly control the vrefbuf inrush current during start-up phase and scaling change, the v dda voltage should be in the range [2.4 v to 3.6 v] and [2.8 v to 3.6 v] respectively for v rs = 0 and v rs = 1. table 72. vrefbuf characteristics (1) (continued) symbol parameter conditions min typ max unit docid027692 rev 2 153/193 stm32l475xx electrical characteristics 181 6.3.20 comparator characteristics table 73. comp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v in comparator input voltage range -0-v dda v bg (2) scaler input voltage - v refint v sc scaler offset voltage - - 5 10 mv i dda (scaler) scaler static consumption from v dda brg_en=0 (bridge disable) - 200 300 na brg_en=1 (bridge enable) - 0.8 1 a t start_scaler scaler startup time - - 100 200 s t start comparator startup time to reach propagation delay specification high-speed mode v dda 2.7 v - - 5 s v dda < 2.7 v - - 7 medium mode v dda 2.7 v - - 15 v dda < 2.7 v - - 25 ultra-low-power mode - - 80 t d (3) propagation delay for 200 mv step with 100 mv overdrive high-speed mode v dda 2.7 v - 55 80 ns v dda < 2.7 v - 65 100 medium mode v dda 2.7 v - 0.55 0.9 s v dda < 2.7 v - 0.65 1 ultra-low-power mode - 5 12 v offset comparator offset error full common mode range --520mv v hys comparator hysteresis no hysteresis - 0 - mv low hysteresis - 8 - medium hysteresis - 15 - high hysteresis - 27 - i dda (comp) comparator consumption from v dda ultra-low- power mode static - 400 600 na with 50 khz 100 mv overdrive square signal -1200- medium mode static - 5 7 a with 50 khz 100 mv overdrive square signal -6- high-speed mode static - 70 100 with 50 khz 100 mv overdrive square signal -75- electrical characteristics stm32l475xx 154/193 docid027692 rev 2 6.3.21 operational ampl ifiers characteristics 1. guaranteed by design, unless otherwise specified. 2. refer to table 25: embedded internal voltage reference . 3. guaranteed by characterization results. table 74. opamp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage (2) -1.8-3.6v cmir common mode input range -0-v dda v vi offset input offset voltage 25 c, no load on output. - - 1.5 mv all voltage/temp. - - 3 ? vi offset input offset voltage drift normal mode - 5 - v/c low-power mode - 10 - trimoffsetp trimlpoffsetp offset trim step at low common input voltage (0.1 ? v dda ) --0.81.1 mv trimoffsetn trimlpoffsetn offset trim step at high common input voltage (0.9 ? v dda ) --11.35 i load drive current normal mode v dda 2 v - - 500 a low-power mode - - 100 i load_pga drive current in pga mode normal mode v dda 2 v - - 450 low-power mode - - 50 r load resistive load (connected to vssa or to vdda) normal mode v dda < 2 v 4- - k ? low-power mode 20 - - r load_pga resistive load in pga mode (connected to vssa or to v dda ) normal mode v dda < 2 v 4.5 - - low-power mode 40 - - c load capacitive load - - - 50 pf cmrr common mode rejection ratio normal mode - -85 - db low-power mode - -90 - docid027692 rev 2 155/193 stm32l475xx electrical characteristics 181 psrr power supply rejection ratio normal mode c load 50 pf, r load 4 k ? dc 70 85 - db low-power mode c load 50 pf, r load 20 k ? dc 72 90 - gbw gain bandwidth product normal mode v dda 2.4 v (opa_range = 1) 550 1600 2200 khz low-power mode 100 420 600 normal mode v dda < 2.4 v (opa_range = 0) 250 700 950 low-power mode 40 180 280 sr (3) slew rate (from 10 and 90% of output voltage) normal mode v dda 2.4 v -700- v/ms low-power mode - 180 - normal mode v dda < 2.4 v -300- low-power mode - 80 - ao open loop gain normal mode 55 110 - db low-power mode 45 110 - v ohsat (3) high saturation voltage normal mode i load = max or r load = min input at v dda . v dda - 100 -- mv low-power mode v dda - 50 -- v olsat (3) low saturation voltage normal mode i load = max or r load = min input at 0. - - 100 low-power mode - - 50 m phase margin normal mode - 74 - low-power mode - 66 - gm gain margin normal mode - 13 - db low-power mode - 20 - t wakeup wake up time from off state. normal mode c load 50 pf, r load 4 k ? follower configuration -510 s low-power mode c load 50 pf, r load 20 k ? follower configuration -1030 i bias opamp input bias current general purpose input ---- (4) na pga gain (3) non inverting gain value - -2- - -4- -8- -16- table 74. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l475xx 156/193 docid027692 rev 2 r network r2/r1 internal resistance values in pga mode (5) pga gain = 2 - 80/80 - k ? /k ? pga gain = 4 - 120/ 40 - pga gain = 8 - 140/ 20 - pga gain = 16 - 150/ 10 - delta r resistance variation (r1 or r2) --15-15% pga gain error pga gain error - -1 - 1 % pga bw pga bandwidth for different non inverting gain gain = 2 - - gbw/ 2 - mhz gain = 4 - - gbw/ 4 - gain = 8 - - gbw/ 8 - gain = 16 - - gbw/ 16 - en voltage noise density normal mode at 1 khz, output loaded with 4 k ? -500- nv/ hz low-power mode at 1 khz, output loaded with 20 k ? -600- normal mode at 10 khz, output loaded with 4 k ? -180- low-power mode at 10 khz, output loaded with 20 k ? -290- i dda (opamp) (3) opamp consumption from v dda normal mode no load, quiescent mode - 120 260 a low-power mode - 45 100 1. guaranteed by design, unless otherwise specified. 2. the temperature range is limited to 0 c-125 c when v dda is below 2 v 3. guaranteed by characterization results. 4. mostly i/o leakage, when used in analog mode. refer to i lkg parameter in table 59: i/o static characteristics . 5. r2 is the internal resistance between opamp output and opam p inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 table 74. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit docid027692 rev 2 157/193 stm32l475xx electrical characteristics 181 6.3.22 temperature sensor characteristics 6.3.23 v bat monitoring characteristics table 75. ts characteristics symbol parameter min typ max unit t l (1) v ts linearity with temperature - 1 2 c avg_slope (2) average slope 2.3 2.5 2.7 mv/c v 30 voltage at 30c (5 c) (3) 0.742 0.76 0.785 v t start (ts_buf) (1) sensor buffer start-up time in continuous mode (4) -815s t start (1) start-up time when entering in continuous mode (4) -70120s t s_temp (1) adc sampling time when reading the temperature 5 - - s i dd (ts) (1) temperature sensor consumption from v dd , when selected by adc -4.77 a 1. guaranteed by design. 2. guaranteed by characterization results. 3. measured at v dda = 3.0 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte. refer to table 8: temperature sensor calibration values . 4. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. table 76. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -39-k ? qratio on v bat measurement - 3 - - er (1) 1. guaranteed by design. error on q -10 - 10 % t s_vbat (1) adc sampling time when reading the vbat 12 - - s table 77. v bat charging characteristics symbol parameter conditions min typ max unit r bc battery charging resistor vbrs = 0 - 5 - k ? vbrs = 1 - 1.5 - electrical characteristics stm32l475xx 158/193 docid027692 rev 2 6.3.24 dfsdm characteristics unless otherwise specified, the parameters given in table 78 for dfsdm are derived from tests performed under the ambient temperature, f apb2 frequency and v dd supply voltage conditions su mmarized in table 22: general operating conditions . ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? vdd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (dfsdm_ckiny, dfsdm_datiny, dfsdm_ckout for dfsdm). table 78. dfsdm characteristics (1) symbol parameter conditions min typ max unit f dfsdmclk dfsdm clock - - - f sysclk mhz f ckin (1/t ckin ) input clock frequency spi mode (sitp[1:0] = 01) - - 20 (f dfsdmclk /4) f ckout output clock frequency ---20mhz ducy ckout output clock frequency duty cycle -455055% t wh(ckin) t wl(ckin) input clock high and low time spi mode (sitp[1:0] = 01), external clock mode (spicksel[1:0] = 0) t ckin /2-0.5 t ckin /2 - ns t su data input setup time spi mode (sitp[1:0]=01), external clock mode (spicksel[1:0] = 0) 0- - t h data input hold time spi mode (sitp[1:0]=01), external clock mode (spicksel[1:0] = 0) 2- - t manchester manchester data period (recovered clock period) manchester mode (sitp[1:0] = 10 or 11), internal clock mode (spicksel[1:0] 0) (ckout div+1) ? t dfsdmclk - (2 ? ckoutdiv) ? t dfsdmclk 1. data based on characterization re sults, not tested in production. docid027692 rev 2 159/193 stm32l475xx electrical characteristics 181 figure 16: dfsdm timing diagram 6.3.25 timer characteristics the parameters given in the followi ng tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 0 6 y 9 6 3 , & . 6 ( / 6 3 , & . 6 ( / 6 3 , & . 6 ( / ' ) 6 ' 0 b & . 2 8 7 w v x w z o w z k w u w i w k w v x w k 6 , 7 3 6 , 7 3 ' ) 6 ' 0 b ' $ 7 $ , 1 \ ' ) 6 ' 0 b & . , 1 , 1 \ 6 3 , & . 6 ( / w v x w k w v x w k 6 , 7 3 6 , 7 3 ' ) 6 ' 0 b ' $ 7 $ , 1 \ 6 , 7 3 6 , 7 3 5 h f r y h u h g f o r f n 5 h f r y h u h g g d w d ' ) 6 ' 0 b ' $ 7 $ , 1 \ 0 d q f k h v w h u w l p l q j 6 3 , w l p l q j 6 3 , & . 6 ( / 6 3 , w l p l q j 6 3 , & . 6 ( / w z o w z k w u w i electrical characteristics stm32l475xx 160/193 docid027692 rev 2 table 79. timx (1) characteristics 1. timx , is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17. symbol parameter conditions min max unit t res(tim) timer resolution time -1-t timxclk f timxclk = 80 mhz 12.5 - ns f ext timer external clock frequency on ch1 to ch4 -0f timxclk /2 mhz f timxclk = 80 mhz 0 40 mhz res tim timer resolution timx (except tim2 and tim5) -16 bit tim2 and tim5 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 80 mhz 0.0125 819.2 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 80 mhz - 53.68 s table 80. iwdg min/max timeout period at 32 khz (lsi) (1) 1. the exact timings still depend on the phasing of the apb in terface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 table 81. wwdg min/max timeout value at 80 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0512 3.2768 ms 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144 docid027692 rev 2 161/193 stm32l475xx electrical characteristics 181 6.3.26 communication interfaces characteristics i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to rm0395 reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still pr esent. only ft_f i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 82. i2c analog filter characteristics (1) 1. guaranteed by design. symbol paramete rminmaxunit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns electrical characteristics stm32l475xx 162/193 docid027692 rev 2 spi characteristics unless otherwise specified, the parameters given in table 83 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 22: general operating conditions . ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 83. spi characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode receiver/full duplex 2.7 < v dd < 3.6 v voltage range 1 -- 24 mhz master mode receiver/full duplex 1.71 < v dd < 3.6 v voltage range 1 13 master mode transmitter 1.71 < v dd < 3.6 v voltage range 1 40 slave mode receiver 1.71 < v dd < 3.6 v voltage range 1 40 slave mode transmitter/full duplex 2.7 < v dd < 3.6 v voltage range 1 26 (2) slave mode transmitter/full duplex 1.71 < v dd < 3.6 v voltage range 1 16 (2) voltage range 2 13 t su(nss) nss setup time slave mode, spi prescaler = 2 4 ? t pclk --ns t h(nss) nss hold time slave mode, spi prescaler = 2 2 ? t pclk --ns t w(sckh) t w(sckl) sck high and low time master mode t pclk -2 t pclk t pclk +2 ns t su(mi) data input setup time master mode 3.5 - - ns t su(si) slave mode 3 - - t h(mi) data input hold time master mode 6.5 - - ns t h(si) slave mode 3 - - t a(so) data output access time slave mode 9 - 36 ns t dis(so) data output disable time slave mode 9 - 16 ns docid027692 rev 2 163/193 stm32l475xx electrical characteristics 181 figure 25. spi timing diagram - slave mode and cpha = 0 t v(so) data output valid time slave mode 2.7 < v dd < 3.6 v voltage range 1 -12.519 ns slave mode 1.71 < v dd < 3.6 v voltage range 1 -12.530 slave mode 1.71 < v dd < 3.6 v voltage range 2 -12.533 t v(mo) master mode - 2.5 12.5 t h(so) data output hold time slave mode 9 - - ns t h(mo) master mode 0 - - 1. guaranteed by characterization results. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value can be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50 %. table 83. spi characteristics (1) (continued) symbol parameter conditions min typ max unit d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 electrical characteristics stm32l475xx 164/193 docid027692 rev 2 figure 26. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . figure 27. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 docid027692 rev 2 165/193 stm32l475xx electrical characteristics 181 quad spi characteristics unless otherwise specified, the parameters given in table 84 and table 85 for quad spi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage condit ions summarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 15 or 20 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics. table 84. quad spi characteristics in sdr mode (1) symbol parameter conditions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 1.71 < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 2.7 < v dd < 3.6 v, c load = 15 pf voltage range 1 --60 1.71 < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc=0 t (ck) /2-2 - t (ck) /2 ns t w(ckl) t (ck) /2 - t (ck) /2+2 t s(in) data input setup time voltage range 1 4 - - voltage range 2 3.5 - - t h(in) data input hold time voltage range 1 5.5 - - voltage range 2 6.5 - - t v(out) data output valid time voltage range 1 - 2.5 5 voltage range 2 - 3 5 t h(out) data output hold time voltage range 1 1.5 - - voltage range 2 2 - - 1. guaranteed by characterization results. electrical characteristics stm32l475xx 166/193 docid027692 rev 2 figure 28. quad spi timing diagram - sdr mode figure 29. quad spi ti ming diagram - ddr mode table 85. quadspi characteristics in ddr mode (1) symbol parameter conditions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 2 < v dd < 3.6 v, c load = 20 pf voltage range 1 --48 1.71 < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 1.71 < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc=0 t (ck) /2-2 - t (ck) /2 ns t w(ckl) t (ck) /2 - t (ck) /2+2 t sf(in) ;t sr(in) data input setup time voltage range 1 and 2 3.5 - - t hf(in) ; t hr(in) data input hold time 6.5 - - t vf(out) ;t vr(out) data output valid time voltage range 1 - 11 12 voltage range 2 15 19 t hf(out) ; t hr(out) data output hold time voltage range 1 6 - - voltage range 2 8 - 1. guaranteed by characterization results. 0 6 y 9 ' d w d r x w s x w ' ' ' & o r f n ' d w d l q s x w ' ' ' w & . w z & . + w z & . / w u & . w i & . w v , 1 w k , 1 w y 2 8 7 w k 2 8 7 0 6 y 9 ' d w d r x w s x w ' ' ' & o r f n ' d w d l q s x w ' ' ' w & . w z & . + w z & . / w u & . w i & . w v i , 1 w k i , 1 w y i 2 8 7 w k u 2 8 7 ' ' ' ' ' ' w y u 2 8 7 w k i 2 8 7 w v u , 1 w k u , 1 docid027692 rev 2 167/193 stm32l475xx electrical characteristics 181 sai characteristics unless otherwise specified, the parameters given in table 86 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (ck,sd,fs). table 86. sai characteristics (1) symbol parameter conditions min max unit f mclk sai main clock output - - 50 mhz f ck sai clock frequency (2) master transmitter 2.7 v dd 3.6 voltage range 1 -18.5 mhz master transmitter 1.71 v dd 3.6 voltage range 1 -12.5 master receiver voltage range 1 -25 slave transmitter 2.7 v dd 3.6 voltage range 1 -22.5 slave transmitter 1.71 v dd 3.6 voltage range 1 -14.5 slave receiver voltage range 1 -25 voltage range 2 - 12.5 t v(fs) fs valid time master mode 2.7 v dd 3.6 -22 ns master mode 1.71 v dd 3.6 -40 t h(fs) fs hold time master mode 10 - ns t su(fs) fs setup time slave mode 1 - ns t h(fs) fs hold time slave mode 2 - ns t su(sd_a_mr) data input setup time master receiver 2.5 - ns t su(sd_b_sr) slave receiver 3 - t h(sd_a_mr) data input hold time master receiver 8 - ns t h(sd_b_sr) slave receiver 4 - electrical characteristics stm32l475xx 168/193 docid027692 rev 2 figure 30. sai master timing waveforms t v(sd_b_st) data output valid time slave transmitter (after enable edge) 2.7 v dd 3.6 -22 ns slave transmitter (after enable edge) 1.71 v dd 3.6 -34 t h(sd_b_st) data output hold time slave transmitter (after enable edge) 10 - ns t v(sd_a_mt) data output valid time master transmitter (after enable edge) 2.7 v dd 3.6 -27 ns master transmitter (after enable edge) 1.71 v dd 3.6 -40 t h(sd_a_mt) data output hold time master tr ansmitter (after enable edge) 10 - ns 1. guaranteed by characterization results. 2. apb clock frequency must be at least twice sai clock frequency. table 86. sai characteristics (1) (continued) symbol parameter conditions min max unit - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 o u t p u t f 3 # + 3 ! ) ? 3 $ ? 8 t r a n s m i t t v & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t h & 3 3 l o t n t v 3 $ ? - 4 t h 3 $ ? - 4 3 l o t n t s u 3 $ ? - 2 t h 3 $ ? - 2 docid027692 rev 2 169/193 stm32l475xx electrical characteristics 181 figure 31. sai slave timing waveforms sdmmc characteristics unless otherwise specified, the parameters given in table 87 for sdio are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 22: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output characteristics. table 87. sd / mmc dynamic characteristics, v dd =2.7 v to 3.6 v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/fpclk2 frequency ratio - - - 4/3 - t w(ckl) clock low time f pp = 50 mhz 8 10 - ns t w(ckh) clock high time f pp = 50 mhz 8 10 - ns cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs f pp = 50 mhz 2 - - ns t ih input hold time hs f pp = 50 mhz 4.5 - - ns cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs f pp = 50 mhz - 12 14 ns t oh output hold time hs f pp = 50 mhz 9 - - ns cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd f pp = 50 mhz 2 - - ns t ihd input hold time sd f pp = 50 mhz 4.5 - - ns - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 i n p u t 3 ! ) ? 3 $ ? 8 t r a n s m i t t s u & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t w # + ( ? 8 t h & 3 3 l o t n t v 3 $ ? 3 4 t h 3 $ ? 3 4 3 l o t n t s u 3 $ ? 3 2 t w # + , ? 8 t h 3 $ ? 3 2 f 3 # + electrical characteristics stm32l475xx 170/193 docid027692 rev 2 figure 32. sdio high-speed mode cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd f pp = 50 mhz - 4.5 5 ns t ohd output hold default time sd f pp = 50 mhz 0 - - ns 1. guaranteed by characterization results. table 88. emmc dynami c characteristics, v dd = 1.71 v to 1.9 v (1)(2) 1. guaranteed by characterization results. 2. c load = 20pf. symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdio_ck/f pclk2 frequency ratio - - - 4/3 - t w(ckl) clock low time f pp = 50 mhz 8 10 - ns t w(ckh) clock high time f pp = 50 mhz 8 10 - ns cmd, d inputs (reference d to ck) in emmc mode t isu input setup time hs f pp = 50 mhz 0 - - ns t ih input hold time hs f pp = 50 mhz 5 - - ns cmd, d outputs (referenced to ck) in emmc mode t ov output valid time hs f pp = 50 mhz - 13.5 15.5 ns t oh output hold time hs f pp = 50 mhz 9 - - ns table 87. sd / mmc dynamic characteristics, v dd =2.7 v to 3.6 v (1) (continued) symbol parameter conditions min typ max unit t 7 # + ( # + $ # - $ o u t p u t $ # - $ i n p u t t # t 7 # + , t / 6 t / ( t ) 3 5 t ) ( t f t r a i docid027692 rev 2 171/193 stm32l475xx electrical characteristics 181 figure 33. sd default mode a i # + $ # - $ o u t p u t t / 6 $ t / ( $ electrical characteristics stm32l475xx 172/193 docid027692 rev 2 usb characteristics the stm32l475xx usb interface is fully complia nt with the usb specification version 2.0 and is usb-if certified (for full-speed device operation). can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). table 89. usb electrical characteristics symbol parameter conditions min typ max unit v ddusb usb transceiver operating voltage 3.0 (1) -3.6v r pui embedded usb_dp pull-up value during idle 900 1250 1600 ? r pur embedded usb_dp pull-up value during reception 1400 2300 3200 z drv (2) output driver impedance (3) driving high and low 28 36 44 ? 1. the stm32l475xx usb functionality is ensured down to 2. 7 v but not the full usb electrical characteristics which are degraded in the 2.7-to-3.0 v voltage range. 2. guaranteed by design. 3. no external termination series resistors are r equired on usb_dp (d+) and usb_dm (d-); the matching impedance is already included in the embedded driver. docid027692 rev 2 173/193 stm32l475xx electrical characteristics 181 6.3.27 fsmc characteristics unless otherwise specified, the parameters given in table 90 to table 95 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage cond itions summarized in table 22 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output characteristics. asynchronous waveforms and timings figure 34 and figure 35 represent asynchronous waveforms and table 90 through table 93 provide the corresponding timings. the result s shown in these tables are obtained with the following fmc configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode, datasetuptime = 0x5) ? busturnaroundduration = 0x0 in all timing tables, the thclk is the hclk clock period. electrical characteristics stm32l475xx 174/193 docid027692 rev 2 figure 34. asynchronous multiplexed psram/nor read waveforms . " , $ a t a & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t v ! ? . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t s u $ a t a ? . % t h ! $ ? . ! $ 6 & - # ? . % & - # ? . / % t w . % t w . / % t v . / % ? . % t h . % ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % t h $ a t a ? . / % & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid027692 rev 2 175/193 stm32l475xx electrical characteristics 181 table 90. asynchronous multiplexed psram/nor read timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk -0.5 3t hclk +2 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk -0.5 2t hclk +0.5 t w(noe) fmc_noe low time t hclk +0.5 t hclk +1 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 3 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 1 t w(nadv) fmc_nadv low time t hclk -0.5 t hclk +1 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high 0 - t h(a_noe) address hold time after fmc_noe high t hclk -0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 2 t su(data_ne) data to fmc_nex high setup time t hclk -2 - t su(data_noe) data to fmc_noe high setup time t hclk -1 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - table 91. asynchronous multiplexed psram/nor read-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk +2 8t hclk +4 ns t w(noe) fmc_nwe low time 5t hclk -1 5t hclk +1.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 - electrical characteristics stm32l475xx 176/193 docid027692 rev 2 figure 35. asynchronous multip lexed psram/nor write waveforms . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v ! ? . % t w . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t v $ a t a ? . ! $ 6 t h ! $ ? . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid027692 rev 2 177/193 stm32l475xx electrical characteristics 181 synchronous waveforms and timings figure 36 and figure 37 represent synchronous waveforms and table 94 and table 95 provide the corresponding timings. the results shown in these tables are obtained with the following fmc configuration: ? burstaccessmode = fmc_ burstaccessmode_enable ? memorytype = fmc_memorytype_cram ? writeburst = fmc_writeburst_enable ? clkdivision = 1 ? datalatency = 1 for nor flash; datalatency = 0 for psram table 92. asynchronous multiplexed psram/nor write timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk -0.5 4t hclk +2 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk -0.5 t hclk +1 t w(nwe) fmc_nwe low time 2xt hclk -1.5 2xt hclk +1. 5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk -0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 3 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 1 t w(nadv) fmc_nadv low time t hclk -0.5 t hclk +1 t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high t hclk -2 - t h(a_nwe) address hold time after fmc_nwe high t hclk -1 - t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk +0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 1.5 t v(data_nadv) fmc_nadv high to data valid - t hclk +4 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - table 93. asynchronous multiplexed psram/nor write-nwait timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk -0.5 9t hclk +2 ns t w(nwe) fmc_nwe low time 7t hclk -1.5 7t hclk +1.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +2 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk -3 - electrical characteristics stm32l475xx 178/193 docid027692 rev 2 in all timing tables, the t hclk is the hclk clock period. figure 36. synchronous multiplexed nor/psram read timings & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . / % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 docid027692 rev 2 179/193 stm32l475xx electrical characteristics 181 table 94. synchronous multiplexed nor/psram read timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk -1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 2.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 1 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 3.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 1.5 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk +1 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 4 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 0 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 2.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 0 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 4 - electrical characteristics stm32l475xx 180/193 docid027692 rev 2 figure 37. synchronous multiplexed psram write timings 0 6 y 9 ) 0 & b & / . ) 0 & b 1 ( [ ) 0 & b 1 $ ' 9 ) 0 & b $ > @ ) 0 & b 1 : ( ) 0 & b $ ' > @ $ ' > @ ' ' ) 0 & b 1 : $ , 7 : $ , 7 & ) * e : $ , 7 3 2 / e w z & / . w z & / . ' d w d o d w h q f \ % 8 6 7 8 5 1 w g & / . / 1 ( [ / w g & / . + 1 ( [ + w g & / . / 1 $ ' 9 / w g & / . / $ 9 w g & / . / 1 $ ' 9 + w g & / . + $ , 9 w g & / . + 1 : ( + w g & / . / 1 : ( / w g & / . + 1 % / + w g & / . / $ ' 9 w g & / . / $ ' , 9 w g & / . / ' d w d w v x 1 : $ , 7 9 & / . + w k & / . + 1 : $ , 7 9 w g & / . / ' d w d ) 0 & b 1 % / docid027692 rev 2 181/193 stm32l475xx electrical characteristics 181 table 95. synchronous multiplexed psram write timings (1)(2) 1. cl = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk -1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 2.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 1 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 3.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 2 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk +1 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 4 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 5.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low - 2.5 t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk +1 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 0 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 4 - package information stm32l475xx 182/193 docid027692 rev 2 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp100 package information figure 38. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! docid027692 rev 2 183/193 stm32l475xx package information 190 table 96. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0. 6220 0.6299 0.6378 d1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0. 6220 0.6299 0.6378 e1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 package information stm32l475xx 184/193 docid027692 rev 2 figure 39. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. figure 40. lqfp100 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering a i c 0 6 y 9 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 3 l q l q g h q w l i l h u 6 7 0 / 9 * 7 < : : 2 s w l r q d o j d w h p d u n docid027692 rev 2 185/193 stm32l475xx package information 190 samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 7.2 lqfp64 package information figure 41. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package information stm32l475xx 186/193 docid027692 rev 2 figure 42. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 97. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid027692 rev 2 187/193 stm32l475xx package information 190 figure 43. lqfp64 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ' d w h f r g h 3 l q l g h q w l i l h u 6 7 0 / 5 * 7 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h < : : package information stm32l475xx 188/193 docid027692 rev 2 7.3 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 22: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v ddiox ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.3.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.3.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm32l4 75xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature ra nge will be best suited to the application. the following examples show how to calculat e the temperature range needed for a given application. table 98. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp100 - 14 14mm 42 docid027692 rev 2 189/193 stm32l475xx package information 190 example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 98 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.115 c = 102.115 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see section 8: part numbering . in this case, parts must be ordered at least with the temperature range suffix 6 (see part numbering). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (45c/w 447 mw) = 105-20.115 = 84.885 c suffix 7: t amax = t jmax - (45c/w 447 mw) = 125-20.115 = 104.885 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 98 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 100 c + (45 c/w 134 mw) = 100 c + 6.03 c = 106.03 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. package information stm32l475xx 190/193 docid027692 rev 2 refer to figure 44 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. figure 44. lqfp64 p d max vs. t a 0 6 y 9 6 x i i l [ 6 x i i l [ 3 ' p : 7 $ ? & docid027692 rev 2 191/193 stm32l475xx part numbering 192 8 part numbering table 99. stm32l475xx ordering information scheme example: stm32 l 475 r g t 6 tr device family stm32 = arm ? based 32-bit microcontroller product type l = ultra-low-power device subfamily 475: stm32l475xx pin count r = 64 pins v = 100 pins flash memory size c = 256 kb of flash memory e = 512 kb of flash memory g = 1 mb of flash memory package t = lqfp ecopack ? 2 temperature range 6 = industrial temperature range, -40 to 85 c (105 c junction) 7 = industrial temperature range, -40 to 105 c (125 c junction) 3 = industrial temperature range, -40 to 125 c (130 c junction) packing tr = tape and reel xxx = programmed parts revision history stm32l475xx 192/193 docid027692 rev 2 9 revision history table 100. document revision history date revision changes 05-feb-2016 1 initial release. 03-mar-2016 2 removed nand from supported memories on cover page. added adc 3 impacting: cover page section 2: description . table 2: stm32l475xx family device features and peripheral counts . table 5: functionalities depending on the working mode . section 3.15.1: temperature sensor . section 3.15.3: vbat battery voltage monitoring . table 15: stm32l475xx pin definitions . section 2: description . updated section 3.26: universal synchronous/asynchronous receiver transmitter (usart) . updated section 3.27: low-power universal asynchronous receiver transmitter (lpuart) . added table 43: wakeup time using usart/lpuart . updated table 54: ems characteristics . updated table 55: emi characteristics . docid027692 rev 2 193/193 stm32l475xx 193 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 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