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DS711 july 25, 2012 www.xilinx.com 1 product specification ? copyright 2010?2012 xilinx, inc. xilinx, the xilinx logo, artix, ise, kintex, spartan, virtex, vivado, zynq, and other design ated brands included herein are trademarks of xilinx in the united states and other countries. amba is a trademark of arm in the eu and other countries. all ot her trademarks are the property of their respective owners. n introduction the processor local bus (plb v4.6) to advanced micro- controller bus architecture (amba ? ) advanced exten- sible interface (axi) bridge translates plbv46 transactions into axi4 transactions. it functions as a slave on the plbv46 and as a master on the axi4. the plbv46 to axi bridge main use model is to connect the axi slaves with plb masters. features the xilinx? plbv46 to axi brid ge is a soft intellectual property (ip) core with the following features: plbv46 slave interface ? connects as a 32/64-bit slave on plb v4.6 buses of 32, 64 or 128 bits ? supports 1:1 (plb:axi) synchronous clock ratio ? supports access by 32, 64-bit plb masters ? supports xilinx simplified plbv46 protocol ? single transfers of 1 to 8 bytes ? optional line transfers of 4 and 8 words ? optional fixed length burst transfers of 2 to 16 data beats of words and double words ? supports optional two leve ls of address pipelining ? supports split bus architecture (simultaneous read and write operations) ? supports optional plb status/interrupt registers and generates interrupts ? supports optional low latency plb point-to-point topology ? supports 1 to 4 address ranges with selectable cache encoding and protection unit support axi master interface ? connects as a 32/64-bit master on 32/64-bit axi4 interface ? connects as a 32-bit master on 32-bit axi4-lite interface ? support burst transfers of 1 to 32 words or 1 to 16 double words of incr type and burst transfers of 4 and 8 only of wrap type ? supports optional genera tion of two outstanding addresses and supports out-of-order read transaction completion and out-of-order write transaction completion ? supports optional limited cache encoding (cacheable/bufferable) and limited protection unit support (secure/non-secure) logicore ip plbv46 to axi bridge (v2.01.a) DS711 july 25, 2012 product specification logicore ip facts table core specifics supported device family (1) zynq?-7000 (2) , virtex?-7 (3) , kintex?-7 (3), artix?-7 (3) , virtex-6 (4) spartan?-6 (5) supported user interfaces plbv46, axi4/axi4-lite resources see ta bl e 1 4 through ta b l e 1 8 . provided with core design files vhdl example design not provided test bench not provided constraints file none simulation model none supported s/w driver n/a tested design flows (6) design entry xilinx platform studio (xps) vivado? design suite (7) simulation mentor graphics modelsim synthesis tools xilinx synthesis technology (xst) vivado synthesis support provided by xilinx@ www.xilinx.com/support notes: 1. for a complete list of supported derivative devices, see e mbedded edition derivative device support . 2. supported in ise design suite implementations only. 3. for more information, see ds180, 7 series fpgas overview . 4. for more information, see ds150, virtex-6 family overview . 5. for more information, see ds160, spartan-6 family overview . 6. for the supported versions of the tools, see the x ilinx design to o l s : release notes guide . 7. supports only 7 series devices.
DS711 july 25, 2012 www.xilinx.com 2 product specification logicore ip plbv46 to axi bridge (v2.01.a) not supported features and limitations plbv46 slave interface ? plb master size greater than 64 bits the following plb features and behaviors are not supported because the xilinx simplifi cation of the plbv46 does not support them: ?aborts ? non-memory transfer types (dma flyby, buffered, pe ripheral to memory, memory to peripheral and dma memory to memory are ignored) ? fixed length burst transfer requests of 17 to 256 data beats ? fixed length bursts of size byte and half word ? premature fixed length burst terminations ? indeterminate burst transfers ? cache line transfers of 16 words ?parity ? transfer attributes ? plb bus locked transfers ? pending request and priority input information ? slave to master interrupts axi master interface ? interface initialization is not supported. ? quality of service signalling is not supported. the following axi features are not supp orted as plbv46 never generates them: ? fixed burst type is not supported. ? axi cache support is limited. ? bufferable and cacheable attributes ca n be selected during configuration. ? read allocate and write allocate attributes are not supported. ? protection unit support is limited. ? privileged and instruction accesses are not supported. ? either secure or non-secure is selected during configuration. ? atomic exclusive transactions and lock transactions ar e not supported. all the axi transactions are normal accesses. ? unaligned transfers are not supported. ? barrier transfers/debug transfers/user signals are not supported.
DS711 july 25, 2012 www.xilinx.com 3 product specification logicore ip plbv46 to axi bridge (v2.01.a) functional description overview the plbv46 to axi bridge translates plb transactions into axi transactions. the bridge functions as a slave on the plb and as a master on the axi. the plbv46 to axi bridge block diagram is shown in figure 1 and described in following sections. plbv46 slave the plbv46 slave module provides a bi directional slave interface to the plb. the plb data bus width can be con- figured by setting the parameters as shown in table 2 . this module decodes the address for the bridge registers and for the slaves on the axi when c_splb_p2p = 0. this mo dule also implements the logic to detect if overlapping write and read requests are issued from the plb. as ax i has independent read and write channels, these requests are issued in such a way that the data coherency is maintained. write buffer the write buffer stores the write data from the plbv46 sl ave module during the posted write transactions. this is enabled when c_splb_support_bursts = 1. the write buffer is implemented in the bridge to free up the master transactions to other cores that might be on the plb. the write buffer contains a first in first out (fifo) of width 32/64-bit and depth of 16. the width of the fifo is directly dependent on c_splb_native_dwidth. the write buffer passes the write data to the axi master module. x-ref target - figure 1 figure 1: plbv46 to axi bridge block diagram DS711_01 plbv46 sla ve plbv46 legend: indicates optional. axi4 axi4-lite interr upt axi full/axi lite axi master write bu ffer read bu ffer bridge control logic register and interr upt
DS711 july 25, 2012 www.xilinx.com 4 product specification logicore ip plbv46 to axi bridge (v2.01.a) read buffer the read buffer stores the read data from the axi master module during out-of-order read transactions. this is enabled when c_m_axi_supports_threads = 1. when en abled, the address pipelining depth on plb is two and outstanding addresses issued on axi are two. the read buffer is needed when these back-to-back read transfers on axi are responded in out-of-order by axi slaves. the re ad buffer contains a fifo of width 32/64-bit and depth of 16. the width of the fifo is directly dependent on c_splb_native_dwidth. the read buffer passes the read data to the plbv46 slave module. bridge control logic the plbv46 to axi bridge needs to split a burst transfer th at crosses a 4 k byte boundary as required by axi. the bridge control logic module generates the 4 kb crossing control signals and provides the length and address sig- nals to the axi master module. this module is not used when c_splb_support_bursts = 0 as axi4-lite inter- face is used on axi side. register and interrupt the register and interrupt module contains the bridge registers and generates interrupts. this is enabled when both parameters c_en_err_regs and c_splb_support_bursts are set to 1. these registers capture the plb request status and qualifiers as well as the target address when a write or read transaction generates an error on the axi side. an interrupt is generated to report these errors. see register descriptions for more details. the register accesses are always 32-bit and only plb sing le transfers are acknowledged in the register address space. the slave size is always 32-bit even when c_splb_native_dwidth is 64. this module is not imple- mented when c_splb_support_bursts = 0 and the error information is sent on sl_mrderr and sl_mwrerr signals. also the interrupt signal is not used. axi master the axi master module provides a bidirectional axi mast er interface on the axi. this interface can be axi memory-mapped interface (axi4) or axi4-lite interfac e (control interface) depending on the parameter c_splb_support_bursts. when c_sp lb_support_burst = 0, only single transfers on plb are supported and the axi4-lite interface is used on the axi side. when c_splb_support_bursts = 1, the axi4 interface is used on axi. the axi data bus width can be 32 or 64-bit s in theaxi4 interface and always fixed at 32 when axi4- lite interface is used. this module receives read data from axi and transmits to either read buffer when the read buffer is enabled or to plbv46 slave module when the read buffer is disabled. during write transfers the write data is received from the write buffer. depending on the desi gn parameters, the axi master module controls the sup- ported limited cache encoding (cache able/bufferable) and limited protecti on encoding (secure/non-secure) sig- nals.
DS711 july 25, 2012 www.xilinx.com 5 product specification logicore ip plbv46 to axi bridge (v2.01.a) i/o signals table 1 shows the input/output (i/o) signals of the plbv46 to axi bridge. ta bl e 1 : i/o signal description port signal name interface i/o initial state description plb system signals p1 splb_clk system i - plb clock p2 splb_rst system i - plb reset, active-high p3 interrupt (1) system o 0 bridge interrupt (edge sensitive, rising) plb interface signals p4 splb_abus[0:c_splb_awidth -1] plb i - plb address bus p5 splb_pavalid plb i - plb primary address valid p6 splb_masterid[0:c_splb_mid_ width - 1] plb i - plb current master identifier p7 splb_rnw plb i - plb read not write p8 splb_be[0 : (c_splb_dwidth/8) - 1] plb i - plb byte enables p9 splb_size[0 : 3] plb i - plb size of requested transfer p10 splb_type[0 : 2] plb i - plb transfer type p11 splb_wrdbus[0 : c_splb_dwidth - 1] plb i - plb write data bus p12 splb_savalid plb i - plb secondary address valid p13 splb_msize[0 : 1] plb i - plb data bus width indicator plb slave interface signals p14 sl_addrack plb o 0 slave address acknowledge p15 sl_ssize[0 : 1] plb o 0 slave data bus size p16 sl_wait plb o 0 slave wait p17 sl_rearbitrate plb o 0 slave bus rearbitrate p18 sl_wrdack plb o 0 slave write data acknowledge p19 sl_wrcomp plb o 0 slave write transfer complete p20 sl_rddbus[0 : c_splb_dwidth - 1] plb o 0 slave read data bus p21 sl_rddack plb o 0 slave read data acknowledge p22 sl_rdcomp plb o 0 slave read transfer complete p23 sl_mbusy[0 : c_splb_num_masters - 1] plb o 0 slave busy p24 sl_mrderr[0 : c_splb_num_masters - 1] plb o 0 slave read error p25 sl_mwrerr[0 : c_splb_num_master s - 1] plb o 0 slave write error p26 sl_rdwdaddr[0 : 3] plb o 0 slave read word address p27 sl_wrbterm plb o 0 slave terminate write burst transfer p28 sl_rdbterm plb o 0 slave terminate read burst transfer
DS711 july 25, 2012 www.xilinx.com 6 product specification logicore ip plbv46 to axi bridge (v2.01.a) unused plb signals p29 splb_uabus[0 : 31] plb i - plb upper address bits p30 splb_rdprim plb i - plb secondary to primary read request indicator p31 splb_wrprim plb i - plb secondary to primary write request indicator p32 plb_abort plb i - plb abort bus request p33 splb_buslock plb i - plb bus lock p34 splb_lockerr plb i - plb lock error p35 splb_wrburst plb i - plb burst write transfer p36 splb_rdburst plb i - plb burst read transfer p37 splb_wrpendreq plb i - plb pending bus write request p38 splb_rdpendreq plb i - plb pending bus read request p39 splb_wrpendpri[0 : 1] plb i - plb pending write request priority p40 splb_rdpendpri[0 : 1] plb i - plb pending read request priority p41 splb_reqpri[0 : 1] plb i - plb current request priority p42 splb_tattribute[0 : 15] plb i - plb transfer attribute p43 sl_mirq[0 : c_splb_num_masters - 1] plb o 0 master interrupt request axi interface signals (2) axi write address channel signals p44 m_axi_awid[ c_m_axi_ thread_id_width -1 : 0] axi_full o 0 write address id: this signal is the identification tag for the write address group of signals p45 m_axi_awaddr[c_m_axi_ addr_width-1 : 0] axi_full/ axi_lite o0 axi write address: the write address bus gives the address of the first transfer in a write burst transaction. p46 m_axi_awlen[7 : 0] axi_full o 0 burst length: this signal gives the exact number of transfers in a write burst. p47 m_axi_awsize[ 2 : 0] axi_full o 0 burst size: this signal indicates the size of each transfer in the write burst. p48 m_axi_awburst[ 1 : 0] axi_full o 0 burst type: this signal, coupled with the size information, details how the address for each write transfer within the burst is calculated. p49 m_axi_awcache[3 : 0] axi_full o 0 cache type: this signal provides additional information about the cacheable characteri stics of the write transfer. ta bl e 1 : i/o signal description (cont?d) port signal name interface i/o initial state description
DS711 july 25, 2012 www.xilinx.com 7 product specification logicore ip plbv46 to axi bridge (v2.01.a) p50 m_axi_awprot[2 : 0] axi_full/ axi_lite o2 protection type: this signal indicates the normal, privileged, or secure protection level of the write transaction and whether the transaction is a data access or an instruction access. the default value is normal non secure data access. p51 m_axi_awvalid axi_full/ axi_lite o0 write address valid: this signal indicates that valid write address and control information are available. p52 m_axi_awready axi_full/ axi_lite i- write address ready: this signal indicates that the slave is ready to accept an address and associated control signals. axi write channel signals p53 m_axi_wdata[c_m_axi_ data_width-1 : 0] axi_full/ axi_lite o 0 write data bus p54 m_axi_wstb[c_m_axi_ data_width/8-1 : 0] axi_full/ axi_lite o0 write strobes: this signal indicates which byte lanes to update in memory. p55 m_axi_wlast axi_full/ axi_lite o0 write last: this signal indicates the last transfer in a write burst. p56 m_axi_wvalid axi_full/ axi_lite o0 write valid: this signal indicates that valid write data and strobes are available. p57 m_axi_wready axi_full/ axi_lite i- write ready: this signal indicates that the slave can accept the write data. axi write response channel signals p58 m_axi_bid[ c_m_axi_ thread_id_width-1 : 0] axi_full i - write response id: this signal is the identification tag of the write response. the bid value must match the awid value of the write transaction to which the slave is responding. p59 m_axi_bresp[1 : 0] axi_full, axi_lite i- write response: this signal indicates the status of the write transaction. p60 m_axi_bvalid axi_full/ axi_lite i- write response valid: this signal indicates that a valid write response is available. p61 m_axi_bready axi_full/ axi_lite o1 response ready: this signal indicates that the master can accept the response information. ta bl e 1 : i/o signal description (cont?d) port signal name interface i/o initial state description
DS711 july 25, 2012 www.xilinx.com 8 product specification logicore ip plbv46 to axi bridge (v2.01.a) axi read address channel signals p62 m_axi_arid[c_m_axi_ thread_id_width-1 : 0] axi_full o 0 read address id: this signal is the identification tag for the read address group of signals. p63 m_axi_araddr[c_m_axi_ addr_width -1 : 0 ] axi_full/ axi_lite o0 read address: the read address bus gives the initial address of a read burst transaction. p64 m_axi_arlen[7 : 0] axi_full o 0 burst length: the burst length gives the exact number of transfers in a read burst. p65 m_axi_arsize[2 : 0] axi_full o 0 burst size: this signal indicates the size of each transfer in the read burst. p66 m_axi_arburst[1 : 0] axi_full o 0 burst type: the burst type, coupled with the size information, details how the address for each read transfer within the burst is calculated. p67 m_axi_arcache[ 3 : 0] axi_full o 0 cache type: this signal provides additional information about the cacheable characteristics of the read transfer. p68 m_axi_arprot[2 : 0] axi_full/ axi_lite o2 protection type: this signal provides protection unit information for the read transaction. the default value is normal non secure data access. p69 m_axi_arvalid axi_full/ axi_lite o0 read address valid: this signal indicates, when high, that the read address and control information is valid and remains stable until the address acknowledgement signal, arredy, is high. p70 m_axi_arready axi_full/ axi_lite i- read address ready: this signal indicates that the slave is ready to accept an address and associated control signals. axi read data channel signals p71 m_axi_rid[c_m_axi_ thread_id_width-1 : 0] axi_full i - read id tag: this signal is the id tag of the read data group of signals. the rid value is generated by the slave and must match the arid value of the read transaction to which it is responding. p72 m_axi_rdata[c_m_axi_ data_width -1 : 0] axi_full/ axi_lite i - read data bus p73 m_axi_rresp[1 : 0] axi_full/ axi_lite i- read response: this signal indicates the status of the read transfer. p74 m_axi_rlast axi_full/ axi_lite i- read last: this signal indicates the last transfer in a read burst. ta bl e 1 : i/o signal description (cont?d) port signal name interface i/o initial state description
DS711 july 25, 2012 www.xilinx.com 9 product specification logicore ip plbv46 to axi bridge (v2.01.a) p75 m_axi_rvalid axi_full/ axi_lite i- read valid: this signal indicates that the required read data is available and the read transfer can complete. p76 m_axi_rready axi_full/ axi_lite o1 read ready: this signal indicates that the master can accept the read data and response information. p77 m_axi_awlock axi_full o 0 lock type: this signal provides additional information about the atomic characteristics of the write transfer. p78 m_axi_arlock axi_full o 0 lock type: this signal provides additional information about the atomic characteristics of the read transfer. unused axi signals p79 m_axi_aclk axi_full/ axi_lite i- axi clock - splb_clk is used on axi side. p80 m_axi_aresetn axi_full/ axi_lite i- axi reset - splb_rst is used on axi side. notes: 1. this signal is not used when c_splb_support_bursts = 0 or c_en_err_regs = 0 as error registers are not enabled. 2. axi_full interface refers to axi memory mapped inte rface (axi4) enabled when c_sp lb_support_bursts = 1 and axi_lite interface refers to axi4-lite in terface enable when c_splb_support_bursts = 0. ta bl e 1 : i/o signal description (cont?d) port signal name interface i/o initial state description
DS711 july 25, 2012 www.xilinx.com 10 product specification logicore ip plbv46 to axi bridge (v2.01.a) design parameters table 2 shows the design parameters of the plbv46 to axi bridge. inferred parameters in addition to the parameters listed in table 2 , there are also parameters that are inferred for each axi interface in the embedded development kit (edk) tools. through the design, these edk-inferred parameters control the behavior of the axi interconnect. for a complete list of the interconnect settings related to the axi interface, see ds768 axi interconnect ip data sheet . ta bl e 2 : design parameters generic feature/descr iption parameter name allowable values default values vhdl type system parameter g1 target fpga family c_family virtex7, kintex7, artix7, zynq, virtex6, spartan6 virtex6 string plb parameters g2 plb least significant address bus width c_splb_awidth 32 32 integer g3 plb data width c_splb_dwidth 32, 64, 128 32 integer g4 width of the slave data bus c_splb_native_dwidth 32,64 32 integer g5 selects point-to-point or shared bus topology 0 = shared bus topology 1 = point-to-point bus topology c_splb_p2p (1) 0 - 1 0 integer g6 plb master id bus width c_splb_mid_width log 2 (c_splb_nu m_masters) with a minimum value of 1 1 integer g7 number of plb masters c_splb_num_masters 1 - 16 1 integer g8 support bursts 0 = do not support bursts (axi4-lite on axi interface) 1 = support bursts (axi4 on axi interface) c_splb_support_ bursts 0 - 1 1 integer g9 support cacheline transfers 0 = do not support cacheline transfers 1 = support cacheline transfers c_splb_support_ cacheline (2) 0 - 1 0 integer g10 number of axi address ranges c_splb_num_addr_rngs 1 - 4 (3) 1 integer g11 plb offset address for all ranges c_splb_rngs_offset valid address (4)(5) 0x0 std_logic _vector g12 plb base address for address range 1 c_splb_rng1_ baseaddr valid address (5) none (4) std_logic _vector g13 plb high address for address range 1 c_splb_rng1_highaddr valid address (6) none (4) std_logic _vector
DS711 july 25, 2012 www.xilinx.com 11 product specification logicore ip plbv46 to axi bridge (v2.01.a) g14 range1 non-secure or secure access 0 = secure normal data access 1 = non-secure normal data access c_splb_rng1_ nonsec_sec (7) 0 - 1 1 integer g15 range1 cache encoding see cache support for details. c_splb_rng1_ cacheable_bufferable (8) 0 - 3 0 integer g16 plb base address for address range 2 c_splb_rng2_baseaddr valid address (5) none (4) std_logic _vector g17 plb high address for address range 2 c_splb_rng2_highaddr valid address (6) none (4) std_logic _vector g18 range 2 non-secure or secure access 0 = secure normal data access 1 = non-secure normal data access c_splb_rng2_ nonsec_sec (7) 0 - 1 1 integer g19 range2 cache encoding see cache support for details. c_splb_rng2_cacheable _bufferable (8) 0 - 3 0 integer g20 plb base address for address range 3 c_splb_rng3_baseaddr valid address (6) none (4) std_logic _vector g21 plb high address for address range 3 c_splb_rng3_highaddr valid address (6) none (4) std_logic _vector g22 range 3 non-secure or secure access 0 = secure normal data access 1 = non-secure normal data access c_splb_rng3_ nonsec_sec (7) 0 - 1 1 integer g23 range3 cache encoding see cache support for details. c_splb_rng3_cacheable _bufferable (8) 0 - 3 0 integer g24 plb base address for address range 4 c_splb_rng4_baseaddr valid address (5) none (4) std_logic _vector g25 plb high address for address range 4 c_splb_rng4_highaddr valid address (6) none (4) std_logic _vector g26 range 4 non-secure or secure access 0 = secure normal data access 1 = non-secure normal data access c_splb_rng4_ nonsec_sec (7) 0 - 1 1 integer g27 range4 cache encoding see cache support for details. c_splb_rng4_cacheable _bufferable (8) 0 - 3 0 integer g28 bridge base address when internal debug registers are enabled c_splb_bridge_ baseaddr valid address (9) none (4) std_logic _vector g29 bridge high address when internal debug registers are enabled c_splb_bridge_ highaddr valid address (9) none (4) std_logic _vector ta bl e 2 : design parameters (cont?d) generic feature/descr iption parameter name allowable values default values vhdl type
DS711 july 25, 2012 www.xilinx.com 12 product specification logicore ip plbv46 to axi bridge (v2.01.a) axi parameters g30 axi identification tag width c_m_axi_thread_id_ width (10) 1-2 1 integer g31 indicates generation of more than one outstanding transfers 0 = master generates one master id 1= master generates two master ids c_m_axi_supports_ threads (10)(11) 0-1 0 integer g32 axi most significant address bus width c_m_axi_addr_width 32 32 integer g33 axi data bus width c_m_axi_data_width 32, 64 32 (12) integer edk tool parameters g34 supports narrow bursts c_supports_narrow_ burst 0-1 0 (13) integer g35 maximum number of data-active read transactions generated. this is set as the read_acceptance parameter on the interconnect. c_interconnect_m_axi_ read_issuing 1-4 2 (14) integer g36 maximum number of data-active write transactions generated. this is set as the write_acceptance parameter on the interconnect. c_interconnect_m_axi_ write_issuing 1-4 2 (14) integer g37 axi interface type c_m_axi_protocol (15) axi4,axi4lite axi4 string plbv46 to axi bridge specific parameters g38 enable error registers for error information and generating interrupt 0 = no error registers are implemented 1 = error registers are implemented c_en_err_regs (16)(17) 0 - 1 0 integer g39 enable byte swapping from plb to axi 0 = no swapping is performed 1 = byte swapping is performed c_en_byte_swap 0-1 0 integer g40 number of no byte swap address regions when c_en_byte_swap is 1. c_nbs_num_addr_rngs 0-4 (18) 0 integer g41 no byte swap base address for address region 1 c_nbs_rng1_baseaddr valid address (19) none std_logic _vector g42 no byte swap high address for address region 1 c_nbs_rng1_highaddr valid address 19) none std_logic _vector ta bl e 2 : design parameters (cont?d) generic feature/descr iption parameter name allowable values default values vhdl type
DS711 july 25, 2012 www.xilinx.com 13 product specification logicore ip plbv46 to axi bridge (v2.01.a) 1. when c_splb_p2p is set to 1, the plbv46 to axi bridge does not require an address range specified by c_splb_rngx_baseaddr and c_splb_rngx_highaddr. also c_splb_rngs_offset is not valid. 2. this can be enabled only when c_splb_support_bursts = 1. when c_splb_support_cacheline is set to zero, 4-word and/or 8-word cache line transactions are not supported on plb. it is recommended to set this to 1 when plb master generates cache line transfers. 3. four sets of address ranges can be specified for the bridge so that different protection and cache encoding can be selected f or different address ranges. the range specified by the various base addresses and corresponding high addresses must comprise a complete, contiguous power of two range such that range = 2 n , and the n least significant bits of the base address must be zero. if an address range needs to support 16 word burst transactions, the base address for this address range must be aligned to a 64-byte address. 4. no default value is specified to ensure that the actual value is set, that is, if the value is not set, a compiler error is generated. high address - base address must be a power of 2. 5. only valid if c_splb_p2p = 0 and should be word align ed. c_splb_rngx_baseaddr+c_spl b_offset represents the base axi address that the plb is allowed to access for the range x (x varies from 1 to 4). for example, if c_splb_offset is 0x00000000, c_splb_rng1_baseaddr repr esents the physical address of ax i. c_splb_rng1_baseaddr value of 0x00000000 will go to physical address 0x00000000. a value of 0x02000000 will go to physical address 0x02000000. if you increase the c_splb_offset to 0x03000000, a c_splb_rng1_baseaddr value of 0x 00000000 will go to physical address 0x03000000, a c_splb_rng1_baseaddr value of 0x 02000000 will go to physical address 0x05000000. 6. c_splb_rngx_highaddr+c_splb_offset repr esents the high axi address that the plb is allowed to access for the range x. 7. the selected protection level is used for the entire range of br idge address and for all the axi transactions. m_axi_arprot[0 ], m_axi_awprot[0], m_axi_arprot[2], m_axi_awprot[2] m_axi_arprot[3] and m_axi_awprot[3] bits are set to zero. 8. the selected transaction attributes are used for the entire range of a bridge address and for all the axi transactions. read allocate and write allocate are set to zero. 9. the user must set these values only when c_en_err_regs = 1. the c_splb_bridge_baseaddr must be a multiple of the range, where the range is c_splb_bridge_h ighaddr - c_splb_bridge_baseaddr + 1. 10. this parameter is not used when c_splb_support_bursts = 0, as the axi interface is axi4-lite and the number of outstanding transfers is always 1. 11. splb_savalid is used only when c_m_axi_supports_threads = 1. 12. c_m_axi_data_width value will be set the same as c_ splb_native_dwidth. c_m_axi_data_width is set to 32 when c_splb_support_bursts = 0 as axi4-lite interface is used on axi side. 13. this parameter is used by interconnect and updated automatically. when c_splb_native_dwidth is 64, c_supports_narrow_burst is set to 1. when c_splb_n ative_dwidth is 32, c_supports_narrow_burst is set to 0 as narrow transfers are not generated. 14. this parameter is used by interconnect and updated automatically. see ta bl e 7 and outstanding requests on axi for more details. 15. when c_splb_support_bursts = 1, c_m_axi_prot ocol is updated automatically to axi4 and when c_splb_support_bursts = 0, c_m_axi_protoc ol is updated automatically to axi4lite. 16. when c_splb_p2p = 1, and c_en_err_regs = 1 all the pl b requests other than the register space address range (c_splb_bridge_baseaddr to c_splb_bridge_baseaddr + 0xf) is transl ated to axi. when c_splb_p2p = 1, and c_en_err_regs = 0 all the plb requests are translated to axi. 17. c_en_err_regs is set to 0, when c_splb_support_bursts = 0 as error registers are not required. g43 no byte swap base address for address region 2 c_nbs_rng2_baseaddr valid address (19) none std_logic _vector g44 no byte swap high address for address region 2 c_nbs_rng2_highaddr valid address (19) none std_logic _vector g45 no byte swap base address for address region 3 c_nbs_rng3_baseaddr valid address (19) none std_logic _vector g46 no byte swap high address for address region 3 c_nbs_rng3_highaddr valid address (19) none std_logic _vector g47 no byte swap base address for address region 4 c_nbs_rng4_baseaddr valid address (19) none std_logic _vector g48 no byte swap high address for address region 4 c_nbs_rng4_highaddr valid address (19) none std_logic _vector ta bl e 2 : design parameters (cont?d) generic feature/descr iption parameter name allowable values default values vhdl type
DS711 july 25, 2012 www.xilinx.com 14 product specification logicore ip plbv46 to axi bridge (v2.01.a) 18. four sets of address ranges can be specified for the no byte swap address regions in the given plb address ranges. this parameter is used when c_en_byte_swap is ?1? only and is igno red when c_en_byte_swap is ?0?. by default the value of the parameter is ?0?.this parameter is required for the axi slaves which have mixed address space for registers and memory.the byte invariance is ignored for the accesses in these address regions. 19. these address ranges are valid based on the c_nbs_num_a ddr_rngs and when c_en_byte_swap is ?1?. the axi slave register address spaces must be provided in these no byte swap address regions. there will not be byte swapping/byte in varianc e for these register addresses. narrow transfers are not allowed in these no byte swap address regions. allowable parameter combinations when c_en_err_regs = 1 and c_splb_support_bursts = 1, c_splb_bridge_baseaddr and c_splb_bridge_highaddr must be specified . the address range specified by c_splb_bridge_baseaddr and c_splb_bridge_highaddr must be a power of 2, and must be at least 0xf in size. for example, if c_splb_bridge_baseaddr = 0xe000000 0, c_splb_bridge_highaddr must be at least = 0xe000000f. parameter - i/o signal dependencies the dependencies between the plbv46 to axi bridge co re design parameters and i/o signals are described in table 3 . in addition, when certain features are parameterized ou t of the design, the related logic is no longer a part of the design. the unused input signals and rela ted output signals are set to a specified value . ta bl e 3 : parameter-i/o signal dependencies generic or port name affects depends relationship description design parameters g3 c_splb_dwidth g4 c_splb_dwidth should be greater than or equal to c_splb_native_dwidth. g3 c_splb_dwidth p8, p11, p20 - affects the number of bits of read and write data bus and byte enables g4 c_splb_native_dwidth g8 the allowed value of c_splb_native_dwidth is 32 when c_splb_support_bursts = 0. g5 c_splb_p2p g10 to g27 when c_splb_p2p = 1, as address decoding is not needed the generics related to address ranges are not used. g5 c_splb_p2p p16, p17 when c_splb_p2p = 1, sl_wait is driven when the bridge is busy. when c_splb_p2p = 0, sl_rearbitrate is driven when the bridge is busy. g6 c_splb_mid_width p6 g9 this value is calculated as: log 2 (c_splb_num_masters) with a minimum value of 1. g7 c_splb_num_masters p23, p24, p25 - affects the width of the sl_mbusy, sl_mwrerr and sl_mrderr
DS711 july 25, 2012 www.xilinx.com 15 product specification logicore ip plbv46 to axi bridge (v2.01.a) g8 c_splb_support_bursts p44, p46 to p49, p58, p62, p64 to p67, p71, p77, p78 when burst support is disabled, the axi4-lite interface is used and signals that are used for axi4 interface are not used. g9 c_splb_support_cacheline g8 c_splb_support_cacheline is valid only when c_splb_support_bursts = 1. g28 c_splb_bridge_baseaddr g8, g34 c_splb_bridge_baseaddr is valid only when c_en_err_regs = 1 and c_splb_support_bursts = 1. g29 c_splb_bridge_highaddr g8, g34 c_splb_bridge_highaddr is valid only when c_en_err_regs = 1 and c_splb_support_bursts = 1. g30 c_m_axi_thread_id_width g8 c_m_axi_thread_id_width is valid only when c_splb_support_bursts = 1. g31 c_m_axi_supports_threads g8 c_m_axi_supports_threads is valid only when c_splb_support_bursts = 1. g33 c_m_axi_data_width g4, g8 c_m_axi_data_width is the same as c_splb_native_dwidth when c_splb_support_bursts = 1. it is fixed at 32 when c_splb_support_bursts = 0. g33 c_m_axi_data_width p53, p54, p72 affects the number of bits of read and write data bus and byte enables g34 c_en_err_regs g8 c_m_axi_supports_ threads is valid only when c_splb_support_bursts = 1. i/o signals p3 interrupt - g8, g34 interrupt signal is available only when c_en_err_reg = 1 and c_splb_support_bursts = 1. p6 splb_masterid[0:c_splb_mid_width - 1] - g6 width of the splb_mastedid varies according to c_splb_mid_width. p8 splb_be[0 : (c_spl b_dwidth/8) -1] - g3 width of the splb_be varies according to c_splb_dwidth p11 splb_wrdbus[0 : c_splb_dwidth - 1] - g3 width of the splb_wrdbus varies according to c_splb_dwidth. ta bl e 3 : parameter-i/o signal dependencies (cont?d) generic or port name affects depends relationship description
DS711 july 25, 2012 www.xilinx.com 16 product specification logicore ip plbv46 to axi bridge (v2.01.a) design details clocking the plbv46 to axi bridge is a synchronous design and uses the plb clock at both plb and axi interfaces. reset splb_rst is synchronous reset input that rese ts the bridge upon assertion. the splb_rst is also used to reset axi interface. byte invariance axi is little endian and plb is big endian. the plbv46 to axi bridge maintains byte invariance, or using xilinx ip terminology, byte addressing integrity is maintained for both 32 and 64-bit width data in the bridge design when c_en_byte_swap = 1. this means that a 32/64-bit data from any address on the plbv46 bus has the bytes swapped in traversing the bridge so th at byte data of byte lanes of the sa me numerical address offsets yields the same byte data when read from the little endian axi side or by a remote master on the big endian plb side. for byte transactions, any byte addressed data read from the axi side or the plb side yields the same byte of data. write strobe signals from the axi master port are similarly swapped. byte and strobe swapping are shown in figure 2 for 32-bit data width on plb and axi (c_splb_native_dwidt h = 32). when c_en_byte_swap = 0, no bytes are swapped. p20 sl_rddbus[0 : c_splb_dwidth - 1] - g3 width of the sl_rddbus varies according to c_splb_dwidth p23 sl_mbusy[0 : c_splb_num_masters - 1] - g7 width of the sl_mbusy varies according to c_splb_num_masters. p24 sl_mwrerr[0 : c_splb_ num_masters - 1] - g7 width of the sl_mwrerr varies according to c_splb_num_masters. p25 sl_mrderr[0 : c_splb_ num_masters - 1] - g7 width of the sl_mrderr varies according to c_splb_num_masters p53 m_axi_wdata[c_m_axi_data_width -1 : 0] - g33 width of the m_axi_wdata varies according to c_m_axi_data_width p54 m_axi_wstrb[(c_m_axi_data_width/8) -1 : 0] - g33 width of the m_axi_wstrb varies according to c_m_axi_data_width. p72 m_axi_rdata[c_m_axi_data_width -1 : 0] - g33 width of the m_axi_rdata varies according to c_m_axi_data_width. ta bl e 3 : parameter-i/o signal dependencies (cont?d) generic or port name affects depends relationship description
DS711 july 25, 2012 www.xilinx.com 17 product specification logicore ip plbv46 to axi bridge (v2.01.a) for the axi slaves having a mixed address space for regi sters and memory require byte swapping for the memory address regions and do not require the byte swapping for register address regions. to address this, the parameter c_nbs_num_addr_rngs must be set based on the number of no byte swap address regions in the given address space. the corresponding no byte swap region base and high addresses must be set to the parameters c_nbs_rngx_baseaddr an d c_nbs_rngx_ highaddr. though the parameter c_en_byteswap is ?1? for the transa ctions in these no byte sw ap address ranges, the byte swapping is not applicable. when c_en_byte_swap =0 for the entire address space irrespective of c_nbs_num_addr_rngs, byte swapping is not applicable. the following table 4 shows the data bits swap and table 5 shows byte enables swap from plb to axi for different values of c_en_byte_swap when c_nbs_num_addr_rngs=0. when c_en_byte_swap=1 and c_nbs_num_addr _rngs/=0, then the data transactions in c_nbs_rngx_baseaddr and c_ nbs_rngx_highaddr regions are same as given in table 4 and table 5 when c_en_byte_swap=0. . ta bl e 4 : data bits swap from plb to axi when c_splb_native_dwidth = 32 plb data bits axi data bits when c_en_byte_swap = 1 axi data bits when c_en_byte_swap = 0 d0 - d7 d7 - d0 d31 - d24 d8 - d15 d15 - d8 d23 - d16 d16- d23 d23 - d16 d15 - d8 d24 - d31 d31 - d24 d7 - d0 ta bl e 5 : byte enables swap from plb to write strobes on axi when c_splb_native_dwidth = 32 plb byte enables axi write strobes when c_en_byte_swap = 1 axi write strobes when c_en_byte_swap = 0 be0 wstrb0 wstrb3 be1 wstrb1 wstrb2 be2 wstrb2 wstrb1 be3 wstrb3 wstrb0 x-ref target - figure 2 figure 2: byte data swap and wrstrb swap to bes as data traverses the plbv46 to axi bridge !8) sidelittleendian bitword .isbyteaddressoffset !8) sidelittleendian bit7342" 0," sidebigendian bitenable 0," sidebigendian bitword .isbyteaddressoffset $3?
DS711 july 25, 2012 www.xilinx.com 18 product specification logicore ip plbv46 to axi bridge (v2.01.a) memory mapping the axi memory map and the plb memory map are one sing le complete 32-bit (4 gb) memory space. the plbv46 slave module in the bridge does not modify the address for axi; hence, the address that is presented on the axi is exactly as received on the plb when c_splb_rngs_offset is set to ?0x00000000?. address decoding address decoding is required in a shared bus interco nnect scheme when c_splb_p2p = 0. in a point to point configuration (c_splb_p2p = 1), there is only one plb ma ster that communicates with the plbv46 to axi bridge. so the bridge responds to all addresses regardless of the address and the plb slave module might be able to reduce resource utilization by eliminating the address decode function and modifying interface behavior to allow for a reduction in latency. in a shared bus topology (c_splb_p2p = 0), the plbv46 to axi bridge decodes the address presented on the address bus. relationships between the write axi channels as the relationship between the address, write data, and write response channels is flexible on axi, the plbv46 to axi bridge issues the write address independent of write data and vice versa. read ordering when c_splb_support_bursts = 1 and c_m_axi_supports_threads = 1, the plbv46 to axi bridge issues the reads on axi with different read transf er id values. the transfers that are requested on splb_savalid are sent on axi with different m_axi_arid . the read reordering depth is 2 and read data interleaving is supported among these transfers. the out-of-order read completion on axi is supported by storing the read data. the axi read slave error is not sent on plb (on sl_mrderr ) for the reads that are completed out of order on axi. when c_m_axi_supports_threads is set to 0, the ax i master module issues the reads with same read transfer id values so that they are received in order. when c_splb_support_bursts = 0, only plb single read transfers are supported and ids are not used. write ordering when c_splb_support_bursts = 1 and c_m_axi_supports_threads = 1, the plbv46 to axi bridge issues write transactions with different transfer id values where the data or dering depth is 2 and allows the write responses in out-of-order. the transfers that are requested on splb_savalid are sent on axi with different m_axi_wid . however the bridge issues the data of write transaction in the same order in which it issues the transaction addresses as the plb sends the write data in order. when c_m_axi_supports_threads is set to 0, the axi master module issues the writes with same write transfer id values so that they are received in order. the write error response is not sent on plb (on sl_mwrerr ) as the write data acknowledge is sent on plb before the data is sent on axi. the user has to enable the error registers (set c_en_err _regs = 1) for such errors. when c_splb_support_bursts = 0, only plb single write transfers are supported and ids are not used.
DS711 july 25, 2012 www.xilinx.com 19 product specification logicore ip plbv46 to axi bridge (v2.01.a) read and write ordering when a read followed by a write (or vice versa) is issued to the same address from the plb, the plbv46 to axi bridge implements an address check against the outstand ing transactions and ensures the transactions are issued and completed in order. when a write followed by write (or read followed by read) to the same address is issued from plb, the plbv46 to axi bridge does not implement the address check against the two addresses and issues these transactions with different id values and assumes that the transactions will complete in order. axi response signaling exokay is considered as okay. protection unit support protection unit support is limited in plbv46 to axi brid ge. privileged and instruction accesses are not supported. all the transactions are normal data a ccesses. either secure or non-secure is selected during configuration by the parameter c_splb_rngx_nonsec_sec . when this is set to 0, m_axi_arprot[1] and m_axi_awprot[1] are set to 0 for address range x (x varies fr om 1 to 4). when this is set to 1, m_axi_arprot[1] & m_axi_awprot[1] are set to 1. when c_splb_p2p = 1, m_axi_arprot[1] and m_axi_awprot[1] are set to ?1? and the remaining bits are set to zero. cache support the bufferable and cacheable transaction attributes of axi transfers are selected by the parameter c_splb_rngx_cacheable_bufferable. assignment of m_axi_awcache and m_axi_arcache for different values of c_splb_rngx_ca cheable_bufferable is shown in table 6 . when c_splb_p2p = 1, m_axi_arcache[3:0] and m_axi_awcache[3:0] are set to zeroes for all the axi requests. bridge error conditions an error on axi results with the response of slverr or decerr . as the bridge supports posted writes and out-of- order reads, these errors cannot be sent on the plb. for this reason the plbv46 to axi bridge implements the optional slave error address register (sear) and slave error status register (sesr). the sesr/sear registers are accessible from the plb and are used for system integratio n and debug or error event logging by a user application. these registers capture the plb request st atus and qualifiers as well as the target address when a read or write transaction generates an error on the axi side. an interrupt signal is driven by the plb slave to the system interrupt controller to report these errors, when interrupts are en abled by using the device global interrupt enable register (dgie) and device interrupt enable register (dier). when both write and read requests on axi generates errors, a write error has more priority than a read error, so the status qualifiers shows the in formation of write request that caused the error. ta bl e 6 : assignment of m_axi_awcache and m_axi_arcache c_splb_rngx_cacheable_bufferable m_axi_awcache[3:0] m_axi_arcache[3:0] 0 ?0000? ?0000? 1 ?0001? ?0001? 2 ?0010? ?0010? 3 ?0011? ?0011?
DS711 july 25, 2012 www.xilinx.com 20 product specification logicore ip plbv46 to axi bridge (v2.01.a) when c_splb_p2p = 0, a bar (base address roll over) error is generated when the plb address overruns the c_splb_rngx_highaddr for rang e x. when c_splb_p2p = 1, a bar error is generated when the plb address overruns 0xffffffff. a bar error is not applicable for single transfers when c_splb_support_bursts = 0. it is the user?s responsibility not to issue burst transfers that cross the plbv 46 to axi bridge?s high address. during such transfers, the plb address is not acknowledged by the bridge and plb_mtimeout is issued by the arbiter after 16 clock cycles. an edge-sensitive interrupt is generated by the bridge if c_en_err_regs is 1 and interrupts are enabled. the sesr register shows the status of the transf er that caused a bar error and the sear shows the address of the transfer. bridge time out condition data phase time out is not implemented inside the brid ge. when a request is issued from the plb, the bridge translates this request into corresponding axi transfer and requests on axi. if this request is not responded by axi, the plbv46 to axi bridge and hence plb waits indefini tely. there is no mechanism implemented inside the plbv46 to axi bridge to come out of this kind of situation. it is assumed that axi responds to all of the axi requests. 4 kb crossing as per the axi specification, bursts must not cross 4 kb boundaries to prevent them from crossing boundaries between slaves and to limit the size of the address increm enter required within slaves. plbv46 to axi bridge takes care of this inside the bridge by splitting the plb burs t transfer into two requests when the plb issues a burst transfer that crossed 4kb boundary. outstanding requests on axi the number of outstanding write /read requests on ax i can be more than 1 when c_splb_support_bursts = 1 and c_m_axi_supports_threads = 1. the read/write transfers that are requested on splb_savalid are requested on axi with a different id and the reordering de pth is 2. therefore, the outstanding read/write request are 2. when a 4 kb crossing is detected in a plb word or double-word burst in both primary and secondary transfers, outstanding write/read requests are 4 (2 for the requests on splb_pavalid and 2 for the requests on splb_savalid ). the following table 7 shows more details on the number of outs tanding requests that are generated on axi depending on the generic combinations. axi4-lite operation when c_splb_support_burst = 0, only single transfers are supported on the plb and the axi4-lite interface is used on axi side. for all the other plb transfers (example : line and burst transfers), the plbv46 to axi bridge does not respond and plb_mtimeout is issued by the arbi ter after 16 clock cycles. ta bl e 7 : outstanding write/read requests c_splb_support_ bursts c_m_axi_support_t hreads c_interconnect_m_axi_ read_issuing/c_interconnect_m_axi_write_issuing 0n a 1 10 2 11 4
DS711 july 25, 2012 www.xilinx.com 21 product specification logicore ip plbv46 to axi bridge (v2.01.a) register descriptions table 8 shows all the plbv46 to axi bridge registers and th eir addresses. these registers are enabled by setting c_en_err_regs to 1. the registers are not used when c_splb_support_burs ts = 0 as no posted writes and out of order reads are supported. slave error status register (sesr) an d slave error address register (sear) the following section details the register descriptions of the sesr and sear. these registers are included only when c_en_err_regs is set to 1. they are used to provide transaction error information to the user application. when these registers are enabled, a base address register (bar) error and slave error or decode error from the axi causes a capture trigger to occur for the sesr and the sear. the sesr captures the plb transa ction qualifiers and the sear captures the plb address for the first offending command. when captured, the data is retained until the user application reads the data from the registers and then rearms the capture mechanism by writing a 0xa0000000 to the sesr address. this write clears the captured information from the sesr and sear. an y other write access to sesr does not generate an error on the plb and has no effect. the assertion of a bar error, slave error or decode error can be used to generate an interrupt to the user application. this requires enabling the device global interrupt enab le register and device interrupt enable register. this interrupt can then be used by the user application to signal the need to service the sesr and sear. when c_en_err_regs is set to 0, the bar error and errors on axi cannot be reported to plb. it is assumed that the user application does not issue transa ctions that generate errors on axi. the sesr is shown in figure 3 and detailed in table 9 . the sear is shown in figure 4 and detailed in table 10 . table 8: plbv46 to axi bridge registers (1) base address + offset (hex) register name access type default value (hex) description c_splb_brdige baseaddr + 0x0 sesr r/w (2) 0x0 slave error status register c_splb_bridge_baseaddr + 0x4 sear r (3) 0x0 slave error address register c_splb_bridge_baseaddr + 0x8 dgie r/w 0x0 device global interrupt enable register c_splb_bridge_baseaddr + 0xc dier r/w 0x 0 device interrupt enable register notes: 1. these registers are included only when c_en_err_regs is set to 1. 2. this register is written with a data value of 0xa0000000 to reset sesr and sear. 3. read only register. writing into this register has no effect. x-ref target - figure 3 figure 3: slave error status register (sesr) $%#%22 3,6%22 "!2 2eserved -)$ 3ize 2.7 $3?
DS711 july 25, 2012 www.xilinx.com 22 product specification logicore ip plbv46 to axi bridge (v2.01.a) table 9: slave error status register (sesr) bit definitions bit(s) name core access reset value description 0-20 reserved n/a 0 reserved 21-23 size r/w (1) ?0000? plb size: this value reflects the splb_size qualifier at the time of error capture.see ibm plb specification for splb_size description. 24-27 mid r/w (1) ?0000? plb master id: this value reflects the splb_masterid qualifier at the time of error capture. see ibm plb specification for splb_masterid description. 28 rnw r/w (1) ?0? plb rnw: this bit reflects the state of the splb_rnw signal at the time of the error capture. ?0? = write command. ?1? = read command. 29 bar r/w (1) ?0? bar error: (2)(3) this bit is asserted when a plb address overruns the address range of the bridge. ?0? = no bar error asserted. ?1? = bar error asserted. 30 decerr r/w (1) ?0? decode error: this bit is asserted when a decode error (decerr) is received from the axi interconnect component. this indicate s that there is no slave at the transaction address. ?0? = no decode error asserted. ?1? = decode error asserted. 31 slverr r/w (1) ?0? slave error: this bit is asserted whenever a slave error (slverr) is received from the axi slave. this indicates that the access has reached the axi slave successfully, but the slave wishes to return an error condition. ?0? = no slave error asserted. ?1? = slave error asserted. notes: 1. this register is cleared by the user application through a system reset or a write to the sesr address with a data value of 0xa0000000. 2. during a bar error, the plbv46 to axi bridge does not send address acknowledge due to which plb_mtimeout is asserted by arbiter. this transfer is not sent on axi. 3. a bar error is applicable for only burst transfers. this bit is always zero when c_splb_support_bursts = 0. x-ref target - figure 4 figure 4: slave error address register (sear) !ddress $3?
DS711 july 25, 2012 www.xilinx.com 23 product specification logicore ip plbv46 to axi bridge (v2.01.a) device global interrupt enable register (dgie) the device global interrupt enable register provides the final enable/disable for the interrupt output and resides in the register and interrupt module. it is a read/write register addressed at an offset 0x8 from base address c_splb_bridge_baseaddr. if interrupts are globally disabled (the dgie bit is set to ?0?), there is no interrupt from the bridge under any circumstances. this is a single bit read/write register as shown in figure 5 . ta ble 11 shows the dgie bit definitions. device interrupt enable register (dier) the device interrupt enable register (dier) is shown in figure 6 . it is a read/write regis ter addressed at an offset 0xc from base address c_splb_bridge_baseaddr. the bit definitions of this register are as shown in table 12 . the device global interrupt enable register provides th e final enable/disable for the interrupt output to the processor and resides in the register and interrupt module. ta bl e 1 0 : slave error address register (sear) bit definitions bit(s) name core access reset value description 0-31 address (0 to 31) r [1] zeros transaction address(0-31): this value reflects the plb address (0 to 31) qualifier at the time of error capture. if the plb address bus is wider than 32 bits, this register contains the least sign ificant 32-bit slice of the address. notes: 1. this register is cleared by the user application through a rese t or a write to the sesr address with a data value of 0xa00000 00. x-ref target - figure 5 figure 5: device global interrupt enable register (dgie) ta bl e 1 1 : device global interrupt enable register (dgie) bit definitions bit(s) name core access reset value description 0 to 30 unused n/a 0 unused 31 dgie read/write ?0? device global interrupt enable: master enable for routing device interrupt to the system interrupt controller. ?1? = enabled ?0? = disabled x-ref target - figure 6 figure 6: device interrupt enab le register (dier) 5nused $')% $3? 5nused 3)% $)% ")% $3?
DS711 july 25, 2012 www.xilinx.com 24 product specification logicore ip plbv46 to axi bridge (v2.01.a) bridge transaction translation table 13 shows translation of plbv46 transaction to axi transactions. for one plb transaction, two axi transactions must be requested when a 4 kb cross is de tected in a plb transfer. ax i allows wrap type burst transactions of 2, 4, 8, and 16 words; however, plb only supports 4, 8 word line transactions. when c_splb_native_dwidth = 64, the m_axi_data_width is set to 64, and a 32-bit plb master request of a word burst of length 16 is sent on ax i as a incr burst transfer of length 16 with a burst si ze 4 bytes in transfer (as a narrow transfer). when c_splb_native_dwidth = 32, the m_axi_data_width is set to 32 and a 64-bit plb master request of a double word burst of length 16 is sent on axi as a incr burst transfer of burst length 32 with a burst size 4 bytes as the maximum burst length supported on axi4 is 256. ta bl e 1 2 : device interrupt enable register (dier) bit definitions bit(s) name core access reset value description 0 to 30 unused n/a 0 unused 29 bie (1) read/write ?0? bar interrupt enable: interrupt enable bit for routing bar error to the s ystem interrupt controller. ?1? = interrupt asserts in response to bar error ?0? = interrupt does not assert in response to bar error 30 die read/write ?0? decerr interr upt enable: interrupt enable bit for routing decode error to the system interrupt controller. ?1? = interrupt asserts in response to decerr ?0? = interrupt does not assert in response to decerr 31 sie read/write ?0? slverr interrupt enable: interrupt enable bit for routing slave error to the system interrupt controller. ?1? = interrupt asserts in response to slverr ?0? = interrupt does not assert in response to slverr notes: 1. bar error is applicable for only burst transfers. th is bit is not used when c_splb_support_bursts = 0. ta bl e 1 3 : plb transaction to axi transaction plb transaction axi transaction description single read or write of 1 to 4 bytes on a 32-bit plb burst read or write of incr type with burst length as 1. when plb issues a single read with 1/2/3 bytes enabled, axi issues it as incr burst with burst length 1 and burst size 2 (number of bytes as 4) and controls strobes during writes and discards the unused bytes during read. single read or write of 1 to 8 bytes on a 64-bit plb burst read or write of incr type with burst length as 1. when plb issues a single read with 1 to 7 bytes enabled, axi issues it as incr burst with burst length 1 and burst size 3(number of bytes as 8) and controls strobes during writes and discards the unused bytes during read
DS711 july 25, 2012 www.xilinx.com 25 product specification logicore ip plbv46 to axi bridge (v2.01.a) timing diagrams the following timing diagrams illustrate the plbv 46 to axi bridge operation for various read and write transfers. ? plb single write transfer is shown in figure 7 . ? plb single read transfer is shown in figure 8 . ? plb 4 word line write transfer are shown in figure 9 . ? plb 8 word line read transfers are shown in figure 10 . ? plb burst write of length 15 transfer are shown in figure 11 . ? plb burst read of length 16 transfer are shown in figure 12 . ? plb burst write of length 10 that crosses 4 kb boundary is shown in figure 13 . one plb transfer is split into two transfers on axi as 4 kb boundary is crossed. ? plb burst read of length 10 that crosses 4 kb boundary is shown in figure 14 . one plb transfer is split into two transfers on axi as 4 kb boundary is crossed. ? plb back to back read and write transfers are shown in figure 15 . ? plb single write and read transfer to the plbv46 to axi bridge register dgie is shown in figure 16 . 4 word cacheline read or write burst read or write of wrap type with burst length as 4. axi is always target word first. 8 word cacheline read or write burst read or write of wrap type with burst length as 8 axi is always target word first. word burst read or write of length 2 to 16 burst read or write of incr type with burst length as 2 to 16 respectively. one plb burst transaction is translated to one axi burst transaction. double word burst read or write of length 2 to 16 burst read or write of incr type with burst length as 4 to 32 respectively when the splb_native_dwidth is 32. burst read or write of incr type with burst length as 2 to 16 respectively, when the splb_native_dwidth is 64. one plb burst transaction is translated to one axi burst transactions. word/double word burst read or write that crosses 4kb boundary burst read or write of incr type with burst lengths that depends on the requested address and length of plb transfer. one plb burst transaction is translated to two axi burst transactions. ta bl e 1 3 : plb transaction to axi transaction (cont?d) plb transaction axi transaction description
DS711 july 25, 2012 www.xilinx.com 26 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 7 figure 7: single write transfer
DS711 july 25, 2012 www.xilinx.com 27 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 8 figure 8: single read transfer DS711_08
DS711 july 25, 2012 www.xilinx.com 28 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 9 figure 9: 4 word line write transfer
DS711 july 25, 2012 www.xilinx.com 29 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 10 figure 10: 8 word line read transfer DS711_10
DS711 july 25, 2012 www.xilinx.com 30 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 11 figure 11: burst write transfer of length 15
DS711 july 25, 2012 www.xilinx.com 31 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 12 figure 12: burst read transfer of length 16 DS711_12
DS711 july 25, 2012 www.xilinx.com 32 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 13 figure 13: burst write transfer of length 10 that crosses 4 kb boundary on axi
DS711 july 25, 2012 www.xilinx.com 33 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 14 figure 14: burst read transfer of length 10 that crosses 4 kb boundary on axi DS711_14
DS711 july 25, 2012 www.xilinx.com 34 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 15 figure 15: back-to-back write and read transfers DS711_15
DS711 july 25, 2012 www.xilinx.com 35 product specification logicore ip plbv46 to axi bridge (v2.01.a) x-ref target - figure 16 figure 16: single write and read transfers to plbv46 to axi bridge register (dgie) DS711_16
DS711 july 25, 2012 www.xilinx.com 36 product specification logicore ip plbv46 to axi bridge (v2.01.a) device utilization and performance benchmarks core performance because the plbv46 to axi bridge is a module that can be used with other design pieces in the field programmable gate array (fpga), the resource utiliz ation and timing numbers reported in this section are estimates only. when the plbv46 to axi bridge is combined with other pieces of the fpga design, the utilization of fpga resources and timing of the design will vary from the results reported here. the plbv46 to axi bridge resource utilization benchmar ks for many parameter comb inations are measured with the artix-7 fpga as the target device are shown in ta ble 14 .. 1. artix-7 fpga (xc7a350t-fbg676-3) ta bl e 1 4 : performance and resource utilization benchmarks for artix-7 (1) fpga and zynq-7000 device parameter values (other parameters at default value) device resources performance c_splb_p2p c_splb_native_ dwidth c_splb_dwidth c_splb_support_ bursts c_splb_support_ cacheline c_en_err_regs c_m_axi_supports_ threads c_splbi_num_ addr_rngs c_en_byte_swap c_nbs_num_addr_rngs slices slice flip-flops luts f max (mhz) 1 32 32 0 na na na na 1 0 63 228 214 240 0 32 64 0 na na na 1 0 0 66 292 208 196 0 32 128 0 na na na 1 0 0 64 292 220 198 0 32 32 1 0 0 0 1 1 0 201 545 560 200 0 32 32 1 0 1 0 2 1 0 261 661 656 200 0 32 32 1 1 1 0 3 1 0 296 691 698 200 0 64 64 1 1 1 0 3 1 0 255 800 828 200 0 32 128 1 1 1 1 4 1 0 477 1040 1294 220 0641281 1 11 4 1 0 502 1172 1436 206 0641281 1 11 1 0 0 542 1172 1437 210 0641281 1 10 4 1 2 358 512 673 200 0641281 1 10 1 1 4 376 512 691 175
DS711 july 25, 2012 www.xilinx.com 37 product specification logicore ip plbv46 to axi bridge (v2.01.a) the plbv46 to axi bridge resource utilization benchmar ks for many parameter comb inations are measured with the virtex?-7 fpga as the target device are shown in table 15 . ta bl e 1 5 : performance and resource utilization benchmarks for virtex-7 fpga (xc7v855t-ffg1157-3) parameter values (other parameters at default value) device resources performance c_splb_p2p c_splb_native_ dwidth c_splb_dwidth c_splb_support_ bursts c_splb_support_ cacheline c_en_err_regs c_m_axi_supports_ threads c_splbi_num_ addr_rngs c_en_byte_swap c_nbs_num_addr_rngs slices slice flip-flops luts f max (mhz) 1 32 32 0 na na na na 1 0 63 228 214 250 0 32 64 0 na na na 1 0 0 62 292 208 240 0321280 nanana1 0 0 65 292 206 240 03232 1 0 00 1 1 0 195 545 561 250 03232 1 0 10 2 1 0 212 661 665 210 03232 1 1 10 3 1 0 292 691 696 236 06464 1 1 10 3 1 0 308 800 820 222 0321281 1 11 4 1 0 499 1040 1288 239 0641281 1 11 4 1 0 697 1172 1423 218 0641281 1 11 1 0 0 622 1172 1418 231 0641281 1 10 4 1 2 337 512 666 210 0641281 1 10 1 1 4 323 512 722 200
DS711 july 25, 2012 www.xilinx.com 38 product specification logicore ip plbv46 to axi bridge (v2.01.a) the plbv46 to axi bridge resource utilization benchmar ks for many parameter combinations are measured with the kintex?-7 fpga as the ta rget device are shown in table 16 . 1. kintex-7 (xc7k410t-ffg676-3) ta bl e 1 6 : performance and resource utilization benchmarks for kintex-7 (1) fpga and zynq-7000 device parameter values (other parameters at default value) device resources performance c_splb_p2p c_splb_native_ dwidth c_splb_dwidth c_splb_support_ bursts c_splb_support_ cacheline c_en_err_regs c_m_axi_supports_ threads c_splbi_num_ addr_rngs c_en_byte_swap c_nbs_num_addr_rngs slices slice flip-flops luts f max (mhz) 1 32 32 0 na na na na 1 0 63 228 214 291 0 32 64 0 na na na 1 0 0 62 292 208 233 0321280 nanana1 0 0 65 292 206 236 03232 1 0 00 1 1 0 195 545 561 243 03232 1 0 10 2 1 0 212 661 665 236 03232 1 1 10 3 1 0 292 691 696 219 06464 1 1 10 3 1 0 308 800 820 232 0321281 1 11 4 1 0 499 1040 1288 249 0641281 1 11 4 1 0 697 1172 1423 237 0641281 1 11 1 0 0 622 1172 1418 213 0641281 1 10 4 1 2 337 512 666 210 0641281 1 10 1 1 4 323 512 722 200
DS711 july 25, 2012 www.xilinx.com 39 product specification logicore ip plbv46 to axi bridge (v2.01.a) the plbv46 to axi bridge resource utilization benchmar ks for many parameter comb inations are measured with the virtex-6 fpga as the target device are shown in table 17 . ta bl e 1 7 : performance and resource utilization benchmarks virtex-6 fpga (xc6vlx130t-ff1156-1) parameter values (other parameters at default value) device resources perfor mance c_splb_p2p c_splb_native_ dwidth c_splb_dwidth c_splb_support_ bursts c_splb_support_ cacheline c_en_err_regs c_m_axi_supports_ threads c_splbi_num_ addr_rngs c_en_byte_swap c_nbs_num_addr_rngs slices slice flip-flops luts f max (mhz) 1 32 32 0 na na na na 1 0 74 228 202 210 0 32 64 0 na na na 1 0 0 64 292 207 170 0 32 128 0 na na na 1 0 0 65 292 202 170 0 32 32 1 0 0 0 1 1 0 209 545 570 176 0 32 32 1 0 1 0 2 1 0 271 661 650 185 0 32 32 1 1 1 0 3 1 0 315 691 698 177 0 64 64 1 1 1 0 3 1 0 241 800 820 170 0 32 128 1 1 1 1 4 1 0 530 1040 1280 160 0 64 128 1 1 1 1 4 1 0 561 1172 1462 160 0 64 128 1 1 1 1 1 0 0 542 1172 1424 171 0 64 128 1 1 1 0 4 1 2 261 512 663 160 0 64 128 1 1 1 0 1 1 4 253 512 716 170
DS711 july 25, 2012 www.xilinx.com 40 product specification logicore ip plbv46 to axi bridge (v2.01.a) the plbv46 to axi bridge resource utilization benchmar ks for many parameter comb inations are measured with the spartan?-6 fpga as the target device are shown in table 18 . read latency and plb bandwidth utilization the core is configured for best possible configuratio n for calculation of latenc y and bandwidth utilization. the read latency from address valid ( splb_pavalid ) to first data beat ( sl_rddack ) of plbv46 to axi bridge is as shown in table 19 . ta bl e 1 8 : performance and resource utilization benchmarks spartan-6 fpga (xc6slx100t-fgg900-2) parameter values (other parameters at default value) device resources perfor mance c_splb_p2p c_splb_native_ dwidth c_splb_dwidth c_splb_support_ bursts c_splb_support_ cacheline c_en_err_regs c_m_axi_supports_ threads c_splb_num_ addr_rngs c_en_byte_swap c_nbs_num_addr_rngs slices slice flip-flops luts f max (mhz) 1 32 32 0 na na na na 1 0 69 228 210 100 0 32 64 0 na na na 1 0 0 88 292 212 100 0 32 128 0 na na na 1 0 0 94 292 198 100 0 32 32 1 0 0 0 1 1 0 202 545 546 100 0 32 32 1 0 1 0 2 1 0 223 661 655 100 0 32 32 1 1 1 0 3 1 0 232 691 688 100 0 64 64 1 1 1 0 3 1 0 299 800 786 100 0 32 128 1 1 1 1 4 1 0 367 1040 1264 100 0 64 128 1 1 1 1 4 1 0 490 1172 1407 100 0 64 128 1 1 1 1 1 0 0 498 1172 1351 100 0641281 110 4 1 2 204 512 664 100 0641281 110 1 1 4 225 512 705 100 ta bl e 1 9 : read latency in plb clocks c_splb_support_bursts c_splb_p2p read latency 0 1 3 clocks 0 0 4 clocks 1 1 5 clocks 1 0 6 clocks
DS711 july 25, 2012 www.xilinx.com 41 product specification logicore ip plbv46 to axi bridge (v2.01.a) best case plb bandwidth utilization, is calculated on the plb by issuing back -to-back burst read and write transfers of length 16 and observed in simulation by requesting 1000 transfers, is as shown in table 20 . for improving core performance c_splb_support_bursts and c_m_axi_supports_threads need to be set to 1. support xilinx provides technical support for this logicore? ip product when used as described in the product documentation. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized be yond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . licensing and ordering information this xilinx logicore ip module is provided at no addi tional cost with the xilinx vivado design suite and ise? design suite embedded edition tools under the terms of the xilinx end user license . information about this and other xilinx logicore ip modules is available at the xilinx intellectual property page. for information on pricing and availability of other xilinx logicore modules and software, please contact your local xilinx sales representative . reference documents the following documents contain reference information important to understanding the plbv46 to axi bridge design: 1. amba? axi protocol version: 2.0 specification (arm ihi 0022c) 2. ibm coreconnect 128-bit processor local bus: architecture specification , version 4.6 3. xilinx plbv46 interconnect and interfaces simplifications an d feature subset specification (rev 0.6), august 15, 2006 4. ds768, axi interconnect ip data sheet 5. ds150 , virtex-6 family overview 6. ds160, spartan-6 family overview 7. ds180, 7 series fpgas overview to search for xilinx documentation, go to w ww.xilinx.com/support . ta bl e 2 0 : plb bandwidth utilization transfer type utilization in percentage back to back writes 76% back to back reads 80% back to back reads and writes 146%
DS711 july 25, 2012 www.xilinx.com 42 product specification logicore ip plbv46 to axi bridge (v2.01.a) revision history the following table shows the revision history for this document: notice of disclaimer the information disclosed to you hereunder (the ?materials?) is provided solely for the selectio n and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are made availa ble ?as is? and with al l faults, xilinx hereby disclaims all warranties and conditions, express, implied, or statutory, including but not limited to warranties of merchantability, non-infringement, or fitness for any particular purpose; and (2) xilinx shall not be liable (whether in contra ct or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includ ing your use of the materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffer ed as a result of any action br ought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had b een advised of the possibility of the same. xilinx assumes no obligation to correct any errors contained in the materials or to notify you of updates to the materials or to product specifications. you may not reproduce, mo dify, distribute, or publicly display th e materials without prior written consent. certain products are subject to the terms and conditions of the limited warranties which can be viewed at http://www.xilinx.com/warranty.htm ; ip cores may be subject to warranty and suppo rt terms contained in a license issued to you by xilinx. xilinx products are not desi gned or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability fo r use of xilinx products in critical applications: http://www.xilinx.com/warranty.htm#critapps . date version description of revisions 9/21/10 1.0 initial xilinx release 3/1/11 1.1 updated to v2.00a for the 13.1 release. 6/22/11 2.0 updated for xps v13.2. added support for artix-7, kintex-7, and virtex-7 devices. 1/18/12 3.0 summary of major core changes ? added the support for byte swapping feature for axi slaves having mixed address space for memory and registers. summary of major documentation change ? table 2 design parameters section updated ? byte invariance section is updated ? timing diagrams for write cycles updated ? device utilization and performance tables updated ? added supported software drivers row to ip facts table 07/25/12 3.1 updated for 14.2/201 2.2. added vivado design suite and zynq-7000 information.

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