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data sheet please read the important notice and warnings at the end of this document revision 2.3 www.infineon.com 2016-10-05 eicedriver? 2edn752x / 2edn852x fast, precise, strong and compatible ? highly efficient smps enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast mosfet and gan switching ? 1 ns channel-to-channel propagatio n delay accuracy enables safe use of two channels in parallel ? two independent 5 a channels enab le numerous deployment options ? industry standard packages and pinout ease system-design upgrades the new reference in ruggedness ? 4.2 v and 8 v uvlo (under voltage lock out) option s ensure instant mosfet protection under abnormal conditions ? -10 v control and enable input robust ness delivers crucial safety margin when driving pulse-transformers or driving mosfets in through hole packaging ? 5 a reverse current robustness eliminates th e need for output protection circuitry. typical applications ?server smps ?telecom smps ? dc-to-dc converter ?bricks ? power tools ?industrial smps ? motor control ?solar smps example topologies ? single and interleaved pfc ? llc, zvs with pulse transformer ? synchronous rectification description the 2edn752x/2edn852x is an advanced du al-channel driver. it is suited to drive logic and normal level mosfets and supports optimos tm , coolmos tm , standard level mosfets, superjunct ion mosfets, as well as igbts and gan power devices. the control and enable inputs are lv-ttl compatible (cmo s 3.3 v) with an input voltage range from -5 v to +20 v. -10 v input pin robustness protects the driver against latch-up or electrical overstress which can be induced by parasitic ground inductances. this greatly enhances system stability.
data sheet 2 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x 4.2 v and 8 v uvlo (under voltage lo ck out) options ensure instant mosf et and gan protection under abnormal conditions. under such circumstances, this uvlo mech anism provides crucial inde pendence from whether and when other supervisors circuitrie s detect abnormal conditions. each of the two outputs is able to sink and source 5 a currents utilizing a true rail-to-rail stage. this ensures very low on resistance of 0.7 ? up to the positive and 0.55 ? down to the negative rail re spectively. very tight channel to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and sink capability of 10 a. industry leading reverse current robustness elim inates the need for schottky diodes at the outputs and reduces the bill-of-material. the pinout of the 2edn family is compatible with th e industry standard. two different control input options, direct and inverted, offer high flexib ility. three package variants, dso 8-pi n, tssop 8-pin, wson 8-pin, allow optimization of pcb board space usage and thermal characteristics. inb ina from controller 2edn752x / 2edn852x gnd vdd outa c vdd enb outb vdd ena load1 load2 1 2 3 4 5 6 7 8 2 3 4 8 7 6 5 r g1 r g2 m 1 m 2
data sheet 3 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 product versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 undervoltage lockout versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 logic versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 package versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 undervoltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 pg-dso-8-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 pg-tssop-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 pg-wson-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table of contents
data sheet 4 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x product versions 1 product versions the 2edn752x / 2edn852x are available in 2 different logic, 2 different undervoltage lockout and 3 package versions. table 1 product versions package type. uvlo control input part number ic topside marking code pg-dso-8-60 4.2v direct 2edn7524f 2n7524af eicedriv xxhyyww inverted 2EDN7523F 2n7523af eicedriv xxhyyww 8v direct 2edn8524f 2n8524af eicedriv xxhyyww inverted 2edn8523f 2n8523af eicedriv xxhyyww pg-tssop-8-1 4.2v direct 2edn7524r 2n7524 ar_xxx hyyww inverted 2edn7523r 2n7523 ar_xxx hyyww 8v direct 2edn8524r 2n8524 ar_xxx hyyww inverted 2edn8523r 2n8523 ar_xxx hyyww pg-wson-8-1 4.2v direct 2edn7524g 2n7524 ag_xxx hyyww inverted 2edn7523g 2n7523 ag_xxx hyyww
data sheet 5 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x product versions 1.1 undervoltage lockout versions the two undervoltage lockout versio ns are indicated by the variable x in the product version 2edny52x: ? y=7: lower voltage for logic level mosfets (4.2 v) ? y=8: higher voltage for standard and superjunction mosfets (8.0 v) please refer to the functional desc ription section for more details in chapter 4 ( undervoltage lockout (uvlo) ). 1.2 logic versions the 2 logic versions are indicated by the va riable x in the product version 2edny52x: ? x=3: inverting input logic ? x=4: non-inverting / direct input logic the logic relations between inputs, en able pins and outputs are given in table 2 for the inverting and non- inverting version 2ednx523 and 2ednx524. the state of the driving output is de fined by the state of the respective input, if the enable inputs ena and enb are high (or left open). a logic ?low? at an enable input or an undervoltage lockout event, due to low voltage at v dd , causes the respective ou tput to be low too, regardless of the input signal. functional description is shown in chapter 3 ( block diagram ) and chapter 4 ( input configurations ). 1.3 package versions the logic and uvlo versions are available in 3 different packages. ? a standard pg-dso-8- 60 (designated by ?f?) ? a leadless pg-wson-8-1 (designated by ?g?) ? a small pg-tssop-8-1 (designated by ?r?) drawings can be viewed in chapter 8 ( outline dimensions ). table 2 logic table inputs output inverting output standard ena enb ina inb uvlo 1) 1) inactive means that vdd is abov e uvlo threshold voltage and releas e logic to control output stage. active means that uvlo disa ble active the output stages. outa outb outa outb xx x x activel l ll ll x x inactivel l ll hl l x inactiveh l l l hl h x inactivel l hl lh x l inactivel h ll lh x h inactivel l lh hh l l inactiveh h l l hh h l inactivel h hl hh l h inactiveh l l h hh h h inactivel l hh
data sheet 6 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x pin configuration and description 2 pin configuration and description the pin configuration for all input versions of 2edn7524f, 2EDN7523F, 2edn8524f and 2edn8523f in the pg- dso-8-60 package is shown in figure 1 . drawings can be viewed in chapter 8 ( pg-dso-8-60 ). figure 1 pin configuration pg-dso-8-60, top view table 3 pin configuration 2edn7524f, 2EDN7523F, 2edn8524f and 2edn8523f in the pg-dso-8-60 package pin symbol description 1 ena enable input channel a logic input; if ena is high or left open, outa is controlled by ina; ena low causes outa low 2 ina input signal channel a logic input, controlling outa (inverting or non-inverting) 3gnd ground 4 inb input signal channel b logic input, controlling outb (inverting or non-inverting) 5 outb driver output channel b low-impedance output with source and sink capability 6 vdd positive supply voltage operating range 4.5 v/8.6v to 20 v 7 outa driver output channel a low-impedance output with source and sink capability 8 enb enable input channel b logic input; if enb is high or left open, outb is controlled by inb; enb low causes outb low 1 2 3 4 8 7 6 5 ena ina gnd inb enb outa vdd outb
data sheet 7 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x pin configuration and description the pin configuration for all input versions of 2edn7524r, 2edn 7523r, 2edn8524r and 2edn8523r in the pg- tssop-8-1 packag e is shown in figure 2 . drawings can be viewed in chapter 8 ( pg-tssop-8-1 ). figure 2 pin configuration pg-tssop-8-1, top view table 4 pin configuration 2edn 7524r, 2edn7523r, 2edn 8524r and 2edn8523r in the pg-tssop-8-1 package pin symbol description 1 ena enable input channel a logic input; if ena is high or left open, outa is controlled by ina; ena low causes outa low 2 ina input signal channel a logic input, controlling outa (non-inverting) 3gnd ground 1) 1) exposed pad sink of pg-tssop-8-1 pack ages has to be connected to gnd pin. 4 inb input signal channel b logic input, controlling outb (non-inverting) 5 outb driver output channel b low-impedance output with source and sink capability 6 vdd positive supply voltage operating range 4.5 v/8.6v to 20 v 7 outa driver output channel a low-impedance output with source and sink capability 8 enb enable input channel b logic input; if enb is high or left open, outb is controlled by inb; enb low causes outb low 1 2 3 4 8 7 6 5 enb outa vdd outb gnd ena ina inb exposed pad
data sheet 8 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x pin configuration and description the pin configuration for direct input versions of 2edn7524g and 2edn7523g in the pg-wson-8-1 package is shown in figure 3 . drawings can be viewed in chapter 8 ( pg-wson-8-1 ). figure 3 pin configuration pg-wson-8-1 , top view table 5 pin configuration 2edn7524g and 2edn7523g in the pg-wson-8-1 package pin symbol description 1 ena enable input channel a logic input; if ena is high or left open, outa is controlled by ina; ena low causes outa low 2 ina input signal channel a logic input, controlling outa (non-inverting) 3gnd ground 1) 1)exposed pad of pg-wson-8-1 packages has to be connected to gnd pin. 4 inb input signal channel b logic input, controlling outb (non-inverting) 5 outb driver output channel b low-impedance output with source and sink capability 6 vdd positive supply voltage operating range 4.5 v/8.6v to 20 v 7 outa driver output channel a low-impedance output with source and sink capability 8 enb enable input channel b logic input; if enb is high or left open, outb is controlled by inb; enb low causes outb low 8 7 6 5 enb outa vdd outb gnd ena ina inb 2 3 4 1 exposed pad
data sheet 9 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x block diagram 3 block diagram a simplified functional block diagram for the non-inverted / direct version is given in figure 4 . please refer to the functional description sect ion for more details in chapter 4 . figure 4 block diagram, direct input, pu ll-up/pull-down resistor configuration ina 1 2 6 7 outa uvlo logic a ena vdd inb 8 4 5 logic b enb 3 gnd outb gnd vdd vdd vdd vdd gnd gnd gnd 40 0k 40 0k 10 0k 10 0k
data sheet 10 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x block diagram a simplified functional block diagram for the inverted version is given in figure 5 . please refer to the functional description section for more details in chapter 4 . figure 5 block diagram, inverting input, pull-up/pull-down resistor configuration ina 1 2 6 7 outa uvlo logic a ena vdd inb 8 4 5 logic b enb 3 gnd outb vdd vdd vdd vdd gnd gnd gnd vdd vdd 40 0k 40 0k 40 0k 40 0k
data sheet 11 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x functional description 4 functional description 4.1 introduction the 2edn752x / 2edn852x is a fast dual-c hannel driver for low-side switches. two true rail-to-rail output stages with very low output impedance and high current capabili ty are chosen to ensure highest flexibility and cover a high variety of applications. the focus on robustness at the input and output side addi tionally gives this device a safety margin in critical abnormal situations. an extended nega tive voltage range protects input pins against ground shifts. no current flows over the esd structure in the ic during a negative input level. all outp uts are robust against reverse current. the interaction with the po wer mosfet, even reverse reflected power will be handled by the strong internal output stage. all inputs are compatible with lv-ttl signal levels. the threshold voltages wi th a typical hysteresis of 1.1 v are kept constant over the supply voltage range. since the 2edn752x / 2edn852x aims partic ularly at fast-switching applications, signal de lays and rise/fall times have been minimized. special effort has been made towards minimizing delay differences between the 2 channels to very low values of typically 1 ns. 4.2 supply voltage the maximum supply voltage is 20 v. th is high voltage can be valuable in order to exploit the full current capability of 2edn752x / 2edn852x wh en driving very large mosfets. th e minimum operating supply voltage is set by the undervoltage lockou t function to a typica l default value of 4.2 v or of 8 v . this lockout function protects power mosfets from running into linear mode with subsequent high power dissipation. 4.3 input configurations as described in chapter 1 , 2edn752x / 2edn852x is available in 2 differen t configurations with respect to the logic configuration of the 4 input pins (input plus enable). the enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left open. the direct pwm inputs are intern ally pulled down to a logic low volt age. this prevents a switch-on event during power up and a not driven input condition. vers ion with inverted pwm input have an internal pull up resistor to prevent unwanted switch-on. all inputs are compatible with lv-ttl levels and provide a hysteresis of 1.1 v typ. this hysteresis is independent of the supply voltage. all input pins have a negative extended voltage range. this prevents cross current over single wires during gnd shifts between signal source (c ontroller) and driver input. 4.4 driver outputs the two rail-to-rail output stages real ized with complementary mos transistors are able to provide a typical 5 a of sourcing and sinking current. this driver output stage has a shoot through protection and current limiting behavior. after a switching event, curr ent limitation is raised up to ac hieve the typical current peak for an excellent fast reaction time of the following power mos transistor. the output impedance is very lo w with a typical value below 0.7 ? for the sourcing p-channel mos and 0.5 ? for the sinking n-channel mos transistor. the use of a p-channel sourcing transistor is crucial for ac hieving true rail- to-rail behaviour and avoiding a source follower?s voltage drop.
data sheet 12 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x functional description gate drive outputs held active low in case of floating inputs enx, inx or during startup or power down once uvlo is not exceeded. under any situation, startup, uvlo or shutdown, outputs are held under defined conditions. 4.5 undervoltage lockout (uvlo) the undervoltage lockout func tion ensures that the output can be switch ed to its high level only if the supply voltage exceeds the uvlo threshold volt age. thus it can be guaranteed, that the switch transistor is not switched on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation. the uvlo level is set to a typical value of 4.2 v / 8 v (with hysteresis). uvlo of 4.2 v is normally used for logic level based mosfets. for higher level, li ke standard and high voltage superjunction mosfets, an uvlo voltage of typical 8 v is available.
data sheet 13 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x characteristics 5 characteristics the absolute maximum ra tings are listed in table 6 . stresses beyond these values may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.1 absolute maximum ratings 5.2 thermal characteristics table 6 absolute maximum ratings parameter symbol values unit note or test condition min. typ. max. positive supply voltage v vdd -0.3 22 v voltage at pins ina, inb, ena, enb v in -10 22 v voltage at pins outa, outb v out -0.3 v vdd +0.3 v note 1) 1) voltage spikes resulting from reverse current peaks are allowed. reverse current peak at pins outa, outb i snkrev i srcrev -5 5 a pk < 500ns junction temperature t j -40 150 c storage temperature t s -55 150 c esd capability v esd 1.5 kv charged device mode (cdm) 2) 2) according to jesd22-c101 esd capability v esd 2.5 kv human body model (hbm) 3) 3) according to jesd22-a114 table 7 thermal characteristics parameter symbol values unit note or test condition min. typ. max. thermal resistance junction- ambient 1) rthja25 125 k/w pg-dso-8-60, t amb =25c thermal resistance junction- case (top) 2) rthjc25 66 k/w pg-dso-8-60, t amb =25c thermal resistance junction- board 3) rthjb25 62 k/w pg-dso-8-60, t amb =25c characterization parameter junction-top 4) thjc25 16 k/w pg-dso-8-60, t amb =25c characterization parameter junction-board 5) thjb25 55 k/w pg-dso-8-60, t amb =25c
data sheet 14 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x characteristics 5.3 operating range thermal resistance junction- ambient 1) rthja25 64 k/w pg-tssop-8-1, t amb =25c thermal resistance junction- case (top) 2) rthjp25 56 k/w pg-tssop-8-1, t amb =25c thermal resistance junction- board 3) rthjb25 55 k/w pg-tssop-8-1, t amb =25c characterization parameter junction-top 4) thjc25 9 k/w pg-tssop-8-1, t amb =25c characterization parameter junction-board 5) thjb25 13 k/w pg-tssop-8-1, t amb =25c thermal resistance junction- ambient 1) rthja25 61 k/w pg-wson-8-1, t amb =25c thermal resistance junction- case (top) 2) rthjp25 54 k/w pg-wson-8-1, t amb =25c thermal resistance junction- board 3) rthjb25 52 k/w pg-wson-8-1, t amb =25c characterization parameter junction-top 4) thjc25 8 k/w pg-wson-8-1, t amb =25c characterization parameter junction-board 5) thjb25 11 k/w pg-wson-8-1, t amb =25c 1) the junction-to-ambient thermal resistance under natura l convection is obtained in a simulation on a jedec- standard, high-k board, as specified in jesd51 -7, in an environment described in jesd51-2a. 2) the junction-to-case (top) thermal resi stance is obtained by simulating a co ld plate test on the package top. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. 3) the junction-to-board thermal resistance is obtained by simu lating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. 4) the characterization parameter junction -top, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining rth, us ing a procedure described in jesd51-2a (sections 6 and 7). 5) the characterization parameter junction -board, estimates the junction temperatur e of a device in a real system and is extracted from the simulation data for obtaining rth, using a procedure described in jesd51-2a (sections 6 and 7). table 8 operating range parameter symbol values unit note or test condition min. typ. max. supply voltage v vdd 4.5 20 v min. defined by uvlo logic input voltage v in -5 20 v junction temperature t j -40 150 c 1) 1) continuous operation above 125 c may reduce life time. table 7 thermal characteristics (continued) parameter symbol values unit note or test condition min. typ. max.
data sheet 15 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x characteristics 5.4 electrical characteristics unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. they are valid within the full operating ra nge. the supply voltage is v vdd = 12 v. typical values are given at t j =25c. table 9 power supply parameter symbol values unit note or test condition min. typ. max. vdd quiescent current i vddqu1 0.5 0.7 1.2 ma out = high, v vdd =12v vdd quiescent current i vddqu2 0.3 0.48 0.7 ma out = low, v vdd =12v table 10 undervoltage lockout for logic level mosfet parameter symbol values uni t note or test condition min. typ. max. undervoltage lockout (uvlo) turn on threshold uvlo on 3.9 4.2 4.5 v undervoltage lockout (uvlo) turn off threshold uvlo off 3.6 3.9 4.2 v uvlo threshold hysteresis uvlo hys 0.3 v table 11 undervoltage lockout for standa rd and superjunction mosfet version parameter symbol values uni t note or test condition min. typ. max. undervoltage lockout (uvlo) turn on threshold uvlo on 7.4 8.0 8.6 v undervoltage lockout (uvlo) turn off threshold uvlo off 6.5 7.0 7.5 v uvlo threshold hysteresis uvlo hys ?1.0?v table 12 logic inputs ina, inb, ena, enb parameter symbol values uni t note or test condition min. typ. max. input voltage threshold for transition lh v inh 1.98 2.1 2.2 v input voltage threshold for transition hl v inl 0.95 1.02 1.1 v input pull up resistor 1) 1) inputs with initial high logic level r inh 400 k ? input pull down resistor 2) 2) inputs with initial low logic level r inl 100 k ?
data sheet 16 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x characteristics table 13 static output caracteristics (see figure 7 ) parameter symbol values unit note or test condition min. typ. max. high level (sourcing) output resistance r onsrc 0.35 0.7 1.2 ? i src = 50ma high level (sourcing) output current i srcpeak 5.0 1) 1) active limited by design at approx. 6.5apk, parameter is not su bject to production test - verified by design / characterization, max. power dissipation must be observed a low level (sinking) output resistance r onsnk 0.28 0.55 1.0 ? i snk = 50ma low level (sinking) output current i snkpeak -5.0 2) 2) active limited by design at approx. -6.5apk, parameter is not subject to pr oduction test - verified by design / characterization, max. power dissipation must be observed a table 14 dynamic characteristics (see figure 6 , figure 7 , figure 8 and figure 9 ) parameter symbol values unit note or test condition min. typ. max. input/enable to output propagation delay t pdlh 15 17 23 ns c load = 1.8 nf, v vdd =12v; low to high transition at input/enable input/enable to output propagation delay t pdhl 15 19 23 ns c load = 1.8 nf, v vdd =12v high to low transition at input/enable input/enable to output propagation delay mismatch between the two channels on the same ic delta t pd 2ns rise time t rise ? 5.3 10 1) 1) parameter verified by design, not 100% tested in production. ns c load = 1.8 nf, v vdd =12v fall time t fall ? 4.5 10 1) ns c load = 1.8 nf, v vdd =12v minimum input pulse width that changes output state t pw ? 6 10 1) ns c load = 1.8 nf, v vdd =12v
data sheet 17 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x timing diagrams 6 timing diagrams figure 6 shows the definition of ri se, fall and delay times for the inputs of the non-inverting / direct version (with enable pin high or open). figure 6 propagation delay, rise and fall time, non-inverted figure 7 shows the definition of rise, fall and delay times fo r the inputs of the inverting version (with enable pins high or open). figure 7 propagation delay, rise and fall time, inverted figure 8 illustrates the undervol tage lockout function. figure 8 uvlo behaviour, input enx and inx drives outx normally high inx out t pdon v in h 90% t pdoff t rise t fal l 10% v in l enx v in h v in l (high) inx v inh v inl out t pdon t pdoff t rise t fal l enx v in h v in l 90% 10% (high) out vdd uvlo on uvlo off
data sheet 18 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x timing diagrams figure 9 illustrates the minimum input pulse width that changes output state. figure 9 tpw, minimum input pulse width that changes output state inx outx v in h 90% v in l enx v in h v in l (high) t pw
data sheet 19 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics 7 typical characteristics figure 10 undervoltage lockout 2ed7x (4.2v) figure 11 undervoltage lockout 2ed8x (8v) 3.7 3.9 4.1 4.3 4.5 -50 0 50 100 150 vdd [v] t junction [c] uvlo on/off vs temperature on value off value inx, enx high indication outx 0.2 0.25 0.3 0.35 0.4 -50 0 50 100 150 vdd delta [v] t junction [c] uvlo hysteresis vs temperature inx, enx high indication outx 6.4 6.8 7.2 7.6 8 8.4 8.8 -50 0 50 100 150 vdd [v] t junction [c] uvlo on/off vs temperature on value off value inx, enx high indication outx 0.85 0.9 0.95 1 1.05 -50 0 50 100 150 vdd delta [v] t junction [c] uvlo hysteresis vs temperature inx, enx high indication outx
data sheet 20 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics figure 12 input (inx) characteristic figure 13 input (enx) characteristic 0.9 1 1.1 1.2 -50 0 50 100 150 vinx delta [v] t junction [c] inx hysteresis vs temperature vdd=12v 0.5 1 1.5 2 2.5 -50 0 50 100 150 vinx [v] t junction [c] input threshold inx to outx vs temperature typ on threshold typ off threshold vdd=12v 0.5 1 1.5 2 2.5 -50 0 50 100 150 venx [v] t junction [c] input threshold enx to outx vs temperature typ on threshold typ off threshold vdd=12v 0.9 1 1.1 1.2 -50 0 50 100 150 venx delta [v] t junction [c] enx hysteresis vs temperature vdd=12v
data sheet 21 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics figure 14 propagation delay (inx) on different input logic levels (see figure 6 ) figure 15 propagation delay (enx) on different input logic levels (see figure 6 ) 12.5 15 17.5 20 22.5 25 -50 0 50 100 150 tpd [ns] t junction [c] vinx to outx propagation delay vs temperature typ input rise-up typ input fall-down vdd=12v input 5v 15 17.5 20 22.5 25 -50 0 50 100 150 tpd [ns] t junction [c] vinx to outx propagation delay vs temperature typ input rise-up typ input fall-down vdd=12v input 3.3v 15 17.5 20 22.5 25 -50 0 50 100 150 tpd [ns] t junction [c] venx to outx propagation delay vs temperature typ input rise-up typ input fall-down vdd=12v enable 5v vdd=12v enable 5v 15 17.5 20 22.5 25 -50 0 50 100 150 tpd [ns] t junction [c] vinx to outx propagation delay vs temperature typ input rise-up typ input fall-down vdd=12v input 3.3v
data sheet 22 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics figure 16 rise / fall times with load on output (see figure 6 ) 3.5 4 4.5 5 5.5 6 6.5 -50 0 50 100 150 ti me [ns ] t junction [c] outx rise/fall time 10% - 90% vs temperature typ turn-on typ turn-off vdd=12v outx with 1.8nf load
data sheet 23 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics figure 17 power consumption related to temperature, supply voltage and frequency 0.2 0.4 0.6 0.8 01020 idd [ma] vdd [v] current consumption vs operating supply vdd outx high outx low tj=25c enx floating (vdd) 0.30 0.40 0.50 0.60 0.70 0.80 -50 0 50 100 150 idd [ma] t junction [c] current consumption vs temperature outx high outx low vdd=12v enx nc 0 10 20 30 40 50 0 250 500 750 1000 i dd [ma] frequency [khz] current consumption vs frequency vdd 4,5v vdd 12v vdd 20v tamb 25c input 50%@3.3v device self-heating load 1.8nf serial
data sheet 24 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x typical characteristics figure 18 output outx with reverse current and resulting power dissipation -7.5 -6.0 -4.5 -3.0 -1.5 -2.25 -2.00 -1.75 -1.50 -1.25 -1.00 -0.75 iout [a ] vout [v] reverse current @outx with outx low vs reverse voltage 10 w 7.5 w 5 w 2.5 w test conditions: tj = 25c, 1s negative pulse fsw = 1khz 0.0 1.5 3.0 4.5 6.0 7.5 0.75 1.00 1.25 1.50 1.75 2.00 iout [a ] vout [v] reverse current @outx with outx high vs reverse voltage 10 w 7.5 w 5 w 2.5 w test conditions: tj = 25c, 1s positive pulse fsw = 1khz
data sheet 25 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x outline dimensions 8 outline dimensions notes 1. for further information on package types, recommendation for board assembly, please go to: http://www.infineon.com/cms/en /product/technology/packages/ . 8.1 pg-dso-8-60 figure 8-1 pg-dso-8-60 outline figure 8-2 pg-dso-8-60 footprint
data sheet 26 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x outline dimensions figure 8-3 pg-dso-8-60 packaging 8.2 pg-tssop-8-1 figure 8-4 pg-tssop-8-1 outline 8 6.4 5.2 0.3 0.3 12 1.75 2.1
data sheet 27 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x outline dimensions figure 8-5 pg-tssop-8-1 footprint figure 8-6 pg-tssop-8-1 packaging
data sheet 28 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x outline dimensions 8.3 pg-wson-8-1 figure 8-7 pg-wson-8-1 outline figure 8-8 pg-wson-8-1 footprint
data sheet 29 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x outline dimensions figure 8-9 pg-wson-8-1 packaging
data sheet 30 revision 2.3 2016-10-05 eicedriver? 2edn752x / 2edn852x revision history , revision 2.3, 2016-10-05 page/ item subjects (major changes since pr evious revision) responsible date updated from version 2.2 25 change all drawings chapter 8 tobias gerber 2016/10/05
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