View BCM20732A0KML2G_8883384.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cyw20732a0 single-chip bluetooth low-energy only soc cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14837 rev. *l revised november 2, 2016 the cypress cyw20732a0 is a bluetooth low-energy (ble)-only soc. the cyw20732a0 radio has been designed to provide low power, low cost, and robust communications for applications operati ng in the globally available 2. 4 ghz unlicensed industrial, s cien- tific, and medical (ism) band. the single-chip ble soc is a monolithic component implemented in a standard digital cmos process and requires minimal external components to make a fully compliant bluetooth device. the cy w20732a0 is available in a 32-pin, 5 mm 5 mm 32-qfn package. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. features bluetooth low-energy (ble)-compliant infrared modulator ir learning supports adaptive frequency hopping excellent receiver sensitivity 10-bit auxiliary adc with nine analog channels on-chip support for serial peripheral interface (master and slave modes) cypress cypressserial control (bsc) interface (compatible with nxp i 2 c slaves) programmable output power control integrated arm co rtex-m3 based microprocessor core on-chip power-on reset (por) support for eeprom and se rial flash interfaces integrated low drop out (ldo) regulator on-chip, software controlled power management unit 32-pin 32-qfn (5 mm 5 mm) package rohs compliant applications the following profiles are supported in rom: battery status blood pressure monitor find me heart rate monitor proximity thermometer weight scale time additional profiles that can be supported from ram include: blood glucose monitor temperature alarm location full qualification and use of th ese profiles may require firmware updates from cypress. some profiles are under development/ approval at bluetooth sig and co nformity with the final approved version is pending. contact your supplier for updates and the latest list of profiles. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number bcm20732 cyw20732 BCM20732A0KML2G cyw20732a0kml2g
document number: 002-14837 rev. *l page 2 of 35 cyw20732a0 figure 1. functional block diagram iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ). processing unit (arm -cm3) system bus bluetooth baseband core 2.4 ghz radio rf control and data t/r switch rf i/o gpio control/ status registers frequency synthesizer 24 mhz ref xtal pmu i/o ring bus i/o ring control registers peripheral interface block 1.2v vdd_core domain vdd_io domain wake 1.2v ldo 1.425v to 3.6v 1.62v to 3.6v 1.2v vdd_core 320k rom 60k ram bsc/spi master interface (bsc is i 2 c- compa ? ble) sda/ mosi scl/ sck high current driver controls 14 gpios 32 khz lpclk 9 adc inputs 24 mhz hclk (24 mhz to 1 mhz) autocal miso 1.2v vdd_rf domain pwm wdt 128 khz lpo 4 32 khz lpclk 128 khz lpclk 32 khz y?o~}??}vo power 1.62v to 3.6v vdd_io 1.2v por 1.2v test uart ir i/o ir mod. and learning spi m/s 3.6v mia por 28 adc inputs ct gp adc vss, vddo, vddc periph uart uart_rxd uart_txd tx rx rts_n cts_n muxed on gpio volt. trans
document number: 002-14837 rev. *l page 3 of 35 cyw20732a0 contents 1. functional description ................................................. 4 1.1 bluetooth baseband core ..................................... 4 1.2 infrared modulator ................................................. 5 1.3 infrared learning ................................................... 5 1.4 adc port ............................................................... 6 1.5 serial peripheral interfac e ..................................... 6 1.6 microprocessor unit .............................................. 7 1.7 integrated radio transceiv er ................................ 8 1.8 peripheral transport unit ...................................... 9 1.9 clock frequencies ............................................... 10 1.10 gpio port .......................................................... 12 1.11 pwm .................................................................. 12 1.12 power management unit ................................... 13 2. pin assignments ........................................................ 15 2.1 pin descriptions .................................................. 15 2.2 ball maps ............................................................. 19 3. specifications ............................................................. 20 3.1 electrical characteristics ..................................... 20 3.2 rf specifications ................................................ 23 3.3 timing and ac characteri stics ............................ 24 3.4 esd test models ................................................ 27 4. mechanical information ............................................. 29 5. ordering information .................................................. 31 a. appendix: acronyms and abbreviations ................ 32 document history .......................................................... 33
document number: 002-14837 rev. *l page 4 of 35 cyw20732a0 1. functional description 1.1 bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time-cri tical functions required for high performance bluetooth operati on. the bbc manages the buffering, segmentation, and data routing for all connections. it al so buffers data that passes through it, handles data flow control, schedules acl tx/rx transactions, monitors bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and compos es and decodes hci packets. in addition to these functions, i t independently handles hci event types and hci command types. the following transmit and receive functions are also implement ed in the bbc hardware to increase tx/rx data reliability and se curity before sending over the air: receive functions: symbol timing recovery, data deframing, forw ard error correction (fec), head er error control (hec), cyclic redundancy check (crc), data decryption, and data dewhitening. transmit functions: data framing, fec generation, hec generation, crc generation, link key generat ion, data encryption, and data whitening. 1.1.1 frequency hopping generator the frequency hopping sequence generator selects the correct ho pping channel number depending on the link controller state, bluetooth clock, and device address. 1.1.2 e0 encryption the encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide minimal processor intervention. 1.1.3 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command controller, which takes softwa re commands, and other controller s that are activated or confi gured by the command controller to perform the link control tasks. each task performs a different bluetooth link controller state. st andby and connection are the two major states. in addition, there ar e five substates: page, page scan, inquiry, and inquiry scan. 1.1.4 adaptive frequency hopping the cyw20732 gathers link quality statistics on a channel-by-channe l basis to facilitate channel assessment and channel map selection. the link quality is determined by using both rf and ba seband signal processing to provide a more accurate frequency hop map. 1.1.5 bluetooth low energy profiles the cyw20732 supports bluetooth low-energy, includi ng the following profiles that are supported 1 in rom: battery status blood pressure monitor find me heart rate monitor proximity thermometer weight scale time the following additional profiles can be supported 1 from ram: blood glucose monitor temperature alarm location custom profile 1. full qualification and use of these profiles may require firmware updates from cypress. some of these profiles are under deve lopment/approval at the bluetooth sig and conformity with the final approved version is pending. contact your supplier for updates and the latest list of profiles.
document number: 002-14837 rev. *l page 5 of 35 cyw20732a0 1.1.6 test mode support the cyw20732 fully supports bluetooth test mode, as described in the bluetooth low energy specification. 1.2 infrared modulator the cyw20732 includes hardware support for infrared tx. the hardware can transmit both modulated and un-modulated waveforms. for modulated waveforms, hardware inserts the desired carrier frequency into all ir transmissions. ir tx can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral uart transmitter. if descriptors are used, they include ir on/off state and the duration between 1 and 32,767 sec. the cyw20732 ir tx firmware driver inserts this information in a hardware fifo and makes sure that all descriptors are played out without a glitch due to u nder run (see figure 2 on page 5 ). figure 2. infrared tx 1.3 infrared learning the cyw20732 includes hardware support for infrared learning. th e hardware can detect both modulated and unmodulated signals. for modulated signals, the cyw20732 can detec t carrier frequencies between 10 khz? 500 khz and the duration that the signal is present or absent. the cyw20732 firmware driver supports furt her analysis and compression of learned signal. the learned signal can then be played back through the cyw20732 ir tx subsystem (see figure 3 ). figure 3. infrared rx
document number: 002-14837 rev. *l page 6 of 35 cyw20732a0 1.4 adc port the cyw20732 contains a 16-bit adc (e ffective number of bits is 10). additionally: there are nine analog input channels in the 32-pin package the following gpios can be used as adc inputs: ? p0 ? p1 ? p8/p33 (select only one) ? p11 ? p12 ? p13/p28 (select only one) ? p14/p38 (select only one) ? p15 ? p32 the conversion time is 10 s. there is a built-in reference with supp ly- or bandgap-based reference modes. the maximum conversion rate is 187 khz. there is a rail-to-rail input swing. the adc consists of an analog adc core t hat performs the actual analog -to-digital conversion and digi tal hardware that processe s the output of the adc core into valid adc output samples. directed by t he firmware, the digital hardware also controls the inpu t multiplexers that select the adc input signal v inp and the adc reference signals v ref . the adc input range is selectable by firmware control: when an input range of 0?3.6v is used, the input impedance is 3 m ? . when an input range of 0?2.4v is used, the input impedance is 1.84 m ? . when an input range of 0?1.2v is used, the input impedance is 680 k ? . adc modes are defined in ta b l e 2 . 1.5 serial peripheral interface the cyw20732 has two independent spi interfaces . one is a master-only interface and the ot her can be either a master or a slave . each interface has a 16-byte transmit buffer and a 16-byte rece ive buffer. to support more flexibility for user applications, t he cyw20732 has optional i/o ports that can be configured individ ually and separately for each functional pin as shown in ta b l e 3 , ta b l e 4 , and table 5 . the cyw20732 acts as a spi master device that s upports 1.8v or 3.3v spi slaves. the cyw20732 can also act as an spi slave device that sup ports a 1.8v or 3.3v spi master. table 2. adc modes mode enob (typical) maximum sampling rate (khz) latency a ( s) a.settling time after switching channels. 0 13 5.859 171 1 12.6 11.7 85 212 46.875 21 3 11.5 93.75 11 410 187 5
document number: 002-14837 rev. *l page 7 of 35 cyw20732a0 1.6 microprocessor unit the cyw20732 microprocessor unit (pu) executes software from th e link control (lc) layer up to the application layer component s. the microprocessor is based on an arm cortex-m3, 32-bit risc processor with embedded ice-rt debug and jtag interface units. the pu has 320 kb of rom for program storage and boot-up, 60 kb of ram for scratch-pad data, and patch ram code. the soc has a total storage of 380 kb, including ram and rom. the internal boot rom provides power-on reset flexibility, whic h enables the same device to be used in different hid applicatio ns with an external serial eeprom or with an extern al serial flash memory. at po wer-up, the lowest layer of the protocol stack is execu ted from the internal rom memory. external patches may be applied to the rom- based firmware to provide flexibility for b ug fixes and feature additions. the devic e can also support the integrati on of user applications. 1.6.1 eeprom interface the cyw20732 provides a cypress serial control (csc) master in terface. bsc is programmed by the cpu to generate four types of bus transfers: read-only, write-only, combined read/write, and co mbined write/read. bsc support s both low-speed and fast mod e devices. bsc is comp atible with an nxp i 2 c slave device, except that ma ster arbitration (multiple i 2 c masters contending for the bus) is not supported. the eeprom can contain customer application configurati on information including application code, config uration data, patches, pairing information, bd_addr, baud rate, sdp service record, and file system information used for code. native support for the microchip 24lc128, microchip 24aa 128, and the stmicroelectronics m24128-br is included. 1.6.2 serial flash interface the cyw20732 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fifos, and the spi core phy logic. table 3. cyw20732 first spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. configured pin name scl sda p24 ? ??p26? ??p32? table 4. cyw20732 second spi set (master mode) pin name spi_clk spi_mosi spi_miso spi_cs a a. any gpio can be used as spi_cs when spi is in master mode. configured pin name p3 p0 p1 ? ?p4p25? p24 p27 ? ? table 5. cyw20732 second spi set (slave mode) pin name spi_clk spi_mosi spi_miso spi_cs configured pin name p3 p0 p1 p2 ?p27?? p24 p33 p25 p26 ???p32
document number: 002-14837 rev. *l page 8 of 35 cyw20732a0 devices natively supported include the following: atmel at25bcm512b mxic mx25v512zui-20g 1.6.3 internal reset figure 4. internal reset timing 1.6.4 external reset the cyw20732 has an integrated power-on reset circuit that complete ly resets all circuits to a known power-on state. an externa l active low reset signal, reset_n, can be used to pu t the cyw20732 in the rese t state. the reset_n pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it . reset_n should only be released after the vddo supply voltage level has been stabilized. figure 5. external reset timing vddo vddo ? por vddc vddo ? por ? threshold vddo ? por ? delay ~ ? 2 ? ms vddc ? por vddc ? por ? threshold vddc ? por ? delay ~ ? 2 ? ms baseband ? reset crystal ? warm \ up ? delay: ? ~ ? 5 ? ms crystal ? enable start ? reading ? eeprom ? and ? firmware ? boot reset_n pulse ? width ? >20 ? s crystal ? enable baseband ? reset start ? reading ? eeprom ? and ? firmware ? boot crystal ? warm \ up ? delay: ? ~ ? 5 ? ms
document number: 002-14837 rev. *l page 9 of 35 cyw20732a0 1.7 integrated radio transceiver the cyw20732 has an integrated radio tran sceiver that is optimized for 2.4 ghz bluetooth wireless systems. it has been designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicens ed ism band. it is fully compliant with blueto oth radio specification 4.0 and meets or e xceeds the requirements to provide the hig hest communication link quality of service. 1.7.1 transmitter path the cyw20732 features a fully integrated transmitter. the baseb and transmit data is gfsk modu lated in the 2.4 ghz ism band. 1.7.2 digital modulator the digital modulator performs the data modulation and filter ing required for the gfsk signal. the fully digital modulator mini mizes any frequency drift or anomalies in the modulati on characteristics of the transmitted signal. 1.7.3 power amplifier the cyw20732 has an integrated power amplifier (pa) t hat can transmit up to +4 dbm for class 2 operation. 1.7.4 receiver path the receiver path uses a low if scheme to downconvert the re ceived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of lin earity, an extended dynamic range, and high-order, on-chip channel filtering to ensure reliable oper ation in the noisy 2.4 ghz ism band. the front- end topology, which has built-in out-of-band at tenuation, enables the cyw20732 to be used in most applications without off-chip filtering. 1.7.5 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 1.7.6 receiver signal strength indicator the radio portion of the cyw20732 provides a receiver signal st rength indicator (rssi) to the baseband. this enables the contro ller to take part in a bluetooth power-controlled link by providing a me tric of its own receiver signal strength to determine whethe r the transmitter should increase or decrease its output power. 1.7.7 local oscillator the local oscillator (lo) provides fast frequency hopping (1 600 hops/second) across the 79 maximum available channels. the cyw20732 uses an internal loop filter. 1.7.8 calibration the cyw20732 radio transceiver features a self-contained automate d calibration scheme. no user interaction is required during normal operation or during manufacturing to provide optimal pe rformance. calibration compensates for filter, matching network, and amplifier gain and phase characteristics to yi eld radio performance within 2% of what is optimal. calibration takes process and temperature variations into account, and it takes place transparently during normal oper ation and hop setting times. 1.7.9 internal ldo regulator the cyw20732 has an integrated 1.2v ldo regulator that provides power to the digital and rf circuits. the 1.2v ldo regulator operates from a 1.425v to 3.63v input supply with a 30 ma maximum load current. note: always place the decoupling capacitors near the pins as closely together as possible. 1.8 peripheral transport unit 1.8.1 cypress serial communications interface the cyw20732 provides a 2-pin master bsc interface, which can be used to retrieve configuration information from an external eeprom or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ics used in mouse devices. the bsc interface is compatible with i 2 c slave devices. the bsc does not support multimaster capability or flexible wait- state insertion by either master or slave devices. the following transfer clock rates are supported by the bsc: 100 khz 400 khz 800 khz (not a standard i 2 c-compatible speed.)
document number: 002-14837 rev. *l page 10 of 35 cyw20732a0 1 mhz (compatibility with high-speed i 2 c-compatible devices is not guaranteed.) the following transfer types are supported by the bsc: read (up to 16 bytes can be read.) write (up to 16 bytes can be written.) read-then-write (up to 16 bytes can be read and up to 16 bytes can be written.) write-then-read (up to 16 bytes can be written and up to 16 bytes can be read.) hardware controls the transfers, requiring minimal firmware setup and supervision. the clock pin (scl) and data pin (sda) are both open-drain i/o pins. pull -up resistors external to the cyw20732 are required on both the scl and sda pins for proper operation. 1.8.2 uart interface the uart is a standard 2-wire interface (rx and tx) and has adjustable baud rates from 9600 bps to 115.2 kbaud. the baud rate can be selected via a vendor-specific uart hci command. the inte rface supports the bluetooth 3.0 uart hci (h4) specification. the default baud rate for h4 is 115.2 kbaud. both high and low baud rates can be supported by running the uart clock at 24 mhz. the cyw20732 uart operates corr ectly with the host uart as long as the combined baud rate error of the two devices is within 5 percent 1.9 clock frequencies the cyw20732 is set with a crystal frequency of 24 mhz. 1.9.1 crystal oscillator the crystal oscillator requires a crystal with an accuracy of 20 ppm as defined by the bluetooth specification. two external l oad capacitors in the range of 5 pf to 30 pf (see figure 6 ) are required to work with the crystal oscillator. the selection of the load capacitors is crystal-dependent. figure 6. recommended oscillator configuration?12 pf load crystal 22 ? pf 20 ? pf crystal xin xout
document number: 002-14837 rev. *l page 11 of 35 cyw20732a0 table 6 shows the recommended crystal specifications. 1.9.2 peripheral block the cyw20732 peripheral blocks all run from a single 128 khz low-po wer rc oscillator. the oscillat or can be turned on at the re quest of any of the peripherals. if the peripheral is not enabled, it shall not assert its clock request line. the keyboard scanner is a special case, in that it may drop it s clock request line even when enabled, and then reassert the clo ck request line if a keypress is detected. 1.9.3 32 khz crystal oscillator figure 7 shows the 32 khz crystal (xtal) osci llator with external components and table 7 on page 11 lists the oscillator?s character- istics. it is a standard pierce oscillator using a comparator wit h hysteresis on the output to create a single-ended digital ou tput. the hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mv. this cir cuit can be operated with a 32 khz or 32.768 khz crystal oscillator or be driven with a clock input at similar frequency. the defaul t component values are: r1 = 10 m ? , c1 = c2 = ~10 pf. the values of c1 and c2 are used to fine-tune the oscillator. figure 7. 32 khz osci llator block diagram table 6. reference crystal electrical specifications parameter conditions minimum typical maximum unit nominal frequency ? ? 24.000 ? mhz oscillation mode ? fundamental ? frequency tolerance @25c ? 10 ? ppm tolerance stability over temp @0c to +70c ? 10 ? ppm equivalent series resistance ? ? ? 60 ? load capacitance ? ? 12 ? pf operating temperature range ? 0 ? +70 c storage temperature range ? ?40 ? +125 c drive level ? ? ? 200 w aging ? ? ? 10 ppm/year shunt capacitance ? ? ? 2 pf table 7. xtal oscillator characteristics parameter symbol conditions minimum typical maximum unit output frequency f oscout ? ? 32.768 ? khz frequency tolerance ? crystal dependent ? 100 ? ppm start-up time t startup ???500ms xtal drive level p drv for crystal selection 0.5 ? ? w c2 c1 r1 32.768 ? khz xtal
document number: 002-14837 rev. *l page 12 of 35 cyw20732a0 1.10 gpio port the cyw20732 has 14 general-purpose i/os (gpios) in the 32-pi n package. all gpios support programmable pull-up and pull-down resistors, and all support a 2 ma drive stre ngth except p26, p27, and p 28, which provide a 16 ma driv e strength at 3.3v supply. the following gpios are available: p0?p4 p8/p33 (dual bonded, only one of two is available.) p11/p27 (dual bonded, only one of two is available.) p12/p26 (dual bonded, only one of two is available.) p13/p28 (dual bonded, only one of two is available.) p14/p38 (dual bonded, only one of two is available.) p15 p24 p25 p32 for a description of all gpios, see table 9 on page 16 . 1.11 pwm the cyw20732 has four internal pwm channels. the pwm module is described as follows: pwm0?3 the following gpios can be mapped as pwms: ? p26 ? p27 ? p14/p28 (dual bonded, only one of two is available.) ? p13 each of the pwm channels, pwm0?3, contains the following registers: ? 10-bit initial value register (read/write) ? 10-bit toggle register (read/write) ? 10-bit pwm counter value register (read) the pwm configuration register is shared among pw m0?3 (read/write). the 12-bit register is used: ? to configure each pwm channel. ? to select the clock of each pwm channel. ? to change the phase of each pwm channel. figure 8 shows the structure of one pwm channel. xtal series resis- tance r series for crystal selection ? ? 70 k ? xtal shunt capaci- tance c shunt for crystal selection ? ? 1.3 pf table 7. xtal oscillator characteristics (cont.) parameter symbol conditions minimum typical maximum unit
document number: 002-14837 rev. *l page 13 of 35 cyw20732a0 figure 8. pwm channel block diagram 1.12 power management unit the power management unit (pmu) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 1.12.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver, which then processes the power-down functions accordingly. 1.12.2 host controller power management power is automatically managed by the firmware based on input dev ice activity. as a power-saving task, the firmware controls th e disabling of the on-chip regulator when in deep sleep mode. pwm_cfg_adr ? register pwm#_init_val_adr ? register pwm#_togg_val_adr ? register pwm#_cntr_adr enable cntr ? value ? is ? cm3 ? readable clk_sel o_flip 10'h000 10'h3ff 10 10 10 example: ? pwm ? cntr ? w/ ? pwm#_init_val ? = ? 0 ? (dashed ? line) pwm ? cntr ? w/ ? pwm#_init_val ? = ? x ? (solid ? line) ?????????????????? 10'hx pwm_out pwm_togg_val_adr pwm_out
document number: 002-14837 rev. *l page 14 of 35 cyw20732a0 1.12.3 bbc power management there are several low-power operations for the bbc: physical layer packet handling turns rf on and off dynamically within packet tx and rx. bluetooth-specified low-power connection mode. while in these low-power connecti on modes, the cyw20732 runs on the low power oscillator (lpo) and wakes up after a predefined time period. the cyw20732 automatically adjusts its pow er dissipation based on user activity. the following power modes are supported: active mode idle mode sleep mode hidoff (deep sleep) mode the cyw20732 transitions to the next lower state after a programm able period of user inactivity. busy mode is immediately enter ed when user activity resumes. in hidoff (deep sleep) mode, the cyw20732 baseband and core are powered off by disabling power to ldoout. the vddo domain remains powered up and will turn the remainder of the chip on when it detects user events. this mode minimizes chip powe r consumption and is intended fo r long periods of inactivity.
document number: 002-14837 rev. *l page 15 of 35 cyw20732a0 2. pin assignments 2.1 pin descriptions table 8. pin descriptions pin number pin name i/o power domain description radio i/o 6 rf i/o vdd_rf rf antenna port rf power supplies 4 vddif i vdd_rf ifpll power supply 5 vddfe i vdd_rf rf front-end supply 7 vddvco i vdd_rf vco, logen supply 8 vddpll i vdd_rf rfpll and crystal oscillator supply power supplies 11 vddc i vddc baseband core supply 28 vddo i vddo i/o pad and core supply 14 vddm i vddm i/o pad supply clock generator and crystal interface 9 xtali i vdd_rf crystal oscillator input. see page 10 for options. 10 xtalo o vdd_rf crystal oscillator output. 1 xtali32k i vddo lpo input is used. alternative function: p11 p27 32 xtalo32k o vddo lpo output. alternative function: p12 p26 core 18 reset_n i/o pu vddo active-low system re set with open-drain output & internal pull-up resistor 17 tmc i vddo test mode control high: test mode connect to gnd if not used. uart 12 uart_rxd i vddm uart serial input ? serial data input for the hci uart interface. leave unconnected if not used. alternative function: gpio3 13 uart_txd o, pu vddm uart serial output ? serial data output for the hci uart interface. leave unconnected if not used. alternative function: gpio2 bsc
document number: 002-14837 rev. *l page 16 of 35 cyw20732a0 15 sda i/o, pu vddm data signal for an external i 2 c device. alternative function: spi_1: mosi (master only) gpio0 cts 16 scl i/o, pu vddm clock signal for an external i 2 c device. alternative function: spi_1: spi_clk (master only) gpio1 rts ldo regulator power supplies 2 ldoin i n/a battery input supply for the ldo 3 ldoout o n/a ldo output table 9. gpio pin descriptions a pin number pin name default di- rection after por state power do- main alternate function description 19 p0 input input floating vddo gpio: p0 a/d converter input peripheral uart: puart_tx spi_2: mosi (master and slave) ir_rx 60hz_main not available during tmc=1 20 p1 input input floating vddo gpio: p1 a/d converter input peripheral uart: puart_rts spi_2: miso (master and slave) ir_tx 21 p3 input input floating vddo gpio: p3 peripheral uart: puart_cts spi_2: spi_clk (master and slave) 22 p2 input input floating vddo gpio: p2 peripheral uart: puart_rx spi_2: spi_cs (slave only) spi_2: spi_mosi (master only) table 8. pin descriptions (cont.) pin number pin name i/o power domain description
document number: 002-14837 rev. *l page 17 of 35 cyw20732a0 23 p4 input input floating vddo gpio: p4 peripheral uart: puart_rx spi_2: mosi (master and slave) ir_tx 24 p8 input input floating vddo gpio: p8 a/d converter input external t/r switch control: ~tx_pd p33 input input floating vddo gpio: p33 a/d converter input spi_2: mosi (slave only) auxiliary clock output: aclk1 peripheral uart: puart_rx 1 p11 input input floating vddo gpio: p11 a/d converter input xtali32k p27 pwm1 input input floating vddo gpio: p27 spi_2: mosi (master and slave) current: 16 ma 32 p12 input input floating vddo gpio: p12 a/d converter input xtalo32k p26 pwm0 input input floating vddo gpio: p26 spi_2: spi_cs (slave only) spi_1: miso (master only) current: 16 ma 29 p13 pwm3 input input floating vddo gpio: p13 a/d converter input p28 pwm2 input input floating vddo gpio: p28 a/d converter input led1 ir_tx current: 16 ma table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por state power do- main alternate function description
document number: 002-14837 rev. *l page 18 of 35 cyw20732a0 30 p14 pwm2 input input floating vddo gpio: p14 a/d converter input p38 input input floating vddo gpio: p38 a/d converter input spi_2: mosi (master and slave) ir_tx 31 p15 input input floating vddo gpio: p15 a/d converter input ir_rx 60 hz_main 27 p24 input input floating vddo gpio: p24 spi_2: spi_clk (master and slave) spi_1: miso (master only) peripheral uart: puart_tx 26 p25 input input floating vddo gpio: p25 spi_2: miso (master and slave) peripheral uart: puart_rx 25 p32 input input floating vddo gpio: p32 a/d converter input spi_2: spi_cs (slave only) spi_1: miso (master only) auxiliary clock output: aclk0 peripheral uart: puart_tx a. during power-on reset, all inputs are disabled. table 9. gpio pin descriptions a (cont.) pin number pin name default di- rection after por state power do- main alternate function description
document number: 002-14837 rev. *l page 19 of 35 cyw20732a0 2.2 ball maps figure 9. 32-pin qfn ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p11/p27/xin32 ldo_in ldo_out vddif vddfe rf vddvco vddpll xtali xtalo vddc uart_rxd uart_txd vddm sda scl tmc rst_n p0 p1 p3 p2 p4 p8/p33 p32 p25 p24 vddo p13/p28 p14/p38 p15 p12/p26/xo32
document number: 002-14837 rev. *l page 20 of 35 cyw20732a0 3. specifications 3.1 electrical characteristics ta b l e 1 0 shows the maximum electrical rating for voltages referenced to vdd pin. ta b l e 11 shows the power supply characteristics for the range t j = 0 to 125c. table 10. maximum electrical rating rating symbol value unit dc supply voltage for rf domain ? 1.4 v dc supply voltage for core domain ? 1.4 v dc supply voltage for vddm domain (uart/i 2 c) ? 3.8 v dc supply voltage for vddo domain ? 3.8 v dc supply voltage for vr3v ? 3.8 v dc supply voltage for vddfe ? 1.4 v voltage on input or output pin ? v ss ? 0.3 to v dd + 0.3 v operating ambient temperature range topr ?30 to +85 c storage temperature range tstg ?40 to +125 c table 11. power supply parameter minimum a a. overall performance degrades beyond minimum and maximum supply voltages. typical maximum a unit dc supply voltage for rf 1.14 1.2 1.26 v dc supply voltage for core 1.14 1.2 1.26 v dc supply voltage for vddm (uart/i 2 c) 1.62 ? 3.63 v dc supply voltage for vddo 1.62 ? 3.63 v dc supply voltage for ldoin 1.425 ? 3.63 v dc supply voltage for vddfe 1.14 1.2 b b. 1.2v for class 2 output with internal vreg. 1.26 v
document number: 002-14837 rev. *l page 21 of 35 cyw20732a0 table 12 shows the digital level characteristics for (vss = 0v). ta b l e 1 3 shows the specifications for the adc characteristics. table 14 shows the specifications fo r the digital voltage levels. table 12. ldo regulator electrical specifications parameter conditions min. typ. max. unit input voltage range ? 1.425 ? 3.63 v default output voltage ? ? 1.2 ? v output voltage range 0.8 ? 1.4 v step size ? 40 or 80 ? mv accuracy at any step ?5 ? +5 % load current ? ? ? 30 ma line regulation vin from 1.425 to 3.63v, i load = 30 ma ?0.2 ? 0.2 %v o /v load regulation i load from 1 a to 30 ma, vin = 3.3v, bonding r = 0.3 ? ?0.10.2%v o /ma quiescent current no load @vin = 3.3v *current limit enabled ?6?a power-down current vin = 3.3v, worst@70c ? 5 200 na table 13. adc specifications parameter symbol conditions min. typ. max. unit number of input channels ? ? ? 9 ? ? channel switching rate f ch ? ? ? 133.33 kch/s input signal range v inp ?0?3.63v reference settling time ? changing refsel 7.5 ? ? ? s input resistance r inp effective, single ended ? 500 ? k ? input capacitance c inp ???5pf conversion rate f c ? 5.859 ? 187 khz conversion time t c ? 5.35 ? 170.7 ? s resolution r ? ? 16 ? bits effective number of bits ? in s pecified performance range ? see table 2 on page 6 ?? absolute voltage measurement error ? using on-chip adc firmware driver ? 2 ? % current i i avdd1p2 + i avdd3p3 ?? 1 ma power p ? ? 1.5 ? mw leakage current i leakage t = 25c ? ? 100 na power-up time t powerup ? ? ? 200 s integral nonlinearity 3 inl in guaranteed performance range ?1 ? 1 lsb a a. lsbs are expressed at the 10-bit level. differential nonlinearity a dnl in guaranteed performance range ?1 ? 1 lsb a
document number: 002-14837 rev. *l page 22 of 35 cyw20732a0 table 15 shows the specifications for current consumption. table 14. digital levels a a. this table is also appl icable to vddmem domain. characteristics symbol min typ max unit input low voltage v il ??0.4v input high voltage v ih 0.75 vddo ? ? v input low voltage (vddo = 1.62v) v il ??0.4v input high voltage (vddo = 1.62v) v ih 1.2 ? ? v output low voltage b b. at the specified drive current for the pad. v ol ??0.4v output high voltage b v oh vddo ? 0.4 ? ? v input capacitance (vddmem domain) c in ?0.12?pf table 15. current consumption a a. currents measured between power terminals (vdd ) using 90% efficient dc-dc converter at 3v. operational mode conditions min typ max unit receive receiver and baseband are both operating, 100% on. ? 9.8 ? ma transmit transmitter and baseband are both operating, 100% on. ? 9.1 ? ma sleep internal lpo is in use. ? 12.0 ? a ? ? 0.65 ?
document number: 002-14837 rev. *l page 23 of 35 cyw20732a0 3.2 rf specifications table 16. receiver rf specifications parameter mode and conditions min typ max unit receiver section a a. 30.8% per. frequency range ? 2402 ? 2480 mhz rx sensitivity (standard) 0.1%ber, 1mbps, dirty transmitter off ? ?93 ? dbm rx sensitivity (low current) ? ?90 ? dbm input ip3 ? ?16 ? ? dbm maximum input ? ?10 ? ? dbm interference performance a , b b. desired signal is 3 db above the reference sensitivity level (defined as ?70 dbm). c/i cochannel 0.1%ber ? ? 21 db c/i 1 mhz adjacent channel 0.1%ber ? ? 15 db c/i 2 mhz adjacent channel 0.1%ber ? ? ?17 db c/i ?? 3 mhz adjacent channel 0.1%ber ? ? ?27 db c/i image channel 0.1%ber ? ? ?9.0 db c/i 1 mhz adjacent to image channel 0.1%ber ? ? ?15 db out-of-band blocking performance (cw) a,b 30 mhz to 2000 mhz 0.1%ber c c. measurement resolution is 10 mhz. ? ?30.0 ? dbm 2003 mhz to 2399 mhz 0.1%ber d d. measurement resolution is 3 mhz. ??35?dbm 2484 mhz to 2997 mhz 0.1%ber d ??35?dbm 3000 mhz to 12.75 ghz 0.1%ber e e. measurement resolution is 25 mhz. ? ?30.0 ? dbm spurious emissions 30 mhz to 1 ghz ? ? ? ?57.0 dbm 1 ghz to 12.75 ghz ? ? ? ?55.0 dbm
document number: 002-14837 rev. *l page 24 of 35 cyw20732a0 3.3 timing and ac characteristics in this section, use th e numbers listed in the reference column of each table to interp ret the following timing diagrams. 3.3.1 uart timing table 17. transmitter rf specifications parameter minimum typical maximum unit transmitter section frequency range 2402 ? 2480 mhz output power adjustment range ?20 ? 4 dbm default output power ? 4.0 ? dbm output power variation ? 2.0 ? db adjacent channel power |m ? n| = 2 ? ? ?20 dbm |m ? n| ?? 3 ? ? ?30 dbm out-of-band spurious emission 30 mhz to 1 ghz ? ? ?36.0 dbm 1 ghz to 12.75 ghz ? ? ?30.0 dbm 1.8 ghz to 1.9 ghz ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ?47.0 dbm lo performance initial carrier frequency tolerance ? ? 150 khz frequency drift frequency drift ? ? 50 khz drift rate ? ? 20 khz/50 s frequency deviation average deviation in payload (sequence used is 0000 1111) 225 ? 275 khz maximum deviation in payload (sequence used is 10101010) 185 ? ? khz channel spacing ? 2 ? mhz table 18. uart timi ng specifications reference characteristics min max unit 1 delay time, uart_cts_n low to ua rt_txd valid ? 24 baud out cycles 2 setup time, uart_cts_n high before midpoint of stop bit ? 10 ns 3 delay time, midpoint of stop bit to uart_rts_n high ? 2 baud out cycles
document number: 002-14837 rev. *l page 25 of 35 cyw20732a0 figure 10. uart timing 3.3.2 spi timing the spi interface supports clock speeds up to 12 mhz with vddio 2.2v. the supported clock spee d is 6 mhz when 2.2v > vddio 1.62v. figure 11 and figure 12 on page 26 show the timing requirements when operating in spi mode 0 and 2, and spi mode 1 and 3, respectively. table 19. spi interface timing specifications reference characteristics min typ max 1 time from csn asserted to first clock edge 1 sck 100 2 master setup time ? ? sck ? 3 master hold time ? sck ? ? 4 slave setup time ? ? sck ? 5 slave hold time ? sck ? ? 6 time from last clock edge to csn deasserted 1 sck 10 sck 100
document number: 002-14837 rev. *l page 26 of 35 cyw20732a0 figure 11. spi timing ? mode 0 and 2 figure 12. spi timing ? mode 1 and 3 3.3.3 bsc interface timing table 20. bsc interface timing specifications reference characteristics min max unit 1 clock frequency ? 100 khz 400 800 1000 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time a 0 ? ns 3 spi_csn spi_clk (mode ? 0) spi_mosi \ first ? bit spi_miso not ? driven first ? bit second ? bit second ? bit last ? bit last ? bit 1 2 6 spi_clk (mode ? 2) not ? driven \ 5 4 3 spi_csn spi_clk (mode ? 1) spi_mosi \ invalid ? bit spi_miso not ? driven invalid ? bit first ? bit first ? bit last ? bit last ? bit 1 2 6 \ not ? driven spi_clk (mode ? 3) 5 4
document number: 002-14837 rev. *l page 27 of 35 cyw20732a0 figure 13. bsc interface timing diagram 7 data input setup time 100 ? ns 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time b 650 ? ns a. as a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of scl to avoid unintended g eneration of start or stop conditions. b. time that the cbus must be free before a new transaction can start. table 20. bsc interface timing specifications reference characteristics min max unit
document number: 002-14837 rev. *l page 28 of 35 cyw20732a0 3.4 esd test models esd can have serious detrim ental effects on all semiconducto r ics and the system that contains them. standards are developed to enhance the quality and reliability of ics by ensuring all devices employed have undergone proper esd design and testing, there by minimizing the detrimental effects of esd. three major test met hods are widely used in the industry today to describe uniform m ethods for assessing esd immunity at component level, human body model (hbm), machine model (mm), and charged device model (cdm). the following standards were used to test this device: 3.4.1 human-body model (hbm) ? ansi/esda/jedec js-001-2012 the hbm has been developed to simulate the action of a human bo dy discharging an accumulated stat ic charge through a device to ground, and employs a series rc network consisting of a 100 pf capacitor and a 1500 ? (ohm) resistor. both positive and negative polarities are used for this test. although, a 100 ms delay is allowable per specification, th e minimum delay used for testing was set to 300 ms between each pulse. 3.4.2 machine model (mm) ? jedec jesd22-a115c the mm has been developed to simulate the rapid discharge from a charged conductive object, such as a metallic tool or fixture. the most common application would be rapid discharge from charged boar d assembly or the charged cables of automated testers. this model consists of a 200 pf capacitor discharged dire ctly into a component with no series resistor (0 ? ). one positive and one negative polarity pulses are applied. the minimum delay between pulses is 500 ms. 3.4.3 charged-device model (cdm) - jedec jesd22-c101e cdm simulates charging/discharging events th at occur in production equipment and proc esses. the potential for a cdm esd events occurs when there is metal-to-metal contact in manufacturing. cdm addresses the possibility that a charge may reside on the lea d frame or package (e.g., from shipping) and discharge through a pin that subsequently is ground ed, causing damage to sensitive devices in the path. discharge current is limited only by the parasitic impedance and capacitance of the device. cdm testing co nsists of charging package to a specified voltage, then discharging the voltage through relev ant package leads. one positive and one negative polarity pulse is applied. the minimum delay between pulses is 200 ms. 3.4.4 results summary esd test voltage level results: hbm +/? 2kv pass cdm +/? 500v pass mm +/? 150v pass
document number: 002-14837 rev. *l page 29 of 35 cyw20732a0 4. mechanical information figure 14. 32-pin 5x5 mm qfn package
document number: 002-14837 rev. *l page 30 of 35 cyw20732a0 ta b l e 2 1 provides dimensions and additional details on the 32-pin 5x5 mm qfn package. 4.0.1 tape reel and packaging specifications the top left corner of the cyw20732 package is si tuated near the sprocket holes, as shown in figure 15 . figure 15. pin 1 orientation table 21. 32-pin 5x5 mm qfn package dimensions (footprint: 0.80) s/n sym dimension comments/sp ecifications 1 a 0.900 0.100 overall height general tolerance: distance: 0.100 angle: 2 a1 0.020 tbd standoff matte finish on package body surface, except ejection and pin 1 marking. ra 0.3 ~ 1.2 m 3 d 5.000 0.100 package length frame base metal thickness 0.203 base 4 e 5.000 0.100 package width all molded body sharp corner radii; unless otherwise specified. r0.200 (maximum) 5 l 0.400 0.075 foot length drawing does not include plastic or metal protrusion of cutting burr. 6 t 0.203 ref. frame thickness compliant to jedec standard: mo-220. 7 b 0.250 0.050 lead width 8 e 0.500 base lead pitch table 22. cyw20732 5 5 1 mm qfn, 32-pin tape reel specifications parameter value quantity per reel 2500 pieces reel diameter 13 inches hub diameter 7 inches tape width 12 mm tape pitch 8 mm pin 1: top left corner of package toward sprocket holes
document number: 002-14837 rev. *l page 31 of 35 cyw20732a0 5. ordering information table 23. ordering information part number package ambient operating temperature cyw20732a0kml2g 32-pin qfn ?30c to +85c
document number: 002-14837 rev. *l page 32 of 35 cyw20732a0 a. appendix: acronyms and abbreviations the following list of acronyms and abbrev iations may appear in this document. term description adc analog-to-digital converter afh adaptive frequency hopping ahb advanced high-performance bus apb advanced peripheral bus apu audio processing unit arm7tdmi-s acorn risc machine 7 thumb instruct ion, debugger, multiplier, ice, synthesizable csc cypress serial control btc bluetooth controller coex coexistence dfu device firmware update dma direct memory access ebi external bus interface hci host control interface hv high voltage idc initial digital calibration if intermediate frequency irq interrupt request jtag joint test action group lcu link control unit ldo low drop-out lhl lean high land lpo low power oscillator lv logicvision mia multiple interface agent pcm pulse code modulation pll phase locked loop pmu power management unit por power-on reset pwm pulse width modulation qd quadrature decoder ram random access memory rf radio frequency rom read-only memory rx/tx receive, transmit spi serial peripheral interface sw software uart universal asynchronous receiver/transmitter upi -processor interface wd watchdog
document number: 002-14837 rev. *l page 33 of 35 cyw20732a0 document history document title: cyw20732a0 single-chip bluetooth low-energy only soc document number: 002-14837 revision ecn orig. of change submission date description of change ** - - 6/27/2011 20732-ds100-r: initial release *a - - 2/24/2012 20732-ds101-r: updated: ? document title changed. ? ?bluetooth low energy features? on page 1. ? table 8: ?gpio pin descriptions,? on page 16. ? table 15: ?receiver rf specifications,? on page 23. ? table 16: ?transmitter rf specifications,? on page 24. ? ?spi timing? on page 25. *b - - 9/17/2012 20732-ds102-r: updated: ? ?preliminary data shee t? to ?data sheet?. ? ?hidoff mode? to ?hidoff (deep sleep) mode?. *c - - 7/10/2013 20732-ds103-r: updated: ? ?bluetooth low energy features? on page 1. ? ?microprocessor unit? on page 07. ? table 9: ?maximum electrical rating,? on page 20 ? table 21: ?ordering information,? on page 31. *d - - 9/17/2013 20732-ds104-r: updated: ? table 14: ?current consumpti on,? on page 22: rx/tx maximum current values. *e - - 10/03/2013 20732-ds105-r: updated: ? table 14: ?current consumption,? on page 22. *f - 12/12/2013 20732-ds106-r: updated: ? table 16: ?transmitter rf specifications,? on page 24 *g - - 3/26/2014 20732-ds107-r: updated: ? figure 14: ?32-pin 5x5 mm qfn package,? on page 30 added: ? table 20: ?32-pin 5x5 mm qfn package dimensions (footprint: 0.80),? on page 30 *h - - 06/05/2014 20732-ds108-r: updated: ? ?uart interface? on page 10. *i - - 11/24/2014 20732-ds109-r: updated: ? table 5: ?reference crystal elec trical specifications,? on page10 *j - - 04/21/2015 20732-ds110-r: updated: ? table15:?receiver rf s pecifications,? on page23
document number: 002-14837 rev. *l page 34 of 35 cyw20732a0 *k - - 02/16/2016 20732-ds111-r: added: ? ?esd test models? on page 27 *l 5448744 utsv 11/02/2016 migrated to cypress template. document title: cyw20732a0 single-chip bluetooth low-energy only soc document number: 002-14837
document number: 002-14837 rev. *l revised november 2, 2016 page 35 of 35 cyw20732a0 ? cypress semiconductor corporation, 2011-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 35

▲Up To Search▲

Price & Availability of BCM20732A0KML2G

	To Download BCM20732A0KML2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .