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| datashee t product structure silicon monolithic integrated circuit this product is not designed protection against radioactive rays . 1/33 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 ? 2014 rohm co., ltd. all rights reserved. www.rohm.com tsz22111 ? 14 ? 001 serial eeprom series standard eeprom i 2 c bus eeprom (2-wire) br24g02-3a general description br24g02-3a is a serial eeprom of i 2 c bus interface method features ? all controls available by 2 ports of serial clock(scl) and serial data(sda) ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 1.6v to 5.5v single power source action most suitable for battery use ? 1mhz action is possible (1.7v to 5.5v) ? up to 8 bytes in page write mode ? self-timed programming cycle ? low current consumption ? prevention of write mistake ? write (write protect) function added ? prevention of write mistake at low voltage ? more than 1 million write cycles ? more than 40 years data retention ? noise filter built in scl / sda terminal ? initial delivery state ffh br24g02-3a capacity bit format type power source voltage package 2kbit 2568 br24g02-3a 1.6v to 5.5v dip-t8 br24g02f-3a sop8 br24g02fj-3a sop-j8 br24g02fvt-3a tssop-b8 br24g02fvj-3a tssop-b8j br24g02fvm-3a msop8 br24g02nux-3a vson008x2030 packages w(typ.) x d(typ.)x h(max.) figure 1. tssop-b8 3.00mm x 6.40mm x 1.20mm msop8 2.90mm x 4.00mm x 0.90mm sop-j8 4.90mm x 6.00mm x 1.65mm sop8 5.00mm x 6.20mm x 1.71mm dip-t8 9.30mm x 6.50mm x 7.10mm tssop-b8j 3.00mm x 4.90mm x 1.10mm v son008x2030 2.00mm x 3.00mm x 0.60mm downloaded from: http:///
2/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 absolute maximum ratings (ta=25 ) parameter symbol ratings unit remarks supply voltage v cc -0.3 to +6.5 v power dissipation pd 450 (sop8) mw when using at ta=25 or higher 4.5mw to be reduced per 1 . 450 (sop-j8) when using at ta=25 or higher 4.5mw to be reduced per 1 . 330 (tssop-b8) when using at ta=25 or higher 3.3mw to be reduced per 1 . 310 (tssop-b8j) when using at ta=25 or higher 3.1mw to be reduced per 1 . 310 (msop8) when using at ta=25 or higher 3.1mw to be reduced per 1 . 300 (vson008x2030) when using at ta=25 or higher 3.0mw to be reduced per 1 . 800 (dip-t8) when using at ta=25 or higher 8.0mw to be reduced per 1 . storage temperature tstg 65 to +150 operation temperature topr 40 to +85 input voltage / output voltage \ -0.3 to vcc+1.0 v the max value of input voltage / ou tput voltage is not over 6.5v. when the pulse width is 50ns or less, the min value of input voltage / output voltage is not under -0.8v. junction temperature tjmax 150 junction temperature at the storage condition electrostatic discharge voltage (human body model) v esd -4000 to +4000 v memory cell characteristics (ta=25 , vcc=1.6v to 5.5v) parameter limits unit min. typ. max write cycles *1 1,000,000 times data retention *1 40 years *1not 100% tested recommended operating ratings parameter symbol ratings unit supply voltage vcc 1.6 to 5.5 v input voltage v in 0 to vcc dc characteristics (unless otherwise specified, ta=-40 to +85 , vcc =1.6 to 5.5v) parameter symbol limits unit conditions min. typ. max. input high voltage1 vih1 0.7vcc vcc+1.0 v 1.7v Q vcc Q 5.5v input low voltage1 vil1 0.3 *1 0.3vcc v 1.7v Q vcc Q 5.5v input high voltage2 vih2 0.8vcc vcc+1.0 v 1.6v Q vcc 1.7v input low voltage2 vil2 0.3 *1 0.2vcc v 1.6v Q vcc 1.7v output low voltage1 vol1 0.4 v iol=3.0ma, 2.5v Q vcc Q 5.5v (sda) output low voltage2 vol2 0.2 v i ol =0.7ma, 1.6v Q vcc 2.5v (sda) input leakage current ili 1 1 a vin=0 to vcc output leakage current ilo 1 1 a vout=0 to vcc (sda) supply current (write) icc1 2.0 ma vcc=5.5v, fscl=1mhz, twr=5ms, byte write, page write supply current (read) icc2 - - 2.0 vcc=5.5v, fscl=1mhz random read, current read, sequential read standby current isb 2.0 a vcc=5.5v, sda, scl=vcc a0, a1, a2=gnd, wp=gnd *1 when the pulse width is 50ns or less, it is -0.8v. downloaded from: http:/// 3/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 ac characteristics (unless otherwise specified, ta= 40 to +85 ) parameter symbol limits (1.6v Q vcc 1.7v) limits (1.7v Q vcc Q 5.5v) unit min. typ. max. min. typ. max. clock frequency fscl - - 400 1000 khz data clock high period thigh 0.6 - - 0.3 s data clock low period tlow 1.2 - - 0.5 s sda, scl (input) rise time *1 tr - - 1 0.12 s sda, scl (input) fall time *1 tf1 - - 1 0.12 s sda (output) fall time *1 tf2 - - 0.12 0.12 s start condition hold time thd:sta 0.6 - - 0.25 s start condition setup time tsu:sta 0.6 - - 0.20 s input data hold time thd:dat 0 - - 0 ns input data setup time tsu:dat 100 - - 50 ns output data delay time tpd 0.1 - 0.9 0.05 0.45 s output data hold time tdh 0.1 - - 0.05 s stop condition setup time tsu:sto 0.6 - - 0.25 s bus free time tbuf 1.2 - - 0.5 s write cycle time twr - - 5 5 ms noise spike width (sda, scl) ti - - 0.05 0.05 s wp hold time thd:wp 1.0 - - 1.0 s wp setup time tsu:wp 0.1 - - 0.1 s wp high period thigh:wp 1.0 - - 1.0 s *1 not 100% tested ac characteristics condition parameter symbol condition unit load capacitance cl 100 pf sda, scl (input) rise time tr 20 ns sda, scl (input) fall time tf1 20 ns input data level vil1/vih1 0.2vcc/0.8vcc v input/output data timing reference level - 0.3vcc/0.7vcc v downloaded from: http:/// 4/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 serial input / output timing figure 2-(e). wp timing at write cancel figure 2-(d). wp timing at write execution figure 2-(c). write cycle timing figure 2-(a). serial input / output timing input read at the rise edge of scl data output in sync with the fall of scl scl sda ( ) sda ( ) tr tf1 thigh tsu:dat tlow thd:dat tdh tpd tbuf thd:sta 70% 30% 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 30% tf2 70% 70% tsu:sta thd:sta tat iti tsu:sto t iti 30% 30% 70% 70% d0 ack twr (n-th address) tat iti t iti 70% 70% data(1) d0 ack d1 data(n) ack twr 30% 70% t iti thd:wp tsu:wp 30% 70% data(1) d0 d1 ack data(n) ack thigh:wp 70% 70% twr 70% (input) (output) figure 2-(b). start-stop bit timing downloaded from: http:/// 5/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 block diagram figure 3. block diagram pin configuration pin descriptions terminal name input/ output function a0 input slave address setting* a1 input slave address setting* a2 input slave address setting* gnd reference voltage of all input / output, 0v sda input/ output serial data input serial data output scl input serial clock input wp input write protect terminal vcc connect the power source. *a0, a1 and a2 are not allowed to use as open. 2kbit eeprom array 8bit 1 br24g02-3a a0 a1 a2 gnd vccwp scl sda 2 3 4 8 7 6 5 8 7 6 5 4 3 2 1 sda scl wp v cc gnd a 2 a1 a0 a ddress decoder word address register data register control circuit high voltage generating circuit power source voltage detection 8bit a ck start stop downloaded from: http:/// 6/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves (the following values are typ. ones) figure 4. input high voltage1,2 vih1,2 (a0, a1, a2, scl, sda, wp) figure 5. input lo w voltage1,2 vil1,2 (a0, a1, a2, scl, sda, wp) figure 6. output low voltage1 vol1 (vcc=2.5v) figure 7. output low voltage2 vol2 (vcc=1.6v) 0 1 2 3 4 5 6 0123456 supply voltage: vcc(v) input low voltage: v il1 (v) t= t= t= spec 0 1 2 3 4 5 6 0123456 su ppl y vol tage: vcc(v) input high voltage: v ih1 (v) t= t= t= spec 0 0.2 0.4 0.6 0.8 1 0123456 l output current: i ol (ma) output low voltage: v ol1 (v) spec t= t= t= 0 0.2 0.4 0.6 0.8 1 0123456 l output current: i ol (ma) output low voltage: v ol2 (v) t= t= t= spec downloaded from: http:/// 7/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves \ continued figure 8. input leakage current ili (a0, a1, a2, scl, wp) figure 9. output leakage current ilo (sda) figure 10. supply current (write) icc1 (fscl=1mhz) figure 11. supply current (read) icc2 (fscl=1mhz) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) input leakage current: i li (a) t= t= t= spec 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) output leakage current: i lo (a) t= t= t= spec 0 0.5 1 1.5 2 2.5 0123456 supply voltage: vcc(v) supply current (write) : icc1(ma) t= t= t= spec 0 0.5 1 1.5 2 2.5 0123456 su ppl y vol tage: vcc(v) supply current (read) : icc2(ma) t= t= t= downloaded from: http:/// 8/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves \ continued figure 12. standby current isb figure 13. clock frequency fscl figure 14. data clock high period thigh figure 15. data clock low period tlow 0.1 1 10 100 1000 10000 0123456 supply voltage: vcc(v) scl frequency: fscl(khz) t= t= t= 0 0.5 1 1.5 2 2.5 0123456 supply voltage: vcc(v) standby current: i sb (a) t= t= t= 0 0.1 0.2 0.3 0.4 0123456 su ppl y vol tage: vcc(v) data clk h time : t high (s) t= t= t= 0 0.1 0.2 0.3 0.4 0.5 0.6 su ppl y vol tage: vcc(v) data clk l time : t low (s) spec t= t= t= downloaded from: http:/// 9/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves \ continued figure 17. start condition hold time thd:sta figure 16. sda (output) fall time tf2 figure 18. start condition setup time tsu:sta figure 19. input data hold time thd:dat(high) 0 0.05 0.1 0.15 0.2 0.25 0.3 supply voltage: vcc(v) start condition hold time: t hd:sta (s) spec t= t= t= 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 supply voltage: vcc(v) sda (output) fall time: t f2 (s) spec t= t= t= -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 supply voltage: vcc(v) start condition setup time: t su:sta (s) t= t= t= -150 -100 -50 0 50 0123456 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec t= t= t= downloaded from: http:/// 10/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves \ continued figure 20. input data hold time thd:dat(low) figure 21. input data setup time tsu:dat(high) figure 22. input data setup time tsu:dat(low) figure 23. l output data delay time tpd0 -150 -100 -50 0 50 0123456 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec t= t= t= 0 10 20 30 40 50 60 0123456 supply voltage: vcc(v) input data set up time: t su:dat (ns) spec t= t= t= 0 10 20 30 40 50 60 0123456 su ppl y vol tage: vcc(v) input data set up time: t su:dat (ns) spec t= t= t= 0 0.1 0.2 0.3 0.4 0.5 0123456 supply voltage: vcc(v) output data delay time: t pd (s) specspec t= t= t= downloaded from: http:/// 11/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 typical performance curves \ continued figure 26. bus free time tbuf figure 24. h output data delay time tpd1 figure 25. stop condition setup time tsu:sto figure 27. write cycle time twr 0 0.1 0.2 0.3 0.4 0.5 0123456 supply voltage: vcc(v) output data delay time: t pd (s) specspec t= t= t= 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) stop condition set up time: t su:sto (s) spec t= t= t= 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage: vcc(v) bus open time before transmission: t buf (s) spec t= t= t= 0 1 2 3 4 5 6 0123456 su ppl y vol tage: vcc(v) internal writing cycle time: t wr (ms) t= t= t= spec downloaded from: http:/// 12/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 figure 31. noise spike width ti (sda l) figure 30. noise spike width ti (sda h) figure 29. noise spike width ti (sc l l) figure 28. noise spike width ti (sc l h) typical performance curves \ continued 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: t i (scl l)(s) spec t= t= t= 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 su ppl y vol tage: vcc(v) noise reduction efective time: t i (scl h)(s) spec t= t= t= 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: t i (sda l)(s) spec t= t= t= 0 0.05 0.1 0.15 0.2 0.25 0.3 0123456 supply voltage: vcc(v) noise reduction efective time: t i (sda h)(s) spec t= t= t= downloaded from: http:/// 13/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 figure 34. wp high time thigh:wp figure 33. wp setup time tsu:wp figure 32. wp hold time thd:wp typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage: vcc(v) wp data hold time: t hd:wp (s) spec t= t= t= -0.3 -0.2 -0.1 0 0.1 0.2 0123456 supply voltage: vcc(v) wp data set up time: t su:w p (s) spec t= t= t= 0 0.2 0.4 0.6 0.8 1 1.2 su ppl y vol tage: vcc(v) wp efective time: t high:wp ( s) t= t= t= downloaded from: http:/// 14/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 timing chart i 2 c bus data communication i 2 c bus data communication starts by start condition input, and en ds by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are master that generates clock and control communication start and end, and slave that is controlled by address peculiar to devices. eeprom becomes slave. and the device that out puts data to bus during data communication is called transmitter, and the device that receives data is called receiver. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefor e, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device ( -com at slave address input of write command, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address in put of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low ' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'low', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detects acknowledge signal (ack signal) 'low'. when acknowledge signal (ack signal) is detected, and stop c ondition is not sent from the master ( -com) side, this ic continues data output. when acknowledge signal (ack signal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are for selecting devices, and plural on es can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write) of slave addr ess is used for designating write or read action, and is as shown below. setting r / w DD to 0 ------- write (setting 0 to word address setting of random read) setting r / w DD to 1 ------- read type slave address maximum number of connected buses br24g02-3a 1 0 1 0 a2 a1 a0 r/ w DD 8 a t a ata ata a tat a a figure 35. data transfer timing downloaded from: http:/// 15/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. up to 8 arbitrary bytes can be written. ? during internal write execution, all input comm ands are ignored, therefore ack is not sent back. ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, data up to 8 bytes can be written in bulk. and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment") ? as for page write cycle of br24g02-3a, after the significant 5 bits of word address are designated arbitrarily, by continuing data input of 2 bytes or mo re, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written. figure 36. byte write cycle figure 37. page write cycle a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w st o p word address data slave address a0 wa 0 d0 a c k sda line ac k ac k a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address ( n ) data(n) slave address a0 wa 0 d0 a c k sda line ac k ac k data ( n+7 ) d0 a c k downloaded from: http:/// 16/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 notes on write cycle continuous input the maximum page numbers of br24g02-3a are 8 by tes. any bytes below these can be written. 1 page=8bytes, but the page write cycle time is 5ms at maximum for 8byte bulk write. it does not stand 5ms at maximum 8byte=40ms(max.) internal address increment page write mode write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addresses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this terminal to vcc or gnd, or control it to h level or l level. do not use it open. in the case of use it as an rom, it is re commended to connect it to pull up or vcc. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. for example, when it is started from address 06h, therefore, increment is made as below, 06h 07h 00h 01h ??? which please note. 06h ??? 06 in hexadecimal, theref ore, 00000110 becomes a binary number. a a a a a a i downloaded from: http:/// 17/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used generally. current read cycle is a command to read data of internal add ress register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, an d stop condition is not sent from master ( -com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ac k signal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycl e, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition w here 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. figure 38. random read cycle figure 40. sequential read cycle (in the case of current read cycle) w r i t e s t a r t r / w ac k s t o p word add ress(n) sd a line a c k a c k data(n) a c k slave address 10 0 1 a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a 1 a2 st a r t d7 r / w re a d wa 0 s t a r t st o p sda line a c k data(n) a c k slave ad dress 10 0 1 a0 a1 a2 d0 d7 r / w r e a d figure 39. current read cycle a t a t a t ata a i a a ata a a a a a a downloaded from: http:/// 18/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 software reset software reset is executed when to avoid malfunction after power on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figure below. (refer to figure 41-(a), figure 41-(b), figure 41-(c)) in dummy clock input area, release the sda bus ('h' by pull up). in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefore, if 'h' is input forcibly, output may conflic t and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignored , therefore ack is not sent ba ck. during internal automatic write execution after write cycle input, next command (slave addr ess) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writing. by us e of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, r/w = 0, when to carry out current read cycle after write, slave address r/w = 1 is sent, and if ack signal sends back 'l', then execute word address input and data output and so forth. figure 41-(a). dummy clock x 14 + start + start + command input start command from start input. figure 41-(b). start + dummy clock x 9 + start + command input 1 2 13 14 scl dummy clock x 14 start x 2 normal command normal command sda scl 2 1 8 9 dummy clock x 9 start start normal command normal command sda figure 41-(c). start x 9 + command input start x 9 scl 1 2 3 8 9 7 normal command normal command sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. twr twr second write command st a r t st a r t s t a r t st a r t s t o p st o p a c k h a c k h a c k l a c k l figure 42. case to continuously write by acknowledge polling downloaded from: http:/// 19/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to c ancel write cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area fr om the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. the area from the rise of scl to take in d0 to input the stop condition is cancel valid area. and, after execution of forced end by wp, standby status gets in. command cancel by start condition and stop condition during command input, by continuously inputting start condition and stop condition, command can be cancelled. ( figure 44 ) however, in ack output area and during data read, sda bus may output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read c ycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. ? rise of d0 taken clock scl d0 ack enlarged view scl sda ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area data is not written. figure 43. wp valid timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address figure 44. case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition enlarged view wp cancel invalid area downloaded from: http:/// 20/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the supply current. maximum value of r pu the maximum value of r pu is determined by the following factors. sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. vcc ilrpu 0.2 vcc vih r pu 0.8v cc v ih i l ex.) vcc =3v il=10 a vih=0.7 vcc from 30 k ? r pu 0.83 0.73 1010 -6 minimum value of r pu the minimum value of r pu is determined by the following factors. when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. volmax=0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. volmax Q vil 0.1 vcc ex.) vcc =3v, vol=0.4v, iol=3ma, microcontroller, eeprom v il =0.3vcc and vol=0.4 v vil=0.3 3 =0.9 v therefore, the condition is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the case there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k to several ten k is recommended in consideration of drive performance of output port of microcontroller. i ol r pu v cc v ol i ol v cc v o l r pu 867 ?? r pu 3 0.4 310 from microcontroller r pu a sda terminal i l i l bus line capacity cbus figure 45. i/o circuit diagram eeprom downloaded from: http:/// 21/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 cautions on microcontroller connection rs in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betwe en the pull up resistance rpu an d the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. sda rise time to be determined by the capacity (cbus) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable cu rrent in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. r pu microcontroller r s eeprom figure 46. i/o circuit diagram figure 47. input / output collision timing a ck 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda microcontroller eeprom 'l'output r s r pu 'h' output over current i figure 49. i/o circuit diagram 1.67 k ? 0.33 0.4 0.13 2010 3 1.13 0.33 r s r pu 1.1v cc -v il ex. v cc =3v v il =0.3v cc v ol =0.4v r pu =20k r s v il v ol 0.1v cc (v cc v ol )r s +v ol +0.1v cc v il r pu +r s v cc r s v cc i 300 ?? = i=a r s 3 1010 -3 i r s r pu micro controller r s eeprom i ol a bus line capacity cbus v ol v cc v il figure 48. i/o circuit diagram downloaded from: http:/// 22/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 i/o equivalence circuit input (a2,a1,a0,scl, wp) input / output (sda) power-up / down conditions at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent th is, functions of por circuit and lvcc circ uit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. toff tr vbot 0 v cc 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p18). ) in the case when the above conditions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and prev ents wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunction ma y occur, therefore, for removi ng these, it is recommended to attach a by pass capacitor (0.1 f) between ic vcc and gnd. at that moment, attach it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. figure 52. rise waveform diagram tlow tsu:dat tdh a fter vcc becomes stable scl v cc sda tsu:dat a fter vcc becomes stable tr toff vbot 10ms or belo w 10ms or larger 0.3v or below 100 or below 10ms or larger 0.2v or below figure 50. input pin circuit diagram figure 51. input / output pin circuit diagram figure 53. when scl= 'h' and sda= 'l' figure 54. when scl='l' and sda='l' downloaded from: http:/// 23/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 operational notes (1) described numeric values and data are design repres entative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluct uations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage an d action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperature exce eding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physical safety co untermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that eac h terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use condi tion, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attention to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shortcircuit between lsi te rminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, ev aluate design sufficiently. downloaded from: http:/// 24/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 part numbering b r 2 4 g 0 2 x x x - 3 a x x x x lineup capacity package orderable part number remark type quantity 2k dip-t8 tube of 2000 br24g02 -3a not halogen free 100% sn sop8 reel of 2500 br24g02f -3agte2 halogen free 100% sn sop-j8 br24g02fj -3agte2 halogen free 100% sn tssop-b8 reel of 3000 br24g02fvt -3age2 halogen free 100% sn tssop-b8j reel of 2500 br24g02fvj -3agte2 halogen free 100% sn msop8 reel of 3000 br24g02fvm -3agttr halogen free 100% sn vson008x2030 reel of 4000 br24g02nux -3attr halogen free 100% sn bus type 24 : i 2 c operating temperature / operating voltage -40 to +85 / 1.6v to 5.5v process code packaging and forming specification e2 : embossed tape and reel (sop8, sop-j8, tssop-b8, tssop-b8j) tr : embossed tape and reel (msop8, vson008x2030) none : tube (dip-t8) revision package blank fj fvj nux : dip-t8 : sop-j8 : tssop-b8j : vson008x2030 f fvt fvm : sop8 : tssop-b8 : msop8 capacity 02=2k g : halogen free blank : not halogen free as an exception, vson008x2030 package will be halogen free with blank t : 100% sn blank : 100% sn downloaded from: http:/// 25/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 physical dimensions tape and reel information ? order quantity needs to be multiple of the minimum quantity. 26/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 ? order quantity needs to be multiple of the minimum quantity. 27/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 ? order quantity needs to be multiple of the minimum quantity. 28/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 29/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 30/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. 31/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 ? order quantity needs to be multiple of the minimum quantity. 32/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 marking diagrams (top view) sop8(top view) 4g02a part number marking lot numbe r 1pin mark sop-j8(top view) 4g02a part number marking lot number 1pin mark tssop-b8j(top view) 2a3 part number marking lot number 1pin mark 4g0 vson008x2030 (top view) 2a3 part number marking lot number 1pin mark 4g0 msop8(top view) 4gb part number marking lot number 1pin mark a tssop-b8(top view) 4g02a part number marking lot numbe r 1pin mark dip-t8 (top view) br24g02a part number marking lot number downloaded from: http:/// 33/33 datasheet datasheet br24g02-3a ? 2014 rohm co., ltd. all rights reserved. www.rohm.co tsz22111 ? 15 ? 001 tsz02201-0r2r0g100570-1-2 27.aug.2014 rev.003 revision history date revision changes 26.dec.2012 001 new release 31.may.2013 002 p1 change format of package line-up table and change title. p.2 add vesd in absolute maximum ratings p.5 add directions in pin descriptions 27.aug.2014 003 p.3 modified tsu:sta (0.25->0.20) p.24 update part numbering. add lineup table downloaded from: http:/// datasheet datasheet notice C ge rev.002 ? 2013 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class | class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used; if flow soldering met hod is preferred, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:/// datasheet datasheet notice C ge rev.002 ? 2013 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under cont rolled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or ot her damages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the information contained in this document. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:/// datasheet datasheet notice C we rev.001 ? 2014 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:/// |
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