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general description the max1970/max1971/max1972 dual-output current-mode pwm buck regulators operate from 2.6v to 5.5v input and deliver a minimum of 750ma on each output. the max1970 and max1972 operate at a fixed 1.4mhz (max1971 operates at 700khz) to reduce output induc- tor and capacitor size and cost. switching the regula- tors 180 out-of-phase also reduces the input capacitor size and cost. ceramic capacitors can be used for input and output. the output voltages are programmable from 1.2v to v in using external feedback resistors, or can be preset to1.8v or 3.3v for output 1 and 1.5v or 2.5v for output 2. when one output is higher than 1.2v, the second can be configured down to sub-1v levels. output accuracy is better than 1% over variations in load, line, and tem- perature. internal soft-start reduces inrush current dur- ing startup. all devices feature power-on reset ( por ). the max1971 includes a reset input (rsi), which forcespor low for 175ms after rsi goes low. the max1970 and max1972 include an open-drain power-fail output(pfo) that monitors input voltage and goes high when the input falls below 3.94v. for usb-powered xdsl modems, this output can be used to detect usb power failure. a minimum switching frequency of 1.2mhz ensures operation outside the xdsl band. applications features ? current-mode, 1.4mhz fixed-frequency pwm operation ? 180 out-of-phase operation reduces input capacitor ? 1% output accuracy over load, line, and temperature ranges ? 750ma guaranteed output current ? 2.6v to 5.5v input ? power-on reset delay of 16.6ms (max1970) or 175ms (max1971 and max1972) ? power-fail output (max1970 and max1972 only) ? power-on reset input (max1971 only) ? operation outside xdsl band ? ultra-compact design with smallest external components ? outputs adjustable from 0.8v to v in or 1.8v/3.3v and 1.5v/2.5v preset ? all-ceramic capacitor application ? soft-start reduces inrush current max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ _____________ maxim integrated products 1 1615 14 13 12 11 10 9 12 34 5 6 7 8 lx1 pgnd lx2in fbsel1 fbsel2 pf0 (max1970/max1972) rsi (max1971) en por top view max1970max1971 max1972 qsop v cc comp1comp2 fb1fb2 ref gnd pin configuration v cc v cc rsien comp1 comp2 fbsel1 fbsel2 ref por por out11.8v 750ma out2 2.5v 750ma rsi lx1fb2 fb1lx2 pgnd in max1971 en v in 2.6v to 5.5v typical operating circuit 19-2297; rev 1; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. xdsl modemsxdsl routers copper gigabit sfp and gbic modules usb-powered devicesdual ldo replacement ordering information part temp range pin-package max1970 eee -40 c to +85 c 16 qsop max1971 eee -40 c to +85 c 16 qsop max1972 eee -40 c to +85 c 16 qsop downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 2 __________________________________________________ _____________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, en, fbsel1, fbsel2, pfo, por , rsi, v cc to gnd ...................................................-0.3v to +6v comp1, comp2, fb1, fb2, ref to gnd .............................................-0.3v to (v cc + 0.3v) lx1, lx2 to pgnd .......................................-0.3v to (v in + 0.3v) pgnd to gnd .......................................................-0.3v to +0.3v continuous power dissipation (t a = +70c) 16-pin qsop (derate 8.3mw/c above +70c)...........667mw operating temperature range ...........................-40c to +85c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c electrical characteristics (v in = v cc = v en = 5v, r por = 100k ? to in, r pfo = 100k ? to in, v rsi = 0, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min typ max units in and v cc in voltage range 2.6 5.5 v max1971 5 10 in supply current switching with no loadv in = 3.3v max1970/max1972 10 20 ma max1970/max1972 1 100 in shutdown current v in = 5.5v, v en = 0 max1971 1 60 a v cc rising 2.40 2.55 v cc undervoltage lockout threshold v cc falling 2.20 2.35 v ref ref voltage i ref = 0, v in = 2.6v to 5.5v 1.188 1.200 1.212 v ref shutdown resistance ref to gnd, v en = 0 10 25 ? ref soft-start current v ref = 1v 20 25 30 a fb1 and fb2 fb_ regulation voltage fbsel_ = unconnected, out1 = fb1, out2 = fb2,v comp_ = 1.20v to 1.80v, v in = 2.6v to 5.5v 1.188 1.200 1.212 v out_ voltage range fbsel_ = unconnected 1.2 v in v v in = 2.6v to 5.5v v comp1 = 1.2v, fbsel1= gnd 1.782 1.800 1.818 out1 regulation voltage v in = 4.5v to 5.5v v comp1 = 1.2v, fbsel1 = v cc 3.2670 3.3 3.330 v v comp2 = 1.2v, fbsel2 = gnd 1.485 1.5 1.150 out2 regulation voltage v in = 2.6v to 5.5v v comp2 = 1.2v, fbsel2 = v cc 2.475 2.5 2.525 v maximum output current guaranteed by design (note 1) 750 ma fbsel1 = gnd 30 60 120 fb1 input resistance measured from fb1 tognd fbsel1 = v cc 30 60 120 k ? fbsel2 = gnd 22.5 45 90 fb2 input resistance measured from fb2 tognd fbsel2 = v cc 22.5 45 90 k ? fb_ input bias current fb1 or fb2, fbsel_ = unconnected, v fb1 = v fb2 = 1.15v 0.01 0.1 a downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ____________________________________ 3 electrical characteristics (continued) (v in = v cc = v en = 5v, r por = 100k ? to in, r pfo = 100k ? to in, v rsi = 0, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min typ max units comp1 and comp2 comp1transconductance fb1 = comp1,v comp1 = 1.2v fbsel1 = unconnected 35 55 85 s comp2transconductance fb2 = comp2,v comp2 = 1.2v fbsel2 = unconnected 35 55 85 s lx1 and lx2 v in = 5.0v 0.20 0.32 v in = 3.3v 0.24 0.37 internal high-sidemosfet on-resistance i lx = -180ma v in =2.6v 0.28 ? v in = 5.0v 0.12 0.23 v in = 3.3v 0.14 0.25 internal low-sidemosfet on-resistance i lx = 180ma v in = 2.6v 0.16 ? lx_ current-sensetransresistance 0.4 0.5 0.6 v/a high side 0.80 1.2 1.60 lx_ current-limitthreshold duty cycle = 100%,v in = 2.6v to 5.5v low side -1.6 -0.85 -0.40 a v lx1 = v lx2 = 5.5v 20 lx_ leakage current v in = 5.5v v lx1 = v lx2 = 0 -20 a max1970/max1972 1.2 1.4 1.6 lx_ switching frequency v in = 2.6v to 5.5v max1971 0.60 0.70 0.80 mhz lx_ maximum duty cycle 100 % max1970/max1972 15 20 lx_ minimum duty cycle v in = 2.6v to 5.5v max1971 10 15 % por v out rising 92 94 por thresholds percentage of v out , v in = 2.6v to 5.5v v out falling 87 90 % max1970 13.3 16.6 20 por delay time (t d ) max1971/max1972 140 175 210 ms por output current, high v por = v in = 5.5v, v fb1 = v fb2 = 1.15v -1 1 a por output voltage, low v fb1 = 1.05v or v fb2 = 1.05v or rsi = in (max1971 only), i por = 1ma 0.01 0.05 v por startup voltage fb1 = fb2 = gnd, i por = 100a, v in = 1.2v 0.01 0.05 v downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 4 __________________________________________________ _____________________________________ electrical characteristics (continued) (v in = v cc = v en = 5v, r por = 100k ? to in, r pfo = 100k ? to in, v rsi = 0, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25c.) parameter conditions min typ max units pfo (max1970 and max1972 only) v cc rising 4.04 4.12 pfo trip threshold in = v cc v cc falling 3.86 3.94 v pfo output current, high pfo = in -1 1 a pfo output voltage, low i pfo = 1ma, v in = 4.3v 0.01 0.05 v en and rsi (max1971 only) v il 0.4 0.95 logic input thresholds in = 2.6v to 5.5v v ih 1.0 1.6 v rsi input resistance internal pullup resistor to in 5 10 20 k ? v il -1 1 en logic input current logic input at 0 or5.5v, v in = 5.5v v ih -1 1 a electrical characteristics (v in = v cc = v en = 5v, v fb1 = v fb2 = 1.15v, r por = 100k ? to in, r pfo = 100k ? to in, rsi = 0, c vcc = 0.1f, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = -40c to +85c. ) (note 2) parameter conditions min typ max units in and v cc in voltage range 2.6 5.5 v max1971 10 in supply current switching with no loadv in = 3.3v max1970/max1972 20 ma max1970/max1972 20 in shutdown current v in = 5.5v, v en = 0 max1971 100 a v cc rising 2.55 v cc undervoltage lockout threshold v cc falling 2.20 v ref ref voltage i ref = 0, v in = 2.6v to 5.5v 1.185 1.212 v ref shutdown resistance ref to gnd, v en =0 25 ? ref soft-start current v ref = 1v 20 30 a fb1 and fb2 fb_ regulation voltage fbsel_ = unconnected, out1 = fb1, out2 = fb2,v comp_ = 1.20v to 1.80v, v in = 2.6v to 5.5v 1.185 1.212 v out_ voltage range fbsel_ = unconnected 1.2 v in v v in = 2.6v to 5.5v v comp1 = 1.2v, fbsel1= gnd 1.778 1.818 out1 regulation voltage v in = 4.5v to 5.5v v comp1 = 1.2v, fbsel1 = v cc 3.259 3.333 v v comp2 = 1.2v, fbsel2 = gnd 1.481 1.515 out2 regulation voltage v in = 2.6v to 5.5v v comp2 = 1.2v, fbsel2 = v cc 2.469 2.525 v maximum output current guaranteed by design (note 1) 750 ma downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ____________________________________ 5 electrical characteristics (continued) (v in = v cc = v en = 5v, v fb1 = v fb2 = 1.15v, r por = 100k ? to in, r pfo = 100k ? to in, rsi = 0, c vcc = 0.1f, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = -40c to +85c. ) (note 2) parameter conditions min typ max units fbsel1 = gnd 30 120 fb1 input resistance measured from fb1 tognd fbsel1 = v cc 30 120 k ? fbsel2 = gnd 22.5 90 fb2 input resistance measured from fb2 tognd fbsel2 = v cc 22.5 90 k ? fb_ input bias current fb1 or fb2, fbsel_ = unconnected, v fb1 = v fb2 = 1.15v 0.1 a comp1 and comp2 comp1transconductance fb1 = comp1,v comp1 = 1.2v fbsel1 = unconnected 35 85 s comp2transconductance fb2 = comp2,v comp2 = 1.2v fbsel2 = unconnected 35 85 s lx1 and lx2 v in = 5.0v 0.32 internal high-sidemosfet on-resistance i lx = -180ma v in = 3.3v 0.37 ? v in = 5.0v 0.23 internal low-sidemosfet on-resistance i lx = 180ma v in = 3.3v 0.25 ? lx_ current-sensetransresistance 0.4 0.6 v/a high side 0.76 1.60 lx_ current-limitthreshold duty cycle = 100%,v in = 2.6v to 5.5v low side -1.6 -0.40 a v lx1 = v lx2 = 5.5v 20 lx_ leakage current v in = 5.5v v lx1 = v lx2 = 0 -20 a max1970/max1972 1.2 1.6 lx_ switching frequency v in = 2.6v to 5.5v max1971 0.60 0.80 mhz max1970/max1972 20 lx_ minimum duty cycle v in = 2.6v to 5.5v max1971 15 % por v out rising 94 por thresholds percentage of v out , v in = 2.6v to 5.5v v out falling 87 % max1970 13.3 20 por delay time (t d ) max1971/max1972 140 210 ms por output current, high v por = v in = 5.5v, v fb1 = v fb2 = 1.15v -1 1 a por output voltage, low v fb1 = 1.05v or v fb2 = 1.05v or rsi = in (max1971 only), i por = 1ma 0.05 v por start-up voltage fb1 = fb2 = gnd, i por = 100a, v in = 1.2v 0.05 v downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 6 __________________________________________________ _____________________________________ electrical characteristics (continued) (v in = v cc = v en = 5v, v fb1 = v fb2 = 1.15v, r por = 100k ? to in, r pfo = 100k ? to in, rsi = 0, c vcc = 0.1f, c ref = 0.1f, fbsel1 = unconnected, fbsel2 = unconnected, t a = -40c to +85c. ) (note 2) parameter conditions min typ max units pfo (max1970 and max1972 only) v cc rising 4.12 pfo trip threshold in = v cc v cc falling 3.86 v pfo output current, high pfo = in -1 1 a pfo output voltage, low i pfo = 1ma, v in = 4.3v 0.05 v en and rsi (max1971 only) v il 0.4 logic input thresholds in = 2.6v to 5.5v v ih 1.6 v rsi input resistance internal pullup resistor to in 5 20 k ? v il -1 1 en logic input current logic input at 0 or5.5v, v in = 5.5v v ih -1 1 a note 1: see the output voltage selection section. note 2: specifications to t a = -40c are guaranteed by design and not production tested. downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo _______________________________________________________________________________________ 7 100 0 0.01 0.1 1 efficiency vs. load current 20 10 max1970toc01 load current (a) efficiency (%) 40 30 60 70 50 80 90 v out2 = 2.5v v out1 = 3.3v max1970/max1972 v in = 5.0v v out1 = 1.8v v out2 = 1.5v 100 0 0.01 0.1 1 efficiency vs. load current 20 10 max1970toc02 load current (a) efficiency (%) 40 30 60 70 50 80 90 v out2 = 2.5v v out1 = 3.3v max1971v in = 5.0v v out1 = 1.8v v out2 = 1.5v 100 0 0.01 0.1 1 efficiency vs. load current 2010 max1970toc03 load current (a) efficiency (%) 4030 60 7050 80 90 v out2 = 2.5v max1970/max1972 v in = 3.3v v out1 = 1.8v v out2 = 1.5v 100 0 0.01 0.1 1 efficiency vs. load current 20 10 max1970toc04 load current (a) efficiency (%) 40 30 60 70 50 80 90 v out2 = 2.5v max1971v in = 3.3v v out1 = 1.8v v out2 = 1.5v 500 0 0 400 800 700 600 500 300 200 100 input current vs. output current 100 50 max1970toc05 output current (ma) input current (ma) 200 150 300 350 250 400 450 v out1 = 3.3v v in = 5.0v v out2 = 2.5v v out1 = 1.8v v out2 = 1.5v max1970/max1972 1.221.17 01 02 0 15 5 reference voltage vs. reference load current 1.18 max1970toc06 reference load current ( a) reference voltage (v) 1.19 1.20 1.21 1.600.40 2.5 4.0 5.5 5.0 4.5 3.5 3.0 oscillator frequency vs. input voltage 0.60 max1970toc07 input voltage (v) oscillator frequency (mhz) 0.80 1.20 1.00 1.40 t a = +85 c max1970/max1972 t a = +25 c t a = -40 c t a = +85 c max1971 t a = +25 c t a = -40 c 3 -3 0 400 800 600 200 change in output voltage vs. load current -2 max1970toc08 load current (ma) change in output voltage (mv) -1 1 0 2 v out1 = 3.3v v out1 = 1.8v v out2 = 1.5v v out2 = 2.5v v in = 5.0v max1970/max1972 typical operating characteristics (t a = +25c, unless otherwise noted.) downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 8 __________________________________________________ _____________________________________ i out1 v out1 40 s/div max1970toc09 v in = 5v v out1 = 3.3v, 100mv/div i out1 = 300ma to 600ma r c1 = 82k ? , c c1 = 680pf load-transient response max1970/max1972 typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) i out2 v out2 40 s/div max1970toc10 v in = 5v v out2 = 1.5v, 100mv/div i out2 = 300ma to 600ma r c2 = 39k ? , c c2 = 680pf load-transient response max1970/max1972 v lx1 i l2 v lx2 i l1 200ns/div max1970toc11 v in = 5v v out1 = 1.8v, v out2 = 2.5v i out1 = 500ma, i out2 = 500ma switching waveforms max1970/max1972 5v/div 200ma/div 5v/div 200ma/div 14 0 0.01 0.1 1 10 maximum output transient duration vs. por comparator overdrive 2 max1970toc12 maximum output transient duration ( s) por comparator overdrive (%) 64 8 10 12 downloaded from: http:///
40ms/div 2v/div max1970toc13 v in = 5v v out1 = 1.8v, v out2 = 2.5v i out1 = 500ma, i out2 = 500ma rsi and por timing v rsi v por typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) 4v4v 0 0 4ms/div 2v/div max1970toc14 v out1 = 1.8v, v out2 = 2.5v v in pf0 pfo and rising input voltage 4v 4v 0 0 4ms/div 2v/div max1970toc15 v out1 = 1.8v, v out2 = 2.5v v in pf0 pfo and falling input voltage 5ms/div 5v/div max1970toc16 max1970v in = 5v v out1 = 3.3v, v out2 = 2.5v i out1 = 375ma, i out2 = 375ma en v out1 por enable response v out2 max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo _______________________________________________________________________________________ 9 downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 10 _________________________________________________ _____________________________________ 5ms/div 5v/div max1970toc17 shutdown response por en v out1 v out2 max1970v in = 5v v out1 = 3.3v, v out2 = 2.5v i out1 = 375ma, i out2 = 375ma typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) name pin max1970/max1972 max1971 function 1 lx1 lx1 inductor connection 1. connect an inductor between lx1 and out1. 2v cc v cc analog supply voltage. bypass with 0.1f to ground. 3 comp1 comp1 out1 regulator compensation. connect series rc network from comp1 to gnd.comp1 is pulled to gnd when the outputs are shut down. see the compensation design section for component values. 4 fb1 fb1 out1 feedback. connected to out1 for internal mode (fbsel1 = gnd or v cc ). use an external resistor-divider from out1 to gnd to set the output voltage from1.2v to v in for external mode (fbsel1 = unconnected). see the output voltage selection section for <1.2v output. 5 fb2 fb2 out2 feedback. connected to out2 for internal mode (fbsel2 = gnd or v cc ). use an external resistor-divider from out2 to gnd to set the output voltage from1.2v to v in for external mode (fbsel2 = unconnected). see the output voltage selection section for <1.2v output. 6 comp2 comp2 out2 regulator compensation. connect series rc network from comp2 to gnd.comp2 is pulled to gnd when the outputs are shut down. see the compensation design section for component values. 7 ref ref reference. bypass with 0.01f to 1.0f capacitor. ref controls the soft-startramp and is pulled to gnd when the outputs are shut down. 8 gnd gnd ground pin description downloaded from: http:///
detailed description the max1970/max1971/max1972 are dual-output,fixed-frequency, current-mode, pwm, step-down dc-dc converters. the max1970 and max1972 switch at 1.4 mhz while the max1971 switches at 700khz. the two converters on each ic switch 180 out of phase with each other to reduce input ripple current. the high-switching frequency allows use of smaller capaci- tors for filtering and decoupling. internal synchronous rectifiers improve efficiency and eliminate the typical schottky freewheeling diode. the on-resistances of the internal mosfets are used to sense the switch cur- rents for controlling and protecting the mosfets, elimi- nating current-sensing resistors to further improve efficiency and cost. the input voltage range is 2.6v to 5.5v. each converter has a three-mode feedback input. internally, out1 is set to either 3.3v or 1.8v, and out2 to 2.5v or 1.5v by connecting fbsel1 and fbsel2 to v cc or gnd, respectively. when fbsel1 or fbsel2 are floating,each output can be set to any voltage between 1.2v and v in through an external resistive divider. having an output below 1.2v is also possible (see the output voltage selection section). dc-dc controller the max1970/max1971/max1972 family of step-downconverters uses a pulse-width-modulating (pwm) current- mode control scheme. the heart of the current-mode pwm controller is an open-loop comparator that com-pares the integrated voltage-feedback signal against the sum of the amplified current-sense signal and the slope compensation ramp. at each rising edge of the internal clock, the internal high-side mosfet turns on until the pwm comparator trips. during this on time, current ramps up through the inductor, sourcing cur- rent to the output and storing energy in a magnetic field. the current-mode feedback system regulates the peak inductor current as a function of the output volt- age error signal. since the average inductor current is nearly the same as the peak inductor current (assum- ing that the inductor value is relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. it pushes the output lc filter pole, normally found in a voltage-mode pwm, to a higher frequency. to preserve inner loop stability and eliminate inductor stair casing, a slope-compensation ramp issummed into the main pwm comparator. during the second half of the cycle, the internal high-side mosfet max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ___________________________________ 11 name pin max1970/max1972 max1971 function 9 por por active-low power-on reset output. open-drain output goes high 16.6ms(max1970) or 175ms (max1971 or max1972) after both outputs reach 92% of nominal value, and rsi (max1971 only) is low. 10 en en enable input. drive high to turn on both out1 and out2. drive low to place thedevice in shutdown. pfo power-fail output. open-drain output goes high when v cc drops below 3.94v. useful for detecting a valid usb input voltage. 11 rsi noninverting reset input. causes por to go low when rsi is high. allows por to go high 175ms after rsi falls, if outputs are in regulation. 12 fbsel2 fbsel2 regulator 2 feedback select. connect to v cc to set v out2 to 2.5v. connect to gnd to set v out2 to 1.5v. leave unconnected to use external feedback resistors. 13 fbsel1 fbsel1 regulator 1 feedback select. connect to v cc to set v out1 to 3.3v. connect to gnd to set v out1 to 1.8v. leave unconnected to use external feedback resistors. 14 in in power-supply voltage. input range from 2.6v to 5.5v. bypass with 10f capacitorto pgnd. 15 lx2 lx2 inductor connection 2. connect an inductor between lx2 and out2. 16 pgnd pgnd power ground pin description (continued) downloaded from: http:///
max1970/max1971/max1972 turns off and the internal low-side n-channel mosfetturns on. now the inductor releases the stored energy as its current ramps down while still providing current to the output. the output capacitor stores charge when the inductor current exceeds the load current and dis- charges when the inductor current is lower, smoothing the voltage across the load. under overload conditions, when the inductor current exceeds the current limit (see the current limit section), the high-side mosfet is not turned on at the rising edge of the clock and the low-side mosfet remains on to let the inductor current ramp down. current sense the current-sense circuit amplifies the current-sensevoltage generated by the high-side mosfets on-resis- tance and the inductor current (r ds(on) ? i inductor ). this amplified current-sense signal and the internalslope compensation signal are summed together into dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 12 _________________________________________________ _____________________________________ figure 1. functional diagram fb select pwm control lx1pgnd rsi pfo por max1970/max1972 only max1971 only clamp error signal regulator 1 regulator 2 fb1 in fbsel1 comp1 ref en comp2 fb2 fbsel2 gnd slope comp current sense soft-start thermal shutdown vok reference voltage 1.2v 2(max1970/ max1972)/ 4(max1971) 2.8mhz oscillator por pfo v cc max1970 max1971 max1972 downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ___________________________________ 13 the pwm comparators inverting input. the pwm com-parator turns off the internal high-side mosfet when this sum exceeds the integrated feedback voltage. current limit the internal mosfet has a current limit of 1.2a (typ). ifthe current flowing out of lx_ exceeds this maximum, the high-side mosfet turns off and the synchronous rectifier mosfet turns on. this lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. there is also a synchro- nous rectifier current limit of -0.85a. this is to protect the device from current flowing into lx_. if the negative current limit is exceeded, the synchronous rectifier is turned off, and the inductor current continues to flow through the high-side mosfet body diode back to the input until the beginning of the next cycle or until the inductor current drops to zero. v cc decoupling due to the high-switching frequency and tight outputtolerance (1%), decoupling between in and v cc is recommended. connect a 10 ? resistor between in and v cc and a 0.1f ceramic capacitor from v cc to gnd. place the resistor and capacitor as close to v cc as possible. startup to reduce the supply inrush current, soft-start circuitryramps up the output voltage during startup. this is done by charging the ref capacitor with a current source of 25a. once ref reaches 1.2v, the output is in full regulation. the soft-start time is determined from: soft-start occurs when power is first applied, and when en is pulled high with power already present. the part also goes through soft-start when coming out of under- voltage lockout (uvlo) or thermal shutdown. the range of capacitor values for c ref is from 0.01f to 1.0f. undervoltage lockout if v cc drops below 2.35v, the max1970/max1971/ max1972 assume that the supply voltage is too low toprovide a valid output voltage, and the uvlo circuit inhibits switching. once v cc rises above 2.4v, the uvlo is disabled and the soft-start sequence initiates. enable a logic-enable input (en) is provided. for normal oper-ation, drive en logic high. driving en low turns off both outputs, and reduces the input supply current to approximately 1a. power-fail output the input voltage is sensed for 5v (typical usb applica-tions), and if v cc drops below 3.94v, the power-fail out- put (pfo) goes high. the time from pfo going high tothe outputs going out of regulation depends on the oper- ating output voltage and currents, and the upstream 5v bus storage capacitor value, which is 120f minimum (per usb specification, version 2.0). the lower the oper- ating voltages and currents, and the higher the storage capacitor, the longer the elapsed time. pfo is an open- drain output, and a 10k ? to 100k ? pullup resistor to v cc , or either output, is recommended. power-on reset power-on reset ( por ) provides a system reset signal. during power-up, por is held low until both outputs reach 92% of their regulated voltages, por continues to be held low for a delayed period, and then goeshigh. this delay time (t d ) for max1970 is 16.6ms. the max1971 and max1972 have a delay of 175ms. figure2 is an example of a timing diagram. the por comparator is designed to be relatively immune to short-duration negative-going output glitch-es.the typical operating characteristics gives a plot of maximum transient duration vs. por comparator over- drive. the graph was generated using a negative-goingpulse applied to an output, starting at 100mv above the actual por threshold, dropping below the por thresh- old by the percentage indicated as comparator over-drive, and then returning to 100mv above the threshold. the graph indicates the maximum pulse width the output transient can have without causing por to trip low. reset input reset input (rsi) is an input on the max1971 that,when driven high, forces the por to go low. when rsi goes low, por goes through a delay time identical to a power-up event. see figure 2 for timing diagram. rsiallows software to command a system reset. rsi must be high for a minimum period of 1s in order to initiate the por . thermal-overload protection thermal-overload protection limits total power dissipa-tion. when the ics junction temperature exceeds t j = +170c, a thermal sensor shuts down the device,allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools by 20c. this results in a pulsed output during continuous overload conditions. during a thermal event, por goes low, pfo goes high, and soft-start is reset. t v i cc ss ref ref ref ref == 48 10 4 . downloaded from: http:///
max1970/max1971/max1972 design procedure output voltage selection both output voltages can be selected in three differentways as indicated by table 1. each output has two pre- set voltages that can be set using fbsel_ and it can also be set to any voltage from 0.8v to v in by using an external resistor voltage-divider.to use a resistor-divider to set the output voltage to 1.2v or higher (figure 5), connect a resistor from fb_ to out_ (r_ a ), and connect a resistor from fb_ to gnd (r_ b ). select the value of r_ b , between 10k ? and 30k ? . then r_ a is calculated by: a resistor-divider can also be used to set the voltage ofone output from 0.8v to 1.2v. to do this, the other out- put must be above 1.2v. figure 6 shows an example of this where out1 is set to 1v. to set the output voltage toless than 1.2v, connect a resistor from fb1 to out1 (r1), and from fb1 to out2 (r2). select values of r1 and r2 such that current flowing through r1 and r2 is about 100a and following equation is satisfied: each output is capable of continuously sourcing up to750ma of current as long as the following condition is met: inductor value a 3.3h to 6.8h inductor with a saturation current of800ma (min) is recommended for most applications. for best efficiency, the inductors dc resistance should be less than 100m ? , and saturation current should be greater than 1a. see table 2 for recommended induc-tors and manufacturers. vivi v a out out out out in 1122 105 + . rr v v out out 12 12 12 1 2 . . = rr v ab out __ . = ? ? ? ? ? ? 12 1 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 14 _________________________________________________ _____________________________________ figure 2. timing diagram v out t d rsi ~1v pkmax v in pfo 4.04v 3.94v t reset = 1 s min t d por downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ___________________________________ 15 figure 3. typical application circuit 1 1110 36 1213 7 8 4 1 915 5 16 2 14 v cc v cc v cc pfoen comp1 v in 3.3v to 5.5v comp2fbsel2 fbsel1 ref por por v out1 3.3vv out2 1.5v pfo 100k ? 82k ? 680pf680pf 39k ? 100k ? 10 ? 10 f 10 f 10 f 0.1 f 0.1 f 4.7 h 4.7 h lx1fb2 fb1lx2 pgnd gnd in max1972 en figure 4. typical application circuit 2 1110 36 1312 7 8 4 1 915 5 16 2 14 v cc v cc v cc pfoen comp1 v in 3.3v to 5.5v comp2fbsel1 fbsel2 ref v out1 3.3vv out2 2.5v pfo 100k ? 82k ? 680pf680pf 62k ? 100k ? 10 ? 10 f 10 f 10 f 0.1 f 0.1 f 4.7 h 4.7 h lx1fb2 fb1lx2 pgnd gnd in max1970 max1972 en por por downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 16 _________________________________________________ _____________________________________ figure 5. setting the output voltage with external resistors 1110 36 1312 7 8 4 1 9 16 2 10 ? 100k ? 14 v cc rsien comp1 comp2 fbsel1 fbsel2 gnd ref v out1 rsi 10 f 10 f 680pf r c1 r c2 680pf 0.1 f 4.7 h 0.1 f lx1fb1 pgnd in max1971 5 10 f r 2a r 2b r 1a r 1b fb2 15 v out2 4.7 h lx2 en v in 2.6v to 5.5v por por figure 6. setting an output below 1.2v 1110 36 1312 7 8 4 1 9 16 2 10 ? 100k ? 14 v cc v cc pfoen comp1 comp2 fbsel1 fbsel2 gnd ref v out1 1.0v rsi 100k ? v cc 10 f 680pf 27k ? 68k ? 680pf 0.1 f 4.7 h 0.1 f lx1fb1 pgnd in max1970 5 10 f r2 13k ? r1 2k ? fb2 15 v out2 2.5v 4.7 h lx2 en v in 3v to 3.6v por por downloaded from: http:///
for most designs, a reasonable inductor value (l init ) is derived from the following equation: keep the inductor current ripple percentage lir between 20% and 40% of the maximum load current for best compromise of cost, size, and performance. the maximum inductor current is: input capacitor the input filter capacitor reduces peak currents drawnfrom the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation:a ceramic capacitor is recommended due to its low equivalent series resistance (esr), equivalent series inductance (esl), and lower cost. choose a capacitor that exhibits less than a 10c temperature rise at the maximum operating rms current for optimum long-term reliability. output capacitor the key selection parameters for the output capacitorare its capacitance, esr, esl, and the voltage rating requirements. these affect the overall stability, output ripple voltage, and transient response of the dc-dc converter. the output ripple is due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitors esr, and the voltage drop due to the capacitors esl. the output voltage ripple due to the output capaci- tance, esr, and esl is: v ripple (esl) = (i p-p /t on ) ? esl or (i p-p /t off ) ? esl, whichever is greater.i p-p is the peak-to-peak inductor current: these equations are suitable for initial capacitor selec-tion, but final values should be set by testing a proto- type or evaluation circuit. as a rule, a smaller ripple current results in less output voltage ripple. since the inductor ripple current is a factor of the inductor value, the output voltage ripple decreases with larger induc- tance. ceramic capacitors are recommended due to their low esr and esl at the switching frequency of the converter. for ceramic capacitors, the ripple voltage due to esl is negligible. load transient response depends on the selected out- put capacitor. during a load transient, the output instantly changes by esr ? ? i load . before the con- i vv fl v v pp in out sw out in = v i esr ripple esr p p () = v i cf ripple c pp out sw () = 8 vv v v ripple ripple c ripple esr ripple esl =+ + () ( ) ( ) i v ivv v iv rms in out out in out out ou = () + 1 1 11 2 2 2 t tinout vv 22 () i lir i l max out max () () =+ ? ? ? ? ? ? 1 2 l vvv vl i ri f init out in out in out max osc = () () max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ___________________________________ 17 table 1. output voltage settings fbsel1 output 1 fbsel2 output 2 v cc 3.3v v cc 2.5v gnd 1.8v gnd 1.5v open ext divider open ext divider table 2. suggested inductors manufacturer part inductance (?) esr (m ) saturationcurrent (a) dimensions (mm) coilcraft do1606 4.7 120 1.2 5.3 ? 5.3 ? 2 sumida cr43-4r7 4.7 108.7 1.15 4.5 ? 4 ? 3.5 sumida cdrh3d16-4r7 4.7 80 0.9 3.8 ? 3.8 ? 0.8 downloaded from: http:///
max1970/max1971/max1972 troller can respond, the output deviates further,depending on the inductor and output capacitor values. after a short time (see the typical operating characteristics ), the controller responds by regulating the output voltage back to its nominal state. the con-troller response time depends on the closed-loop bandwidth. with a higher bandwidth, the response time is faster, thus preventing the output from deviating fur- ther from its regulating value. compensation design an internal transconductance error amplifier is used tocompensate the control loop. connect a series resistor and capacitor between comp and gnd to form a pole- zero pair. the external inductor, internal high-side mosfet, output capacitor, compensation resistor, and compensation capacitor determine the loop stability. the inductor and output capacitor are chosen based on performance, size, and cost. additionally, the com- pensation resistor and capacitor are selected to opti- mize control-loop stability. the component values shown in the typical application circuits (figures 3, 4, and 5) yield stable operation over a broad range of input-to-output voltages. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. the voltage across the internal high-side mosfets on-resistance (r ds(on) ) is used to sense the inductor current. current mode control eliminates the double pole caused by theinductor and output capacitor, which has large phase shift that requires more elaborate error-amplifier com- pensation. a simple type 1 compensation with single compensation resistor (r c ) and compensation capaci- tor (c c ) is all that is needed to have a stable and high- bandwidth loop.the basic regulator loop consists of a power modulator, an output feedback divider, and an error amplifier. the power modulator has dc gain set by gmc x r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. below are equations that define the power modulator:the pole frequency for the modulator is: the zero frequency for the output capacitor esr is: where, r load = v out /i out(max) , and gmc = 2s. the feedback divider has a gain of g fb = v fb /v out , where v fb is equal to 1.2v. the transconductance error ampli- fier has a dc gain, g ea(dc) , of 60db. a dominant pole is set by the compensation capacitor, c c , the output resistance of the error amplifier (r oea ), 20m ? , and the compensation resistor, r c . a zero is set by r c and c c . the pole frequency set by the transconductance ampli-fier output resistance, and compensation resistor and capacitor is: the zero frequency set by the compensation capacitor and resistor is: for best stability and response performance, the closed-loop unity-gain frequency must be much higher than the modulator pole frequency. in addition, the closed-loop unity-gain frequency should be approxi- mately 50khz. the loop gain equation at unity gain fre- quency then is: where g ea(fc) = gm ea ? r c , and g mod(fc) = gmc ? r load ? fp mod / fc , where gm ea = 50s, r c can be calculated as:the error-amplifier compensation zero formed by r c and c c is set at the modulator pole frequency at maxi- mum load. c c is calculated as follows: cv c ri c out out c out max = () r v gm v g c o ea fb mod fc = () gg v v ea fc mod fc fb o () () = 1 fz cr ea cc = 1 2 fp cr ea c oea = 1 2 fz c esr esr out = 1 2 fp c r esr mod out load = + () 1 2 g gmc r mod load = dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 18 _________________________________________________ _____________________________________ downloaded from: http:///
as the load current decreases, the modulator pole alsodecreases; however, the modulator gain increases accordingly, and the closed-loop unity-gain frequency remains the same. below is a numerical example to cal- culate r c and c c values of the typical application cir- cuit of figure 4, where: v out = 2.5v i out(max) = 0.6a c out = 10f r esr = 0.010 ? gm ea = 50s gm c = 2s f switch = 1.4mhz r load = v out /i out(max) = 2.5v/0.6a = 4.167 ? fp mod = 1/[2 c out (r load + r esr )] = 1/[2 x 10 x 10 -6 (4.167 + 0.01)] = 3.80khz. fz esr = 1/[2 c out r esr ] = 1/[2 x 10 x 10 -6 x 0.01] = 1.59mhz. pick a closed-loop unity-gain frequency (f c ) of 50khz. the power modulator gain at fc is: g mod (fc) = gmc x r load xfp mod /f c = 2 x 4.167 x 3.80k/50k = 0.635 then: r c = v o /(gm ea v fb g mod (fc)) = 2.5/(50 x 10 -6 x 1.2 x 0.635) 62k ? c c = v out x(c out /r c ) x i out (max) = 2.5 x 4.7 x 10 -6 /62k x 0.6 680pf applications information pcb layout careful pcb layout is critical to achieve clean and sta-ble operation. the switching power stage requires par- ticular attention. follow these guidelines for good pcb layout: 1) place decoupling capacitors as close to ic pins as possible. keep power ground plane (connected topgnd) and signal ground plane (connected to gnd) separate. connect the two ground planes together with a single connection from pgnd to gnd. 2) input and output capacitors are connected to the power ground plane; all other capacitors are con-nected to signal ground plane. 3) keep the high-current paths as short and wide as possible. 4) if possible, connect in, lx1, lx2, and pgnd sepa- rately to a large land area to help cool the ic to fur-ther improve efficiency and long-term reliability. 5) ensure all feedback connections are short and direct. place the feedback resistors as close to theic as possible. 6) route high-speed switching nodes away from sen- sitive analog areas (fb1, fb2, comp1, comp2). max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo ___________________________________________________ ___________________________________ 19 downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo 20 _________________________________________________ _____________________________________ package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 16 qsop e16-5 21-0055 chip information transistor count: 5428process: bicmos downloaded from: http:///
max1970/max1971/max1972 dual, 180 out-of-phase, 1.4mhz, 750ma step- down regulator with por and rsi/pfo maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/02 initial release 1 2/09 updated formula in the output voltage selection section. 14 downloaded from: http:///

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