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ultralow distortion, low power, low noise, high speed op amp data sheet ada4857-1 / ada4857-2 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2008C2017 analog devices, inc. all rights reserved. technical support www.analog.com features high speed 850 mhz, ?3 db bandwidth (g = +1, r l = 1 k, lfcsp) 750 mhz, ?3 db bandwidth (g = +1, r l = 1 k, soic) 2800 v/s slew rate low distortion: ?88 dbc at 10 mhz (g = +1, r l = 1 k) low power: 5 ma/amplifier at 10 v low noise: 4.4 nv/hz wide supply voltage range: 5 v to 10 v power-down feature available in 3 mm 3 mm 8-lead lfcsp (single), 8-lead soic (single), and 4 mm 4 mm 16-lead lfcsp (dual) applications instrumentation if and baseband amplifiers active filters adc drivers dac buffers connection diagrams figure 1. 8-lead lfcsp (cp) figure 2. 8-lead soic (r) figure 3. 16-lead lfcsp (cp) general description the ada4857 is a unity-gain stable, high speed, voltage feedback amplifier with low distortion, low noise, and high slew rate. with a spurious-free dynamic range (sfdr) of ?88 dbc at 10 mhz, the ada4857 is an ideal solution for a variety of applications, including ultrasounds, ate, active filters, and adc drivers. the analog devices, inc., proprietary next-generation xfcb process and innovative architecture enables such high performance amplifiers. the ada4857 has 850 mhz bandwidth, 2800 v/s slew rate, and settles to 0.1% in 15 ns. with a wide supply voltage range (5 v to 10 v), the ada4857 is an ideal candidate for systems that require high dynamic range, precision, and speed. the ada4857-1 amplifier is available in a 3 mm 3 mm, 8-lead lfcsp and a standard 8-lead soic. the ada4857-2 is available in a 4 mm 4 mm, 16-lead lfcsp. the lfcsp features an exposed paddle that provides a low thermal resistance path to the printed circuit board (pcb). this path enables more efficient heat transfer and increases reliability. the ada4857 works over the extended industrial temperature range (?40c to +125c). pd fb ?in +in out +v s nc ?v s a da4857-1 top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2 . the exposed pad may be connected to gnd or vs. 3 4 1 2 6 5 8 7 07040-001 fb 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 out 6 nc 5 nc = no connect a da4857-1 top view (not to scale) 07040-002 a da4857-2 top view (not to scale) 07040-003 12 11 10 1 3 4 9 2 6 5 7 8 1 6 1 5 1 4 1 3 notes 1. nc = no connect. do not connect to this pin. 2. the exposed pad may be connected to gnd or vs. ?in1 +in1 nc ?v s2 ?v s1 out1 +v s1 pd1 fb1 nc +in2 ?in2 out2 +v s2 pd2 fb2
ada4857-1/ada4857-2 data sheet rev. d | page 2 of 21 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagrams ...................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v supply ................................................................................... 3 ? +5 v supply ................................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? maximum power dissipation ..................................................... 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 9 ? test circuits ..................................................................................... 16 ? applications information .............................................................. 17 ? power-down operation ............................................................ 17 ? capacitive load considerations .............................................. 17 ? recommended values for various gains ................................ 17 ? active low-pass filter (lpf) .................................................... 18 ? noise ............................................................................................ 19 ? circuit considerations .............................................................. 19 ? pcb layout ................................................................................. 19 ? power supply bypassing ............................................................ 19 ? grounding ................................................................................... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 21 ? revision history 1/2017rev. c to rev. d changes to figure 1 .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to figure 5 .......................................................................... 7 added figure 40 and figure 43; renumbered sequentially ..... 14 added figure 44, figure 45, figure 46, figure 47, and figure 48 ................................................................................... 15 changes to power-down operation section .............................. 17 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 9/2013rev. b to rev. c changes to figure 1 and figure 3 ................................................... 1 change to figure 5 ........................................................................... 7 change to figure 7 ........................................................................... 8 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 8/2011rev. a to rev. b changes to table 1 conditions ....................................................... 3 changes to table 2 conditions ....................................................... 4 changes to typical performance characteristics conditions .... 9 changes to figure 18 ...................................................................... 10 changes to figure 42 ...................................................................... 15 changes to table 9 .......................................................................... 16 changes to ordering guide .......................................................... 20 11/2008rev. 0 to rev. a changes to table 5 ............................................................................. 7 changes to table 7 ............................................................................. 8 changes to figure 32...................................................................... 13 added figure 44; renumbered sequentially .............................. 15 changes to layout .......................................................................... 15 changes to table 8 .......................................................................... 16 added active low-pass filter (lfp) section ............................. 17 added figure 48 and figure 49; renumbered sequentially ..... 17 changes to grounding section .................................................... 18 exposed paddle notation added to outline dimensions ........ 19 changes to ordering guide .......................................................... 20 5/2008revision 0: initial version
data sheet ada4857-1/ada4857-2 rev. d | page 3 of 21 specifications 5 v supply t a = 25c, g = 2, r g = r f = 499 , r s = 100 for g = 1 (soic), r l = 1 k to ground, pd = no connect, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit dynamic performance C3 db bandwidth (lfcsp/soic) gain (g) = 1, v out = 0.2 v p-p 650 850/750 mhz g = 1, v out = 2 v p-p 600/550 mhz g = 2, v out = 0.2 v p-p 400/350 mhz full power bandwidth g = 1, v out = 2 v p-p, thd < ?40 dbc 110 mhz bandwidth for 0.1 db flatness (lfcsp/soic) g = 2, v out = 2 v p-p, r l = 150 75/90 mhz slew rate (10% to 90%) g = 1, v out = 4 v step 2800 v/s settling time to 0.1% g = 2, v out = 2 v step 15 ns noise/harmonic performance harmonic distortion f = 1 mhz, g = 1, v out = 2 v p-p (hd2) ?108 dbc f = 1 mhz, g = 1, v out = 2 v p-p (hd3) ?108 dbc f = 10 mhz, g = 1, v out = 2 v p-p (hd2) ?88 dbc f = 10 mhz, g = 1, v out = 2 v p-p (hd3) ?93 dbc f = 50 mhz, g = 1, v out = 2 v p-p (hd2) ?65 dbc f = 50 mhz, g = 1, v out = 2 v p-p (hd3) ?62 dbc input voltage noise f = 100 khz 4.4 nv/hz input current noise f = 100 khz 1.5 pa/hz dc performance input offset voltage 2 4.5 mv t min to t max 7.2 mv input offset voltage drift t min to t max 2.3 22 v/c input bias current ?2 ?3.3 a t min to t max ?3.8 a input bias offset current 50 800 na open-loop gain v out = ?2.5 v to +2.5 v 57 db pd (power-down) pin pd input voltage chip powered down (+v s ? 2) v chip powered down, t min to t max (+v s ? 1.7) v chip enabled (+v s ? 4.2) v chip enabled, t min to t max (+v s C 5.3) v turn-off time 50% off pd to <10% of final v out , v in = 1 v, g = 2 55 s turn-on time 50% off pd to <10% of final v out , v in = 1 v, g = 2 33 ns pd pin leakage current chip enabled 58 a chip powered down 80 a input characteristics input resistance common mode 8 m differential mode 4 m input capacitance common mode 2 pf input common-mode voltage range 4 v common-mode rejection ratio v cm = 1 v ?78 ?86 db v cm = ?3.6 v to +3.7 v, t min to t max ?70 db
ada4857-1/ada4857-2 data sheet rev. d | page 4 of 21 parameter test conditions/comments min typ max unit output characteristics output overdrive recovery time v in = 2.5 v, g = 2 10 ns output voltage swing high r l = 1 k +v s ? 1 v r l = 1 k, t min to t max +v s ? 1.3 v r l = 100 +v s C 1.3 v r l = 100 , t min to t max +v s ? 2 v low r l = 1 k ?v s + 1 v r l = 1 k, t min to t max ?v s + 1.3 v r l = 100 ?v s + 1.3 v r l = 100 , t min to t max ?v s + 3 v output current 50 ma short-circuit current sinking and sourcing 125 ma capacitive load drive 30% overshoot, g = 2 10 pf power supply operating range 4.5 10.5 v quiescent current 5 5.5 ma quiescent current (power down) pd v cc ? 2 v 350 450 a positive power supply rejection +v s = 4.5 v to 5.5 v, ?v s = ?5 v ?59 ?62 db negative power supply rejection +v s = 5 v, ?v s = ?4.5 v to ?5.5 v ?65 ?68 db +5 v supply t a = 25c, g = 2, r f = r g = 499 , r s = 100 for g = 1 (soic), r l = 1 k to midsupply, pd = no connect, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit dynamic performance C3 db bandwidth (lfcsp/soic) g = 1, v out = 0.2 v p-p 595 800/750 mhz g = 1, v out = 2 v p-p 500/400 mhz g = 2, v out = 0.2 v p-p 360/300 mhz full power bandwidth g = 1, v out = 2 v p-p, thd < ?40 dbc 95 mhz bandwidth for 0.1 db flatness (lfcsp/soic) g = 2, v out = 2 v p-p, r l = 150 50/40 mhz slew rate (10% to 90%) g = 1, v out = 2 v step 1500 v/s settling time to 0.1% g = 2, v out = 2 v step 15 ns noise/harmonic performance harmonic distortion f = 1 mhz, g = 1, v out = 2 v p-p (hd2) ?92 dbc f = 1 mhz, g = 1, v out = 2 v p-p (hd3) ?90 dbc f = 10 mhz, g = 1, v out = 2 v p-p (hd2) ?81 dbc f = 10 mhz, g = 1, v out = 2 v p-p (hd3) ?71 dbc f = 50 mhz, g = 1, v out = 2 v p-p (hd2) ?69 dbc f = 50 mhz, g = 1, v out = 2 v p-p (hd3) ?55 dbc input voltage noise f = 100 khz 4.4 nv/hz input current noise f = 100 khz 1.5 pa/hz dc performance input offset voltage 1 4.2 mv t min to t max 6.4 mv input offset voltage drift t min to t max 4.6 23 v/c input bias current ?1.7 ?3.3 a t min to t max ?4.1 a input bias offset current 50 800 na open-loop gain v out = 1.25 v to 3.75 v 57 db
data sheet ada4857- 1/ada4857 - 2 rev. d | page 5 of 21 parameter test conditions/comments min typ max unit pd (power - down) pin pd input voltage chip powered down (+ v s ? 2) v chip powered down, t min to t max (+ v s ? 1.4) v chip enabled (+ v s ? 4.2) v chip enabled, t min to t max (+v s ? 4.8) v turn - off time 50% off pd to <10% of final v out , v in = 1 v, g = 2 38 s turn - on time 50% off pd to <10% of final v out , v in = 1 v, g = 2 30 ns pd pin leakage current chip enable 8 a chip powered down 30 a input characteristics input resistance common mode 8 m differential mode 4 m input capacitance common mode 2 pf input common - mode voltage range 1 to 4 v common - mode rejection ratio v cm = 2 v to 3 v ?76 ?84 db v cm = 1.3 v to 3.7 v, t min to t max ?70 db output characteristics overdrive recovery time g = 2 15 ns output voltage swing high r l = 1 k + v s ? 1 v r l = 1 k, t min to t max +v s ? 1.3 v r l = 100 + v s C 1.1 v r l = 100 , t min to t max +v s C 1.7 v low r l = 1 k ? v s + 1 v r l = 1 k, t min to t max ?v s + 1.3 v r l = 100 ? v s + 1.1 v r l = 100 , t min to t max ?v s + 1.6 v output current 50 ma short - circuit current sinking and sourcing 75 ma capacitive load drive 30% overshoot, g = 2 10 pf power supply operating range 4.5 10.5 v quiescent current 4.5 5 ma quiescent current (power down) pd v cc ? 2 v 250 350 a positive power supply rejection +v s = 4.5 v to 5.5 v, ?v s = 0 v ?58 ?62 db negative power supply rejection +v s = 5 v, ?v s = ?0.5 v to +0.5 v ?65 ?68 db
ada4857-1/ada4857-2 data sheet rev. d | page 6 of 21 absolute maximum rat ings table 3 . parameter rating supply voltage 11 v power dissipation see figure 4 common - mode input voltage ?v s + 0.7 v to +v s ? 0.7 v differential input voltage v s exposed paddle voltage ?v s storage temperature range ?65c to +125c operating temperature range ?40c to +1 2 5c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliabilit y. thermal resistance ja is specified for the worst - case conditions, that is , ja is specified for device soldered in circuit board for surface - mount packages. table 4 . package type ja jc unit 8- lead soic 115 15 c/w 8- lead lfcsp 94.5 34.8 c/w 16 - lead lfc sp 68.2 19 c/w maximum power dissip ation the maximum safe power dissipation for the ada4857 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the glass transition temperature, the properties of the plastic change. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4857 . exceeding a junction temper ature of 175 c for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in t he die due to the ada4857 drive at the output. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). p d = quiescent power + ( total drive pow er ? load power ) ( ) l out l out s ss d r v r v v ivp 2 C 2 ? ? ? ? ? ? ? ? += ( ) ( ) l s ss d r v ivp 2 4/ += figure 4 . maximum power dissipation vs. temperature for a 4 - layer board esd caution 0 0.5 1.0 1.5 2.0 2.5 3.0 C40 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 100 110 120 07040-004 ambient temperature (c) maximum power dissipation (w) ada4857-1 (soic) ada4857-1 (lfcsp) ada4857-2 (lfcsp)
data sheet ada4857-1/ada4857-2 rev. d | page 7 of 21 pin configurations and function descriptions figure 5. 8-lead lfcsp pin configuration figure 6. 8-lead soic pin configuration table 5. 8-lead lfcsp pin function descriptions pin no. mnemonic description 1 pd power down. 2 fb feedback. 3 ?in inverting input. 4 +in noninverting input. 5 ?v s negative supply. 6 nc no connect. 7 out output. 8 +v s positive supply. ep gnd or v s exposed pad. the exposed pad may be connected to gnd or v s . table 6. 8-lead soic pin function descriptions pin no. mnemonic description 1 fb feedback. 2 ?in inverting input. 3 +in noninverting input. 4 ?v s negative supply. 5 nc no connect. 6 out output. 7 +v s positive supply. 8 pd power down. pd fb ?in +in out +v s nc ?v s notes 1. nc = no connect. do not connect to this pin. 2 . the exposed pad may be connected to gnd or vs. 3 4 1 2 6 5 8 7 07040-005 ada4857-1 top view (not to scale) fb 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 out 6 nc 5 nc = no connect ada4857-1 07040-006 top view (not to scale)
ada4857- 1/ada4857 - 2 data sheet rev. d | page 8 of 21 figure 7 . 16 - lead lfcsp pin configuration table 7 . 16 - lead lfcsp pin function descriptions pin no. mnemonic description 1 ?in1 inverting input 1 . 2 +in1 noninverting input 1 . 3, 11 nc no connect . 4 ?v s2 negative supply 2 . 5 out2 output 2 . 6 +v s2 positive supply 2 . 7 pd2 power down 2 . 8 fb2 feedback 2 . 9 ?in2 inverting input 2 . 10 +in2 noninverting input 2 . 12 ?v s1 negative supply 1 . 13 out1 output 1 . 14 +v s1 positive supply 1 . 15 pd1 power down 1 . 16 fb1 feedback 1 . ep gnd or v s exposed pad . the exposed pad may be connect ed to gnd or v s . 07040-007 12 1 1 10 1 3 4 9 2 6 5 7 8 16 15 14 13 notes 1. nc = no connec t . do not connect t o this pin. 2. the exposed p ad m a y be connected t o gnd or vs. Cin1 +in1 nc Cv s2 Cv s1 out1 +v s1 pd1 fb1 nc +in2 Cin2 out2 +v s2 pd2 fb2 ada4857-2 top view (not to scale)
data sheet ada4857- 1/ada4857 - 2 rev. d | page 9 of 21 typical performance characteristics t = 25 c , g = + 1 , r f = 0 ? , and, r g open , r s = 1 00 ? for soic, (for g = + 2 , r f = r g = 499 ? ) , unless otherwise noted. figure 8. small signal frequency responses for various gains ( lfcsp ) figure 9. small signal frequency response for various supply voltages ( lfcsp ) figure 10 . small signal frequency response for various temperatures ( lfcsp) figure 11 . large signal frequency responses for various gains ( lf csp ) figure 12 . small signal frequency response for various capacitive loads ( lf csp) figure 13 . large signal frequency response vs. v out (lfcsp) C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-008 frequency (mhz) normalized closed-loop gain (db) g = +1 g = +2 g = +5 g = +10 v s = 5v r l = 1k? v out = 0.2v p-p C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-009 frequency (mhz) closed-loop gain (db) g = +1 r l = 1k? v out = 0.2v p-p 5v +5v C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-010 frequency (mhz) closed-loop gain (db) C40c +125c +25c g = +1 v s = 5v r l = 1k? v out = 0.2v p-p C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-011 frequency (mhz) normalized closed-loop gain (db) g = +1 g = +2 g = +10 v s = 5v r l = 1k? v out = 2v p-p g = +5 1 10 100 1000 07040-012 frequency (mhz) closed-loop gain (db) no cap load g = +2 v s = 5v r l = 1k? v out = 0.2v p-p C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 5pf 10pf C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-013 frequency (mhz) closed-loop gain (db) g = +1 v s = 5v r l = 100? 1v p-p 4v p-p
ada4857- 1/a da4857 - 2 data sheet rev. d | page 10 of 21 figure 14 . small signal frequency response for various resistive loads ( lfcsp ) figure 15 . small signal frequency response for various gains ( lfcsp ) figure 16 . harmonic distortion vs. frequency and gain (lfcsp) figure 17 . large signal frequency response for various resistive loads ( lf csp) figure 18 . small signal frequency response for various gains (soic) , r s = 1 00 ? for g = +1 figure 19 . harmonic distortion vs. frequency and load (lfcsp) 1 10 100 1000 07040-014 frequency (mhz) closed-loop gain (db) r l = 100? g = +2 v s = 5v v out = 0.2v p-p C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 8 9 r l = 1k? C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-015 frequency (mhz) normalized closed-loop gain (db) v s = 5v r l = 1k? v out = 0.2v p-p g = +1 g = +2 g = +10 g = +5 C120 C110 C100 C90 C80 C70 C60 C50 C40 0.2 1 10 100 g = +1, hd2 g = +1, hd3 g = +2, hd2 g = +2, hd3 07040-016 frequency (mhz) distortion (dbc) v s = 5v v out = 2v p-p r l = 1k ? C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-017 frequency (mhz) closed-loop gain (db) g = +1 v s = 5v v out = 2v p-p r l = 100? r l = 1k? C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 1 10 100 1000 07040-018 frequenc y (mhz) normalized closed-loo p gain (db) v s = 5v r l = 1k? v out = 0.2v p-p g = +1 g = +10 g = +5 g = +2 100? v in r l r t r s v out +v s Cv s g = +1 C120 C110 C100 C90 C80 C70 C60 C50 C40 0.2 1 10 100 r l = 100 ? , hd2 r l = 100 ? , hd3 r l = 1k ? , hd3 07040-019 frequency (mhz) distortion (dbc) g = +1 v s = 5v v out = 2v p-p r l = 1k ? , hd2
data sheet ada4857- 1/ada4857 - 2 rev. d | page 11 of 21 figure 20 . harmonic distortion vs. output v oltage figure 21 . 0.1 db flatness vs. frequency for various output voltages (soic) figure 22 . large signal transient response for various output voltage s (soic) figure 23 . short - term settling time (lfcsp) figure 24 . 0.1 db flatness vs. frequency for various output voltages ( lf csp) figure 25 . large signal transient response for various output voltage s ( lf csp) 1 2 3 4 5 6 7 8 C120 C110 C100 C90 C80 C70 C60 C50 C40 hd2, f = 10mhz hd3, f = 1mhz hd3, f = 10mhz hd2, f = 1mhz 07040-020 output voltage (v p-p) distortion (dbc) g = +2 v s = 5v r l = 1k ? 5.7 5.8 5.9 6.1 6.0 6.2 6.3 1 10 100 07040-021 frequency (mhz) closed-loop gain (db) v out = 2v p-p v out = 0.2v p-p v s = 5v g = +2 r l = 150 ? output voltage (v) 07040-022 time (10ns/div) 2.5 C2.5 C2.0 2.0 C1.5 1.5 C1.0 1.0 C0.5 0 0.5 4v p-p 2v p-p v s = 5v r l = 1k? g = +2 settling time (%) 07040-023 time (5ns/div) 0.5 C0.5 C0.4 0.4 C0.3 0.3 C0.2 0.2 C0.1 0 0.1 output input v out = 2v p-p g = +2 v s = 5 5.7 5.8 5.9 6.1 6.0 6.2 6.3 1 10 100 07040-024 frequency (mhz) closed-loop gain (db) v out = 2v p-p v out = 0.2v p-p v s = 5v g = +2 r l = 150 ? output voltage (v) 07040-025 time (10ns/div) 2.5 C2.5 C2.0 2.0 C1.5 1.5 C1.0 1.0 C0.5 0 0.5 4v p-p 2v p-p v s = 5v r l = 1k? g = +1
ada4857- 1/a da4857 - 2 data sheet rev. d | page 12 of 21 figure 26 . small signal transient response for various capaci tive loads ( lfcsp ) figure 27 . small signal transient response for various supply voltages (lfcsp) figure 28 . closed - loop output impedance vs. frequency for various gains figure 29 . large signal transient response for various load resistances ( soic ) figure 30 . large signal transient response for various load resistances (lfcsp) figure 31 . closed - loop input impedance vs. frequency output voltage (v) 07040-026 time (10ns/div) 0.25 C0.25 C0.20 0.20 C0.15 0.15 C0.10 0.10 C0.05 0 0.05 c l = 10pf c l = 1.5pf v s = 5v r l = 1k? g = +1 output voltage (v) 07040-027 time (10ns/div) 0.25 C0.25 C0.20 0.20 C0.15 0.15 C0.10 0.10 C0.05 0 0.05 v s = 5v v s = 2.5v r l = 1k? g = +1 0.1 1 10 100 1000 1000 0.1 1 10 100 07040-028 frequency (mhz) closed-loop output impedance ( ?) v s = 5v g = +2 g = +5 output voltage (v) 07040-029 time (10ns/div) 2.0 C2.0 C1.6 1.6 C1.2 1.2 C0.8 0.8 C0.4 0 0.4 r l = 1k? r l = 100? v s = 5v g = +2 output voltage (v) 07040-030 time (10ns/div) 2.0 C2.0 C1.6 1.6 C1.2 1.2 C0.8 0.8 C0.4 0 0.4 r l = 1k? r l = 100? v s = 5v g = +1 1 10 100 1000 07040-031 frequency (mhz) closed-loop input impedance ( k ?) v s = 5v g = +2 0.01 0.1 1 10 100
data sheet ada4857- 1/ada4857 - 2 rev. d | page 13 of 21 figure 32 . open - loop gain and phase vs. frequency figure 33 . input overdrive recovery for various resistive loads figure 34 . power supply rejection ratio (psrr) vs. frequency figure 35 . pd isolation vs. frequency figure 36 . output overdrive recovery for various resistive loads figure 37 . common - mode rejection ratio (cmrr) vs. frequency phase gain C10 0 10 20 30 40 50 60 80 70 0.1 C180 C160 C140 C120 C100 C80 C60 C40 C20 0 1 10 100 1000 open-loop phase (degrees) 07040-032 frequency (mhz) open-loop gain (db) v s = 5v r l = 1k ? 07040-033 output voltage (v) time (40ns/div) 8 C8 6 C6 C4 4 C2 0 2 output r l = 100? output r l = 1k? input v s = 5v g = +1 C30 C20 C10 0 10 C80 C70 C60 C50 C40 0.1 1 10 100 1000 07040-034 frequency (mhz) psrr (db) Cpsrr +psrr v s = 5v r l = 1k ? soic lfcsp C30 C20 C10 0 C100 C70 C80 C90 C60 C50 C40 0.1 1 10 100 1000 07040-035 frequency (mhz) pd isolation (db) g = +2 v s = 5v r l = 1k ? pd = 3v 07040-036 output voltage (v) time (200ns/div) 8 C8 6 C6 C4 4 C2 0 2 output r l = 100? output r l = 1k? 2 input v s = 5v g = +2 C30 C90 C80 C70 C60 C50 C40 0.1 1 10 100 1000 07040-037 frequency (mhz) cmrr (db) v s = 5v r l = 1k ?
ada4857- 1/a da4857 - 2 data sheet rev. d | page 14 of 21 figure 38 . input current noise vs. frequency figure 39 . supply current figure 40 . input offset voltage distribution , v s = 5 v figure 41 . input voltage noise vs. frequency figure 42 . disable/enable switching speed figure 43 . input offset voltage distribution, v s = 5 v 07040-050 frequency (hz) current noise (pa/ hz) 1 10 100 10 100 1k 10k 100k 1m v s = 5v 50 40 30 20 10 4.95 4.90 4.85 5.00 0 07040-042 supply current (ma) count 5.15 5.10 5.05 n = 238 mean: 5.00 sd: 0.02 0 5 10 15 20 25 30 35 40 C5 C4 C3 C2 C1 0 1 2 3 4 5 number of amplifiers input offset voltage (mv) v s = 5 v 07040-240 07040-041 frequency (hz) voltage noise (nv/hz) 1 10 1000 100 1 10 100 1k 10k 100k 1m v s = 5v 07040-043 voltage (v) time (20 s/div) 3.5 C0.5 3.0 0 0.5 2.5 1.0 1.5 2.0 output pd input 0 5 10 15 20 25 30 35 40 C5 C4 C3 C2 C1 0 1 2 3 4 5 number of amplifiers input offset voltage (mv) v s = 5 v 07040-243
data sheet ada4857- 1/ada4857 - 2 rev. d | page 15 of 21 figure 44 . input offset voltage distribution over temperature, v s = 5 v 0 1 0 2 0 3 0 4 0 5 0 6 0 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 n u m b e r o f a m p li f i e r s input of f s e t v o l t a g e ( m v ) C 4 0 c + 1 2 5 c v s = 5 v 07040-244 0 5 1 0 1 5 2 0 2 5 3 0 C1 5 C1 0 C5 0 5 1 0 1 5 n u m b e r o f a m p li f i e r s input of f s e t v o l t a g e dri ft ( v /c) 07040-245 v s = 5 v C500 C400 C300 C200 C100 0 100 200 300 400 500 C4 C3 C2 C1 0 1 2 3 4 common-mode rejection (v/v) common-mode voltage (v) 07040-246 0 1 0 2 0 3 0 4 0 60 5 0 70 C7 C6 C5 C4 C3 C2 C1 0 1 2 3 4 5 6 7 n u m b e r o f a m p li f i e r s input of f s e t v o l t a g e ( m v ) C 4 0 c + 1 2 5 c v s = 5 v 07040-247 0 5 1 0 1 5 2 0 2 5 C1 5 C1 0 C5 0 5 1 0 1 5 n u m b e r o f a m p li f i e r s input of f s e t v o l t a g e dri ft ( v /c) 07040-248 v s = 5 v
ada4857- 1/a da4857 - 2 data sheet rev. d | page 16 of 21 t est c ircuits figure 49 . noninverting load configuration figure 50 . positive power supply rejection figure 51 . typical capacitive load configuration (lfcsp) figure 52 . common - mode rejection figure 53 . negative power supply rejection figure 54 . typical capacitive load configuration (soic) v in r s v out 0.1f 0.1f 0.1f 10f +v s Cv s 49.9? 07040-047 r l + 10f + v out 0.1f 49.9? +v s Cv s 07040-045 r l 10f + ac v in v out 0.1f 0.1f 0.1f 10f +v s Cv s 49.9? 07040-051 r l r f r g c l + 10f + v in v out 0.1f 0.1f 0.1f 10f +v s Cv s 1k? 1k? 1k? 1k? 07040-046 53.6? r l + 10f + 0.1f v out +v s Cv s 07040-048 r l 10f + ac 49.9? v in v out 0.1f 0.1f 0.1f 10f +v s Cv s r g r f 49.9 ? 07040-049 r l c l + 10f + 40 ? r snub
data sheet ada4857- 1/ada4857 - 2 rev. d | page 17 of 21 a pplications informat ion power - down operation the pd pin power s down the chip, reducing the quiescent current and the overall power consumption. to enable the device, pull the pd pin low . table 8 provides the pd pin voltages that e nable the correct operation at different supplies. t hese volta ges are applicable for ambient tem perature only. consult table 1 and table 2 when designing for use at the full operating temperature range . note that pd does not put the output in a high - z state, which means that the ada4857 must not be used as a multiplexer. table 8 . pd operation table g uide supply voltage condition 5 v 2.5 v +5 v enabled +0.8 v ?1.7 v +0.8 v powered down +3 v +0.5 v +3 v capacitive load con s iderations when driving a capacitive load using the soic package , r snub reduce s the peaking ( s ee figure 54 ). an optimum resistor value of 40 ? is found to maintain th e peaking within 1 db for any capacitive load up to 40 p f. recommended values f or various gains table 9 provides a useful reference for determining various gains and associated performance. r f and r g are kept low to minimize their contribution to the overall noise performance of the amplifier. table 9 . various gain and recommended resistor values associated w ith conditions ; v s = 5 v, t a = 25c, r l = 1 k? , r t = 49.9 ? gain r s () (csp/ soic ) r f () r g () ? 3 db ss bw (mhz) (csp/soic) slew rate (v/s), v out = 2 v step ada 4857 voltage noise (nv/hz), rto total system noise (nv/hz), rto +1 0/ 100 0 n/a 850 /750 2350 4.4 4.49 +2 0/ 0 499 499 360 /320 1680 8.8 9.89 +5 0/ 0 499 124 90 /89 516 22.11 23.49 +10 0/ 0 499 56.2 43 /40 213 43.47 45.31
ada4857-1/ada4857-2 data sheet rev. d | page 18 of 21 active low-pass filter (lpf) active filters are used in many applications such as antialiasing filters and high frequency communication if strips. with a 410 mhz gain bandwidth product and high slew rate, the ada4857-2 is an ideal candidate for active filters. figure 55 shows the frequency response of 90 mhz and 45 mhz lpfs. in addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. in this case, a 90 mhz bandwidth with a 2 v p-p output swing requires at least 2800 v/s. the circuit shown in figure 56 is a 4-pole, sallen-key lpf. the filter comprises two identical cascaded sallen-key lpf sections, each with a fixed gain of g = 2. the net gain of the filter is equal to g = 4 or 12 db. the actual gain shown in figure 55 is 12 db. this does not take into account the output voltage being divided in half by the series matching termination resistor, r t , and the load resistor. setting the resistors equal to each other greatly simplifies the design equations for the sallen-key filter. to achieve 90 mhz, the value of r must be set to 182 . however, if the value of r is doubled, the corner frequency is cut in half to 45 mhz. this would be an easy way to tune the filter by simply multiplying the value of r (182 ) by the ratio of 90 mhz and the new corner frequency in megahertz. figure 55 shows the output of each stage is of the filter and the two different filters corresponding to r = 182 and r = 365 . resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. due to the low capacitance values used in the filter circuit, the pcb layout and minimization of parasitics is critical. a few picofarads can detune the corner frequency, f c of the filter. the capacitor values shown in figure 56 actually incorporate some stray pcb capacitance. capacitor selection is critical for optimal filter performance. capacitors with low temperature coefficients, such as npo ceramic capacitors and silver mica, are good choices for filter elements. figure 55. low-pass filter response figure 56. 4-pole, sallen-key low-pass filter ( ada4857-2 ) ?42 ?39 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 0.1 1 10 100 500 07040-074 frequency (mhz) magnitude (db) out1, f = 90mhz out2, f = 90mhz out1, f = 45mhz out2, f = 45mhz r l = 100 ? v s = 5v u1 c1 3.9pf c2 5.6pf r r t 49.9 ? r r1 348 ? r r2 348 ? r t 49.9 ? +in1 ?5v +5v 0.1f 0.1f 10f 10f u2 c3 3.9pf c4 5.6pf r r3 348 ? r4 348 ? ?5v +5v 0.1f 0.1f 10f 10f out2 07040-075 out1
data sheet ada4857-1/ada4857-2 rev. d | page 19 of 21 noise to analyze the noise performance of an amplifier circuit, identify the noise sources and determine if the source has a significant contribution to the overall noise performance of the amplifier. to simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nv/ ? hz, is equivalent to the noise in a 1 hz bandwidth). the noise model shown in figure 57 has six individual noise sources: the johnson noise of the three resistors, the operational amplifier voltage noise, and the current noise in each input of the amplifier. each noise source has its own contribution to the noise at the output. noise is generally referred to input (rti), but it is often easier to calculate the noise referred to the output (rto) and then divide by the noise gain to obtain the rti noise. figure 57. operational amplifier noise analysis model all resistors have johnson noise that is calculated by )4( kbtr where: k is boltzmanns constant (1.38 10 C23 j/k). b is the bandwidth in hertz. t is the absolute temperature in kelvin. r is the resistance in ohms. a simple relationship that is easy to remember is that a 50 resistor generates a johnson noise of 1 nv/ ? hz at 25c. in applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. each resistor is a noise source. attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. a summary of noise performance for the amplifier and associated resistors can be seen in table 9. circuit considerations careful and deliberate attention to detail when laying out the ada4857 board yields optimal performance. power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. pcb layout because the ada4857 can operate up to 850 mhz, it is essential that rf board layout techniques be employed. all ground and power planes under the pins of the ada4857 must be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. a single mounting pad on the soic footprint can add as much as 0.2 pf of capacitance to ground if the ground plane is not cleared from under the mounting pads. the low distortion pinout of the ada4857 increases the separation distance between the inputs and the supply pins, which improves the second harmonics. in addition, the feedback pin reduces the distance between the output and the inverting input of the amplifier, which helps minimize the parasitic inductance and capacitance of the feedback path, reducing ringing and peaking. power supply bypassing power supply bypassing for the ada4857 was optimized for frequency response and distortion performance. figure 49 shows the recommended values and location of the bypass capacitors. the 0.1 f bypassing capacitors must be placed as close as possible to the supply pins. power supply bypassing is critical for stability, frequency response, distortion, and psr performance. the capacitor between the two supplies helps improve psr and distortion performance. the 10 f electrolytic capacitors must be close to the 0.1 f capacitors; however, it is not as critical. in some cases, additional paralleled capacitors can help improve frequency and transient response. grounding ground and power planes must be used where possible. ground and power planes reduce the resistance and inductance of the power planes and ground returns. the returns for the input, output terminations, bypass capacitors, and r g must all be kept as close to the ada4857 as possible. the output load ground and the bypass capacitor grounds must be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. the ada4857 lfscp packages feature an exposed paddle. for optimum electrical and thermal performance, solder this paddle to the ground plane or the power plane. for more information on high speed circuit design, see a practical guide to high-speed printed-circuit- board layout at www.analog.com. gain from b to output = ? r2 r1 gain from a to output = noise gain = ng = 1 + i n? v n v n, r1 v n, r3 r1 r2 i n+ r3 4ktr2 4ktr1 4ktr3 v n, r2 b a v n 2 + 4ktr3 + 4ktr1 r2 2 r1 + r2 i n+ 2 r3 2 + i n? 2 r1 r2 2 + 4ktr2 r1 2 r1 + r2 r1 + r2 rti noise = rto noise = ng rti noise v out + 0 7040-073 r2 r1
ada4857-1/ada4857-2 data sheet rev. d | page 20 of 21 outline dimensions figure 58. 8-lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp-8-13) dimensions shown in millimeters figure 59. 8-lead standard small outline package [soic_n] (r-8) dimensions shown in millimeters and (inches) top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.55 1.45 1.35 1.84 1.74 1.64 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 12-07-2010-a p i n 1 i n d i c a t o r ( r 0 . 1 5 ) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10
data sheet ada4857-1/ada4857-2 rev. d | page 21 of 21 figure 60. 16-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.75 mm package height (cp-16-23) dimensions shown in millimeters ordering guide model 1 temperature range package description pack age option ordering quantity branding ada4857-1ycpz-r2 C40c to +125c 8-lead lfcsp cp-8-13 250 h15 ada4857-1ycpz-rl C40c to +125c 8-lead lfcsp cp-8-13 5,000 h15 ada4857-1ycpz-r7 C40c to +125c 8-lead lfcsp cp-8-13 1,500 h15 ada4857-1yrz C40c to +125c 8-lead soic_n r-8 98 ada4857-1yrz-r7 C40c to +125c 8-lead soic_n r-8 2,500 ada4857-2ycpz-r2 C40c to +125c 16-lead lfcsp cp-16-23 250 ada4857-2ycpz-rl C40c to +125c 16-lead lfcsp cp-16-23 5,000 ada4857-2ycpz-r7 C40c to +125c 16-lead lfcsp cp-16-23 1,500 ADA4857-2YCP-EBZ evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-220-wggc. 111908-a 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.70 0.60 0.50 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 2.25 2.10 sq 1.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. ?2008C2017 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07040-0-1/17(d)

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