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? semiconductor components industries, llc, 2016 august, 2016 ? rev. 2 1 publication order number: ncv7708f/d ncv7708f double hex driver the ncv7708f is a fully protect ed hex half bridge driver designed specifically for automotive and industrial motion control applications. the six low and high side drivers are freely configurable and can be controlled separately. this allows for high side, low side, and h?bridge control. h?bridge control provides forward, reverse, brake, and high impedance states. the drivers are controlled via a standard spi interface. features ? ultra low quiescent current sleep mode ? six independent high?side and six independent low?side drivers ? integrated freewheeling protection (ls and hs) ? internal upper and lower clamp diodes ? configurable as h?bridge drivers ? r ds(on) = 0.6 (typ) ? 5 mhz spi control ? spi valid frame detection ? compliance with 5 v and 3.3 v systems ? overvoltage lockout ? undervoltage lockout ? fault reporting ? current limit ? overtemperature protection ? internally fused lead in soic?28 ? ssop?24 nb epad ? these are pb?free devices typical applications ? automotive ? industrial ? dc motor management device package shipping ? a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package marking diagrams soic?28 dw suffix case 751f www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. ncv7708f awlyywwg ncv7708fdwr2g* soic?28w (pb?free) 1000 / tape & reel ssop?24 nb ep dq suffix case 940ak ncv7708f awlyywwg ordering information NCV7708FDQR2G ssop?24n (pb?free) 1000 / tape & reel *contact your local sales representative for the ncv7708f device availability in soic?28 package .
ncv7708f www. onsemi.com 2 figure 1. block diagram undervoltage lockout overvoltage lockout vs cp drive 2 vs cp drive 3 vs cp drive 4 vs cp drive 5 vs cp drive 6 gnd outh2 outl2 outh3 outl3 outh4 outl4 outh5 outl5 outh6 outl6 vs cp vs2 vs1 vs2 vs1 vs2 16 bit logic and latch spi csb sclk si so v cc en fault detect logic bias enable por charge pump control logic outh1 waveshaping drive 1 vs high?side driver low?side driver outl1 waveshaping spi control thermal warning/shutdown overcurrent under?load fault analog bias vs1 vs1? vs2? vrail vrail vrail
ncv7708f www. onsemi.com 3 figure 2. pin connection 1 gnd gnd gnd gnd gnd gnd csb vs2 sclk outl4 si outh4 outl6 outh5 outh6 outl5 gnd gnd v cc vs1 en so outl1 outh1 outh3 outl3 outl2 outh2 soic?28 1 gnd gnd gnd gnd csb vs2 sclk outl4 si outh4 outl6 outh5 outh6 outl5 v cc vs1 en so outl1 outh1 outh3 outl3 outl2 outh2 ssop?24 pin description pin no. symbol description ssop?24 soic?28 1 1 outl5 output low side 5. open drain output driver with internal reverse diode. 2 2 outh5 output high side 5. open source output driver with internal reverse diode. drain connected to vs2?. 3 3 outh4 output high side 4. open source output driver with internal reverse diode. drain connected to vs2?. 4 4 outl4 output low side 4. open drain output driver with internal reverse diode. 5 5 vs2 power supply input for the high?side output drivers 4, 5, and 6. 6 6 gnd ground 7 7 gnd ground ? 8 gnd ground ? 9 gnd ground 8 10 vs1 power supply input for the high?side output drivers 1, 2, and 3 9 11 outl3 output low side 3. open drain output driver with internal reverse diode. 10 12 outh3 output high side 3. open source output driver with internal reverse diode. drain connected to vs1?. 11 13 outh2 output high side 2. open source output driver with internal reverse diode. drain connected to vs1?. 12 14 outl2 output low side 2. open drain output driver with internal reverse diode. 13 15 outh1 output high side 1. open source output driver with internal reverse diode. drain connected to vs1?. 14 16 outl1 output low side 1. open drain output driver with internal reverse diode. 15 17 en enable. input high wakes the ic up from sleep mode. 16 18 so serial output. 16 bit serial communications output. 17 19 v cc power supply input for logic. 18 20 gnd ground 19 21 gnd ground ? 22 gnd ground ? 23 gnd ground 20 24 csb chip select bar. active low serial port operation. 21 25 sclk serial clock. clock input for use with spi communication. 22 26 si serial input. 16 bit serial communications input. 23 27 outl6 output low side 6. open drain output driver with internal reverse diode. 24 28 outh6 output high side 6. open source output driver with internal reverse diode. drain connected to vs2?.
ncv7708f www. onsemi.com 4 maximum ratings rating value unit power supply voltage (vs1, vs2) (dc) (ac), t < 500 ms, ivsx > ?2 a ?0.3 to 40 ?1.0 v output pin outhx (dc) (ac ? inductive clamping) ?0.3 to 40 ?8.0 v output pin outlx (dc) (ac), t < 500 ms, ioutlx > ?2 a (ac inductive clamping) ?0.3 to 36 ?1.0 45 v pin voltage (logic input pins, si, sclk, csb, so, en, v cc ) ?0.3 to 5.5 v output current (outl1, outl2, outl3, outl4, outl5, outl6, outh1, outh2, outh3, outh4, outh5, outh6) (dc) vds = 12 v (dc) vds = 20 v (dc) vds = 40 v (ac) vds = 12 v, (50 ms pulse, 1 s period) (ac) vds = 20 v, (50 ms pulse, 1 s period) (ac) vds = 40 v, (50 ms pulse, 1 s period) ?1.5 to 1.5 ?0.7 to 0.7 ?0.25 to 0.25 ?2.0 to 2.0 ?0.9 to 0.9 ?0.3 to 0.3 a electrostatic discharge, human body model, vs1, vs2, outx (note 1) 4.0 kv electrostatic discharge, human body model, all other pins 2.0 kv electrostatic discharge, machine model 200 v electrostatic discharge, charged device model 1.0 kv short circuit reliability characterization (aec?q10x) grade a ? operating junction temperature ?40 to 150 c storage temperature range ?55 to 150 c moisture sensitivity level soic?28 ssop?24 epad msl 3 msl 2 ? peak reflow soldering temperature: pb?free, 60 to 150 seconds at 217 c (note 2) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. tested with a vs1/vs2 power supply common point. 2. for additional information, please see or download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. thermal conditions thermal parameters test conditions, typical value unit board details (note 3) board details (note 4) soic?28 junction?to?lead (psi?jl8, jl8 ) or pins 6?9, 20?23 10 11 c/w junction?to?ambient (r ja , ja ) 78 63 c/w ssop?24 epad junction?to?board (r b ) ? 2 c/w junction?to?ambient (r ja ) ? 54 c/w junction?to?lead (r jl ) ? 7 c/w 3. 1?oz copper, 240 mm 2 copper area, 0.062 thick fr4. this is the minimum pad board size. 4. 1?oz copper, 986 mm 2 copper area, 0.062 thick fr4.
ncv7708f www. onsemi.com 5 recommended operating conditions rating symbol value unit min max digital supply input voltage (v cc ) v ccmax 3.15 5.25 v battery supply input voltage (v s ) v smax 5.5 28 v dc output current (i(outlx), i(outhx)) dc max ? 0.5 a junction temperature t j ?40 150 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. electrical characteristics (?40 c < t j < 150 c, 5.5 v < vsx < 40 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic symbol test conditions min typ max unit general supply current (vs1 + vs2) sleep mode (note 5) i vs_sleep vs1 = vs2 = 13.2 v, v cc = csb = 5 v, en = si = sclk = 0 v (?40 c to 85 c) ? 1.0 2.5 a supply current (vs1) active mode i vs1_act en = v cc , 5.5 v < vsx < 35 v no load ? 1.25 2.5 ma supply current (v cc ) ? sleep mode (note 5) i vcc_sleep csb = v cc , en = si = sclk = 0 v (?40 c to 85 c) ? 1.0 2.5 a supply current (v cc ) ? active mode i vcc_act en = csb = v cc , si = sclk = 0 v ? 1.5 3.0 ma supply current (vs2) active mode i vs2_act en = v cc , 5.5 v < vsx < 35 v no load ? 1.25 2.5 ma v cc power?on?reset threshold v ccpor ? 2.55 2.9 v vsx undervoltage detection threshold v suv vsx decreasing 3.7 4.1 4.5 v vsx undervoltage detection hysteresis v suv_hys 100 365 450 mv vsx overvoltage detection threshold v sov vsx increasing 33 36.5 40.0 v vsx overvoltage detection hysteresis v sov_hys 1 2.5 4.0 v thermal warning (note 6) t tw 120 140 170 c thermal warning hysteresis (note 6) t tw_hys ? 20 ? c thermal shutdown (note 6) t tsd 155 175 195 c ratio of thermal shutdown to thermal warning (note 6) t tsd /t tw 1.05 1.20 ? ? outputs output high r ds(on) (source and sink) r dson_src r dson_snk i out = ?500 ma 25 c ?40 c < t j < 150 c ? ? 0.6 ? 1.3 1.7 source leakage current i src outh(1?6) = 0 v, vsx = 40 v, v cc = 5 v outh(1?6) = 0 v, vsx = 13.2 v, v cc = 5v ?5.0 ?1.0 ? ? ? ? a product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. for temperatures above 85 c, refer to graphs for vsx and v cc sleep current vs. temperature on page 17. 6. thermal characteristics are not subject to production test. 7. refer to ?typical high?side negative clamp voltage? graph on page 17. 8. current limit is active with and without overcurrent detection. 9. not production tested.
ncv7708f www. onsemi.com 6 electrical characteristics (?40 c < t j < 150 c, 5.5 v < vsx < 40 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic unit max typ min test conditions symbol outputs sink leakage current i snk outl(1?6) = 34 v, v cc = 5 v outl(1?6) = 34 v, v cc = 5 v, t = 25 c ? ? ? ? 5.0 1.0 a power transistor body diode forward voltage v bd_fwd i f = 500 ma ? 0.9 1.3 v high?side clamping voltage (note 7) v clp_hs i (outhx) = ?50 ma ? ? ?0.7 v low?side clamping voltage v clp_ls i (outlx) = 50 ma 36 ? 45 v under load under load detection threshold (outlx) i ul_ls v cc = 5 v, vsx = 13.2 v 2.0 8.0 16 ma under load detection threshold (outhx) i ul_hs v cc = 5 v, vsx = 13.2 v ?16 ?8.0 ?2.0 ma under load detection delay time t ul_del v cc = 5 v, vsx = 13.2 v 200 350 600 s overcurrent overcurrent shutdown threshold (outhx) i ocsd_hs v cc = 5 v, vsx = 13.2 v, bit13 = 1 ?2.0 ?1.45 ?1.1 a overcurrent shutdown threshold (outlx) i ocsd_ls v cc = 5 v, vsx = 13.2 v, bit13 = 1 1.1 1.45 2.0 a overcurrent shutdown delay time t ocsd_0 t ocsd_1 v cc = 5 v, vsx = 13.2 v, bit13 = 0 bit13 = 1 80 10 200 25 400 50 s s current limit (note 8) current limit (outhx) i lim_hs v cc = 5 v, vsx = 13.2 v ?5.0 ?3.0 ?2.0 a current limit (outlx) i lim_ls v cc = 5 v, vsx = 13.2 v 2.0 3.0 5.0 a logic inputs (en, si, sclk, csb ) input threshold ? high input threshold ? low v inth 2.0 ? ? ? ? 0.8 v input hysteresis (si, sclk, csb) v inhys_spi 100 300 600 mv input hysteresis (en) v inhys_en 100 400 800 mv pull?down resistance (en, si, sclk) r pd en = si = sclk = v cc 50 125 250 k pull?up resistance (csb) r pu csb = 0 v 50 125 250 k input capacitance (note 9) c in ? 10 15 pf logic output (so) output high v soh i out = 1 ma v cc ? 1.0 v cc ? 0.7 ? v output low v sol i out = ?1.6 ma ? 0.2 0.4 v tri?state leakage i so csb = v cc , 0 v < so < v cc ?10 ? 10 a tri?state input capacitance (note 9) c so csb = v cc , 0 v < v cc < 5.25 v ? 10 15 pf timing specifications high side turn on time t hson vs = 13.2 v, r load = 25 ? 7.5 13 s high side turn off time t hsoff vs = 13.2 v, r load = 25 ? 3.0 6.0 s low side turn on time t lson vs = 13.2 v, r load = 25 ? 6.5 13 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. for temperatures above 85 c, refer to graphs for vsx and v cc sleep current vs. temperature on page 17. 6. thermal characteristics are not subject to production test. 7. refer to ?typical high?side negative clamp voltage? graph on page 17. 8. current limit is active with and without overcurrent detection. 9. not production tested.
ncv7708f www. onsemi.com 7 electrical characteristics (?40 c < t j < 150 c, 5.5 v < vsx < 40 v, 3.15 v < v cc < 5.25 v, en = v cc , unless otherwise specified) characteristic unit max typ min test conditions symbol timing specifications low side turn off time t lsoff vs = 13.2 v, r load = 25 ? 2.0 5.0 s high side rise time t hsr vs = 13.2 v, r load = 25 ? 4.0 8.0 s high side fall time t hsf vs = 13.2 v, r load = 25 ? 2.0 3.0 s low side rise time t lsr vs = 13.2 v, r load = 25 ? 1.0 2.0 s low side fall time t lsf vs = 13.2 v, r load = 25 ? 1.0 3.0 s non?overlap time t hsofflson high side turn off to low side turn on 1.5 ? ? s non?overlap time t lsoffhson low side turn off to high side turn on 1.5 ? ? s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. for temperatures above 85 c, refer to graphs for vsx and v cc sleep current vs. temperature on page 17. 6. thermal characteristics are not subject to production test. 7. refer to ?typical high?side negative clamp voltage? graph on page 17. 8. current limit is active with and without overcurrent detection. 9. not production tested. electrical characteristics (?40 c < t j < 150 c, 5.5 v < vsx < 40 v, en = v cc = 5 v, unless otherwise specified) characteristic conditions symbol min typ max unit serial peripheral interface (v cc = 5 v) sclk frequency f sclk ? ? 5.0 mhz sclk clock period v cc = 5 v v cc = 3.3 v t sclk 200 500 ? ? ? ? ns sclk high time t clkh 85 ? ? ns sclk low time t clkl 85 ? ? ns sclk setup time t clksu1 t clksu2 85 85 ? ? ? ? ns si setup time t sisu 50 ? ? ns si hold time t siht 50 ? ? ns csb setup time t csbsu1 t csbsu2 100 100 ? ? ? ? ns csb high time (note 10) t csbht 5.0 ? ? s so enable after csb falling edge t socsbf ? ? 200 ns so disable after csb rising edge t socsbr ? ? 200 ns so rise time (10% to 90%) c load = 40 pf t sorise ? 10 25 ns so fall time (90% to 10%) c load = 40 pf t sofall ? 10 25 ns so valid time (note 11) sclk high to so 50% t sov ? 50 100 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 10. this is the minimum time the user must wait between spi commands. 11. not tested in production
ncv7708f www. onsemi.com 8 figure 3. spi timing diagram csb so tsocsbf tsocsbr si so sclk tiht tisu tsov csb sclk tclksu1 tclkh tclkl tcsbsu1 tclksu2 tcsbht tcsbsu2 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
ncv7708f www. onsemi.com 9 spi communication standard 16?bit communication has been implemented for the communication of this ic to turn drivers on and off, and to report faults. (reference the spi communication frame format diagram). the lsb (least significant bit) is clocked in first. for spi communication, the device must first be enabled (en = high). the spi inputs are ttl compatible and the so output high level is defined by the applied vcc. the active-low csb input has a pull?up resistor. spi communication is active when csb is low. providing a pull-up resistor insures the communication bus is not active should the communication link between the microcontroller and ncv7708f become open. sclk and si have pull?down resistors. this provides known states when the spi is not active. communication is implemented as follows: 1. csb goes low to allow serial data transfer. 2. a 16 bit word is clocked (sclk) into the si (serial input) pin. the si input signal is latched on the falling edge of sclk. 3. current so data is simultaneously shifted out on every rising edge of sclk starting with the lsb (tw). 4. csb goes high to transfer the clocked in information to the data registers. (note: so is tristate when csb is high.) 5. the si data will be accepted when a valid spi frame is detected. a valid spi frame consists of the above conditions and a complete set of multiples of 16 bit words. invalid frames are ignored with previous input data intact. figure 4. spi communication frame format srr out l1 out h1 out l2 out h2 out l3 out h3 out l4 out h4 out l5 out h5 out l6 out h6 ocd uld ovlo uld old out h6 out l6 out h5 out l5 out h4 out l4 out h3 out l3 out h2 out l2 out h1 out l1 tw psf csb si sclk so lsb msb 0123456789101112131415
ncv7708f www. onsemi.com 10 the table below defines the programming bits and diagnostic bits. fault information is sequentially clocked out the so pin of the ncv7708f as programming information is clocked into the si pin of the device. daisy chain communication between spi compatible ic?s is possible by connection of the serial output pin (so) to the input of the sequential ic (si). input data bit # bit description bit status 15 overvoltage lock out control (ovlo) 0 = disable 1 = enable 14 under load detection shut down control (uld) 0 = disable 1 = enable 13 overcurrent detection shut down control (ocd) 0 = 200 sec 1 = 25 sec 12 outh6 0 = off 1 = on 11 outl6 0 = off 1 = on 10 outh5 0 = off 1 = on 9 outl5 0 = off 1 = on 8 outh4 0 = off 1 = on 7 outl4 0 = off 1 = on 6 outh3 0 = off 1 = on 5 outl3 0 = off 1 = on 4 outh2 0 = off 1 = on 3 outl2 0 = off 1 = on 2 outh1 0 = off 1 = on 1 outl1 0 = off 1 = on 0 status register reset (srr) 0 = no reset 1 = reset output data bit # bit description bit status 15 power supply fail signal (ovlo or uvlo = psf) 0 = no fault 1 = fault 14 under load detect signal (uld) 0 = no fault 1 = fault 13 over load detect signal (old) 0 = no fault 1 = fault 12 outh6* 0 = off 1 = on 11 outl6* 0 = off 1 = on 10 outh5* 0 = off 1 = on 9 outl5* 0 = off 1 = on 8 outh4* 0 = off 1 = on 7 outl4* 0 = off 1 = on 6 outh3* 0 = off 1 = on 5 outl3* 0 = off 1 = on 4 outh2* 0 = off 1 = on 3 outl2* 0 = off 1 = on 2 outh1* 0 = off 1 = on 1 outl1* 0 = off 1 = on 0 thermal warning (tw) 0 = not in tw 1 = in tw *output bits [1:12] represent the state of the designated outputs. status register reset ? srr sending srr = 1 clears status memory and reactivates faulted output. the previous si data pattern must be sent with srr to preserve device configuration and output states. srr takes effect at the rising edge of csb. if a fault is still present when srr is sent, protection can be re?engaged and shutdown can recur. the device can also be reset by toggling the en pin or by vcc power-on reset. when asserted, all latched faults are cleared (tw, old, uld, and psf).
ncv7708f www. onsemi.com 11 characteristic timing diagrams ls turn off hs turn on csb tlsoff tlstr thstr tlsoffhson thson hs turn off ls turn on csb thsoff tlson tlstf thstf thsofflson 10% 10% 10% 10% 90% 90% 90% 90% 50% figure 5. detailed driver timing 50% 50% 50% 50% 50%
ncv7708f www. onsemi.com 12 detailed operating description general the ncv7708f double hex driver provides drive capability for three independent h?bridge configurations, or 6 high side configurations with 6 low side configurations, or any combination of arrangements. each output drive is characterized for a 500 ma load and has a typical 1.0 a surge capability (at 13.2 v). strict adherence to integrated circuit die temperature is necessary. maximum die temperature is 150 c. this may limit the number of drivers enabled at one time. output drive control and fault reporting is handled via the spi (serial peripheral interface) port. sleep mode an enable function (en = low) provides a low quiescent sleep current mode when the device is not being utilized. no data is stored when the device is in sleep mode. input impedance a pull down resistor is provided on the en input to ensure the device is off if the input signal is lost. pull down resistors are also provided on the si and sclk inputs. a pull up resistor is provided for the csb input for the same reason. a loss of signal pulls the csb input high to stop any spurious signals into the spi port. power up/down control an undervoltage lockout circuit prevents the output drivers from turning on unintentionally. this control is provided by monitoring the voltages on the vs1, vs2, and v cc pins. each analog power pin (vs1 or vs2) powers their respective high?side output drivers and supporting charge pump. vs1 powers outh1, outh2, and outh3. vs2 powers outh4, outh5, and outh6. all low?side drivers are powered by vrail via v cc . all drivers are initialized in the off (high impedance) condition. power up sequencing of v cc , vs1, and vs2 is up to the user. the voltage on vs1 and vs2 should be operated at the same potential. if the vsx supply moves into either of the vs under voltage or overvoltage regions (with (ovlo = 1), the output drivers are switched to high z, but command and status data is preserved. internal power?up circuitry on the logic supply pin supports a smooth turn on transition. v cc power up resets the internal logic such that all output drivers will be off as power is applied. exceeding the under voltage lockout threshold on v cc allows info rmation to be input through the spi port for turn on control. logic information remains intact over the entire vs1 and vs2 voltage range. current limit outx current is limited per the current limit electrical parameter for each driver. the magnitude of the current has a minimum specification of 2 a at v cc = 5 v and vsx = 13.2 v. the output is protected for high power conditions during current limit by thermal shutdown and the overcurrent detection shutdown function. overcurrent detection shutdown protects the device during current limit because the overcurrent threshold is below the current limit threshold. the overcurrent detection shutdown control timer is initiated at the overcurrent shutdown threshold which starts before the current limit is reached. note: high currents will cause a rise in die temperature. devices will not be allowed to turn on if the die temperature exceeds the thermal shutdown temperature. overcurrent shutdown (bit13 = 1) effected outputs will turn off when the overcurrent shutdown threshold has been breached for the overcurrent shutdown delay time. the respective old status bit will be set to a ?1? and the driver will latch off. the driver can only be turned back on via the spi port with a spi command that includes an srr = 1. note: high currents will cause a rise in die temperature. devices will not be allowed to turn on if the die temperature exceeds the thermal shutdown temperature. overcurrent detection shut down ocd input bit 13 outx ocd condition output data bit 13 over load detect (old) status outx status current limit of all drivers 0 0 0 unchanged 3 a (typ.) 0 1 1 (need srr to reset) outx latches off after 200 s (typ.) (need srr to reset) 3 a (typ.) 1 0 0 unchanged 3 a (typ.) 1 1 1 (need srr to reset) outx latches off after 25 s (typ.) (need srr to reset) 3 a (typ.)
ncv7708f www. onsemi.com 13 overcurrent detection shut down control timer there are two protection mechanisms for output current, overcurrent and current limit. 1. current limit ? always active with a typical threshold of 3 a. 2. overcurrent detection ? selectable shutdown time via bit 13 with a typical threshold of 1.45 a. figure 6 shows the typical performance of a part which has exceeded the 1.45 a overcurrent detection threshold and started the shutdown control timer. when bit 13 = 1, the shutdown time is 25 sec. when bit 13 = 0, the shutdown time is 200 sec. once an overcurrent shutdown delay time event has been detected by the ncv7708f, the timer setting cannot be interrupted by an attempted change via a spi command of bit 13. input bit 13 overcurrent shutdown delay time 0 200 sec 1 25 sec figure 6. output current shutdown control 3 a 1.45 a 3 a 1.45 a outx current bit13 = 1 outx current bit13 = 0 200 sec 25 sec (current limit) (overcurrent) (current limit) (overcurrent)
ncv7708f www. onsemi.com 14 under load detection the under?load detection is accomplished by monitoring the current from each output driver. a minimum load current (this is the maximum detection threshold) is required when the drivers are turned on. if the under?load circuit detection threshold has been crossed for more than the under?load delay time, the bit indicator (output bit #14) will be set to a 1. in addition, the offending driver will be turned off only if input bit 14 (uld) is set to 1 (true). the ncv7708f uses a global under load timer. an under load condition starts the global under load delay timer. if under load occurs in another channel after the global timer has been started, the delay for any subsequent under load will be the remainder of the initially started timer. the timer runs continuously with any persistent under load condition. the under load detect bit is reset by setting input data bit 0, srr = 1. under load detection shut down uld input bit 14 outx uld condition output data bit 14 under load detect (uld) status outx status 0 0 0 unchanged 0 1 1 (need srr to reset) unchanged 1 0 0 unchanged 1 1 1 (need srr to reset) outx latches off (need srr to reset) undervoltage lockout (psf) undervoltage shutdown circuitry monitors the voltage on the vs1 and vs2 pins. when the undervoltage threshold level has been breached on both or either one of the vsx supply inputs, output bit 15 (psf) will be set and all outputs will turn off. turn on/off status is maintained in the logic circuitry. when proper input voltage levels are re?established, the programmed outputs will return to programmed operation. the power supply fail bit is reset by setting input data bit 0, srr = 1. undervoltage lock out (uvlo) shut down vsx uvlo condition output data bit 15 power supply fail (psf) status outx status 0 0 unchanged 1 1 (need srr to reset) all outputs off (remain off until vsx is out of uvlo) overvoltage shutdown (psf) overvoltage shutdown circuitry monitors the voltage on the vs1 and vs2 pins. when the overvoltage threshold voltage level has been breached on both or either one of the vsx supply inputs, output bit 15 will be set and, if input bit 15 (ovlo) is set to 1, all drivers will turn off. turn on/off status is main tained in the logic circuitry. when proper input voltage levels are re?established, the programmed outputs will turn back on. overvoltage shutdown can be disabled by using the spi input bit 15 (ovlo = 0). the power supply fail bit is reset by setting input data bit 0, srr = 1. overvoltage lock out (ovlo) shut down ovlo in- put bit 15 vsx ovlo condition output data bit 15 power supply fail (psf) status outx status 0 0 0 unchanged 0 1 1 (need srr to reset) unchanged 1 0 0 unchanged 1 1 1 (need srr to reset) all outputs latch off while in ovlo return to programmed state out of ovlo
ncv7708f www. onsemi.com 15 thermal shutdown six independent thermal shutdown circuits are featured (one common sensor for each hs and ls transistor pair). each sensor has two levels, one to give a thermal w arning (tw) and a higher one, thermal shutdown, which will shut the drivers off. when the part reaches the temperature point of thermal warning, the output data bit 0 (tw) will be set to a 1, and the outputs will remain on. with one or more sensors detecting the thermal shutdown level, all channels will be turned off simultaneously. all outputs will return to normal operation when the part thermally recovers (thermal toggling), because the thermal shutdown does not change the channel selection. the output data bit 0, thermal warning, will latch and remain set, even after cooling, and is reset by using a software command to input bit 0 (srr = 1). since thermal warning precedes a thermal shutdown, software polling of this bit will allow for load control and possible prevention of thermal shutdown conditions. thermal warning information can be retrieved immediately without performing a complete spi access cycle. figure 7 displays how this is accomplished. bringing the csb pin from a 1 to a 0 with si = 0 immediately displays the information on output data bit 0, thermal warning. as the temperature of the ncv7708f changes from a condition from below the thermal warning threshold to above the thermal warning threshold, the state of the so pin changes and this level is available immediately when the csb goes to 0. a 0 on so indicates there is no thermal warning, while a 1 indicates the ic is above the thermal warning threshold. this warning bit is reset by setting input data bit 0, srr = 1. csb sclk so csb sclk so twh ntw no thermal warning thermal warning high tristate level tristate level figure 7. access to temperature warning information shows the thermal information is available immediately with activation of the csb signal without having to toggle the sclk line.
ncv7708f www. onsemi.com 16 applications drawing the applications drawing below displays the range with which this part can drive a multitude of loads. 1. h?bridge driver configuration 2. low side driver 3. high side driver figure 8. application drawing m vsx outhx outlx gnd vsx outhx outlx gnd 1 3 vsx outhx outlx gnd 2 c emc1 10 nf (optional) c emc2 10 nf (optional) c emc3 10 nf (optional) c emc4 10 nf (optional) v bat c in reverse battery diode any combination of h?bridge, high?side, or low?side drivers can be designed in. this allows for flexibility in many systems. h?bridge driver configuration the ncv7708f has the flexibility of controlling each driver independently. when the device is set up in an h?bridge configuration, the software design has to take care of avoiding simultaneous activation of connected hs and ls transistors. resulting high shoot through currents could cause irreversible damage to the device. overvoltage clamping ? driving inductive loads to avoid excessive voltages when driving inductive loads in a single?side?mode (ls or hs switch, no freewheeling path), the ncv7708f provides internal clamping diodes. thus any load type can be driven without the requirement of external freewheeling diodes. due to high power dissipation during clamping, the maximum energy capability of the driver transistor has to be considered.
ncv7708f www. onsemi.com 17 typical operating characteristics figure 9. high?side negative clamp voltage vs. reverse current figure 10. v cc sleep supply current vs. temperature high side pin voltage (v) high side current (a) t j , temperature ( c) v cc sleep current ( a) figure 11. low?side clamping voltage vs. temperature t j , temperature ( c) low side clamping voltage (v) 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?50 ?30 ?10 10 30 50 70 90 110 130 150 1.8 2.0 v cc = 5.25 v 36 37 38 39 40 41 42 43 44 ?50 ?30 ?10 10 30 50 70 90 110 130 150 45 i out = 50 ma figure 12. vs1 + vs2 sleep current vs. temperature t j , temperature ( c) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?50 ?30 ?10 10 30 50 70 90 110 130 150 1.8 2.0 vs1 + vs2 sleep current ( a) t a = 25 c
ncv7708f www. onsemi.com 18 table 1. fault handling fault fault memory serial output bit driver condition during fault driver condition after parameters within specified limits output register clear requirement current limit 3 a (input ocd bit 13 = 0)* latched offending driver is latched off after 200 sec offending driver is latched off valid spi frame with srr set to 1 over load 1.45 a (input ocd bit 13 = 1)* latched offending driver is latched off by overcurrent timer after 25 sec offending driver is latched off valid spi frame with srr set to 1 under load (input uld bit 14 = 0) latched unchanged unchanged valid spi frame with srr set to 1 under load (input uld bit 14 = 1) latched offending driver is latched off after 350 sec offending driver is latched off valid spi frame with srr set to 1 falls below power supply fail (ovlo) latched output driver on bit 15 = 0 outputs return to their previous programmed state psf bit is cleared when vsx falls below the hysteresis voltage level and srr set to 1 output driver switched to high z bit 15 = 1 outputs return to their previous programmed state psf bit is cleared when vsx falls below the hysteresis voltage level and srr set to 1 power supply fail (uvlo) latched output driver switched to high z return to programmed state valid spi frame with srr set to 1 thermal warning (tw) latched output driver on drivers in normal operation valid spi frame with srr set to 1 thermal shutdown no thermal shutdown bit all drivers turns off return to programmed state no thermal shutdown bit all specified currents and times refer to typical numbers. *current limit performance is independent of overcurrent (bit13). the output will always limit to current limit independent of bit 13.
ncv7708f www. onsemi.com 19 figure 13. soic?28 ja vs. copper spreader area copper heat spreader area (sqmm) ja ( c/w) 160 140 120 100 80 60 40 20 0 0 100 1000 900 200 300 400 800 700 600 500 1 oz 2 oz figure 14. ssop24 narrow body exposed pad ja vs. copper spreader area copper heat spreader area (sqmm) ja ( c/w) 160 140 120 100 80 60 40 20 0 0 100 1000 900 200 300 400 800 700 600 500 1 oz 2 oz 100 90 80 70 60 50 40 30 20 10 0 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) r(t) ( c/w) figure 15. soic 28?lead single pulse heating curve 50 sqmm 500 sqmm 100 sqmm 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) r(t) ( c/w) figure 16. soic 28?lead thermal duty cycle curve on 986 mm 2 spreader test board 10 1 50% duty cycle 20% 10% 5% 2% 1% single pulse
ncv7708f www. onsemi.com 20 180 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) r(t) ( c/w) figure 17. ssop24 narrow body exposed pad single pulse heating curve 160 140 120 100 80 60 40 20 0 50 sqmm 100 sqmm 500 sqmm 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) r(t) ( c/w) figure 18. ssop24 lead single pulse heating curve 100 10 1 0.1 0.01 50% duty cycle 20% 10% 5% 2% 1% single pulse
ncv7708f www. onsemi.com 21 package dimensions soic?28 wb case 751f?05 issue h a1 1 15 14 28 b s x m 0.025 y s t m 0.25 y m seating plane a dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 g 1.27 bsc h 10.05 10.55 l 0.41 0.90 m 0 8 l c pin 1 ident d e h 0.10 ?x? ?y? g ?t? m notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold protrusion 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable damber pr5otrusion shall not be 0.13 totatl in excess of b dimension at maximum material condition. 11.00 28x 0.52 28x 1.30 1.27 dimensions: millimeters 1 pitch soldering footprint* 28 14 15 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
ncv7708f www. onsemi.com 22 package dimensions ssop24 nb ep case 940ak issue o dim min max millimeters a 1.70 a1 0.00 0.10 l 0.40 0.85 e 0.65 bsc c 0.09 0.20 h 0.25 0.50 b 0.19 0.30 l2 0.25 bsc m 0 8 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. dambar protrusion shall be 0.10 max. at mmc. dambar cannot be located on the lower radius of the foot. dimension b applies to the flat section of the lead between 0.10 to 0.25 from the lead tip. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension d is determined at datum plane h. 5. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimension e1 is determined at da- tum plane h. 6. datums a and b are determined at datum plane h. 7. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 8. contours of the thermal pad are un- controlled within the region defined by dimensions d2 and e2. pin 1 reference 0.10 seating plane 24x b e detail a --- soldering footprint l l2 gauge detail a e1 3.90 bsc plane seating plane c c h end view a-b m 0.12 d c top view side view a-b 0.20 c 112 24 a b d 2x 12 tips a1 a2 c c 24x d 8.64 bsc e 6.00 bsc 24x 1.15 24x 0.40 0.65 dimensions: millimeters pitch 6.40 1 2x a m 13 0.20 c 0.20 c 2x 0.10 c recommended a2 1.65 1.10 e e1 d note 5 note 6 note 6 note 4 a-b m 0.15 d c bottom view e2 note 8 d2 note 8 a-b m 0.15 d c 2.84 5.63 d2 5.28 5.58 e2 2.44 2.64 l1 1.00 ref h a1 note 7 l1 h on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7708f/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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