note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: for existing customer transition, and for new customers or new appli- cations, refer to your allegro sales representative. 8-bit serial input dmos power driver A6595 date of status change: may 3, 2010 these parts are no longer in production the device should not be purchased for new design applications. samples are no longer available. discontinued product
description the A6595 combines an 8-bit cmos shift register and accompanying data latches, control circuitry, and dmos power driver outputs. power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. the serial-data input, cmos shift register and latches allow direct interfacing with microprocessor-based systems. serial- data input rates are over 5 mhz. use with ttl may require appropriate pull-up resistors to ensure an input logic high. a cmos serial-data output enables cascade connections in applications requiring additional drive lines. the A6595 dmos open-drain outputs are capable of sinking up to 750 ma. all of the output drivers are disabled (the dmos sink drivers turned off) by the output enable input high. the A6595 is furnished in a 20-pin dual in-line plastic package that is lead (pb) free, with 100% matte tin leadframe plating. copper leadframe base material, reduced supply current requirements, and low on-state resistance allow the device to sink 150 ma from all outputs continuously, to ambient temperatures to 125c. 26185.120a features and benefits ? 50 v minimum output clamp voltage ? 250 ma output current (all outputs simultaneously) ? 1.3 typical r ds(on) ? low power consumption ? replacements for tpic6595n and tpic6595dw 8-bit serial input dmos power driver package: 20-pin dip (suffix a) pin-out diagram not to scale A6595 logic ground 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 serial data out serial data in logic supply v dd strobe power ground clock clk st out 7 out 6 out 5 out 0 out 1 out 2 out 3 out 4 10 11 power ground power ground output enable oe register clear power ground latches register register latches clr
8-bit serial input dmos power driver A6595 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating units logic supply voltage v dd 7.0 v input voltage range v i ?0.3 to 7.0 v output voltage v o 50 v output drain current i o continuous, each output, all outputs on 250 ma i om pulsed t w 100 s, duty cycle 2%; each out- put, all outputs on 750 ma pulsed t w 100 s, duty cycle 2%; 2.0 a single-pulse avalanche energy e as 75 mj operating ambient temperature t a range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *these cmos devices have input static protection (class 3) but are still susceptible to damage if exposed to extremely high sta tic electrical charges. selection guide part number packing A6595ka-t 18 pieces per tube thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja on 4-layer pcb based on jedec standard 32 oc/w *additional thermal information available on the allegro website. 50 75 100 125 150 4.0 0.5 0 allowable package power dissipation in watts ambient temperature o c ) 3.5 3.0 2.5 2.0 1.0 1.5 25
8-bit serial input dmos power driver A6595 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com power ground dwg. fp-013-5 clock serial data in strobe output enable (active low) serial data out serial-parallel shift register d-type latches v dd logic supply register clear (active low) out 0 out n logic ground power ground grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally. functional block diagram 2 g3 c2 srg8 c1 r 1d 2 4 5 6 7 14 15 16 17 18 9 12 8 3 13 device logic diagram
8-bit serial input dmos power driver A6595 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com truth table s t n e t n o c t u p t u o s t n e t n o c h c t a l l a i r e s s t n e t n o c r e t s i g e r t f i h s t u p t u o a t a d k c o l c a t a d input input i 0 i 1 i 2 ... i 6 i 7 output strobe i 0 i 1 i 2 ... i 6 i 7 enable i 0 i 1 i 2 ?i 6 i 7 hhr 0 r 1 ?r 5 r 6 r 6 llr 0 r 1 ?r 5 r 6 r 6 xr 0 r 1 r 2 ?r 6 r 7 r 7 xxx ? xx x ? r 0 r 1 r 2 ?r 6 r 7 p 0 p 1 p 2 ?p 6 p 7 p 7 p 0 p 1 p 2 ?p 6 p 7 lp 0 p 1 p 2 ?p 6 p 7 xxx ? xx h hhh ? hh l = low logic level h = high logic level x = irrelevant p = present state r = previous stat e serial data out logic inputs dw g. ep-063-2 v dd ou t dmos power driver output in dwg. ep-010-1 5 v dd dwg. ep-063-3 ou t recommended operating conditions over operating temperature range logic supply voltage range, v dd ............... 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
8-bit serial input dmos power driver A6595 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com limits s t i n u . x a m . p y t . n i m s n o i t i d n o c t s e t l o b m y s c i t s i r e t c a r a h c output breakdown v (br)dsx i o v ? ? 0 5 a m 1 = voltage off-state output i dsx v o 0 . 1 5 0 . 0 ? v 0 4 = a current v o = 40 v, t a = 125 c ? 0.15 5.0 a static drain-source r ds(on) i o = 250 ma, v dd = 4.5 v ? 1.3 2.0 on-state resistance i o = 250 ma, v dd = 4.5 v, t a = 125 c? 2.0 3.2 i o = 500 ma, v dd = 4.5 v (see note) ? 1.3 2.0 nominal output i on v ds(on) = 0.5 v, t a = 85 c?250?ma current logic input current i ih v i = v dd 0 . 1 ? ? v 5 . 5 = a i il v i = 0, v dd 0 . 1 - ? ? v 5 . 5 = a logic input hysteresis v i(hys) ?1.3? v serial-data v oh i oh = -20 a, v dd = 4.5 v 4.4 4.49 ? v output voltage i oh = -4 ma, v dd = 4.5 v 4.1 4.3 ? v v ol i ol = 20 a, v dd = 4.5 v ? 0.002 0.1 v i ol = 4 ma, v dd = 4.5 v ? 0.2 0.4 v prop. delay time t plh i o = 250 ma, c l = 30 pf ? 650 ? ns t phl i o = 250 ma, c l = 30 pf ? 150 ? ns output rise time t r i o = 250 ma, c l = 30 pf ? 7500 ? ns output fall time t f i o = 250 ma, c l = 30 pf ? 425 ? ns supply current i dd(off) 0 0 1 5 1 ? w o l s t u p n i l l a a i dd(on) v dd = 5.5 v, outputs on ? 150 300 a i dd(fclk) f clk = 5 mhz, c l = 30 pf, outputs off ? 0.6 5.0 ma typi ca l data is at v dd = 5 v and is for design information only . note ? pulse test, duration 100 s, duty cycle 2% . electrical characteristics at t a = +25 c, v dd = 5 v, t ir = t if 10 ns (unless otherwise specified). typical data is at vdd = 5 v and is for design information only. note ? pulse test, duration 100 s, duty cycle 2%.
8-bit serial input dmos power driver A6595 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) a. data active time before clock pulse (data set-up time), t su(d) .......................................... 10 ns b. data active time after clock pulse (data hold time), t h(d) .............................................. 10 ns c. clock pulse width, t w(clk) ............................................. 20 ns d. time between clock activation and strobe, t su(st) ....................................................... 50 ns e. strobe pulse width, t w(st) ............................................... 50 ns f. output enable pulse width, t w(oe) ................................ 4.5 s note ? timing is representative of a 12.5 mhz clock. higher speeds are attainable. serial data present at the input is transferred to the shift reg- ister on the rising edge of the clock input pulse. on succeed- ing clock pulses, the registers shift data information towards the serial data output. information present at any register is transferred to the respective latch on the rising edge of the strobe input pulse (serial-to-parallel conversion). when the output enable input is high, the output source drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input low, the outputs are controlled by the state of their respective latches. clock serial data i n strobe output enable ou t n dwg. wp-029-2 50% serial data ou t data data 50% 50% 50% c a b d e low = all outputs enabled p t data 50% p t low = output o n hi gh = output of f output enable ou t n dwg. wp-030-2 data 10% 50% phl t plh t high = all outputs disable d 90% f t r t
8-bit serial input dmos power driver A6595 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com test circuits single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2 dwg. ep-066-1 ou t input i o v o t av i as = 1.0 a v (br)ds x v o(on) 0.11 100 mh +15 v dut
8-bit serial input dmos power driver A6595 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal descriptions terminal no. terminal name function 1 power ground reference terminal for output voltage measurements (out 0-3 ). 2 logic supply (v dd ) the logic supply voltage (typically 5 v). 3 serial data in serial-data input to the shift-register. 4-7 out 0-3 current-sinking, open-drain dmos output terminals. 8 clear when (active) low, the registers are cleared (set low). 9 output enable when (active) low, the output drivers are enabled; when high, all output driv- ers are turned off (blanked). 10 power ground reference terminal for output voltage measurements (out 0-3 ). 11 power ground reference terminal for output voltage measurements (out 0-7 ). 12 strobe data strobe input terminal; shift register data is latched on rising edge. 13 clock clock input terminal for data shift on rising edge. 14-17 out 4-7 current-sinking, open-drain dmos output terminals. 18 serial data out cmos serial-data output to the following shift register. 19 logic ground reference terminal for input voltage measurements. 20 power ground reference terminal for output voltage measurements (out 4-7 ). note ? grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
8-bit serial input dmos power driver A6595 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com c seating plane 5.33 max 0.46 0.12 6.35 +0.76 ?0.25 26.16 +0.76 ?1.27 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 7.62 2.54 0.38 +0.10 ?0.05 2 1 20 a preliminary dimensions, for reference only dimensions in inches metric dimensions (mm) in brackets, for reference only (reference jedec ms-001 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area package a, 20-pin dip copyright ?2000-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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